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[PATCH] ppc32: IBM 40x and 4xx fixes
authorAndrew Morton <akpm@osdl.org>
Fri, 13 Feb 2004 07:48:11 +0000 (23:48 -0800)
committerLinus Torvalds <torvalds@home.osdl.org>
Fri, 13 Feb 2004 07:48:11 +0000 (23:48 -0800)
commitcec6721d2be7b8b82516c96ae941c386703506c6
tree65cfe1de82a536000a929be1c23dd44a1bdd08catree | snapshot
parent959fb245e0a538fc35420c0f92cd796990bd2928commit | diff
[PATCH] ppc32: IBM 40x and 4xx fixes

From: Tom Rini <trini@kernel.crashing.org>

On IBM 40x and IBM 4xx (or more specifically, all Book E processors), the
Save/Restor Registers 2 and 3 Critical Save and Restore Registers 0 and 1
are logically and functionally equivalent.  And since the 40x is the early
variant on the Book E model, make generic 4xx/BookE code refer to
CSRR0/CSRR1, and map these to SRR2/SRR3 on 40x.
arch/ppc/kernel/entry.S diff | blob | history
include/asm-ppc/reg_booke.h diff | blob | history
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