#elif defined(CONFIG_ARCH_INTEGRATOR)
-#include <asm/hardware/serial_amba.h>
+#include <asm/hardware/amba_serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
.endm
.macro senduart,rd,rx
- strb \rd, [\rx, #AMBA_UARTDR]
+ strb \rd, [\rx, #UART01x_DR]
.endm
.macro waituart,rd,rx
system, say Y to this option. The driver can handle 1, 2, or 3 port
cards. If unsure, say N.
-config SERIAL_AMBA
- tristate "ARM AMBA serial port support"
+config SERIAL_AMBA_PL010
+ tristate "ARM AMBA PL010 serial port support"
depends on ARM_AMBA
select SERIAL_CORE
help
- This selects the ARM(R) AMBA(R) PrimeCell UART. If you have an
- Integrator platform, say Y or M here.
+ This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
+ an Integrator/AP or Integrator/PP2 platform, say Y or M here.
If unsure, say N.
-config SERIAL_AMBA_CONSOLE
+config SERIAL_AMBA_PL010_CONSOLE
bool "Support for console on AMBA serial port"
- depends on SERIAL_AMBA=y
+ depends on SERIAL_AMBA_PL010=y
select SERIAL_CORE_CONSOLE
---help---
Say Y here if you wish to use an AMBA PrimeCell UART as the system
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
-config SERIAL_INTEGRATOR
- bool
- depends on SERIAL_AMBA && ARCH_INTEGRATOR
- default y
+config SERIAL_AMBA_PL011
+ tristate "ARM AMBA PL011 serial port support"
+ depends on ARM_AMBA
+ select SERIAL_CORE
+ help
+ This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
+ an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M
+ here.
+
+ If unsure, say N.
+
+config SERIAL_AMBA_PL011_CONSOLE
+ bool "Support for console on AMBA serial port"
+ depends on SERIAL_AMBA_PL011=y
+ select SERIAL_CORE_CONSOLE
+ ---help---
+ Say Y here if you wish to use an AMBA PrimeCell UART as the system
+ console (the system console is the device which receives all kernel
+ messages and warnings and which allows logins in single user mode).
+
+ Even if you say Y here, the currently visible framebuffer console
+ (/dev/tty0) will still be used as the system console by default, but
+ you can alter that using a kernel command line option such as
+ "console=ttyAM0". (Try "man bootparam" or see the documentation of
+ your boot loader (lilo or loadlin) about how to pass options to the
+ kernel at boot time.)
config SERIAL_CLPS711X
tristate "CLPS711X serial port support"
obj-$(CONFIG_SERIAL_8250) += 8250.o $(serial-8250-y)
obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
-obj-$(CONFIG_SERIAL_AMBA) += amba.o
+obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
+obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
obj-$(CONFIG_SERIAL_PXA) += pxa.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
--- /dev/null
+/*
+ * linux/drivers/char/amba.c
+ *
+ * Driver for AMBA serial ports
+ *
+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * Copyright 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
+ *
+ * This is a generic driver for ARM AMBA-type serial ports. They
+ * have a lot of 16550-like features, but are not register compatible.
+ * Note that although they do have CTS, DCD and DSR inputs, they do
+ * not have an RI input, nor do they have DTR or RTS outputs. If
+ * required, these have to be supplied via some other means (eg, GPIO)
+ * and hooked into this driver.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/hardware/amba.h>
+
+#if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/serial_core.h>
+
+#include <asm/hardware/amba_serial.h>
+
+#define UART_NR 2
+
+#define SERIAL_AMBA_MAJOR 204
+#define SERIAL_AMBA_MINOR 16
+#define SERIAL_AMBA_NR UART_NR
+
+#define AMBA_ISR_PASS_LIMIT 256
+
+/*
+ * Access macros for the AMBA UARTs
+ */
+#define UART_GET_INT_STATUS(p) readb((p)->membase + UART010_IIR)
+#define UART_PUT_ICR(p, c) writel((c), (p)->membase + UART010_ICR)
+#define UART_GET_FR(p) readb((p)->membase + UART01x_FR)
+#define UART_GET_CHAR(p) readb((p)->membase + UART01x_DR)
+#define UART_PUT_CHAR(p, c) writel((c), (p)->membase + UART01x_DR)
+#define UART_GET_RSR(p) readb((p)->membase + UART01x_RSR)
+#define UART_GET_CR(p) readb((p)->membase + UART010_CR)
+#define UART_PUT_CR(p,c) writel((c), (p)->membase + UART010_CR)
+#define UART_GET_LCRL(p) readb((p)->membase + UART010_LCRL)
+#define UART_PUT_LCRL(p,c) writel((c), (p)->membase + UART010_LCRL)
+#define UART_GET_LCRM(p) readb((p)->membase + UART010_LCRM)
+#define UART_PUT_LCRM(p,c) writel((c), (p)->membase + UART010_LCRM)
+#define UART_GET_LCRH(p) readb((p)->membase + UART010_LCRH)
+#define UART_PUT_LCRH(p,c) writel((c), (p)->membase + UART010_LCRH)
+#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
+#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
+#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART01x_FR_TMSK) == 0)
+
+#define UART_DUMMY_RSR_RX /*256*/0
+#define UART_PORT_SIZE 64
+
+/*
+ * On the Integrator platform, the port RTS and DTR are provided by
+ * bits in the following SC_CTRLS register bits:
+ * RTS DTR
+ * UART0 7 6
+ * UART1 5 4
+ */
+#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
+#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
+
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct uart_amba_port {
+ struct uart_port port;
+ unsigned int dtr_mask;
+ unsigned int rts_mask;
+ unsigned int old_status;
+};
+
+static void pl010_stop_tx(struct uart_port *port, unsigned int tty_stop)
+{
+ unsigned int cr;
+
+ cr = UART_GET_CR(port);
+ cr &= ~UART010_CR_TIE;
+ UART_PUT_CR(port, cr);
+}
+
+static void pl010_start_tx(struct uart_port *port, unsigned int tty_start)
+{
+ unsigned int cr;
+
+ cr = UART_GET_CR(port);
+ cr |= UART010_CR_TIE;
+ UART_PUT_CR(port, cr);
+}
+
+static void pl010_stop_rx(struct uart_port *port)
+{
+ unsigned int cr;
+
+ cr = UART_GET_CR(port);
+ cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
+ UART_PUT_CR(port, cr);
+}
+
+static void pl010_enable_ms(struct uart_port *port)
+{
+ unsigned int cr;
+
+ cr = UART_GET_CR(port);
+ cr |= UART010_CR_MSIE;
+ UART_PUT_CR(port, cr);
+}
+
+static void
+#ifdef SUPPORT_SYSRQ
+pl010_rx_chars(struct uart_port *port, struct pt_regs *regs)
+#else
+pl010_rx_chars(struct uart_port *port)
+#endif
+{
+ struct tty_struct *tty = port->info->tty;
+ unsigned int status, ch, rsr, max_count = 256;
+
+ status = UART_GET_FR(port);
+ while (UART_RX_DATA(status) && max_count--) {
+ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+ tty->flip.work.func((void *)tty);
+ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+ printk(KERN_WARNING "TTY_DONT_FLIP set\n");
+ return;
+ }
+ }
+
+ ch = UART_GET_CHAR(port);
+
+ *tty->flip.char_buf_ptr = ch;
+ *tty->flip.flag_buf_ptr = TTY_NORMAL;
+ port->icount.rx++;
+
+ /*
+ * Note that the error handling code is
+ * out of the main execution path
+ */
+ rsr = UART_GET_RSR(port) | UART_DUMMY_RSR_RX;
+ if (rsr & UART01x_RSR_ANY) {
+ if (rsr & UART01x_RSR_BE) {
+ rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ goto ignore_char;
+ } else if (rsr & UART01x_RSR_PE)
+ port->icount.parity++;
+ else if (rsr & UART01x_RSR_FE)
+ port->icount.frame++;
+ if (rsr & UART01x_RSR_OE)
+ port->icount.overrun++;
+
+ rsr &= port->read_status_mask;
+
+ if (rsr & UART01x_RSR_BE)
+ *tty->flip.flag_buf_ptr = TTY_BREAK;
+ else if (rsr & UART01x_RSR_PE)
+ *tty->flip.flag_buf_ptr = TTY_PARITY;
+ else if (rsr & UART01x_RSR_FE)
+ *tty->flip.flag_buf_ptr = TTY_FRAME;
+ }
+
+ if (uart_handle_sysrq_char(port, ch, regs))
+ goto ignore_char;
+
+ if ((rsr & port->ignore_status_mask) == 0) {
+ tty->flip.flag_buf_ptr++;
+ tty->flip.char_buf_ptr++;
+ tty->flip.count++;
+ }
+ if ((rsr & UART01x_RSR_OE) &&
+ tty->flip.count < TTY_FLIPBUF_SIZE) {
+ /*
+ * Overrun is special, since it's reported
+ * immediately, and doesn't affect the current
+ * character
+ */
+ *tty->flip.char_buf_ptr++ = 0;
+ *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
+ tty->flip.count++;
+ }
+ ignore_char:
+ status = UART_GET_FR(port);
+ }
+ tty_flip_buffer_push(tty);
+ return;
+}
+
+static void pl010_tx_chars(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->info->xmit;
+ int count;
+
+ if (port->x_char) {
+ UART_PUT_CHAR(port, port->x_char);
+ port->icount.tx++;
+ port->x_char = 0;
+ return;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+ pl010_stop_tx(port, 0);
+ return;
+ }
+
+ count = port->fifosize >> 1;
+ do {
+ UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ } while (--count > 0);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (uart_circ_empty(xmit))
+ pl010_stop_tx(port, 0);
+}
+
+static void pl010_modem_status(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int status, delta;
+
+ UART_PUT_ICR(&uap->port, 0);
+
+ status = UART_GET_FR(&uap->port) & UART01x_FR_MODEM_ANY;
+
+ delta = status ^ uap->old_status;
+ uap->old_status = status;
+
+ if (!delta)
+ return;
+
+ if (delta & UART01x_FR_DCD)
+ uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
+
+ if (delta & UART01x_FR_DSR)
+ uap->port.icount.dsr++;
+
+ if (delta & UART01x_FR_CTS)
+ uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
+
+ wake_up_interruptible(&uap->port.info->delta_msr_wait);
+}
+
+static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct uart_port *port = dev_id;
+ unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
+ int handled = 0;
+
+ spin_lock(&port->lock);
+
+ status = UART_GET_INT_STATUS(port);
+ if (status) {
+ do {
+ if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
+#ifdef SUPPORT_SYSRQ
+ pl010_rx_chars(port, regs);
+#else
+ pl010_rx_chars(port);
+#endif
+ if (status & UART010_IIR_MIS)
+ pl010_modem_status(port);
+ if (status & UART010_IIR_TIS)
+ pl010_tx_chars(port);
+
+ if (pass_counter-- == 0)
+ break;
+
+ status = UART_GET_INT_STATUS(port);
+ } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
+ UART010_IIR_TIS));
+ handled = 1;
+ }
+
+ spin_unlock(&port->lock);
+
+ return IRQ_RETVAL(handled);
+}
+
+static unsigned int pl010_tx_empty(struct uart_port *port)
+{
+ return UART_GET_FR(port) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int pl010_get_mctrl(struct uart_port *port)
+{
+ unsigned int result = 0;
+ unsigned int status;
+
+ status = UART_GET_FR(port);
+ if (status & UART01x_FR_DCD)
+ result |= TIOCM_CAR;
+ if (status & UART01x_FR_DSR)
+ result |= TIOCM_DSR;
+ if (status & UART01x_FR_CTS)
+ result |= TIOCM_CTS;
+
+ return result;
+}
+
+static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int ctrls = 0, ctrlc = 0;
+
+ if (mctrl & TIOCM_RTS)
+ ctrlc |= uap->rts_mask;
+ else
+ ctrls |= uap->rts_mask;
+
+ if (mctrl & TIOCM_DTR)
+ ctrlc |= uap->dtr_mask;
+ else
+ ctrls |= uap->dtr_mask;
+
+ __raw_writel(ctrls, SC_CTRLS);
+ __raw_writel(ctrlc, SC_CTRLC);
+}
+
+static void pl010_break_ctl(struct uart_port *port, int break_state)
+{
+ unsigned long flags;
+ unsigned int lcr_h;
+
+ spin_lock_irqsave(&port->lock, flags);
+ lcr_h = UART_GET_LCRH(port);
+ if (break_state == -1)
+ lcr_h |= UART01x_LCRH_BRK;
+ else
+ lcr_h &= ~UART01x_LCRH_BRK;
+ UART_PUT_LCRH(port, lcr_h);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static int pl010_startup(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ int retval;
+
+ /*
+ * Allocate the IRQ
+ */
+ retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
+ if (retval)
+ return retval;
+
+ /*
+ * initialise the old status of the modem signals
+ */
+ uap->old_status = UART_GET_FR(port) & UART01x_FR_MODEM_ANY;
+
+ /*
+ * Finally, enable interrupts
+ */
+ UART_PUT_CR(port, UART01x_CR_UARTEN | UART010_CR_RIE |
+ UART010_CR_RTIE);
+
+ return 0;
+}
+
+static void pl010_shutdown(struct uart_port *port)
+{
+ /*
+ * Free the interrupt
+ */
+ free_irq(port->irq, port);
+
+ /*
+ * disable all interrupts, disable the port
+ */
+ UART_PUT_CR(port, 0);
+
+ /* disable break condition and fifos */
+ UART_PUT_LCRH(port, UART_GET_LCRH(port) &
+ ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN));
+}
+
+static void
+pl010_set_termios(struct uart_port *port, struct termios *termios,
+ struct termios *old)
+{
+ unsigned int lcr_h, old_cr;
+ unsigned long flags;
+ unsigned int baud, quot;
+
+ /*
+ * Ask the core to calculate the divisor for us.
+ */
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ quot = uart_get_divisor(port, baud);
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ lcr_h = UART01x_LCRH_WLEN_5;
+ break;
+ case CS6:
+ lcr_h = UART01x_LCRH_WLEN_6;
+ break;
+ case CS7:
+ lcr_h = UART01x_LCRH_WLEN_7;
+ break;
+ default: // CS8
+ lcr_h = UART01x_LCRH_WLEN_8;
+ break;
+ }
+ if (termios->c_cflag & CSTOPB)
+ lcr_h |= UART01x_LCRH_STP2;
+ if (termios->c_cflag & PARENB) {
+ lcr_h |= UART01x_LCRH_PEN;
+ if (!(termios->c_cflag & PARODD))
+ lcr_h |= UART01x_LCRH_EPS;
+ }
+ if (port->fifosize > 1)
+ lcr_h |= UART01x_LCRH_FEN;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /*
+ * Update the per-port timeout.
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ port->read_status_mask = UART01x_RSR_OE;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= UART01x_RSR_BE;
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= UART01x_RSR_BE;
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART01x_RSR_OE;
+ }
+
+ /*
+ * Ignore all characters if CREAD is not set.
+ */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= UART_DUMMY_RSR_RX;
+
+ /* first, disable everything */
+ old_cr = UART_GET_CR(port) & ~UART010_CR_MSIE;
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ old_cr |= UART010_CR_MSIE;
+
+ UART_PUT_CR(port, 0);
+
+ /* Set baud rate */
+ quot -= 1;
+ UART_PUT_LCRM(port, ((quot & 0xf00) >> 8));
+ UART_PUT_LCRL(port, (quot & 0xff));
+
+ /*
+ * ----------v----------v----------v----------v-----
+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+ * ----------^----------^----------^----------^-----
+ */
+ UART_PUT_LCRH(port, lcr_h);
+ UART_PUT_CR(port, old_cr);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *pl010_type(struct uart_port *port)
+{
+ return port->type == PORT_AMBA ? "AMBA" : NULL;
+}
+
+/*
+ * Release the memory region(s) being used by 'port'
+ */
+static void pl010_release_port(struct uart_port *port)
+{
+ release_mem_region(port->mapbase, UART_PORT_SIZE);
+}
+
+/*
+ * Request the memory region(s) being used by 'port'
+ */
+static int pl010_request_port(struct uart_port *port)
+{
+ return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
+ != NULL ? 0 : -EBUSY;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void pl010_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_AMBA;
+ pl010_request_port(port);
+ }
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+ int ret = 0;
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
+ ret = -EINVAL;
+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
+ ret = -EINVAL;
+ if (ser->baud_base < 9600)
+ ret = -EINVAL;
+ return ret;
+}
+
+static struct uart_ops amba_pl010_pops = {
+ .tx_empty = pl010_tx_empty,
+ .set_mctrl = pl010_set_mctrl,
+ .get_mctrl = pl010_get_mctrl,
+ .stop_tx = pl010_stop_tx,
+ .start_tx = pl010_start_tx,
+ .stop_rx = pl010_stop_rx,
+ .enable_ms = pl010_enable_ms,
+ .break_ctl = pl010_break_ctl,
+ .startup = pl010_startup,
+ .shutdown = pl010_shutdown,
+ .set_termios = pl010_set_termios,
+ .type = pl010_type,
+ .release_port = pl010_release_port,
+ .request_port = pl010_request_port,
+ .config_port = pl010_config_port,
+ .verify_port = pl010_verify_port,
+};
+
+static struct uart_amba_port amba_ports[UART_NR] = {
+ {
+ .port = {
+ .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
+ .mapbase = INTEGRATOR_UART0_BASE,
+ .iotype = SERIAL_IO_MEM,
+ .irq = IRQ_UARTINT0,
+ .uartclk = 14745600,
+ .fifosize = 16,
+ .ops = &amba_pl010_pops,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .dtr_mask = 1 << 5,
+ .rts_mask = 1 << 4,
+ },
+ {
+ .port = {
+ .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
+ .mapbase = INTEGRATOR_UART1_BASE,
+ .iotype = SERIAL_IO_MEM,
+ .irq = IRQ_UARTINT1,
+ .uartclk = 14745600,
+ .fifosize = 16,
+ .ops = &amba_pl010_pops,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .dtr_mask = 1 << 7,
+ .rts_mask = 1 << 6,
+ }
+};
+
+#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
+
+static void
+pl010_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct uart_port *port = &amba_ports[co->index].port;
+ unsigned int status, old_cr;
+ int i;
+
+ /*
+ * First save the CR then disable the interrupts
+ */
+ old_cr = UART_GET_CR(port);
+ UART_PUT_CR(port, UART01x_CR_UARTEN);
+
+ /*
+ * Now, do each character
+ */
+ for (i = 0; i < count; i++) {
+ do {
+ status = UART_GET_FR(port);
+ } while (!UART_TX_READY(status));
+ UART_PUT_CHAR(port, s[i]);
+ if (s[i] == '\n') {
+ do {
+ status = UART_GET_FR(port);
+ } while (!UART_TX_READY(status));
+ UART_PUT_CHAR(port, '\r');
+ }
+ }
+
+ /*
+ * Finally, wait for transmitter to become empty
+ * and restore the TCR
+ */
+ do {
+ status = UART_GET_FR(port);
+ } while (status & UART01x_FR_BUSY);
+ UART_PUT_CR(port, old_cr);
+}
+
+static void __init
+pl010_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
+{
+ if (UART_GET_CR(port) & UART01x_CR_UARTEN) {
+ unsigned int lcr_h, quot;
+ lcr_h = UART_GET_LCRH(port);
+
+ *parity = 'n';
+ if (lcr_h & UART01x_LCRH_PEN) {
+ if (lcr_h & UART01x_LCRH_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+
+ if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
+ *bits = 7;
+ else
+ *bits = 8;
+
+ quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8;
+ *baud = port->uartclk / (16 * (quot + 1));
+ }
+}
+
+static int __init pl010_console_setup(struct console *co, char *options)
+{
+ struct uart_port *port;
+ int baud = 38400;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ /*
+ * Check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+ if (co->index >= UART_NR)
+ co->index = 0;
+ port = &amba_ports[co->index].port;
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+ pl010_console_get_options(port, &baud, &parity, &bits);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+extern struct uart_driver amba_reg;
+static struct console amba_console = {
+ .name = "ttyAM",
+ .write = pl010_console_write,
+ .device = uart_console_device,
+ .setup = pl010_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &amba_reg,
+};
+
+#define AMBA_CONSOLE &amba_console
+#else
+#define AMBA_CONSOLE NULL
+#endif
+
+static struct uart_driver amba_reg = {
+ .owner = THIS_MODULE,
+ .driver_name = "ttyAM",
+ .dev_name = "ttyAM",
+ .major = SERIAL_AMBA_MAJOR,
+ .minor = SERIAL_AMBA_MINOR,
+ .nr = UART_NR,
+ .cons = AMBA_CONSOLE,
+};
+
+static int pl010_probe(struct amba_device *dev, void *id)
+{
+ int i;
+
+ for (i = 0; i < UART_NR; i++) {
+ if (amba_ports[i].port.mapbase != dev->res.start)
+ continue;
+
+ amba_ports[i].port.dev = &dev->dev;
+ uart_add_one_port(&amba_reg, &amba_ports[i].port);
+ amba_set_drvdata(dev, &amba_ports[i]);
+ break;
+ }
+
+ return 0;
+}
+
+static int pl010_remove(struct amba_device *dev)
+{
+ struct uart_amba_port *uap = amba_get_drvdata(dev);
+
+ if (uap)
+ uart_remove_one_port(&amba_reg, &uap->port);
+
+ amba_set_drvdata(dev, NULL);
+
+ return 0;
+}
+
+static int pl010_suspend(struct amba_device *dev, u32 state)
+{
+ struct uart_amba_port *uap = amba_get_drvdata(dev);
+
+ if (uap)
+ uart_suspend_port(&amba_reg, &uap->port);
+
+ return 0;
+}
+
+static int pl010_resume(struct amba_device *dev)
+{
+ struct uart_amba_port *uap = amba_get_drvdata(dev);
+
+ if (uap)
+ uart_resume_port(&amba_reg, &uap->port);
+
+ return 0;
+}
+
+static struct amba_id pl010_ids[] __initdata = {
+ {
+ .id = 0x00041010,
+ .mask = 0x000fffff,
+ },
+ { 0, 0 },
+};
+
+static struct amba_driver pl010_driver = {
+ .drv = {
+ .name = "uart-pl010",
+ },
+ .id_table = pl010_ids,
+ .probe = pl010_probe,
+ .remove = pl010_remove,
+ .suspend = pl010_suspend,
+ .resume = pl010_resume,
+};
+
+static int __init pl010_init(void)
+{
+ int ret;
+
+ printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
+
+ ret = uart_register_driver(&amba_reg);
+ if (ret == 0) {
+ ret = amba_driver_register(&pl010_driver);
+ if (ret)
+ uart_unregister_driver(&amba_reg);
+ }
+ return ret;
+}
+
+static void __exit pl010_exit(void)
+{
+ amba_driver_unregister(&pl010_driver);
+ uart_unregister_driver(&amba_reg);
+}
+
+module_init(pl010_init);
+module_exit(pl010_exit);
+
+MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
+MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * linux/drivers/char/amba.c
+ *
+ * Driver for AMBA serial ports
+ *
+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * Copyright 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
+ *
+ * This is a generic driver for ARM AMBA-type serial ports. They
+ * have a lot of 16550-like features, but are not register compatible.
+ * Note that although they do have CTS, DCD and DSR inputs, they do
+ * not have an RI input, nor do they have DTR or RTS outputs. If
+ * required, these have to be supplied via some other means (eg, GPIO)
+ * and hooked into this driver.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/hardware/amba.h>
+#include <asm/hardware/clock.h>
+
+#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/serial_core.h>
+
+#include <asm/hardware/amba_serial.h>
+
+#define UART_NR 14
+
+#define SERIAL_AMBA_MAJOR 204
+#define SERIAL_AMBA_MINOR 64
+#define SERIAL_AMBA_NR UART_NR
+
+#define AMBA_ISR_PASS_LIMIT 256
+
+#define UART_DUMMY_RSR_RX 256
+
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct uart_amba_port {
+ struct uart_port port;
+ struct clk *clk;
+ unsigned int im; /* interrupt mask */
+ unsigned int old_status;
+};
+
+static void pl011_stop_tx(struct uart_port *port, unsigned int tty_stop)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
+ uap->im &= ~UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void pl011_start_tx(struct uart_port *port, unsigned int tty_start)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
+ uap->im |= UART011_TXIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void pl011_stop_rx(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
+ uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
+ UART011_PEIM|UART011_BEIM|UART011_OEIM);
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void pl011_enable_ms(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
+ uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+}
+
+static void
+#ifdef SUPPORT_SYSRQ
+pl011_rx_chars(struct uart_amba_port *uap, struct pt_regs *regs)
+#else
+pl011_rx_chars(struct uart_amba_port *uap)
+#endif
+{
+ struct tty_struct *tty = uap->port.info->tty;
+ unsigned int status, ch, rsr, max_count = 256;
+
+ status = readw(uap->port.membase + UART01x_FR);
+ while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
+ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+ tty->flip.work.func((void *)tty);
+ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+ printk(KERN_WARNING "TTY_DONT_FLIP set\n");
+ return;
+ }
+ }
+
+ ch = readw(uap->port.membase + UART01x_DR);
+
+ *tty->flip.char_buf_ptr = ch;
+ *tty->flip.flag_buf_ptr = TTY_NORMAL;
+ uap->port.icount.rx++;
+
+ /*
+ * Note that the error handling code is
+ * out of the main execution path
+ */
+ rsr = readw(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
+ if (rsr & UART01x_RSR_ANY) {
+ if (rsr & UART01x_RSR_BE) {
+ rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
+ uap->port.icount.brk++;
+ if (uart_handle_break(&uap->port))
+ goto ignore_char;
+ } else if (rsr & UART01x_RSR_PE)
+ uap->port.icount.parity++;
+ else if (rsr & UART01x_RSR_FE)
+ uap->port.icount.frame++;
+ if (rsr & UART01x_RSR_OE)
+ uap->port.icount.overrun++;
+
+ rsr &= uap->port.read_status_mask;
+
+ if (rsr & UART01x_RSR_BE)
+ *tty->flip.flag_buf_ptr = TTY_BREAK;
+ else if (rsr & UART01x_RSR_PE)
+ *tty->flip.flag_buf_ptr = TTY_PARITY;
+ else if (rsr & UART01x_RSR_FE)
+ *tty->flip.flag_buf_ptr = TTY_FRAME;
+ }
+
+ if (uart_handle_sysrq_char(&uap->port, ch, regs))
+ goto ignore_char;
+
+ if ((rsr & uap->port.ignore_status_mask) == 0) {
+ tty->flip.flag_buf_ptr++;
+ tty->flip.char_buf_ptr++;
+ tty->flip.count++;
+ }
+ if ((rsr & UART01x_RSR_OE) &&
+ tty->flip.count < TTY_FLIPBUF_SIZE) {
+ /*
+ * Overrun is special, since it's reported
+ * immediately, and doesn't affect the current
+ * character
+ */
+ *tty->flip.char_buf_ptr++ = 0;
+ *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
+ tty->flip.count++;
+ }
+ ignore_char:
+ status = readw(uap->port.membase + UART01x_FR);
+ }
+ tty_flip_buffer_push(tty);
+ return;
+}
+
+static void pl011_tx_chars(struct uart_amba_port *uap)
+{
+ struct circ_buf *xmit = &uap->port.info->xmit;
+ int count;
+
+ if (uap->port.x_char) {
+ writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+ uap->port.icount.tx++;
+ uap->port.x_char = 0;
+ return;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
+ pl011_stop_tx(&uap->port, 0);
+ return;
+ }
+
+ count = uap->port.fifosize >> 1;
+ do {
+ writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ uap->port.icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ } while (--count > 0);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(&uap->port);
+
+ if (uart_circ_empty(xmit))
+ pl011_stop_tx(&uap->port, 0);
+}
+
+static void pl011_modem_status(struct uart_amba_port *uap)
+{
+ unsigned int status, delta;
+
+ status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+
+ delta = status ^ uap->old_status;
+ uap->old_status = status;
+
+ if (!delta)
+ return;
+
+ if (delta & UART01x_FR_DCD)
+ uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
+
+ if (delta & UART01x_FR_DSR)
+ uap->port.icount.dsr++;
+
+ if (delta & UART01x_FR_CTS)
+ uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
+
+ wake_up_interruptible(&uap->port.info->delta_msr_wait);
+}
+
+static irqreturn_t pl011_int(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct uart_amba_port *uap = dev_id;
+ unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
+ int handled = 0;
+
+ spin_lock(&uap->port.lock);
+
+ status = readw(uap->port.membase + UART011_MIS);
+ if (status) {
+ do {
+ writew(status & ~(UART011_TXIS|UART011_RTIS|
+ UART011_RXIS),
+ uap->port.membase + UART011_ICR);
+
+ if (status & (UART011_RTIS|UART011_RXIS))
+#ifdef SUPPORT_SYSRQ
+ pl011_rx_chars(uap, regs);
+#else
+ pl011_rx_chars(uap);
+#endif
+ if (status & (UART011_DSRMIS|UART011_DCDMIS|
+ UART011_CTSMIS|UART011_RIMIS))
+ pl011_modem_status(uap);
+ if (status & UART011_TXIS)
+ pl011_tx_chars(uap);
+
+ if (pass_counter-- == 0)
+ break;
+
+ status = readw(uap->port.membase + UART011_MIS);
+ } while (status != 0);
+ handled = 1;
+ }
+
+ spin_unlock(&uap->port.lock);
+
+ return IRQ_RETVAL(handled);
+}
+
+static unsigned int pl01x_tx_empty(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int status = readw(uap->port.membase + UART01x_FR);
+ return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int pl01x_get_mctrl(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int result = 0;
+ unsigned int status = readw(uap->port.membase + UART01x_FR);
+
+#define BIT(uartbit, tiocmbit) \
+ if (status & uartbit) \
+ result |= tiocmbit
+
+ BIT(UART01x_FR_DCD, TIOCM_CAR);
+ BIT(UART01x_FR_DSR, TIOCM_DSR);
+ BIT(UART01x_FR_CTS, TIOCM_CTS);
+ BIT(UART011_FR_RI, TIOCM_RNG);
+#undef BIT
+ return result;
+}
+
+static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+
+ cr = readw(uap->port.membase + UART011_CR);
+
+#define BIT(tiocmbit, uartbit) \
+ if (mctrl & tiocmbit) \
+ cr |= uartbit; \
+ else \
+ cr &= ~uartbit
+
+ BIT(TIOCM_RTS, UART011_CR_RTS);
+ BIT(TIOCM_DTR, UART011_CR_DTR);
+ BIT(TIOCM_OUT1, UART011_CR_OUT1);
+ BIT(TIOCM_OUT2, UART011_CR_OUT2);
+ BIT(TIOCM_LOOP, UART011_CR_LBE);
+#undef BIT
+
+ writew(cr, uap->port.membase + UART011_CR);
+}
+
+static void pl011_break_ctl(struct uart_port *port, int break_state)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned long flags;
+ unsigned int lcr_h;
+
+ spin_lock_irqsave(&uap->port.lock, flags);
+ lcr_h = readw(uap->port.membase + UART011_LCRH);
+ if (break_state == -1)
+ lcr_h |= UART01x_LCRH_BRK;
+ else
+ lcr_h &= ~UART01x_LCRH_BRK;
+ writew(lcr_h, uap->port.membase + UART011_LCRH);
+ spin_unlock_irqrestore(&uap->port.lock, flags);
+}
+
+static int pl011_startup(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+ int retval;
+
+ /*
+ * Try to enable the clock producer.
+ */
+ retval = clk_enable(uap->clk);
+ if (retval)
+ goto out;
+
+ /*
+ * Allocate the IRQ
+ */
+ retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
+ if (retval)
+ goto clk_dis;
+
+ writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
+ uap->port.membase + UART011_IFLS);
+
+ /*
+ * Provoke TX FIFO interrupt into asserting.
+ */
+ cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
+ writew(cr, uap->port.membase + UART011_CR);
+ writew(0, uap->port.membase + UART011_FBRD);
+ writew(1, uap->port.membase + UART011_IBRD);
+ writew(0, uap->port.membase + UART011_LCRH);
+ writew(0, uap->port.membase + UART01x_DR);
+ while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
+ barrier();
+
+ cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
+ writew(cr, uap->port.membase + UART011_CR);
+
+ /*
+ * initialise the old status of the modem signals
+ */
+ uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+
+ /*
+ * Finally, enable interrupts
+ */
+ spin_lock_irq(&uap->port.lock);
+ uap->im = UART011_RXIM | UART011_RTIM;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ spin_unlock_irq(&uap->port.lock);
+
+ return 0;
+
+ clk_dis:
+ clk_disable(uap->clk);
+ out:
+ return retval;
+}
+
+static void pl011_shutdown(struct uart_port *port)
+{
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned long val;
+
+ /*
+ * disable all interrupts
+ */
+ spin_lock_irq(&uap->port.lock);
+ uap->im = 0;
+ writew(uap->im, uap->port.membase + UART011_IMSC);
+ writew(0xffff, uap->port.membase + UART011_ICR);
+ spin_unlock_irq(&uap->port.lock);
+
+ /*
+ * Free the interrupt
+ */
+ free_irq(uap->port.irq, uap);
+
+ /*
+ * disable the port
+ */
+ writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
+
+ /*
+ * disable break condition and fifos
+ */
+ val = readw(uap->port.membase + UART011_LCRH);
+ val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
+ writew(val, uap->port.membase + UART011_LCRH);
+
+ /*
+ * Shut down the clock producer
+ */
+ clk_disable(uap->clk);
+}
+
+static void
+pl011_set_termios(struct uart_port *port, struct termios *termios,
+ struct termios *old)
+{
+ unsigned int lcr_h, old_cr;
+ unsigned long flags;
+ unsigned int baud, quot;
+
+ /*
+ * Ask the core to calculate the divisor for us.
+ */
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ quot = port->uartclk * 4 / baud;
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ lcr_h = UART01x_LCRH_WLEN_5;
+ break;
+ case CS6:
+ lcr_h = UART01x_LCRH_WLEN_6;
+ break;
+ case CS7:
+ lcr_h = UART01x_LCRH_WLEN_7;
+ break;
+ default: // CS8
+ lcr_h = UART01x_LCRH_WLEN_8;
+ break;
+ }
+ if (termios->c_cflag & CSTOPB)
+ lcr_h |= UART01x_LCRH_STP2;
+ if (termios->c_cflag & PARENB) {
+ lcr_h |= UART01x_LCRH_PEN;
+ if (!(termios->c_cflag & PARODD))
+ lcr_h |= UART01x_LCRH_EPS;
+ }
+ if (port->fifosize > 1)
+ lcr_h |= UART01x_LCRH_FEN;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /*
+ * Update the per-port timeout.
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ port->read_status_mask = UART01x_RSR_OE;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= UART01x_RSR_BE;
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= UART01x_RSR_BE;
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART01x_RSR_OE;
+ }
+
+ /*
+ * Ignore all characters if CREAD is not set.
+ */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= UART_DUMMY_RSR_RX;
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ pl011_enable_ms(port);
+
+ /* first, disable everything */
+ old_cr = readw(port->membase + UART011_CR);
+ writew(0, port->membase + UART011_CR);
+
+ /* Set baud rate */
+ writew(quot & 0x3f, port->membase + UART011_FBRD);
+ writew(quot >> 6, port->membase + UART011_IBRD);
+
+ /*
+ * ----------v----------v----------v----------v-----
+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+ * ----------^----------^----------^----------^-----
+ */
+ writew(lcr_h, port->membase + UART011_LCRH);
+ writew(old_cr, port->membase + UART011_CR);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *pl011_type(struct uart_port *port)
+{
+ return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
+}
+
+/*
+ * Release the memory region(s) being used by 'port'
+ */
+static void pl010_release_port(struct uart_port *port)
+{
+ release_mem_region(port->mapbase, SZ_4K);
+}
+
+/*
+ * Request the memory region(s) being used by 'port'
+ */
+static int pl010_request_port(struct uart_port *port)
+{
+ return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
+ != NULL ? 0 : -EBUSY;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void pl010_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_AMBA;
+ pl010_request_port(port);
+ }
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+ int ret = 0;
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
+ ret = -EINVAL;
+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
+ ret = -EINVAL;
+ if (ser->baud_base < 9600)
+ ret = -EINVAL;
+ return ret;
+}
+
+static struct uart_ops amba_pl011_pops = {
+ .tx_empty = pl01x_tx_empty,
+ .set_mctrl = pl011_set_mctrl,
+ .get_mctrl = pl01x_get_mctrl,
+ .stop_tx = pl011_stop_tx,
+ .start_tx = pl011_start_tx,
+ .stop_rx = pl011_stop_rx,
+ .enable_ms = pl011_enable_ms,
+ .break_ctl = pl011_break_ctl,
+ .startup = pl011_startup,
+ .shutdown = pl011_shutdown,
+ .set_termios = pl011_set_termios,
+ .type = pl011_type,
+ .release_port = pl010_release_port,
+ .request_port = pl010_request_port,
+ .config_port = pl010_config_port,
+ .verify_port = pl010_verify_port,
+};
+
+static struct uart_amba_port *amba_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
+
+static inline void
+pl011_console_write_char(struct uart_port *port, char ch)
+{
+ unsigned int status;
+
+ do {
+ status = readw(port->membase + UART01x_FR);
+ } while (status & UART01x_FR_TXFF);
+ writew(ch, port->membase + UART01x_DR);
+}
+
+static void
+pl011_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct uart_port *port = &amba_ports[co->index]->port;
+ unsigned int status, old_cr, new_cr;
+ int i;
+
+ /*
+ * First save the CR then disable the interrupts
+ */
+ old_cr = readw(port->membase + UART011_CR);
+ new_cr = old_cr & ~UART011_CR_CTSEN;
+ new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
+ writew(new_cr, port->membase + UART011_CR);
+
+ /*
+ * Now, do each character
+ */
+ for (i = 0; i < count; i++) {
+ pl011_console_write_char(port, s[i]);
+ if (s[i] == '\n')
+ pl011_console_write_char(port, '\r');
+ }
+
+ /*
+ * Finally, wait for transmitter to become empty
+ * and restore the TCR
+ */
+ do {
+ status = readw(port->membase + UART01x_FR);
+ } while (status & UART01x_FR_BUSY);
+ writew(old_cr, port->membase + UART011_CR);
+}
+
+static void __init
+pl011_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
+{
+ if (readw(port->membase + UART011_CR) & UART01x_CR_UARTEN) {
+ unsigned int lcr_h, ibrd, fbrd;
+
+ lcr_h = readw(port->membase + UART011_LCRH);
+
+ *parity = 'n';
+ if (lcr_h & UART01x_LCRH_PEN) {
+ if (lcr_h & UART01x_LCRH_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+
+ if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
+ *bits = 7;
+ else
+ *bits = 8;
+
+ ibrd = readw(port->membase + UART011_IBRD);
+ fbrd = readw(port->membase + UART011_FBRD);
+
+ *baud = port->uartclk * 4 / (64 * ibrd + fbrd);
+ }
+}
+
+static int __init pl011_console_setup(struct console *co, char *options)
+{
+ struct uart_amba_port *uap;
+ int baud = 38400;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+ int ret;
+
+ /*
+ * Check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+ if (co->index >= UART_NR)
+ co->index = 0;
+ uap = amba_ports[co->index];
+
+ ret = clk_enable(uap->clk);
+ if (ret)
+ return ret;
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+ pl011_console_get_options(&uap->port, &baud, &parity, &bits);
+
+ return uart_set_options(&uap->port, co, baud, parity, bits, flow);
+}
+
+extern struct uart_driver amba_reg;
+static struct console amba_console = {
+ .name = "ttyAMA",
+ .write = pl011_console_write,
+ .device = uart_console_device,
+ .setup = pl011_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &amba_reg,
+};
+
+#define AMBA_CONSOLE (&amba_console)
+#else
+#define AMBA_CONSOLE NULL
+#endif
+
+static struct uart_driver amba_reg = {
+ .owner = THIS_MODULE,
+ .driver_name = "ttyAMA",
+ .dev_name = "ttyAMA",
+ .major = SERIAL_AMBA_MAJOR,
+ .minor = SERIAL_AMBA_MINOR,
+ .nr = UART_NR,
+ .cons = AMBA_CONSOLE,
+};
+
+static int pl011_probe(struct amba_device *dev, void *id)
+{
+ struct uart_amba_port *uap;
+ void *base;
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
+ if (amba_ports[i] == NULL)
+ break;
+
+ if (i == ARRAY_SIZE(amba_ports)) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
+ if (uap == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ base = ioremap(dev->res.start, PAGE_SIZE);
+ if (!base) {
+ ret = -ENOMEM;
+ goto free;
+ }
+
+ memset(uap, 0, sizeof(struct uart_amba_port));
+ uap->clk = clk_get(&dev->dev, "UARTCLK");
+ if (IS_ERR(uap->clk)) {
+ ret = PTR_ERR(uap->clk);
+ goto unmap;
+ }
+
+ uap->port.dev = &dev->dev;
+ uap->port.mapbase = dev->res.start;
+ uap->port.membase = base;
+ uap->port.iotype = UPIO_MEM;
+ uap->port.irq = dev->irq[0];
+ uap->port.uartclk = clk_get_rate(uap->clk);
+ uap->port.fifosize = 16;
+ uap->port.ops = &amba_pl011_pops;
+ uap->port.flags = UPF_BOOT_AUTOCONF;
+ uap->port.line = i;
+
+ amba_ports[i] = uap;
+
+ amba_set_drvdata(dev, uap);
+ ret = uart_add_one_port(&amba_reg, &uap->port);
+ if (ret) {
+ amba_set_drvdata(dev, NULL);
+ amba_ports[i] = NULL;
+ clk_put(uap->clk);
+ unmap:
+ iounmap(base);
+ free:
+ kfree(uap);
+ }
+ out:
+ return ret;
+}
+
+static int pl011_remove(struct amba_device *dev)
+{
+ struct uart_amba_port *uap = amba_get_drvdata(dev);
+ int i;
+
+ amba_set_drvdata(dev, NULL);
+
+ uart_remove_one_port(&amba_reg, &uap->port);
+
+ for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
+ if (amba_ports[i] == uap)
+ amba_ports[i] = NULL;
+
+ iounmap(uap->port.membase);
+ clk_put(uap->clk);
+ kfree(uap);
+ return 0;
+}
+
+static struct amba_id pl011_ids[] __initdata = {
+ {
+ .id = 0x00041011,
+ .mask = 0x000fffff,
+ },
+ { 0, 0 },
+};
+
+static struct amba_driver pl011_driver = {
+ .drv = {
+ .name = "uart-pl011",
+ },
+ .id_table = pl011_ids,
+ .probe = pl011_probe,
+ .remove = pl011_remove,
+};
+
+static int __init pl011_init(void)
+{
+ int ret;
+ printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
+
+ ret = uart_register_driver(&amba_reg);
+ if (ret == 0) {
+ ret = amba_driver_register(&pl011_driver);
+ if (ret)
+ uart_unregister_driver(&amba_reg);
+ }
+ return ret;
+}
+
+static void __exit pl011_exit(void)
+{
+ amba_driver_unregister(&pl011_driver);
+ uart_unregister_driver(&amba_reg);
+}
+
+module_init(pl011_init);
+module_exit(pl011_exit);
+
+MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
+MODULE_DESCRIPTION("ARM AMBA serial port driver");
+MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * linux/drivers/char/amba.c
- *
- * Driver for AMBA serial ports
- *
- * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
- *
- * Copyright 1999 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
- *
- * This is a generic driver for ARM AMBA-type serial ports. They
- * have a lot of 16550-like features, but are not register compatible.
- * Note that although they do have CTS, DCD and DSR inputs, they do
- * not have an RI input, nor do they have DTR or RTS outputs. If
- * required, these have to be supplied via some other means (eg, GPIO)
- * and hooked into this driver.
- */
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/serial.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/device.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-
-#if defined(CONFIG_SERIAL_AMBA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-
-#include <linux/serial_core.h>
-
-#include <asm/hardware/serial_amba.h>
-
-#define UART_NR 2
-
-#define SERIAL_AMBA_MAJOR 204
-#define SERIAL_AMBA_MINOR 16
-#define SERIAL_AMBA_NR UART_NR
-
-#define AMBA_ISR_PASS_LIMIT 256
-
-/*
- * Access macros for the AMBA UARTs
- */
-#define UART_GET_INT_STATUS(p) readb((p)->membase + AMBA_UARTIIR)
-#define UART_PUT_ICR(p, c) writel((c), (p)->membase + AMBA_UARTICR)
-#define UART_GET_FR(p) readb((p)->membase + AMBA_UARTFR)
-#define UART_GET_CHAR(p) readb((p)->membase + AMBA_UARTDR)
-#define UART_PUT_CHAR(p, c) writel((c), (p)->membase + AMBA_UARTDR)
-#define UART_GET_RSR(p) readb((p)->membase + AMBA_UARTRSR)
-#define UART_GET_CR(p) readb((p)->membase + AMBA_UARTCR)
-#define UART_PUT_CR(p,c) writel((c), (p)->membase + AMBA_UARTCR)
-#define UART_GET_LCRL(p) readb((p)->membase + AMBA_UARTLCR_L)
-#define UART_PUT_LCRL(p,c) writel((c), (p)->membase + AMBA_UARTLCR_L)
-#define UART_GET_LCRM(p) readb((p)->membase + AMBA_UARTLCR_M)
-#define UART_PUT_LCRM(p,c) writel((c), (p)->membase + AMBA_UARTLCR_M)
-#define UART_GET_LCRH(p) readb((p)->membase + AMBA_UARTLCR_H)
-#define UART_PUT_LCRH(p,c) writel((c), (p)->membase + AMBA_UARTLCR_H)
-#define UART_RX_DATA(s) (((s) & AMBA_UARTFR_RXFE) == 0)
-#define UART_TX_READY(s) (((s) & AMBA_UARTFR_TXFF) == 0)
-#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & AMBA_UARTFR_TMSK) == 0)
-
-#define UART_DUMMY_RSR_RX 256
-#define UART_PORT_SIZE 64
-
-/*
- * On the Integrator platform, the port RTS and DTR are provided by
- * bits in the following SC_CTRLS register bits:
- * RTS DTR
- * UART0 7 6
- * UART1 5 4
- */
-#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
-#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
-
-/*
- * We wrap our port structure around the generic uart_port.
- */
-struct uart_amba_port {
- struct uart_port port;
- unsigned int dtr_mask;
- unsigned int rts_mask;
- unsigned int old_status;
-};
-
-static void ambauart_stop_tx(struct uart_port *port, unsigned int tty_stop)
-{
- unsigned int cr;
-
- cr = UART_GET_CR(port);
- cr &= ~AMBA_UARTCR_TIE;
- UART_PUT_CR(port, cr);
-}
-
-static void ambauart_start_tx(struct uart_port *port, unsigned int tty_start)
-{
- unsigned int cr;
-
- cr = UART_GET_CR(port);
- cr |= AMBA_UARTCR_TIE;
- UART_PUT_CR(port, cr);
-}
-
-static void ambauart_stop_rx(struct uart_port *port)
-{
- unsigned int cr;
-
- cr = UART_GET_CR(port);
- cr &= ~(AMBA_UARTCR_RIE | AMBA_UARTCR_RTIE);
- UART_PUT_CR(port, cr);
-}
-
-static void ambauart_enable_ms(struct uart_port *port)
-{
- unsigned int cr;
-
- cr = UART_GET_CR(port);
- cr |= AMBA_UARTCR_MSIE;
- UART_PUT_CR(port, cr);
-}
-
-static void
-#ifdef SUPPORT_SYSRQ
-ambauart_rx_chars(struct uart_port *port, struct pt_regs *regs)
-#else
-ambauart_rx_chars(struct uart_port *port)
-#endif
-{
- struct tty_struct *tty = port->info->tty;
- unsigned int status, ch, rsr, max_count = 256;
-
- status = UART_GET_FR(port);
- while (UART_RX_DATA(status) && max_count--) {
- if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
- tty->flip.work.func((void *)tty);
- if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
- printk(KERN_WARNING "TTY_DONT_FLIP set\n");
- return;
- }
- }
-
- ch = UART_GET_CHAR(port);
-
- *tty->flip.char_buf_ptr = ch;
- *tty->flip.flag_buf_ptr = TTY_NORMAL;
- port->icount.rx++;
-
- /*
- * Note that the error handling code is
- * out of the main execution path
- */
- rsr = UART_GET_RSR(port) | UART_DUMMY_RSR_RX;
- if (rsr & AMBA_UARTRSR_ANY) {
- if (rsr & AMBA_UARTRSR_BE) {
- rsr &= ~(AMBA_UARTRSR_FE | AMBA_UARTRSR_PE);
- port->icount.brk++;
- if (uart_handle_break(port))
- goto ignore_char;
- } else if (rsr & AMBA_UARTRSR_PE)
- port->icount.parity++;
- else if (rsr & AMBA_UARTRSR_FE)
- port->icount.frame++;
- if (rsr & AMBA_UARTRSR_OE)
- port->icount.overrun++;
-
- rsr &= port->read_status_mask;
-
- if (rsr & AMBA_UARTRSR_BE)
- *tty->flip.flag_buf_ptr = TTY_BREAK;
- else if (rsr & AMBA_UARTRSR_PE)
- *tty->flip.flag_buf_ptr = TTY_PARITY;
- else if (rsr & AMBA_UARTRSR_FE)
- *tty->flip.flag_buf_ptr = TTY_FRAME;
- }
-
- if (uart_handle_sysrq_char(port, ch, regs))
- goto ignore_char;
-
- if ((rsr & port->ignore_status_mask) == 0) {
- tty->flip.flag_buf_ptr++;
- tty->flip.char_buf_ptr++;
- tty->flip.count++;
- }
- if ((rsr & AMBA_UARTRSR_OE) &&
- tty->flip.count < TTY_FLIPBUF_SIZE) {
- /*
- * Overrun is special, since it's reported
- * immediately, and doesn't affect the current
- * character
- */
- *tty->flip.char_buf_ptr++ = 0;
- *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
- tty->flip.count++;
- }
- ignore_char:
- status = UART_GET_FR(port);
- }
- tty_flip_buffer_push(tty);
- return;
-}
-
-static void ambauart_tx_chars(struct uart_port *port)
-{
- struct circ_buf *xmit = &port->info->xmit;
- int count;
-
- if (port->x_char) {
- UART_PUT_CHAR(port, port->x_char);
- port->icount.tx++;
- port->x_char = 0;
- return;
- }
- if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
- ambauart_stop_tx(port, 0);
- return;
- }
-
- count = port->fifosize >> 1;
- do {
- UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- port->icount.tx++;
- if (uart_circ_empty(xmit))
- break;
- } while (--count > 0);
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-
- if (uart_circ_empty(xmit))
- ambauart_stop_tx(port, 0);
-}
-
-static void ambauart_modem_status(struct uart_port *port)
-{
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int status, delta;
-
- UART_PUT_ICR(&uap->port, 0);
-
- status = UART_GET_FR(&uap->port) & AMBA_UARTFR_MODEM_ANY;
-
- delta = status ^ uap->old_status;
- uap->old_status = status;
-
- if (!delta)
- return;
-
- if (delta & AMBA_UARTFR_DCD)
- uart_handle_dcd_change(&uap->port, status & AMBA_UARTFR_DCD);
-
- if (delta & AMBA_UARTFR_DSR)
- uap->port.icount.dsr++;
-
- if (delta & AMBA_UARTFR_CTS)
- uart_handle_cts_change(&uap->port, status & AMBA_UARTFR_CTS);
-
- wake_up_interruptible(&uap->port.info->delta_msr_wait);
-}
-
-static irqreturn_t ambauart_int(int irq, void *dev_id, struct pt_regs *regs)
-{
- struct uart_port *port = dev_id;
- unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
-
- status = UART_GET_INT_STATUS(port);
- do {
- if (status & (AMBA_UARTIIR_RTIS | AMBA_UARTIIR_RIS))
-#ifdef SUPPORT_SYSRQ
- ambauart_rx_chars(port, regs);
-#else
- ambauart_rx_chars(port);
-#endif
- if (status & AMBA_UARTIIR_MIS)
- ambauart_modem_status(port);
- if (status & AMBA_UARTIIR_TIS)
- ambauart_tx_chars(port);
-
- if (pass_counter-- == 0)
- break;
-
- status = UART_GET_INT_STATUS(port);
- } while (status & (AMBA_UARTIIR_RTIS | AMBA_UARTIIR_RIS |
- AMBA_UARTIIR_TIS));
-
- return IRQ_HANDLED;
-}
-
-static unsigned int ambauart_tx_empty(struct uart_port *port)
-{
- return UART_GET_FR(port) & AMBA_UARTFR_BUSY ? 0 : TIOCSER_TEMT;
-}
-
-static unsigned int ambauart_get_mctrl(struct uart_port *port)
-{
- unsigned int result = 0;
- unsigned int status;
-
- status = UART_GET_FR(port);
- if (status & AMBA_UARTFR_DCD)
- result |= TIOCM_CAR;
- if (status & AMBA_UARTFR_DSR)
- result |= TIOCM_DSR;
- if (status & AMBA_UARTFR_CTS)
- result |= TIOCM_CTS;
-
- return result;
-}
-
-static void ambauart_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int ctrls = 0, ctrlc = 0;
-
- if (mctrl & TIOCM_RTS)
- ctrlc |= uap->rts_mask;
- else
- ctrls |= uap->rts_mask;
-
- if (mctrl & TIOCM_DTR)
- ctrlc |= uap->dtr_mask;
- else
- ctrls |= uap->dtr_mask;
-
- __raw_writel(ctrls, SC_CTRLS);
- __raw_writel(ctrlc, SC_CTRLC);
-}
-
-static void ambauart_break_ctl(struct uart_port *port, int break_state)
-{
- unsigned long flags;
- unsigned int lcr_h;
-
- spin_lock_irqsave(&port->lock, flags);
- lcr_h = UART_GET_LCRH(port);
- if (break_state == -1)
- lcr_h |= AMBA_UARTLCR_H_BRK;
- else
- lcr_h &= ~AMBA_UARTLCR_H_BRK;
- UART_PUT_LCRH(port, lcr_h);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int ambauart_startup(struct uart_port *port)
-{
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- int retval;
-
- /*
- * Allocate the IRQ
- */
- retval = request_irq(port->irq, ambauart_int, 0, "amba", port);
- if (retval)
- return retval;
-
- /*
- * initialise the old status of the modem signals
- */
- uap->old_status = UART_GET_FR(port) & AMBA_UARTFR_MODEM_ANY;
-
- /*
- * Finally, enable interrupts
- */
- UART_PUT_CR(port, AMBA_UARTCR_UARTEN | AMBA_UARTCR_RIE |
- AMBA_UARTCR_RTIE);
-
- return 0;
-}
-
-static void ambauart_shutdown(struct uart_port *port)
-{
- /*
- * Free the interrupt
- */
- free_irq(port->irq, port);
-
- /*
- * disable all interrupts, disable the port
- */
- UART_PUT_CR(port, 0);
-
- /* disable break condition and fifos */
- UART_PUT_LCRH(port, UART_GET_LCRH(port) &
- ~(AMBA_UARTLCR_H_BRK | AMBA_UARTLCR_H_FEN));
-}
-
-static void
-ambauart_set_termios(struct uart_port *port, struct termios *termios,
- struct termios *old)
-{
- unsigned int lcr_h, old_cr;
- unsigned long flags;
- unsigned int baud, quot;
-
- /*
- * Ask the core to calculate the divisor for us.
- */
- baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
- quot = uart_get_divisor(port, baud);
-
- switch (termios->c_cflag & CSIZE) {
- case CS5:
- lcr_h = AMBA_UARTLCR_H_WLEN_5;
- break;
- case CS6:
- lcr_h = AMBA_UARTLCR_H_WLEN_6;
- break;
- case CS7:
- lcr_h = AMBA_UARTLCR_H_WLEN_7;
- break;
- default: // CS8
- lcr_h = AMBA_UARTLCR_H_WLEN_8;
- break;
- }
- if (termios->c_cflag & CSTOPB)
- lcr_h |= AMBA_UARTLCR_H_STP2;
- if (termios->c_cflag & PARENB) {
- lcr_h |= AMBA_UARTLCR_H_PEN;
- if (!(termios->c_cflag & PARODD))
- lcr_h |= AMBA_UARTLCR_H_EPS;
- }
- if (port->fifosize > 1)
- lcr_h |= AMBA_UARTLCR_H_FEN;
-
- spin_lock_irqsave(&port->lock, flags);
-
- /*
- * Update the per-port timeout.
- */
- uart_update_timeout(port, termios->c_cflag, baud);
-
- port->read_status_mask = AMBA_UARTRSR_OE;
- if (termios->c_iflag & INPCK)
- port->read_status_mask |= AMBA_UARTRSR_FE | AMBA_UARTRSR_PE;
- if (termios->c_iflag & (BRKINT | PARMRK))
- port->read_status_mask |= AMBA_UARTRSR_BE;
-
- /*
- * Characters to ignore
- */
- port->ignore_status_mask = 0;
- if (termios->c_iflag & IGNPAR)
- port->ignore_status_mask |= AMBA_UARTRSR_FE | AMBA_UARTRSR_PE;
- if (termios->c_iflag & IGNBRK) {
- port->ignore_status_mask |= AMBA_UARTRSR_BE;
- /*
- * If we're ignoring parity and break indicators,
- * ignore overruns too (for real raw support).
- */
- if (termios->c_iflag & IGNPAR)
- port->ignore_status_mask |= AMBA_UARTRSR_OE;
- }
-
- /*
- * Ignore all characters if CREAD is not set.
- */
- if ((termios->c_cflag & CREAD) == 0)
- port->ignore_status_mask |= UART_DUMMY_RSR_RX;
-
- /* first, disable everything */
- old_cr = UART_GET_CR(port) & ~AMBA_UARTCR_MSIE;
-
- if (UART_ENABLE_MS(port, termios->c_cflag))
- old_cr |= AMBA_UARTCR_MSIE;
-
- UART_PUT_CR(port, 0);
-
- /* Set baud rate */
- quot -= 1;
- UART_PUT_LCRM(port, ((quot & 0xf00) >> 8));
- UART_PUT_LCRL(port, (quot & 0xff));
-
- /*
- * ----------v----------v----------v----------v-----
- * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
- * ----------^----------^----------^----------^-----
- */
- UART_PUT_LCRH(port, lcr_h);
- UART_PUT_CR(port, old_cr);
-
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static const char *ambauart_type(struct uart_port *port)
-{
- return port->type == PORT_AMBA ? "AMBA" : NULL;
-}
-
-/*
- * Release the memory region(s) being used by 'port'
- */
-static void ambauart_release_port(struct uart_port *port)
-{
- release_mem_region(port->mapbase, UART_PORT_SIZE);
-}
-
-/*
- * Request the memory region(s) being used by 'port'
- */
-static int ambauart_request_port(struct uart_port *port)
-{
- return request_mem_region(port->mapbase, UART_PORT_SIZE, "serial_amba")
- != NULL ? 0 : -EBUSY;
-}
-
-/*
- * Configure/autoconfigure the port.
- */
-static void ambauart_config_port(struct uart_port *port, int flags)
-{
- if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_AMBA;
- ambauart_request_port(port);
- }
-}
-
-/*
- * verify the new serial_struct (for TIOCSSERIAL).
- */
-static int ambauart_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
- int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
- ret = -EINVAL;
- if (ser->irq < 0 || ser->irq >= NR_IRQS)
- ret = -EINVAL;
- if (ser->baud_base < 9600)
- ret = -EINVAL;
- return ret;
-}
-
-static struct uart_ops amba_pops = {
- .tx_empty = ambauart_tx_empty,
- .set_mctrl = ambauart_set_mctrl,
- .get_mctrl = ambauart_get_mctrl,
- .stop_tx = ambauart_stop_tx,
- .start_tx = ambauart_start_tx,
- .stop_rx = ambauart_stop_rx,
- .enable_ms = ambauart_enable_ms,
- .break_ctl = ambauart_break_ctl,
- .startup = ambauart_startup,
- .shutdown = ambauart_shutdown,
- .set_termios = ambauart_set_termios,
- .type = ambauart_type,
- .release_port = ambauart_release_port,
- .request_port = ambauart_request_port,
- .config_port = ambauart_config_port,
- .verify_port = ambauart_verify_port,
-};
-
-static struct uart_amba_port amba_ports[UART_NR] = {
- {
- .port = {
- .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
- .mapbase = INTEGRATOR_UART0_BASE,
- .iotype = SERIAL_IO_MEM,
- .irq = IRQ_UARTINT0,
- .uartclk = 14745600,
- .fifosize = 16,
- .ops = &amba_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
- .line = 0,
- },
- .dtr_mask = 1 << 5,
- .rts_mask = 1 << 4,
- },
- {
- .port = {
- .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
- .mapbase = INTEGRATOR_UART1_BASE,
- .iotype = SERIAL_IO_MEM,
- .irq = IRQ_UARTINT1,
- .uartclk = 14745600,
- .fifosize = 16,
- .ops = &amba_pops,
- .flags = ASYNC_BOOT_AUTOCONF,
- .line = 1,
- },
- .dtr_mask = 1 << 7,
- .rts_mask = 1 << 6,
- }
-};
-
-#ifdef CONFIG_SERIAL_AMBA_CONSOLE
-
-static void
-ambauart_console_write(struct console *co, const char *s, unsigned int count)
-{
- struct uart_port *port = &amba_ports[co->index].port;
- unsigned int status, old_cr;
- int i;
-
- /*
- * First save the CR then disable the interrupts
- */
- old_cr = UART_GET_CR(port);
- UART_PUT_CR(port, AMBA_UARTCR_UARTEN);
-
- /*
- * Now, do each character
- */
- for (i = 0; i < count; i++) {
- do {
- status = UART_GET_FR(port);
- } while (!UART_TX_READY(status));
- UART_PUT_CHAR(port, s[i]);
- if (s[i] == '\n') {
- do {
- status = UART_GET_FR(port);
- } while (!UART_TX_READY(status));
- UART_PUT_CHAR(port, '\r');
- }
- }
-
- /*
- * Finally, wait for transmitter to become empty
- * and restore the TCR
- */
- do {
- status = UART_GET_FR(port);
- } while (status & AMBA_UARTFR_BUSY);
- UART_PUT_CR(port, old_cr);
-}
-
-static void __init
-ambauart_console_get_options(struct uart_port *port, int *baud,
- int *parity, int *bits)
-{
- if (UART_GET_CR(port) & AMBA_UARTCR_UARTEN) {
- unsigned int lcr_h, quot;
- lcr_h = UART_GET_LCRH(port);
-
- *parity = 'n';
- if (lcr_h & AMBA_UARTLCR_H_PEN) {
- if (lcr_h & AMBA_UARTLCR_H_EPS)
- *parity = 'e';
- else
- *parity = 'o';
- }
-
- if ((lcr_h & 0x60) == AMBA_UARTLCR_H_WLEN_7)
- *bits = 7;
- else
- *bits = 8;
-
- quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8;
- *baud = port->uartclk / (16 * (quot + 1));
- }
-}
-
-static int __init ambauart_console_setup(struct console *co, char *options)
-{
- struct uart_port *port;
- int baud = 38400;
- int bits = 8;
- int parity = 'n';
- int flow = 'n';
-
- /*
- * Check whether an invalid uart number has been specified, and
- * if so, search for the first available port that does have
- * console support.
- */
- if (co->index >= UART_NR)
- co->index = 0;
- port = &amba_ports[co->index].port;
-
- if (options)
- uart_parse_options(options, &baud, &parity, &bits, &flow);
- else
- ambauart_console_get_options(port, &baud, &parity, &bits);
-
- return uart_set_options(port, co, baud, parity, bits, flow);
-}
-
-extern struct uart_driver amba_reg;
-static struct console amba_console = {
- .name = "ttyAM",
- .write = ambauart_console_write,
- .device = uart_console_device,
- .setup = ambauart_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = -1,
- .data = &amba_reg,
-};
-
-static int __init ambauart_console_init(void)
-{
- register_console(&amba_console);
- return 0;
-}
-console_initcall(ambauart_console_init);
-
-#define AMBA_CONSOLE &amba_console
-#else
-#define AMBA_CONSOLE NULL
-#endif
-
-static struct uart_driver amba_reg = {
- .owner = THIS_MODULE,
- .driver_name = "ttyAM",
- .dev_name = "ttyAM",
- .major = SERIAL_AMBA_MAJOR,
- .minor = SERIAL_AMBA_MINOR,
- .nr = UART_NR,
- .cons = AMBA_CONSOLE,
-};
-
-static int __init ambauart_init(void)
-{
- int ret;
-
- printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
-
- ret = uart_register_driver(&amba_reg);
- if (ret == 0) {
- int i;
-
- for (i = 0; i < UART_NR; i++)
- uart_add_one_port(&amba_reg, &amba_ports[i].port);
- }
- return ret;
-}
-
-static void __exit ambauart_exit(void)
-{
- int i;
-
- for (i = 0; i < UART_NR; i++)
- uart_remove_one_port(&amba_reg, &amba_ports[i].port);
-
- uart_unregister_driver(&amba_reg);
-}
-
-module_init(ambauart_init);
-module_exit(ambauart_exit);
-
-MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
-MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_CHARDEV(SERIAL_AMBA_MAJOR, SERIAL_AMBA_MINOR);
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/serial_amba.h
+ *
+ * Internal header file for AMBA serial ports
+ *
+ * Copyright (C) ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
+#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
+
+/* -------------------------------------------------------------------------------
+ * From AMBA UART (PL010) Block Specification
+ * -------------------------------------------------------------------------------
+ * UART Register Offsets.
+ */
+#define UART01x_DR 0x00 /* Data read or written from the interface. */
+#define UART01x_RSR 0x04 /* Receive status register (Read). */
+#define UART01x_ECR 0x04 /* Error clear register (Write). */
+#define UART010_LCRH 0x08 /* Line control register, high byte. */
+#define UART010_LCRM 0x0C /* Line control register, middle byte. */
+#define UART010_LCRL 0x10 /* Line control register, low byte. */
+#define UART010_CR 0x14 /* Control register. */
+#define UART01x_FR 0x18 /* Flag register (Read only). */
+#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
+#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
+#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
+#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
+#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
+#define UART011_LCRH 0x2c /* Line control register. */
+#define UART011_CR 0x30 /* Control register. */
+#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
+#define UART011_IMSC 0x38 /* Interrupt mask. */
+#define UART011_RIS 0x3c /* Raw interrupt status. */
+#define UART011_MIS 0x40 /* Masked interrupt status. */
+#define UART011_ICR 0x44 /* Interrupt clear register. */
+#define UART011_DMACR 0x48 /* DMA control register. */
+
+#define UART01x_RSR_OE 0x08
+#define UART01x_RSR_BE 0x04
+#define UART01x_RSR_PE 0x02
+#define UART01x_RSR_FE 0x01
+
+#define UART011_FR_RI 0x100
+#define UART011_FR_TXFE 0x080
+#define UART011_FR_RXFF 0x040
+#define UART01x_FR_TXFF 0x020
+#define UART01x_FR_RXFE 0x010
+#define UART01x_FR_BUSY 0x008
+#define UART01x_FR_DCD 0x004
+#define UART01x_FR_DSR 0x002
+#define UART01x_FR_CTS 0x001
+#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
+
+#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
+#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
+#define UART011_CR_OUT2 0x2000 /* OUT2 */
+#define UART011_CR_OUT1 0x1000 /* OUT1 */
+#define UART011_CR_RTS 0x0800 /* RTS */
+#define UART011_CR_DTR 0x0400 /* DTR */
+#define UART011_CR_RXE 0x0200 /* receive enable */
+#define UART011_CR_TXE 0x0100 /* transmit enable */
+#define UART011_CR_LBE 0x0080 /* loopback enable */
+#define UART010_CR_RTIE 0x0040
+#define UART010_CR_TIE 0x0020
+#define UART010_CR_RIE 0x0010
+#define UART010_CR_MSIE 0x0008
+#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
+#define UART01x_CR_SIREN 0x0002 /* SIR enable */
+#define UART01x_CR_UARTEN 0x0001 /* UART enable */
+
+#define UART011_LCRH_SPS 0x80
+#define UART01x_LCRH_WLEN_8 0x60
+#define UART01x_LCRH_WLEN_7 0x40
+#define UART01x_LCRH_WLEN_6 0x20
+#define UART01x_LCRH_WLEN_5 0x00
+#define UART01x_LCRH_FEN 0x10
+#define UART01x_LCRH_STP2 0x08
+#define UART01x_LCRH_EPS 0x04
+#define UART01x_LCRH_PEN 0x02
+#define UART01x_LCRH_BRK 0x01
+
+#define UART010_IIR_RTIS 0x08
+#define UART010_IIR_TIS 0x04
+#define UART010_IIR_RIS 0x02
+#define UART010_IIR_MIS 0x01
+
+#define UART011_IFLS_RX1_8 (0 << 3)
+#define UART011_IFLS_RX2_8 (1 << 3)
+#define UART011_IFLS_RX4_8 (2 << 3)
+#define UART011_IFLS_RX6_8 (3 << 3)
+#define UART011_IFLS_RX7_8 (4 << 3)
+#define UART011_IFLS_TX1_8 (0 << 0)
+#define UART011_IFLS_TX2_8 (1 << 0)
+#define UART011_IFLS_TX4_8 (2 << 0)
+#define UART011_IFLS_TX6_8 (3 << 0)
+#define UART011_IFLS_TX7_8 (4 << 0)
+
+#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
+#define UART011_BEIM (1 << 9) /* break error interrupt mask */
+#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
+#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
+#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
+#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
+#define UART011_RXIM (1 << 4) /* receive interrupt mask */
+#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
+#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
+#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
+#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
+
+#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
+#define UART011_BEIS (1 << 9) /* break error interrupt status */
+#define UART011_PEIS (1 << 8) /* parity error interrupt status */
+#define UART011_FEIS (1 << 7) /* framing error interrupt status */
+#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
+#define UART011_TXIS (1 << 5) /* transmit interrupt status */
+#define UART011_RXIS (1 << 4) /* receive interrupt status */
+#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
+#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
+#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
+#define UART011_RIMIS (1 << 0) /* RI interrupt status */
+
+#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
+#define UART011_BEIC (1 << 9) /* break error interrupt clear */
+#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
+#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
+#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
+#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
+#define UART011_RXIC (1 << 4) /* receive interrupt clear */
+#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
+#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
+#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
+#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
+
+#define UART011_DMAONERR (1 << 2) /* disable dma on error */
+#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
+#define UART011_RXDMAE (1 << 0) /* enable receive dma */
+
+#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
+#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
+
+#endif
+++ /dev/null
-/*
- * linux/include/asm-arm/hardware/serial_amba.h
- *
- * Internal header file for AMBA serial ports
- *
- * Copyright (C) ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
-#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
-
-/* -------------------------------------------------------------------------------
- * From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03)
- * -------------------------------------------------------------------------------
- * UART Register Offsets.
- */
-#define AMBA_UARTDR 0x00 /* Data read or written from the interface. */
-#define AMBA_UARTRSR 0x04 /* Receive status register (Read). */
-#define AMBA_UARTECR 0x04 /* Error clear register (Write). */
-#define AMBA_UARTLCR_H 0x08 /* Line control register, high byte. */
-#define AMBA_UARTLCR_M 0x0C /* Line control register, middle byte. */
-#define AMBA_UARTLCR_L 0x10 /* Line control register, low byte. */
-#define AMBA_UARTCR 0x14 /* Control register. */
-#define AMBA_UARTFR 0x18 /* Flag register (Read only). */
-#define AMBA_UARTIIR 0x1C /* Interrupt indentification register (Read). */
-#define AMBA_UARTICR 0x1C /* Interrupt clear register (Write). */
-#define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */
-
-#define AMBA_UARTRSR_OE 0x08
-#define AMBA_UARTRSR_BE 0x04
-#define AMBA_UARTRSR_PE 0x02
-#define AMBA_UARTRSR_FE 0x01
-
-#define AMBA_UARTFR_TXFF 0x20
-#define AMBA_UARTFR_RXFE 0x10
-#define AMBA_UARTFR_BUSY 0x08
-#define AMBA_UARTFR_DCD 0x04
-#define AMBA_UARTFR_DSR 0x02
-#define AMBA_UARTFR_CTS 0x01
-#define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)
-
-#define AMBA_UARTCR_RTIE 0x40
-#define AMBA_UARTCR_TIE 0x20
-#define AMBA_UARTCR_RIE 0x10
-#define AMBA_UARTCR_MSIE 0x08
-#define AMBA_UARTCR_IIRLP 0x04
-#define AMBA_UARTCR_SIREN 0x02
-#define AMBA_UARTCR_UARTEN 0x01
-
-#define AMBA_UARTLCR_H_WLEN_8 0x60
-#define AMBA_UARTLCR_H_WLEN_7 0x40
-#define AMBA_UARTLCR_H_WLEN_6 0x20
-#define AMBA_UARTLCR_H_WLEN_5 0x00
-#define AMBA_UARTLCR_H_FEN 0x10
-#define AMBA_UARTLCR_H_STP2 0x08
-#define AMBA_UARTLCR_H_EPS 0x04
-#define AMBA_UARTLCR_H_PEN 0x02
-#define AMBA_UARTLCR_H_BRK 0x01
-
-#define AMBA_UARTIIR_RTIS 0x08
-#define AMBA_UARTIIR_TIS 0x04
-#define AMBA_UARTIIR_RIS 0x02
-#define AMBA_UARTIIR_MIS 0x01
-
-#define ARM_BAUD_460800 1
-#define ARM_BAUD_230400 3
-#define ARM_BAUD_115200 7
-#define ARM_BAUD_57600 15
-#define ARM_BAUD_38400 23
-#define ARM_BAUD_19200 47
-#define ARM_BAUD_14400 63
-#define ARM_BAUD_9600 95
-#define ARM_BAUD_4800 191
-#define ARM_BAUD_2400 383
-#define ARM_BAUD_1200 767
-
-#define AMBA_UARTRSR_ANY (AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE)
-#define AMBA_UARTFR_MODEM_ANY (AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS)
-
-#endif
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