00-INDEX
- this file.
-ARM-README
- - information for using Linux on the ARM architecture.
BUG-HUNTING
- brute force method of doing binary search of patches to find bug.
Changes
- info on using the enhanced interrupt hardware on SMP boards.
IO-mapping.txt
- how to access I/O mapped memory from within device drivers.
-SMP.txt
- - notes, and "To Fix" list for multi-processor Linux. (see smp.tex)
+README.DAC960
+ - info on Mylex DAC960/DAC1100 PCI RAID Controller Driver for Linux
VGA-softcursor.txt
- how to change your VGA cursor from a blinking underscore.
+acpi.txt
+ - info on ACPI Driver Interface
arm/
- directory with info about Linux on the ARM architecture.
+atm.txt
+ - info on Linux ATM support
binfmt_misc.txt
- info on the kernel support for extra binary formats.
cdrom/
- directory with information on the CD-ROM drivers that Linux has.
+computone.txt
+ - info on Computone Intelliport II/Plus Multiport Serial Driver
cpqarray.txt
- info on using Compaq's SMART2 Intelligent Disk Array Controllers.
devices.tex
- how to use the RAM disk as an initial/temporary root filesystem.
ioctl-number.txt
- how to implement and register device/driver ioctl calls.
+isapnp.txt
+ - info on Linux ISA Plug & Play support
isdn/
- directory with info on the Linux ISDN support, and supported cards.
java.txt
- directory with info on various aspects of networking with Linux.
nfsroot.txt
- short guide on setting up a diskless box with NFS root filesystem
+nmi_watchdog.txt
+ - info on NMI watchdog for SMP systems
oops-tracing.txt
- how to decode those nasty internal kernel error dump messages.
paride.txt
- directory with info on using Linux with the PowerPC.
proc.txt
- detailed info on Linux's /proc filesystem.
+proc_usb_info.txt
+ - info on /proc/bus/usb direcory generated for USB devices
ramdisk.txt
- short guide on how to set up and use the RAM disk.
riscom8.txt
- directory with info on the /proc/sys/* files
sysrq.txt
- info on the magic SysRq key
-transname.txt
- - how to use name translation to ease use of diskless systems.
unicode.txt
- info on the Unicode character/font mapping used in Linux.
video4linux/
- directory with info regarding video/TV/radio cards and linux.
+vm/
+ - directory with info on the Linux vm code.
watchdog.txt
- how to auto-reboot Linux if it has "fallen and can't get up". ;-)
xterm-linux.xpm
===
Due to changes in the PPP driver and routing code, those of you
-using PPP networking will need to upgrade your pppd.
+using PPP networking will need to upgrade your pppd to at least
+version 2.3.9. See ftp://cs.anu.edu.au/pub/software/ppp/ for newest
+versions.
-See ftp://cs.anu.edu.au/pub/software/ppp/ for newest versions.
+ You must make sure that the special device file /dev/ppp exists.
+It can be made by executing this command as root:
+
+ mknod /dev/ppp c 108 0
+
+ If you have built ppp support as modules, you should put the lines
+below in your /etc/modules.conf file. I assume you want asynchronous
+ppp; replace ppp_async by ppp_synctty if you want synchronous ppp.
+
+ alias char-major-108 ppp_generic
+ alias tty-ldisc-3 ppp_async
iBCS
====
The safe and default value for this is N.
+SysKonnect SK-98xx support
+CONFIG_SK98LIN
+ Say Y here if you have a SysKonnect SK-98xx Gigabit Ethernet Server
+ Adapter. The following adapters are supported by this driver:
+ - SK-9841 (single link 1000Base-LX)
+ - SK-9842 (dual link 1000Base-LX)
+ - SK-9843 (single link 1000Base-SX)
+ - SK-9844 (dual link 1000Base-SX)
+ - SK-9821 (single link 1000Base-T)
+ - SK-9822 (dual link 1000Base-T)
+ The dual link adapters support a link-failover feature.
+ Read Documentation/networking/sk98lin.txt for information about
+ optional driver parameters.
+ Questions concerning this driver may be addresse to:
+ linux@syskonnect.de
+
+ If you want to compile this driver as a module ( = code which can be
+ inserted in and removed from the running kernel whenever you want),
+ say M here and read Documentation/modules.txt. This is recommended.
+ The module will be called sk98lin.o.
+
AMD LANCE and PCnet (AT1500 and NE2100) support
CONFIG_LANCE
If you have a network (Ethernet) card of this type, say Y and read
+++ /dev/null
-*NEWSFLASH*
-This kernel release needs a minor bug fix for pppd to run properly with
-the new routing code. When your pppd doesn't work apply the following
-patch to pppd-2.2.0f or update to the newest pppd version.
-
-Patch:
-
---- ppp-2.2.0f/pppd/sys-linux.c-o Wed Sep 17 00:23:01 1997
-+++ ppp-2.2.0f/pppd/sys-linux.c Wed Sep 17 00:23:11 1997
-@@ -927,8 +927,11 @@
-
- if (ioctl(sockfd, SIOCADDRT, &rt) < 0)
- {
-+/* The new linux routing code doesn't like routes on down devices. */
-+#if 0
- syslog (LOG_ERR, "ioctl(SIOCADDRT) device route: %m");
- return (0);
-+#endif
- }
- return 1;
- }
-
-
--Andi Kleen
---------------------------------------------------------------------
-
-The PPP support for this kernel requires the 2.2.0 version of the
-pppd daemon. You will find the current version of the daemon on
-sunsite.unc.edu in the /pub/Linux/system/Network/serial directory.
-
-Sunsite has many mirror sites. Please feel free to obtain it from
-a mirror site close to you.
-
-If you attempt to use a version of pppd which is not compatible
-then you will have some error condition. It usually is reflected
-in that an ioctl operation will generate a fatal error.
-
-Please do not use earlier versions of the 2.2 package. If you
-obtained a copy from merit.edu or bellatrix then please get an
-update from the sunsite site.
-
-The CCP (Compression Control Protocol) which is supported by this
-code is functional. You will need a compatible BSD compressor on
-your peer site to use the code.
-
-The BSD compression code will only build as a loadable module. There
-was an earlier version which would build it into the kernel but that
-functionality has been removed for various reasons.
-
---
-Al Longyear longyear@netcom.com
--- /dev/null
+(C)Copyright 1999 SysKonnect.
+===========================================================================
+
+sk98lin.txt created 11-Nov-1999
+
+Readme File for sk98lin.o v3.02
+SK-NET Gigabit Ethernet Adapter SK-98xx Driver for Linux
+
+This file contains
+(1) OVERVIEW
+(2) REQUIRED FILES
+(3) INSTALLATION
+(4) INCLUSION OF THE ADAPTER AT SYSTEM START
+(5) DRIVER PARAMETERS
+(6) LARGE FRAME SUPPORT
+(7) TROUBLESHOOTING
+(8) HISTORY
+
+===========================================================================
+
+
+
+(1) OVERVIEW
+============
+
+The sk98lin driver supports the SysKonnect SK-NET Gigabit Ethernet
+Adapter SK-98xx family on Linux 2.2.x.
+It has been tested with Linux on Intel/x86 and ALPHA machines.
+From v3.02 on, the driver is integrated in the linux kernel source.
+***
+
+
+(2) REQUIRED FILES
+==================
+
+The linux kernel source.
+No additional files required.
+***
+
+
+(3) INSTALLATION
+================
+
+The following steps describe the actions that are required to install
+the driver and to start it manually. These steps should be carried
+out for the initial driver setup. Once confirmed to be ok, they can
+be included in the system start which is described in the next
+chapter.
+
+NOTE 1: You must have 'root' access to the system to perform
+ the following tasks.
+NOTE 2: IMPORTANT: In case of problems, please read the section
+ "Troubleshooting" below.
+
+1) The driver can either be integrated into the kernel or it can
+ be compiled as a module.
+ Select the appropriate option during the kernel configuration.
+ For use as a module, your kernel must have
+ 'loadable module support' enabled.
+ For automatic driver start, you also need 'Kernel module loader'
+ enabled.
+ Configure those options, build and install the new kernel. If you
+ choose to use the driver as a module, do "make modules" and
+ "make modules_install".
+ Reboot your system.
+
+4) Load the module manually by entering:
+ insmod sk98lin.o
+ If the SysKonnect SK-98xx adapter is installed in your
+ computer and you have a /proc filesystem, running the command
+ 'more /proc/net/dev' should produce an output containing a
+ line with the following format:
+ eth0: 0 0 ...
+ which means that your adapter has been found and initialized.
+
+ NOTE 1: If you have more than one SysKonnect SK-98xx adapter, the
+ adapters will be listed as 'eth0', 'eth1', 'eth2', etc.
+ For each adapter, repeat the steps 5) and 6).
+ NOTE 2: If you have other Ethernet adapters installed,
+ your SysKonnect SK-98xx adapter can be mapped to 'eth1' or
+ 'eth2' ...
+ The module installation message (in system logfile or
+ on console, depending on /etc/syslog.conf) prints a line
+ for each adapter that is found, containing the
+ corresponding 'ethX'.
+
+5) Select an IP address and assign it to the respective adapter by
+ entering:
+ ifconfig eth0 <ip-address>
+ This causes the adapter to connect to the ethernet. The solitary
+ yellow LED at the adapter is now active, the link status LED of
+ the primary port is on and the link status LED of the secondary
+ port (on dual port adapters) is blinking (only if the laters are
+ connected to a switch or hub).
+ You will also get a status message on the console saying
+ "ethX: network connection up using port Y" and indicating
+ the selected connection parameters.
+
+ NOTE: If you are in doubt about IP addresses, ask your network
+ administrator for assistance.
+
+6) Your adapter should now be fully operational.
+ Use 'ping <otherstation>' to verify the connection to other
+ computers on your network.
+ By entering 'ifconfig', you can check the number of packets sent
+ and received by your adapter and additional some other information
+ regarding the adapter configuration.
+
+7) The driver module can be stopped and unloaded using the following
+ commands:
+ ifconfig eth0 down
+ rmmod sk98lin
+***
+
+
+(4) INCLUSION OF THE ADAPTER AT SYSTEM START
+============================================
+
+Since a large number of different Linux distributions are
+available, we are unable to describe a general installation procedure
+for the driver module.
+Because the driver is now integrated in the kernel, installation should
+be easy, using the standard mechanism of your distribution.
+Refer to the distribution's manual for installation of ethernet adapters.
+***
+
+
+(5) DRIVER PARAMETERS
+=====================
+
+Parameters can be set at the command line while loading the
+module with 'insmod'. The configuration tools of some distributions
+can also give parameters to the driver module.
+If you use the kernel module loader, you can set driver parameters
+in the file /etc/conf.modules. Insert a line of the form:
+
+options sk98lin ...
+
+For "...", use the same syntax as described below for the command
+line paramaters of insmod.
+You either have to reboot your computer or unload and reload
+the driver to activate the new parameters.
+The syntax of the driver parameters is:
+
+insmod sk98lin parameter=value1[,value2[,value3...]]
+
+value1 is for the first adapter, value2 for the second one etc.
+All Parameters are case sensitive, so write them exactly as
+shown below.
+
+Sample: Suppose you have two adapters. You want to set AutoNegotiation
+ on Port A of the first adapter to ON and on Port A of the
+ second adapter to OFF.
+ You also want to set DuplexCapabilities on Port A of the first
+ adapter to FULL and on Port A of the second adapter to HALF.
+ You must enter:
+
+ insmod sk98lin.o AutoNeg_A=On,Off DupCap_A=Full,Half
+
+NOTE: The number of adapters that can be configured this way is
+ limited in the driver (file skge.c, constant SK_MAX_CARD_PARAM).
+ The current limit is 16. If you happen to install
+ more adapters, adjust this and recompile.
+
+
+5.1 Per-Port Parameters
+-----------------------
+Those setting are available for each port on the adapter.
+In the following description, '?' stands for the port for
+which you set the parameter (A or B).
+
+- Auto Negotiation
+ Parameter: AutoNeg_?
+ Values: On, Off, Sense
+ Default: Sense
+
+ The "Sense"-mode finds out automatically whether the link
+ partner supports autonegotiation or not.
+
+- Duplex Capabilities
+ Parameter: DupCap_?
+ Values: Half, Full, Both
+ Default: Both
+
+ This parameters is relevant only if autonegotiation for
+ this port is not "Sense". If autonegotiation is "On", all
+ three values are possible. If it is "Off", only "Full" and
+ "Half" are allowed.
+ It is usefull if your link partner does not support all
+ possible combinations.
+
+- Flow Control
+ Parameter: FlowCtrl_?
+ Values: Sym, SymOrRem, LocSend, None
+ Default: SymOrRem
+
+ This parameter can be used to set the flow control capabilities
+ that the port reports during autonegotiation.
+ The meaning of the different modes is:
+-- Sym = Symetric: both link partners are allowed to send PAUSE frames
+-- SymOrRem = SymetricOrRemote: both or only remote partner are allowed
+ to send PAUSE frames
+-- LocSend = LocalSend: only local link partner is allowed to send
+ PAUSE frames
+-- None: no link partner is allowed to send PAUSE frames
+
+ NOTE: This parameter is ignored if autonegotiation is set to "Off".
+
+- Role in Master-Slave-Negotiation (1000Base-T only).
+ Parameter: Role_?
+ Values: Auto, Master, Slave
+ Default: Auto
+
+ This parameter is only valid for the SK-9821 and SK-9822 adapters.
+ For two 1000Base-T ports to communicate, one must take the role as
+ master (providing timing information), while the other must be slave.
+ Normally, this is negotiated between the two ports during link
+ establishment. If this should ever fail, you can force a port to a
+ specific setting with this parameter.
+
+
+5.2 Per-Adapter Parameters
+--------------------------
+
+- Preferred Port
+ Parameter: PrefPort
+ Values: A, B
+ Default: A
+
+ This is used to force the preferred port to A or B (on two-port NICs).
+ The preferred port is the one that is used if both are detected as
+ fully functional.
+
+- RLMT (Redundant Link Management Technology) Mode
+ Parameter: RlmtMode
+ Values: CheckLinkState,CheckLocalPort, CheckSeg
+ Default: CheckLinkState
+
+ RLMT (the driver part that decides which port to use) knows three
+ ways of checking if a port is available for use:
+
+-- CheckLinkState = Check link state only: RLMT uses the link state
+ reported by the adapter hardware for each individual port to determine
+ whether a port can be used for all network traffic or not.
+
+-- CheckLocalPort - Check other port on adapter: RLMT sends test frames
+ from each port to each other port and checks if they are received by
+ the other port, respectively. Thus, the ports must be connected to the
+ network such that LLC test frames can be exchanged between them
+ (i.e. there must be no routers between the ports).
+
+-- CheckSeg - Check other port and segmentation: RLMT checks the other port
+ and in addition requests information from the Gigabit Ethernet
+ switch next to each port to see if the network is segmented between
+ the ports. Thus, this mode is only to be used if you have Gigabit
+ Ethernet switches installed in your network that have been configured
+ to use the Spanning Tree protocol.
+
+ NOTE: The modes CheckLocalPort and CheckSeg are meant to operate in
+ configurations where a network path between the ports on one
+ adapter exists. Especially, they are not designed to work where
+ adapters are connected back-to-back.
+***
+
+
+(6) LARGE FRAME SUPPORT
+=======================
+
+Large frames (also called jumbo frames) are now supported by the
+driver. This can result in a greatly improved throughput if
+transfering large amounts of data.
+To enable large frames, set the MTU (maximum transfer unit)
+of the interface to the value you wish (up to 9000). The command
+for this is:
+ ifconfig eth0 mtu 9000
+This will only work if you have two adapters connected back-to-back
+or if you use a switch that supports large frames. When using a
+switch, it should be configured to allow large frames, without
+autonegotiating for them.
+The setting must be done on all adapters that can be reached by
+the large frames. If one adapter is not set to receive large frames,
+it will simply drop them.
+
+NOTE: If you look at the statistics (with netstat) in large frame
+ mode while there is traffic on the net, you will see the
+ RX error counter go up. This is because the adapter hardware
+ counts received large frames as errors, although they are
+ received correctly. So ignore this counter in that case.
+
+You can switch back to the standard ethernet frame size with:
+ ifconfig eth0 mtu 1500
+***
+
+
+(7) TROUBLESHOOTING
+===================
+
+If you run into problems during installation, check those items:
+
+Problem: The SK-98xx adapter can not be found by the driver.
+Reason: Look in /proc/pci for the following entry:
+ 'Ethernet controller: SysKonnect SK-98xx ...'
+ If this entry exists, then the SK-98xx adapter has been
+ found by the system and should be able to be used.
+ If this entry does not exist or if the file '/proc/pci'
+ is not there, then you may have a hardware problem or PCI
+ support may not be enabled in your kernel.
+ The adapter can be checked using the diagnostic program
+ which is available from the SysKonnect web site:
+ www.syskonnect.de
+ Some COMPAQ machines have a problem with PCI under
+ Linux. This is described in the 'PCI howto' document
+ (included in some distributions or available from the
+ www, e.g. at 'www.linux.org'). This might be fixed in the
+ 2.2.x kernel series (I've not tested it).
+
+Problem: Programs such as 'ifconfig' or 'route' can not be found or
+ you get an error message 'Operation not permitted'.
+Reason: You are not logged in as user 'root'. Logout and
+ login as root or change to root via 'su'.
+
+Problem: Using the command 'ping <address>', you get a message
+ "ping: sendto: Network is unreachable".
+Reason: Your route is not set up correct.
+ If you are using RedHat, you probably forgot
+ to set up the route in 'network configuration'.
+ Check the existing routes with the 'route' command
+ and check if there is an entry for 'eth0' and if
+ it is correct.
+
+Problem: The driver can be started, the adapter is connected
+ to the network, but you can not receive or transmit
+ any packet; e.g. 'ping' does not work.
+Reason: You have an incorrect route in your routing table.
+ Check the routing table with the command 'route' and
+ read the manual pages about route ('man route').
+NOTE: Although the 2.2.x kernel versions generate the routing
+ entry automatically, you may have problems of this kind
+ here, too. We found a case where the driver started correct
+ at system boot, but after removing and reloading the driver,
+ the route of the adapter's network pointed to the 'dummy0'
+ device and had to be corrected manually.
+
+Problem: You want to use your computer as a router between
+ multiple IP subnetworks (using multiple adapters), but
+ you can not reach computers in other subnetworks.
+Reason: Either the router's kernel is not configured for IP
+ forwarding or there is a problem with the routing table
+ and gateway configuration in at least one of the
+ computers.
+
+Problem: At the start of the driver, you get an error message:
+ "eth0: -- ERROR --
+ Class: internal Software error
+ Nr: 0xcc
+ Msg: SkGeInitPort() cannot init running ports"
+Reason: You are using a driver compiled for single processor
+ machines on an multiprocessor machine with SMP (Symetric
+ MultiProcessor) kernel.
+ Configure your kernel appropriate and recompile the kernel or
+ the modules.
+
+If your problem is not listed here, please contact SysKonnect's technical
+support for help (linux@syskonnect.de).
+When contacting our technical support, please ensure that the
+following information is available:
+- System Manufacturer and Model
+- Boards in your system
+- Distribution
+- Kernel version
+***
+
+
+(8) HISTORY
+===========
+
+VERSION 3.02
+Problems fixed:
+- None
+New Features:
+- Integration in linux kernel source.
+Known limitations:
+- None
+
+VERSION 3.02
+Problems fixed:
+- None
+New Features:
+- Full source release
+Known limitations:
+- None
+
+VERSION 3.00
+Problems fixed:
+- None
+New Features:
+- Support for 1000Base-T adapters (SK-9821 and SK-9822)
+Known limitations:
+- None
+
+VERSION 1.07
+Problems fixed:
+- RlmtMode parameter value strings were wrong (#10437)
+- Driver sent too many RLMT frames (#10439)
+- Driver did not recognize network segmentation (#10440)
+- RLMT switched too often on segmented network (#10441)
+Known limitations:
+- None
+
+VERSION 1.06
+Problems fixed:
+- System panic'ed after some time when running with
+ RlmtMode=CheckOtherLink or RlmtMode=CheckSeg (#10421)
+ Panic message: "Kernel panic: skput: over ... dev: eth0"
+- Driver did not switch back to default port when connected
+ back-to-back (#10422).
+Changes:
+- RlmtMode parameter names have changed
+New features:
+- There is now a version for ALPHA processors
+Known limitations:
+- None
+
+VERSION 1.05
+Problems fixed:
+- Driver failed to load on kernels with version information
+ for module symbols enabled
+Known limitations:
+- None
+
+VERSION 1.04
+Problems fixed:
+- Large frame support does work now (no autonegotiation
+ support for large frames, just manually selectable)
+New Features:
+- Receive checksumming in hardware
+- Performance optimizations
+ Some numbers (on two PII-400 machines, back-to-back):
+ netpipe: 300 MBit/sec, with large frames: 470 MBit/sec
+ ttcp: 38 MByte/sec, with large frames: 60 MByte/sec
+ ttcp (UDP send): 66 MByte/sec, with large frames: 106 MByte/sec
+Known limitations:
+- None
+
+VERSION 1.03
+Problems fixed:
+- Unloading with "rmmod" caused segmentation fault (#10415)
+- The link LED flickered from time to time, if no link was
+ established (#10402)
+- Installation problems with RedHat 6.0 (#10409)
+New Features:
+- Connection state ouput at "network connection up"
+Known limitations:
+- None
+
+VERSION 1.02
+Problems fixed:
+- Failed with multiple adapters
+- Failed with Single Port adapters
+- Startup string was only displayed if adapter found
+- No link could be established on certain switches when the switches were
+ rebooted. (#10377)
+Known limitations:
+- Segmentation fault at "rmmod" with kernel 2.2.3 on some machines
+
+VERSION 1.01
+Problems fixed:
+- Sensor status was not set back to 'ok' after 'warning/error'. (#10386)
+Changes:
+- improved parallelism in driver
+
+VERSION 1.00
+Known limitations:
+- not tested with all kernel versions (I don't have that much time :-)
+- only x86 version available (if you need others, ask for it)
+- source code not completely available
+
+***End of Readme File***
+
+
ADVANSYS SCSI DRIVER
P: Bob Frey
-M: Bob Frey <bobf@advansys.com>
+M: linux@advansys.com
W: http://www.advansys.com/linux.html
L: linux-scsi@vger.rutgers.edu
S: Maintained
if [ -f VIDEO_MODULES ]; then inst_mod VIDEO_MODULES video; fi; \
if [ -f FC4_MODULES ]; then inst_mod FC4_MODULES fc4; fi; \
if [ -f IRDA_MODULES ]; then inst_mod IRDA_MODULES net; fi; \
+ if [ -f SK98LIN_MODULES ]; then inst_mod SK98LIN_MODULES net; fi; \
if [ -f USB_MODULES ]; then inst_mod USB_MODULES usb; fi; \
if [ -f PCMCIA_MODULES ]; then inst_mod PCMCIA_MODULES pcmcia; fi; \
if [ -f PCMCIA_NET_MODULES ]; then inst_mod PCMCIA_NET_MODULES pcmcia; fi; \
load(START_ADDR+(4*KERNEL_SIZE), KERNEL_ORIGIN, KERNEL_SIZE);
load(START_ADDR, START_ADDR+(4*KERNEL_SIZE), KERNEL_SIZE);
- memset((char*)ZERO_PAGE(0), 0, PAGE_SIZE);
- strcpy((char*)ZERO_PAGE(0), envval);
+ memset((char*)ZERO_PGE, 0, PAGE_SIZE);
+ strcpy((char*)ZERO_PGE, envval);
#ifdef INITRD_SIZE
- ((long *)(ZERO_PAGE(0)+256))[0] = initrd_start;
- ((long *)(ZERO_PAGE(0)+256))[1] = INITRD_SIZE;
+ ((long *)(ZERO_PGE+256))[0] = initrd_start;
+ ((long *)(ZERO_PGE+256))[1] = INITRD_SIZE;
#endif
runkernel();
nbytes = 0;
}
envval[nbytes] = '\0';
- strcpy((char*)ZERO_PAGE(0), envval);
+ strcpy((char*)ZERO_PGE, envval);
srm_printk(" Ok\nNow booting the kernel\n");
runkernel();
#include <asm/fpu.h>
#include <asm/irq.h>
#include <asm/machvec.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/semaphore.h>
#define __KERNEL_SYSCALLS__
};
\f
void __init
-apecs_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+apecs_init_arch(void)
{
struct pci_controler *hose;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = APECS_CONF;
};
\f
void __init
-cia_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+cia_init_arch(void)
{
struct pci_controler *hose;
struct resource *hae_mem;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
- hae_mem = alloc_resource(mem_start);
+ hose = alloc_pci_controler();
+ hae_mem = alloc_resource();
hose->io_space = &ioport_resource;
hose->mem_space = hae_mem;
};
\f
void __init
-lca_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+lca_init_arch(void)
{
struct pci_controler *hose;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = LCA_CONF;
static int
mcpcia_read_config_byte(struct pci_dev *dev, int where, u8 *value)
{
- struct pci_controler *hose = dev->sysdata ? : probing_hose;
+ struct pci_controler *hose = dev->sysdata;
unsigned long addr, w;
unsigned char type1;
static int
mcpcia_read_config_word(struct pci_dev *dev, int where, u16 *value)
{
- struct pci_controler *hose = dev->sysdata ? : probing_hose;
+ struct pci_controler *hose = dev->sysdata;
unsigned long addr, w;
unsigned char type1;
static int
mcpcia_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
- struct pci_controler *hose = dev->sysdata ? : probing_hose;
+ struct pci_controler *hose = dev->sysdata;
unsigned long addr;
unsigned char type1;
static int
mcpcia_write_config(struct pci_dev *dev, int where, u32 value, long mask)
{
- struct pci_controler *hose = dev->sysdata ? : probing_hose;
+ struct pci_controler *hose = dev->sysdata;
unsigned long addr;
unsigned char type1;
}
static void __init
-mcpcia_new_hose(unsigned long *mem_start, int h)
+mcpcia_new_hose(int h)
{
struct pci_controler *hose;
struct resource *io, *mem, *hae_mem;
int mid = hose2mid(h);
- hose = alloc_pci_controler(mem_start);
- io = alloc_resource(mem_start);
- mem = alloc_resource(mem_start);
- hae_mem = alloc_resource(mem_start);
+ hose = alloc_pci_controler();
+ io = alloc_resource();
+ mem = alloc_resource();
+ hae_mem = alloc_resource();
hose->io_space = io;
hose->mem_space = hae_mem;
}
void __init
-mcpcia_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+mcpcia_init_arch(void)
{
extern asmlinkage void entInt(void);
struct pci_controler *hose;
/* First, find how many hoses we have. */
for (h = 0; h < MCPCIA_MAX_HOSES; ++h) {
if (mcpcia_probe_hose(h)) {
- mcpcia_new_hose(mem_start, h);
+ mcpcia_new_hose(h);
hose_count++;
}
}
};
\f
void __init
-polaris_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+polaris_init_arch(void)
{
struct pci_controler *hose;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = POLARIS_DENSE_CONFIG_BASE;
};
\f
void __init
-pyxis_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+pyxis_init_arch(void)
{
struct pci_controler *hose;
unsigned int temp;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = PYXIS_CONF;
};
\f
void __init
-t2_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+t2_init_arch(void)
{
struct pci_controler *hose;
unsigned int i;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = T2_CONF;
mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
unsigned char *type1)
{
- struct pci_controler *hose = dev->sysdata ? : probing_hose;
+ struct pci_controler *hose = dev->sysdata;
unsigned long addr;
u8 bus = dev->bus->number;
u8 device_fn = dev->devfn;
return PCIBIOS_DEVICE_NOT_FOUND;
__kernel_stb(value, *(vucp)addr);
+ mb();
return PCIBIOS_SUCCESSFUL;
}
return PCIBIOS_DEVICE_NOT_FOUND;
__kernel_stw(value, *(vusp)addr);
+ mb();
return PCIBIOS_SUCCESSFUL;
}
return PCIBIOS_DEVICE_NOT_FOUND;
*(vuip)addr = value;
+ mb();
return PCIBIOS_SUCCESSFUL;
}
#define FN __FUNCTION__
static void __init
-tsunami_init_one_pchip(tsunami_pchip *pchip, int index,
- unsigned long *mem_start)
+tsunami_init_one_pchip(tsunami_pchip *pchip, int index)
{
struct pci_controler *hose;
if (tsunami_probe_read(&pchip->pctl.csr) == 0)
return;
- hose = alloc_pci_controler(mem_start);
- hose->io_space = alloc_resource(mem_start);
- hose->mem_space = alloc_resource(mem_start);
+ hose = alloc_pci_controler();
+ hose->io_space = alloc_resource();
+ hose->mem_space = alloc_resource();
hose->config_space = TSUNAMI_CONF(index);
hose->index = index;
hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
- hose->io_space->end = hose->io_space->start + 0xffff;
+ hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE;
hose->io_space->name = pci_io_names[index];
+ hose->io_space->flags = IORESOURCE_IO;
hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
+ /* the IOMEM address space is larger than 32bit but most pci
+ cars doesn't support 64bit address space so we stick with
+ 32bit here (see the TSUNAMI_MEM_SPACE define). */
hose->mem_space->end = hose->mem_space->start + 0xffffffff;
hose->mem_space->name = pci_mem_names[index];
+ hose->mem_space->flags = IORESOURCE_MEM;
- request_resource(&ioport_resource, hose->io_space);
- request_resource(&iomem_resource, hose->mem_space);
+ if (request_resource(&ioport_resource, hose->io_space) < 0)
+ printk(KERN_ERR "failed to request IO on hose %d", index);
+ if (request_resource(&iomem_resource, hose->mem_space) < 0)
+ printk(KERN_ERR "failed to request IOMEM on hose %d", index);
/*
* Set up the PCI->physical memory translation windows.
}
void __init
-tsunami_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+tsunami_init_arch(void)
{
#ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
extern asmlinkage void entInt(void);
/* Find how many hoses we have, and initialize them. TSUNAMI
and TYPHOON can have 2, but might only have 1 (DS10). */
- tsunami_init_one_pchip(TSUNAMI_pchip0, 0, mem_start);
+ tsunami_init_one_pchip(TSUNAMI_pchip0, 0);
if (TSUNAMI_cchip->csc.csr & 1L<<14)
- tsunami_init_one_pchip(TSUNAMI_pchip1, 1, mem_start);
+ tsunami_init_one_pchip(TSUNAMI_pchip1, 1);
}
static inline void
*/
#include <linux/config.h>
+#include <asm/pgalloc.h>
/* Whee. Both TSUNAMI and POLARIS don't have an HAE. Fix things up for
the GENERIC kernel by defining the HAE address to be that of the cache.
* David Mosberger (davidm@cs.arizona.edu)
*/
+/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
+
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/bootmem.h>
#include <asm/machvec.h>
#include "proto.h"
*/
struct pci_controler *hose_head, **hose_tail = &hose_head;
-struct pci_controler *probing_hose;
/*
* Quirks.
{ 0 }
};
+#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
+#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
+#define KB 1024
+#define MB (1024*KB)
+#define GB (1024*MB)
+unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
+ unsigned long start, unsigned long size)
+{
+ unsigned long alignto;
+
+ if (res->flags & IORESOURCE_IO)
+ {
+ /*
+ * Aligning to 0x800 rather than the minimum base of
+ * 0x400 is an attempt to avoid having devices in
+ * any 0x?C?? range, which is where the de4x5 driver
+ * probes for EISA cards.
+ *
+ * Adaptecs, especially, resent such intrusions.
+ */
+ alignto = MAX(0x800, size);
+ start = ALIGN(start, alignto);
+ }
+ else if (res->flags & IORESOURCE_MEM)
+ {
+ /*
+ * The following holds at least for the Low Cost
+ * Alpha implementation of the PCI interface:
+ *
+ * In sparse memory address space, the first
+ * octant (16MB) of every 128MB segment is
+ * aliased to the very first 16 MB of the
+ * address space (i.e., it aliases the ISA
+ * memory address space). Thus, we try to
+ * avoid allocating PCI devices in that range.
+ * Can be allocated in 2nd-7th octant only.
+ * Devices that need more than 112MB of
+ * address space must be accessed through
+ * dense memory space only!
+ */
+ /* align to multiple of size of minimum base */
+ alignto = MAX(0x1000, size);
+ start = ALIGN(start, alignto);
+ if (size > 7 * 16*MB)
+ printk(KERN_WARNING "PCI: dev %s "
+ "requests %ld bytes of contiguous "
+ "address space---don't use sparse "
+ "memory accesses on this device!\n",
+ dev->name, size);
+ else
+ {
+ if (((start / (16*MB)) & 0x7) == 0) {
+ start &= ~(128*MB - 1);
+ start += 16*MB;
+ start = ALIGN(start, alignto);
+ }
+ if (start/(128*MB) != (start + size)/(128*MB)) {
+ start &= ~(128*MB - 1);
+ start += (128 + 16)*MB;
+ start = ALIGN(start, alignto);
+ }
+ }
+ }
+
+ return start;
+}
+#undef MAX
+#undef ALIGN
+#undef KB
+#undef MB
+#undef GB
/*
* Pre-layout host-independant device initialization.
*/
static void __init
-pcibios_assign_special(void)
+pcibios_assign_special(struct pci_dev * dev)
{
- struct pci_dev *dev;
- int i;
-
/* The first three resources of an IDE controler are often magic,
so leave them unchanged. This is true, for instance, of the
Contaq 82C693 as seen on SX164 and DP264. */
- for (dev = pci_devices; dev; dev = dev->next) {
- if (dev->class >> 8 != PCI_CLASS_STORAGE_IDE)
- continue;
+ if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE)
+ {
+ int i;
+
/* Resource 1 of IDE controller is the address of HD_CMD
register which actually occupies a single byte (0x3f6
for ide0) in reported 0x3f4-3f7 range. We have to fix
controller. */
dev->resource[1].start += 2;
dev->resource[1].end = dev->resource[1].start;
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- if (dev->resource[i].flags)
+ for (i = 0; i < PCI_NUM_RESOURCES; i++)
+ if (dev->resource[i].flags && dev->resource[i].start)
pci_claim_resource(dev, i);
- }
}
}
return str;
}
+void __init
+pcibios_fixup_resource(struct resource *res, struct resource *root)
+{
+ res->start += root->start;
+ res->end += root->start;
+}
+
+void __init
+pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
+{
+ /* Update device resources. */
+
+ int i;
+
+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+ if (!dev->resource[i].start)
+ continue;
+ if (dev->resource[i].flags & IORESOURCE_IO)
+ pcibios_fixup_resource(&dev->resource[i],
+ bus->resource[0]);
+ else if (dev->resource[i].flags & IORESOURCE_MEM)
+ pcibios_fixup_resource(&dev->resource[i],
+ bus->resource[1]);
+ }
+ pcibios_assign_special(dev);
+}
+
void __init
pcibios_fixup_bus(struct pci_bus *bus)
{
/* Propogate hose info into the subordinate devices. */
- struct pci_controler *hose = probing_hose;
+ struct pci_controler *hose = (struct pci_controler *) bus->sysdata;
struct pci_dev *dev;
bus->resource[0] = hose->io_space;
bus->resource[1] = hose->mem_space;
for (dev = bus->devices; dev; dev = dev->sibling)
- dev->sysdata = hose;
+ if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
+ pcibios_fixup_device_resources(dev, bus);
}
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
- unsigned long where, size;
- u32 reg;
-
- where = PCI_BASE_ADDRESS_0 + (resource * 4);
- size = res->end - res->start;
- pci_read_config_dword(dev, where, ®);
- reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
- pci_write_config_dword(dev, where, reg);
+ int where;
+ u32 reg;
+
+ where = PCI_BASE_ADDRESS_0 + (resource * 4);
+ reg = (res->start - root->start) | (res->flags & 0xf);
+ pci_write_config_dword(dev, where, reg);
+ if ((res->flags & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
+ == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64))
+ {
+ pci_write_config_dword(dev, where+4, 0);
+ printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name);
+ }
/* ??? FIXME -- record old value for shutdown. */
}
return PCI_SLOT(dev->devfn);
}
+void __init
+pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
+{
+ ranges->io_start -= bus->resource[0]->start;
+ ranges->io_end -= bus->resource[0]->start;
+ ranges->mem_start -= bus->resource[1]->start;
+ ranges->mem_end -= bus->resource[1]->start;
+}
+
void __init
common_init_pci(void)
{
for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
hose->first_busno = next_busno;
hose->last_busno = 0xff;
- probing_hose = hose;
bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
hose->bus = bus;
next_busno = hose->last_busno = bus->subordinate;
next_busno += 1;
}
- probing_hose = NULL;
- pcibios_assign_special();
pci_assign_unassigned_resources(alpha_mv.min_io_address,
alpha_mv.min_mem_address);
pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
struct pci_controler * __init
-alloc_pci_controler(unsigned long *mem_start)
+alloc_pci_controler(void)
{
- unsigned long start = *mem_start;
struct pci_controler *hose;
- if (start & 31)
- start = (start | 31) + 1;
- hose = (void *) start;
- start = (unsigned long) (hose + 1);
- *mem_start = start;
- memset(hose, 0, sizeof(*hose));
+ hose = alloc_bootmem(sizeof(*hose));
*hose_tail = hose;
hose_tail = &hose->next;
}
struct resource * __init
-alloc_resource(unsigned long *mem_start)
+alloc_resource(void)
{
- unsigned long start = *mem_start;
struct resource *res;
- if (start & 31)
- start = (start | 31) + 1;
- res = (void *) start;
- start = (unsigned long) (res + 1);
- *mem_start = start;
- memset(res, 0, sizeof(*res));
+ res = alloc_bootmem(sizeof(*res));
return res;
}
/* The hose list. */
extern struct pci_controler *hose_head, **hose_tail;
-extern struct pci_controler *probing_hose;
extern void common_init_pci(void);
extern u8 common_swizzle(struct pci_dev *, u8 *);
-extern struct pci_controler *alloc_pci_controler(unsigned long *);
-extern struct resource *alloc_resource(unsigned long *);
+extern struct pci_controler *alloc_pci_controler(void);
+extern struct resource *alloc_resource(void);
extern const char *const pci_io_names[];
extern const char *const pci_mem_names[];
/* core_apecs.c */
extern struct pci_ops apecs_pci_ops;
-extern void apecs_init_arch(unsigned long *, unsigned long *);
+extern void apecs_init_arch(void);
extern void apecs_pci_clr_err(void);
extern void apecs_machine_check(u64, u64, struct pt_regs *);
/* core_cia.c */
extern struct pci_ops cia_pci_ops;
-extern void cia_init_arch(unsigned long *, unsigned long *);
+extern void cia_init_arch(void);
extern void cia_machine_check(u64, u64, struct pt_regs *);
/* core_lca.c */
extern struct pci_ops lca_pci_ops;
-extern void lca_init_arch(unsigned long *, unsigned long *);
+extern void lca_init_arch(void);
extern void lca_machine_check(u64, u64, struct pt_regs *);
/* core_mcpcia.c */
extern struct pci_ops mcpcia_pci_ops;
-extern void mcpcia_init_arch(unsigned long *, unsigned long *);
+extern void mcpcia_init_arch(void);
extern void mcpcia_machine_check(u64, u64, struct pt_regs *);
/* core_polaris.c */
extern struct pci_ops polaris_pci_ops;
-extern void polaris_init_arch(unsigned long *, unsigned long *);
+extern void polaris_init_arch(void);
extern void polaris_machine_check(u64, u64, struct pt_regs *);
/* core_pyxis.c */
extern struct pci_ops pyxis_pci_ops;
-extern void pyxis_init_arch(unsigned long *, unsigned long *);
+extern void pyxis_init_arch(void);
extern void pyxis_machine_check(u64, u64, struct pt_regs *);
/* core_t2.c */
extern struct pci_ops t2_pci_ops;
-extern void t2_init_arch(unsigned long *, unsigned long *);
+extern void t2_init_arch(void);
extern void t2_machine_check(u64, u64, struct pt_regs *);
/* core_tsunami.c */
extern struct pci_ops tsunami_pci_ops;
-extern void tsunami_init_arch(unsigned long *, unsigned long *);
+extern void tsunami_init_arch(void);
extern void tsunami_machine_check(u64, u64, struct pt_regs *);
/* setup.c */
* Copyright (C) 1995 Linus Torvalds
*/
+/* 2.3.x bootmem, 1999 Andrea Arcangeli <andrea@suse.de> */
+
/*
* Bootup setup stuff.
*/
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ioport.h>
+#include <linux/bootmem.h>
#ifdef CONFIG_RTC
#include <linux/timex.h>
#include <asm/hwrpb.h>
#include <asm/dma.h>
#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/mmu_context.h>
#include "proto.h"
#include "pci_impl.h"
#define N(a) (sizeof(a)/sizeof(a[0]))
-static unsigned long find_end_memory(void);
static struct alpha_machine_vector *get_sysvec(long, long, long);
static struct alpha_machine_vector *get_sysvec_byname(const char *);
static void get_sysnames(long, long, char **, char **);
* initialized, we need to copy things out into a more permanent
* place.
*/
-#define PARAM ZERO_PAGE(0)
+#define PARAM ZERO_PGE
#define COMMAND_LINE ((char*)(PARAM + 0x0000))
#define COMMAND_LINE_SIZE 256
#define INITRD_START (*(unsigned long *) (PARAM+0x100))
request_resource(io, standard_io_resources+i);
}
-void __init
-setup_arch(char **cmdline_p, unsigned long * memory_start_p,
- unsigned long * memory_end_p)
+#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
+#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
+#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
+#define PFN_MAX PFN_DOWN(0x80000000)
+static void __init setup_memory(void)
{
+ struct memclust_struct * cluster;
+ struct memdesc_struct * memdesc;
+ unsigned long start_pfn, bootmap_size;
extern char _end[];
+ int i;
+
+ /* alloc the bootmem after the kernel */
+ start_pfn = PFN_UP(virt_to_phys(_end));
+ SRM_printf("_end %p\n", _end);
+
+ /* find free clusters, and init and free the bootmem accordingly */
+ memdesc = (struct memdesc_struct *) (hwrpb->mddt_offset + (unsigned long) hwrpb);
+
+ for (cluster = memdesc->cluster, i = memdesc->numclusters;
+ i > 0; i--, cluster++)
+ {
+ unsigned long end;
+
+ printk("memcluster %d, usage %02lx, start %8lu, end %8lu\n",
+ i, cluster->usage, cluster->start_pfn,
+ cluster->numpages);
+
+ /* Bit 0 is console/PALcode reserved. Bit 1 is
+ non-volatile memory -- we might want to mark
+ this for later */
+ if (cluster->usage & 3)
+ continue;
+
+ end = cluster->start_pfn + cluster->numpages;
+ if (end > max_low_pfn)
+ max_low_pfn = end;
+ }
+ /* Enforce maximum of 2GB even if there is more. Blah. */
+ if (max_low_pfn > PFN_MAX)
+ max_low_pfn = PFN_MAX;
+ SRM_printf("max_low_pfn %d\n", max_low_pfn);
+
+ /* allocate the bootmem array after the kernel and mark
+ the whole MM as reserved */
+ bootmap_size = init_bootmem(start_pfn, max_low_pfn);
+
+ for (cluster = memdesc->cluster, i = memdesc->numclusters;
+ i > 0; i--, cluster++)
+ {
+ unsigned long end, start;
+ /* Bit 0 is console/PALcode reserved. Bit 1 is
+ non-volatile memory -- we might want to mark
+ this for later */
+ if (cluster->usage & 3)
+ continue;
+
+ start = PFN_PHYS(cluster->start_pfn);
+ if (start < PFN_PHYS(start_pfn) + bootmap_size)
+ start = PFN_PHYS(start_pfn) + bootmap_size;
+ if (PFN_DOWN(start) >= PFN_MAX)
+ continue;
+
+ end = PFN_PHYS(cluster->start_pfn + cluster->numpages);
+ if (PFN_DOWN(end) > PFN_MAX)
+ end = PFN_PHYS(PFN_MAX);
+
+ if (start >= end)
+ continue;
+ free_bootmem(start, end-start);
+ }
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ initrd_start = INITRD_START;
+ if (initrd_start) {
+ initrd_end = initrd_start+INITRD_SIZE;
+ printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
+ (void *) initrd_start, INITRD_SIZE);
+
+ if (initrd_end > phys_to_virt(PFN_PHYS(max_low_pfn))) {
+ printk("initrd extends beyond end of memory "
+ "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
+ initrd_end, phys_to_virt(PFN_PHYS(max_low_pfn)));
+ initrd_start = initrd_end = 0;
+ }
+ else
+ reserve_bootmem(virt_to_phys(initrd_start), INITRD_SIZE);
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+}
+#undef PFN_UP
+#undef PFN_DOWN
+#undef PFN_PHYS
+#undef PFN_MAX
+
+void __init
+setup_arch(char **cmdline_p)
+{
struct alpha_machine_vector *vec = NULL;
struct percpu_struct *cpu;
char *type_name, *var_name, *p;
alpha_using_srm = strncmp((const char *)hwrpb->ssn, "MILO", 4) != 0;
#endif
+ SRM_printf("Booting on %s%s%s using machine vector %s\n",
+ type_name, (*var_name ? " variation " : ""),
+ var_name, alpha_mv.vector_name);
+
printk("Booting "
#ifdef CONFIG_ALPHA_GENERIC
"GENERIC "
wrmces(0x7);
/* Find our memory. */
- *memory_end_p = find_end_memory();
- *memory_start_p = (unsigned long) _end;
-
-#ifdef CONFIG_BLK_DEV_INITRD
- initrd_start = INITRD_START;
- if (initrd_start) {
- initrd_end = initrd_start+INITRD_SIZE;
- printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
- (void *) initrd_start, INITRD_SIZE);
-
- if (initrd_end > *memory_end_p) {
- printk("initrd extends beyond end of memory "
- "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
- initrd_end, (unsigned long) memory_end_p);
- initrd_start = initrd_end = 0;
- }
- }
-#endif
+ setup_memory();
/* Initialize the machine. Usually has to do with setting up
DMA windows and the like. */
if (alpha_mv.init_arch)
- alpha_mv.init_arch(memory_start_p, memory_end_p);
+ alpha_mv.init_arch();
/* Reserve standard resources. */
reserve_std_resources();
#endif
}
-static unsigned long __init
-find_end_memory(void)
-{
- int i;
- unsigned long high = 0;
- struct memclust_struct * cluster;
- struct memdesc_struct * memdesc;
-
- memdesc = (struct memdesc_struct *)
- (INIT_HWRPB->mddt_offset + (unsigned long) INIT_HWRPB);
- cluster = memdesc->cluster;
-
- for (i = memdesc->numclusters ; i > 0; i--, cluster++) {
- unsigned long tmp;
- tmp = (cluster->start_pfn + cluster->numpages) << PAGE_SHIFT;
- if (tmp > high)
- high = tmp;
- }
-
- /* Round it up to an even number of pages. */
- high = (high + PAGE_SIZE) & (PAGE_MASK*2);
-
- /* Enforce maximum of 2GB even if there is more. Blah. */
- if (high > 0x80000000UL)
- high = 0x80000000UL;
- return PAGE_OFFSET + high;
-}
-
-
static char sys_unknown[] = "Unknown";
static char systype_names[][16] = {
"0",
#include <asm/irq.h>
#include <asm/bitops.h>
#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/hardirq.h>
#include <asm/softirq.h>
+#include <asm/mmu_context.h>
#define __KERNEL_SYSCALLS__
#include <asm/unistd.h>
}
static inline void __init
-xl_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+xl_init_arch(void)
{
struct pci_controler *hose;
* Create our single hose.
*/
- hose = alloc_pci_controler(mem_start);
+ hose = alloc_pci_controler();
hose->io_space = &ioport_resource;
hose->mem_space = &iomem_resource;
hose->config_space = LCA_CONF;
}
static inline void __init
-alphabook1_init_arch(unsigned long *mem_start, unsigned long *mem_end)
+alphabook1_init_arch(void)
{
/* The AlphaBook1 has LCD video fixed at 800x600,
37 rows and 100 cols. */
screen_info.orig_video_cols = 100;
screen_info.orig_video_lines = 37;
- lca_init_arch(mem_start, mem_end);
+ lca_init_arch();
}
#define __EXTERN_INLINE inline
#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#undef __EXTERN_INLINE
#include <linux/signal.h>
* Copyright (C) 1995 Linus Torvalds
*/
+/* 2.3.x zone allocator, 1999 Andrea Arcangeli <andrea@suse.de> */
+
#include <linux/config.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/swap.h>
+#include <linux/bootmem.h> /* max_low_pfn */
#ifdef CONFIG_BLK_DEV_INITRD
#include <linux/blk.h>
#endif
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/hwrpb.h>
#include <asm/dma.h>
+#include <asm/mmu_context.h>
-#define DEBUG_POISON 0
+static unsigned long totalram_pages;
extern void die_if_kernel(char *,struct pt_regs *,long);
extern void show_net_buffers(void);
pmd = (pmd_t *) __get_free_page(GFP_KERNEL);
if (pgd_none(*pgd)) {
if (pmd) {
- clear_page((unsigned long)pmd);
+ clear_page((void *)pmd);
pgd_set(pgd, pmd);
return pmd + offset;
}
pte = (pte_t *) __get_free_page(GFP_KERNEL);
if (pmd_none(*pmd)) {
if (pte) {
- clear_page((unsigned long)pte);
+ clear_page((void *)pte);
pmd_set(pmd, pte);
return pte + offset;
}
__bad_page(void)
{
memset((void *) EMPTY_PGE, 0, PAGE_SIZE);
- return pte_mkdirty(mk_pte((unsigned long) EMPTY_PGE, PAGE_SHARED));
+ return pte_mkdirty(mk_pte(mem_map + MAP_NR(EMPTY_PGE), PAGE_SHARED));
}
void
#endif
}
-extern unsigned long free_area_init(unsigned long, unsigned long);
-
static inline unsigned long
load_PCB(struct thread_struct * pcb)
{
* paging_init() sets up the page tables: in the alpha version this actually
* unmaps the bootup page table (as we're now in KSEG, so we don't need it).
*/
-unsigned long
-paging_init(unsigned long start_mem, unsigned long end_mem)
+void paging_init(void)
{
- int i;
unsigned long newptbr;
- struct memclust_struct * cluster;
- struct memdesc_struct * memdesc;
unsigned long original_pcb_ptr;
+ unsigned int zones_size[MAX_NR_ZONES] = {0, 0, 0};
+ unsigned long dma_pfn, high_pfn;
- /* initialize mem_map[] */
- start_mem = free_area_init(start_mem, end_mem);
-
- /* find free clusters, update mem_map[] accordingly */
- memdesc = (struct memdesc_struct *)
- (hwrpb->mddt_offset + (unsigned long) hwrpb);
- cluster = memdesc->cluster;
- for (i = memdesc->numclusters ; i > 0; i--, cluster++) {
- unsigned long pfn, nr;
-
- /* Bit 0 is console/PALcode reserved. Bit 1 is
- non-volatile memory -- we might want to mark
- this for later */
- if (cluster->usage & 3)
- continue;
- pfn = cluster->start_pfn;
- nr = cluster->numpages;
-
- while (nr--)
- clear_bit(PG_reserved, &mem_map[pfn++].flags);
+ dma_pfn = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+ high_pfn = max_low_pfn;
+
+#define ORDER_MASK (~((1 << (MAX_ORDER-1))-1))
+#define ORDER_ALIGN(n) (((n) + ~ORDER_MASK) & ORDER_MASK)
+
+ dma_pfn = ORDER_ALIGN(dma_pfn);
+ high_pfn = ORDER_ALIGN(high_pfn);
+
+#undef ORDER_MASK
+#undef ORDER_ALIGN
+
+ if (dma_pfn > high_pfn)
+ zones_size[ZONE_DMA] = high_pfn;
+ else
+ {
+ zones_size[0] = dma_pfn;
+ zones_size[ZONE_NORMAL] = high_pfn - dma_pfn;
}
+ /* initialize mem_map[] */
+ free_area_init(zones_size);
+
/* Initialize the kernel's page tables. Linux puts the vptb in
the last slot of the L1 page table. */
- memset((void *) ZERO_PAGE(0), 0, PAGE_SIZE);
+ memset((void *)ZERO_PGE, 0, PAGE_SIZE);
memset(swapper_pg_dir, 0, PAGE_SIZE);
newptbr = ((unsigned long) swapper_pg_dir - PAGE_OFFSET) >> PAGE_SHIFT;
pgd_val(swapper_pg_dir[1023]) =
phys_to_virt(original_pcb_ptr);
}
original_pcb = *(struct thread_struct *) original_pcb_ptr;
-
- return start_mem;
}
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM)
}
#endif
-#if DEBUG_POISON
-static void
-kill_page(unsigned long pg)
-{
- unsigned long *p = (unsigned long *)pg;
- unsigned long i = PAGE_SIZE, v = 0xdeadbeefdeadbeef;
- do {
- p[0] = v;
- p[1] = v;
- p[2] = v;
- p[3] = v;
- p[4] = v;
- p[5] = v;
- p[6] = v;
- p[7] = v;
- i -= 64;
- p += 8;
- } while (i != 0);
-}
-#else
-#define kill_page(pg)
-#endif
-
void
-mem_init(unsigned long start_mem, unsigned long end_mem)
+mem_init(void)
{
- unsigned long tmp;
-
- end_mem &= PAGE_MASK;
- max_mapnr = num_physpages = MAP_NR(end_mem);
- high_memory = (void *) end_mem;
- start_mem = PAGE_ALIGN(start_mem);
-
- /*
- * Mark the pages used by the kernel as reserved.
- */
- tmp = KERNEL_START;
- while (tmp < start_mem) {
- set_bit(PG_reserved, &mem_map[MAP_NR(tmp)].flags);
- tmp += PAGE_SIZE;
- }
-
- for (tmp = PAGE_OFFSET ; tmp < end_mem ; tmp += PAGE_SIZE) {
- if (tmp >= MAX_DMA_ADDRESS)
- clear_bit(PG_DMA, &mem_map[MAP_NR(tmp)].flags);
- if (PageReserved(mem_map+MAP_NR(tmp)))
- continue;
- atomic_set(&mem_map[MAP_NR(tmp)].count, 1);
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start && tmp >= initrd_start && tmp < initrd_end)
- continue;
-#endif
- kill_page(tmp);
- free_page(tmp);
- }
- tmp = nr_free_pages << PAGE_SHIFT;
- printk("Memory: %luk available\n", tmp >> 10);
- return;
+ max_mapnr = num_physpages = max_low_pfn;
+ totalram_pages += free_all_bootmem();
+ printk("Memory: %luk available\n", totalram_pages >> 10);
}
void
addr = (unsigned long)(&__init_begin);
for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
- mem_map[MAP_NR(addr)].flags &= ~(1 << PG_reserved);
- atomic_set(&mem_map[MAP_NR(addr)].count, 1);
- kill_page(addr);
+ ClearPageReserved(mem_map + MAP_NR(addr));
+ set_page_count(mem_map+MAP_NR(addr), 1);
free_page(addr);
+ totalram_pages++;
}
printk ("Freeing unused kernel memory: %ldk freed\n",
(&__init_end - &__init_begin) >> 10);
}
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+ for (; start < end; start += PAGE_SIZE) {
+ ClearPageReserved(mem_map + MAP_NR(start));
+ set_page_count(mem_map+MAP_NR(start), 1);
+ free_page(start);
+ totalram_pages++;
+ }
+ printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+}
+#endif
+
void
si_meminfo(struct sysinfo *val)
{
- int i;
-
- i = max_mapnr;
- val->totalram = 0;
+ val->totalram = totalram_pages;
val->sharedram = 0;
- val->freeram = nr_free_pages << PAGE_SHIFT;
- val->bufferram = atomic_read(&buffermem);
- while (i-- > 0) {
- if (PageReserved(mem_map+i))
- continue;
- val->totalram++;
- if (!atomic_read(&mem_map[i].count))
- continue;
- val->sharedram += atomic_read(&mem_map[i].count) - 1;
- }
- val->totalram <<= PAGE_SHIFT;
- val->sharedram <<= PAGE_SHIFT;
- return;
+ val->freeram = nr_free_pages();
+ val->bufferram = atomic_read(&buffermem_pages);
+ val->totalhigh = 0;
+ val->freehigh = 0;
+ val->mem_unit = PAGE_SIZE;
}
empeg_config:
$(RM) arch/arm/defconfig
cp arch/arm/def-configs/empeg arch/arm/defconfig
-
-
bcs 1b
movs r4, r5
mov r5, #0
+ mov r1, #5 @ only here to fix NeTTroms which dont set r1
movne pc, r0
mov r0, #0
# CONFIG_BLK_DEV_CMD640 is not set
# CONFIG_BLK_DEV_RZ1000 is not set
CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_BLK_DEV_IDEDMA=y
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_IDEDMA_PCI_AUTO=y
+# IDEDMA_NEW_DRIVE_LISTINGS is not set
+IDEDMA_PCI_EXPERIMENTAL=y
CONFIG_BLK_DEV_OFFBOARD=y
-CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_AEC6210 is not set
+# CONFIG_BLK_DEV_CMD646 is not set
+CONFIG_BLK_DEV_CY82C693=y
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_PDC202XX=y
+# PDC202XX_FORCE_BURST_BIT is not set
+# PDC202XX_FORCE_MASTER_MODE is not set
# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_CMD646 is not set
CONFIG_BLK_DEV_SL82C105=y
+CONFIG_BLK_DEV_IDEDMA=y
+CONFIG_IDEDMA_AUTO=y
# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_BLK_CPQ_DA is not set
#
# Additional Block Devices
# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_VIA82C586 is not set
# CONFIG_BLK_DEV_CMD646 is not set
CONFIG_BLK_DEV_SL82C105=y
# CONFIG_IDE_CHIPSETS is not set
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/dma.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/proc-fns.h>
#include <asm/semaphore.h>
#include <asm/system.h>
static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
+ if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
+ dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
+ switch (PCI_FUNC(dev->devfn)) {
+ case 1: return 14;
+ case 2: return 15;
+ case 3: return 12;
+ }
+
return irqmap_ebsa285[(slot + pin) & 3];
}
#define DEV(v,d) ((v)<<16|(d))
switch (DEV(dev->vendor, dev->device)) {
case DEV(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142):
+ case DEV(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C885):
+ case DEV(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_YELLOWFIN):
return IRQ_NETWINDER_ETHER100;
case DEV(PCI_VENDOR_ID_WINBOND2, 0x5a5a):
return IRQ_ISA_HARDDISK1;
case DEV(PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000):
+ case DEV(PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010):
return IRQ_NETWINDER_VGA;
default:
--- /dev/null
+struct hw_pci {
+ void (*init)(void);
+ unsigned long io_start;
+ unsigned long mem_start;
+ u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
+ int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
+};
+
+void __init dc21285_init(void);
#include "../lib/constants.h"
+#ifndef MODE_SVC
+#define MODE_SVC 0x13
+#endif
+
.text
#define PF_TRACESYS 0x20
.endm
.macro restore_user_regs
- mrs r1, cpsr @ disable IRQs
- orr r1, r1, #I_BIT
ldr r0, [sp, #S_PSR] @ Get calling cpsr
- msr cpsr, r1
+ msr cpsr_c, #I_BIT | MODE_SVC @ disable IRQs
msr spsr, r0 @ save in spsr_svc
ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0
/* If we're optimising for StrongARM the resulting code won't
run on an ARM7 and we can save a couple of instructions.
--pb */
-#ifdef __ARM_ARCH_4__
- .macro arm700_bug_check, instr, temp
- .endm
-#else
.macro arm700_bug_check, instr, temp
+#ifndef __ARM_ARCH_4__
and \temp, \instr, #0x0f000000 @ check for SWI
teq \temp, #0x0f000000
bne .Larm700bug
- .endm
#endif
+ .endm
.macro enable_irqs, temp
mrs \temp, cpsr
adr\cond \reg, \label
.endm
+ .macro alignment_trap, rbase, rtemp, sym
+#ifdef CONFIG_ALIGNMENT_TRAP
+ ldr \rtemp, [\rbase, #OFF_CR_ALIGNMENT(\sym)]
+ mcr p15, 0, \rtemp, c1, c0
+#endif
+ .endm
+
/*
* Invalid mode handlers
*/
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_ro
-
mrs r9, cpsr @ Enable interrupts if they were
tst r3, #I_BIT
biceq r9, r9, #I_BIT @ previously
-
mov r0, r2
/*
* This routine must not corrupt r9
#else
bl cpu_data_abort
#endif
- msr cpsr, r9
+ msr cpsr_c, r9
mov r3, sp
bl SYMBOL_NAME(do_DataAbort)
+ msr cpsr_c, #I_BIT | MODE_SVC
ldr r0, [sp, #S_PSR]
msr spsr, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
@
adrsvc ne, lr, 1b
bne do_IRQ
- ldr r0, [sp, #S_PSR]
+ ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
mov r1, sp @ struct pt_regs *regs
bl SYMBOL_NAME(do_undefinstr)
-1: ldr lr, [sp, #S_PSR] @ Get SVC cpsr
+1: msr cpsr_c, #I_BIT | MODE_SVC
+ ldr lr, [sp, #S_PSR] @ Get SVC cpsr
msr spsr, lr
ldmia sp, {r0 - pc}^ @ Restore SVC registers
/*
* User mode handlers
*/
-#ifdef DEBUG_UNDEF
-t: .ascii "Prefetch -> undefined instruction\n\0"
- .align
-#endif
.align 5
__dabt_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
stmia sp, {r0 - r12} @ save r0 - r12
ldmia r4, {r0 - r2} @ Get USR pc, cpsr
stmia r3, {r0 - r2} @ Save USR pc, cpsr, old_r0
stmdb r3, {sp, lr}^
-
-#ifdef CONFIG_ALIGNMENT_TRAP
- ldr r7, [r4, #OFF_CR_ALIGNMENT(__temp_abt)]
- mcr p15, 0, r7, c1, c0
-#endif
-
+ alignment_trap r4, r7, __temp_abt
mov fp, #0
#ifdef MULTI_CPU
ldr r2, .LCprocfns
#else
bl cpu_data_abort
#endif
- mrs r3, cpsr @ Enable interrupts if they were
- bic r3, r3, #I_BIT @ previously
- msr cpsr, r3
-
+ msr cpsr_c, #MODE_SVC @ Enable interrupts
mov r3, sp
adrsvc al, lr, ret_from_sys_call
b SYMBOL_NAME(do_DataAbort)
ldmia r4, {r5 - r7} @ get saved PC, SPSR
stmia r8, {r5 - r7} @ save pc, psr, old_r0
stmdb r8, {sp, lr}^
-
-#ifdef CONFIG_ALIGNMENT_TRAP
- ldr r7, [r4, #OFF_CR_ALIGNMENT(__temp_irq)]
- mcr p15, 0, r7, c1, c0
-#endif
-
+ alignment_trap r4, r7, __temp_irq
mov fp, #0
1: get_irqnr_and_base r0, r6, r5
movne r1, sp
ldmia r4, {r5 - r7}
stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0
stmdb r8, {sp, lr}^ @ Save user r0 - r12
-
-#ifdef CONFIG_ALIGNMENT_TRAP
- ldr r7, [r4, #OFF_CR_ALIGNMENT(__temp_und)]
- mcr p15, 0, r7, c1, c0
-#endif
-
+ alignment_trap r4, r7, __temp_und
mov fp, #0
adrsvc al, r9, ret_from_sys_call @ r9 = normal FP return
adrsvc al, lr, fpundefinstr @ lr = undefined instr return
fpundefinstr: mov r0, lr
mov r1, sp
- mrs r4, cpsr @ Enable interrupts
- bic r4, r4, #I_BIT
- msr cpsr, r4
+ msr cpsr_c, #MODE_SVC @ Enable interrupts
adrsvc al, lr, ret_from_sys_call
b SYMBOL_NAME(do_undefinstr)
ldmia r4, {r5 - r7} @ Get USR pc, cpsr
stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0
stmdb r8, {sp, lr}^ @ Save sp_usr lr_usr
-
-#ifdef CONFIG_ALIGNMENT_TRAP
- ldr r7, [r4, #OFF_CR_ALIGNMENT(__temp_abt)]
- mcr p15, 0, r7, c1, c0
-#endif
-
+ alignment_trap r4, r7, __temp_abt
mov fp, #0
- mrs r7, cpsr @ Enable interrupts if they were
- bic r7, r7, #I_BIT @ previously
- msr cpsr, r7
+ msr cpsr_c, #MODE_SVC @ Enable interrupts
mov r0, r5 @ address (pc)
mov r1, sp @ regs
bl SYMBOL_NAME(do_PrefetchAbort) @ call abort handler
msr spsr, lr
ldmia sp, {r0 - pc}^ @ Restore USR registers
+#ifdef DEBUG_UNDEF
+t: .ascii "Prefetch -> undefined instruction\n\0"
+ .align
+#endif
+
#include "entry-common.S"
.text
@
@ now branch to the relevent MODE handling routine
@
- bic r13, lr, #63
- orr r13, r13, #0x93
- msr spsr, r13 @ switch to SVC_32 mode
+ msr spsr_c, #I_BIT | MODE_SVC @ switch to SVC_32 mode
and lr, lr, #15
- adr r13, .LCtab_irq
- ldr lr, [r13, lr, lsl #2]
+ ldr lr, [pc, lr, lsl #2]
movs pc, lr @ Changes mode and branches
+
+.LCtab_irq: .word __irq_usr @ 0 (USR_26 / USR_32)
+ .word __irq_invalid @ 1 (FIQ_26 / FIQ_32)
+ .word __irq_invalid @ 2 (IRQ_26 / IRQ_32)
+ .word __irq_svc @ 3 (SVC_26 / SVC_32)
+ .word __irq_invalid @ 4
+ .word __irq_invalid @ 5
+ .word __irq_invalid @ 6
+ .word __irq_invalid @ 7
+ .word __irq_invalid @ 8
+ .word __irq_invalid @ 9
+ .word __irq_invalid @ a
+ .word __irq_invalid @ b
+ .word __irq_invalid @ c
+ .word __irq_invalid @ d
+ .word __irq_invalid @ e
+ .word __irq_invalid @ f
+
+ .align 5
+
/*
* Data abort dispatcher - dispatches it to the correct handler for the processor mode
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
@
@ now branch to the relevent MODE handling routine
@
- bic r13, lr, #63
- orr r13, r13, #0x93
- msr spsr, r13 @ switch to SVC_32 mode
+ msr spsr_c, #I_BIT | MODE_SVC @ switch to SVC_32 mode
and lr, lr, #15
- adr r13, .LCtab_dabt
- ldr lr, [r13, lr, lsl #2]
+ ldr lr, [pc, lr, lsl #2]
movs pc, lr @ Changes mode and branches
+.LCtab_dabt: .word __dabt_usr @ 0 (USR_26 / USR_32)
+ .word __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
+ .word __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
+ .word __dabt_svc @ 3 (SVC_26 / SVC_32)
+ .word __dabt_invalid @ 4
+ .word __dabt_invalid @ 5
+ .word __dabt_invalid @ 6
+ .word __dabt_invalid @ 7
+ .word __dabt_invalid @ 8
+ .word __dabt_invalid @ 9
+ .word __dabt_invalid @ a
+ .word __dabt_invalid @ b
+ .word __dabt_invalid @ c
+ .word __dabt_invalid @ d
+ .word __dabt_invalid @ e
+ .word __dabt_invalid @ f
+
+ .align 5
+
/*
* Prefetch abort dispatcher - dispatches it to the correct handler for the processor mode
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
@
@ now branch to the relevent MODE handling routine
@
- bic r13, lr, #63
- orr r13, r13, #0x93
- msr spsr, r13 @ switch to SVC_32 mode
+ msr spsr_c, #I_BIT | MODE_SVC @ switch to SVC_32 mode
ands lr, lr, #15
ldreq lr, .LCtab_pabt
ldrne lr, .LCtab_pabt + 4
movs pc, lr
+.LCtab_pabt: .word __pabt_usr
+ .word __pabt_invalid
+
+ .align 5
+
/*
* Undef instr entry dispatcher - dispatches it to the correct handler for the processor mode
* Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
@
@ now branch to the relevent MODE handling routine
@
- bic r13, lr, #63
- orr r13, r13, #0x93
- msr spsr, r13 @ switch to SVC_32 mode
+ msr spsr_c, #I_BIT | MODE_SVC @ switch to SVC_32 mode
and lr, lr, #15
- adr r13, .LCtab_und
- ldr lr, [r13, lr, lsl #2]
+ ldr lr, [pc, lr, lsl #2]
movs pc, lr @ Changes mode and branches
+.LCtab_und: .word __und_usr @ 0 (USR_26 / USR_32)
+ .word __und_invalid @ 1 (FIQ_26 / FIQ_32)
+ .word __und_invalid @ 2 (IRQ_26 / IRQ_32)
+ .word __und_svc @ 3 (SVC_26 / SVC_32)
+ .word __und_invalid @ 4
+ .word __und_invalid @ 5
+ .word __und_invalid @ 6
+ .word __und_invalid @ 7
+ .word __und_invalid @ 8
+ .word __und_invalid @ 9
+ .word __und_invalid @ a
+ .word __und_invalid @ b
+ .word __und_invalid @ c
+ .word __und_invalid @ d
+ .word __und_invalid @ e
+ .word __und_invalid @ f
+
+ .align 5
+
/*=============================================================================
* Undefined FIQs
*-----------------------------------------------------------------------------
*/
.align 5
-.LCtab_irq: .word __irq_usr @ 0 (USR_26 / USR_32)
- .word __irq_invalid @ 1 (FIQ_26 / FIQ_32)
- .word __irq_invalid @ 2 (IRQ_26 / IRQ_32)
- .word __irq_svc @ 3 (SVC_26 / SVC_32)
- .word __irq_invalid @ 4
- .word __irq_invalid @ 5
- .word __irq_invalid @ 6
- .word __irq_invalid @ 7
- .word __irq_invalid @ 8
- .word __irq_invalid @ 9
- .word __irq_invalid @ a
- .word __irq_invalid @ b
- .word __irq_invalid @ c
- .word __irq_invalid @ d
- .word __irq_invalid @ e
- .word __irq_invalid @ f
-
-.LCtab_und: .word __und_usr @ 0 (USR_26 / USR_32)
- .word __und_invalid @ 1 (FIQ_26 / FIQ_32)
- .word __und_invalid @ 2 (IRQ_26 / IRQ_32)
- .word __und_svc @ 3 (SVC_26 / SVC_32)
- .word __und_invalid @ 4
- .word __und_invalid @ 5
- .word __und_invalid @ 6
- .word __und_invalid @ 7
- .word __und_invalid @ 8
- .word __und_invalid @ 9
- .word __und_invalid @ a
- .word __und_invalid @ b
- .word __und_invalid @ c
- .word __und_invalid @ d
- .word __und_invalid @ e
- .word __und_invalid @ f
-
-.LCtab_dabt: .word __dabt_usr @ 0 (USR_26 / USR_32)
- .word __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
- .word __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
- .word __dabt_svc @ 3 (SVC_26 / SVC_32)
- .word __dabt_invalid @ 4
- .word __dabt_invalid @ 5
- .word __dabt_invalid @ 6
- .word __dabt_invalid @ 7
- .word __dabt_invalid @ 8
- .word __dabt_invalid @ 9
- .word __dabt_invalid @ a
- .word __dabt_invalid @ b
- .word __dabt_invalid @ c
- .word __dabt_invalid @ d
- .word __dabt_invalid @ e
- .word __dabt_invalid @ f
-
-.LCtab_pabt: .word __pabt_usr
- .word __pabt_invalid
-
.LCvswi: .word vector_swi
.LCsirq: .word __temp_irq
str r3, [r0], #4
add r3, r3, #1 << 20
str r3, [r0], #4
+1:
#endif
#endif
#ifdef CONFIG_ARCH_RPC
arch_reset(reboot_mode);
+ mdelay(1000);
printk("Reboot failed -- System halted\n");
-
while (1);
}
/*
* Task structure and kernel stack allocation.
- *
- * Taken from the i386 version.
*/
+static struct task_struct *task_struct_head;
+static unsigned int nr_task_struct;
+
#ifdef CONFIG_CPU_32
-#define EXTRA_TASK_STRUCT 8
-static struct task_struct *task_struct_stack[EXTRA_TASK_STRUCT];
-static int task_struct_stack_ptr = -1;
+#define EXTRA_TASK_STRUCT 4
+#else
+#define EXTRA_TASK_STRUCT 0
#endif
struct task_struct *alloc_task_struct(void)
{
struct task_struct *tsk;
-#ifndef EXTRA_TASK_STRUCT
- tsk = ll_alloc_task_struct();
-#else
- int index;
+ if (EXTRA_TASK_STRUCT)
+ tsk = task_struct_head;
+ else
+ tsk = NULL;
- index = task_struct_stack_ptr;
- if (index >= EXTRA_TASK_STRUCT/2)
- goto use_cache;
-
- tsk = ll_alloc_task_struct();
-
- if (!tsk) {
- index = task_struct_stack_ptr;
+ if (tsk) {
+ task_struct_head = tsk->next_task;
+ nr_task_struct -= 1;
+ } else
+ tsk = ll_alloc_task_struct();
- if (index >= 0) {
-use_cache: tsk = task_struct_stack[index];
- task_struct_stack_ptr = index - 1;
- }
- }
-#endif
#ifdef CONFIG_SYSRQ
- /* You need this if you want SYSRQ-T to give sensible stack
- * usage information
+ /*
+ * The stack must be cleared if you want SYSRQ-T to
+ * give sensible stack usage information
*/
if (tsk) {
char *p = (char *)tsk;
memzero(p+KERNEL_STACK_SIZE, KERNEL_STACK_SIZE);
}
#endif
-
return tsk;
}
-void free_task_struct(struct task_struct *p)
+void __free_task_struct(struct task_struct *p)
{
-#ifdef EXTRA_TASK_STRUCT
- int index = task_struct_stack_ptr + 1;
-
- if (index < EXTRA_TASK_STRUCT) {
- task_struct_stack[index] = p;
- task_struct_stack_ptr = index;
+ if (EXTRA_TASK_STRUCT && nr_task_struct < EXTRA_TASK_STRUCT) {
+ p->next_task = task_struct_head;
+ task_struct_head = p;
+ nr_task_struct += 1;
} else
-#endif
ll_free_task_struct(p);
}
struct pt_regs * childregs;
struct context_save_struct * save;
+ atomic_set(&p->thread.refcount, 1);
+
childregs = ((struct pt_regs *)((unsigned long)p + 8192)) - 1;
*childregs = *regs;
childregs->ARM_r0 = 0;
/*
* Initialise the boot-time allocator
*/
- bootmem_end += init_bootmem(bootmem_end >> PAGE_SHIFT, end_pfn);
+ bootmem_end += init_bootmem(bootmem_end >> PAGE_SHIFT, end_pfn, PHYS_OFFSET);
/*
* Register all available RAM with the bootmem allocator.
#include <asm/ucontext.h>
#include <asm/uaccess.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
{
int version, ret;
- lock_kernel();
version = call >> 16; /* hack for backward compatibility */
call &= 0xffff;
- if (call <= SEMCTL)
- switch (call) {
- case SEMOP:
- ret = sys_semop (first, (struct sembuf *)ptr, second);
- goto out;
- case SEMGET:
- ret = sys_semget (first, second, third);
- goto out;
- case SEMCTL: {
- union semun fourth;
- ret = -EINVAL;
+ switch (call) {
+ case SEMOP:
+ return sys_semop (first, (struct sembuf *)ptr, second);
+ case SEMGET:
+ return sys_semget (first, second, third);
+ case SEMCTL: {
+ union semun fourth;
+ if (!ptr)
+ return -EINVAL;
+ if (get_user(fourth.__pad, (void **) ptr))
+ return -EFAULT;
+ return sys_semctl (first, second, third, fourth);
+ }
+
+ case MSGSND:
+ return sys_msgsnd (first, (struct msgbuf *) ptr,
+ second, third);
+ case MSGRCV:
+ switch (version) {
+ case 0: {
+ struct ipc_kludge tmp;
if (!ptr)
- goto out;
- ret = -EFAULT;
- if (get_user(fourth.__pad, (void **) ptr))
- goto out;
- ret = sys_semctl (first, second, third, fourth);
- goto out;
- }
- default:
- ret = -EINVAL;
- goto out;
+ return -EINVAL;
+ if (copy_from_user(&tmp,(struct ipc_kludge *) ptr,
+ sizeof (tmp)))
+ return -EFAULT;
+ return sys_msgrcv (first, tmp.msgp, second,
+ tmp.msgtyp, third);
}
- if (call <= MSGCTL)
- switch (call) {
- case MSGSND:
- ret = sys_msgsnd (first, (struct msgbuf *) ptr,
- second, third);
- goto out;
- case MSGRCV:
- switch (version) {
- case 0: {
- struct ipc_kludge tmp;
- ret = -EINVAL;
- if (!ptr)
- goto out;
- ret = -EFAULT;
- if (copy_from_user(&tmp,(struct ipc_kludge *) ptr,
- sizeof (tmp)))
- goto out;
- ret = sys_msgrcv (first, tmp.msgp, second, tmp.msgtyp, third);
- goto out;
- }
- case 1: default:
- ret = sys_msgrcv (first, (struct msgbuf *) ptr, second, fifth, third);
- goto out;
- }
- case MSGGET:
- ret = sys_msgget ((key_t) first, second);
- goto out;
- case MSGCTL:
- ret = sys_msgctl (first, second, (struct msqid_ds *) ptr);
- goto out;
default:
- ret = -EINVAL;
- goto out;
+ return sys_msgrcv (first,
+ (struct msgbuf *) ptr,
+ second, fifth, third);
}
- if (call <= SHMCTL)
- switch (call) {
- case SHMAT:
- switch (version) {
- case 0: default: {
- ulong raddr;
- ret = sys_shmat (first, (char *) ptr, second, &raddr);
- if (ret)
- goto out;
- ret = put_user (raddr, (ulong *) third);
- goto out;
- }
- case 1: /* iBCS2 emulator entry point */
- ret = -EINVAL;
- if (!segment_eq(get_fs(), get_ds()))
- goto out;
- ret = sys_shmat (first, (char *) ptr, second, (ulong *) third);
- goto out;
- }
- case SHMDT:
- ret = sys_shmdt ((char *)ptr);
- goto out;
- case SHMGET:
- ret = sys_shmget (first, second, third);
- goto out;
- case SHMCTL:
- ret = sys_shmctl (first, second, (struct shmid_ds *) ptr);
- goto out;
- default:
- ret = -EINVAL;
- goto out;
+ case MSGGET:
+ return sys_msgget ((key_t) first, second);
+ case MSGCTL:
+ return sys_msgctl (first, second, (struct msqid_ds *) ptr);
+
+ case SHMAT:
+ switch (version) {
+ default: {
+ ulong raddr;
+ ret = sys_shmat (first, (char *) ptr, second, &raddr);
+ if (ret)
+ return ret;
+ return put_user (raddr, (ulong *) third);
}
- else
- ret = -EINVAL;
-out:
- unlock_kernel();
- return ret;
+ case 1: /* iBCS2 emulator entry point */
+ if (!segment_eq(get_fs(), get_ds()))
+ return -EINVAL;
+ return sys_shmat (first, (char *) ptr,
+ second, (ulong *) third);
+ }
+ case SHMDT:
+ return sys_shmdt ((char *)ptr);
+ case SHMGET:
+ return sys_shmget (first, second, third);
+ case SHMCTL:
+ return sys_shmctl (first, second,
+ (struct shmid_ds *) ptr);
+ default:
+ return -EINVAL;
+ }
}
/* Fork a new task - this creates a new program thread.
#define reg r5
#define stack r6
-.Ldumpstm: stmfd sp!, {instr, reg, stack, lr}
+.Ldumpstm: stmfd sp!, {instr, reg, stack, r7, lr}
mov stack, r0
mov instr, r1
mov reg, #9
-
+ mov r7, #0
1: mov r3, #1
tst instr, r3, lsl reg
beq 2f
+ add r7, r7, #1
+ teq r7, #4
+ moveq r7, #0
+ moveq r3, #'\n'
+ movne r3, #' '
ldr r2, [stack], #-4
mov r1, reg
adr r0, .Lfp
bl SYMBOL_NAME(printk)
2: subs reg, reg, #1
bpl 1b
-
+ teq r7, #0
+ adrne r0, .Lcr
+ blne SYMBOL_NAME(printk)
mov r0, stack
- LOADREGS(fd, sp!, {instr, reg, stack, pc})
+ LOADREGS(fd, sp!, {instr, reg, stack, r7, pc})
-.Lfe: .ascii "Function entered at [<%p>] from [<%p>]\n"
- .byte 0
-.Lfp: .ascii " r%d = %p\n"
- .byte 0
+.Lfe: .asciz "Function entered at [<%p>] from [<%p>]\n"
+.Lfp: .asciz " r%d = %08X%c"
+.Lcr: .asciz "\n"
.align
.Ldsi: .word 0x00e92dd8 >> 2
.word 0x00e92d00 >> 2
#include <asm/system.h>
#include <asm/segment.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/dma.h>
#include <asm/hardware.h>
#include <asm/setup.h>
void __init paging_init(void)
{
void *zero_page, *bad_page, *bad_table;
+ unsigned int zone_size[3];
#ifdef CONFIG_CPU_32
#define TABLE_OFFSET (PTRS_PER_PTE)
pagetable_init();
flush_tlb_all();
- free_area_init(max_low_pfn);
+ /*
+ * Initialise the zones and mem_map
+ */
+ zonesize_init(zone_size);
+ free_area_init(zone_size);
/*
* finish off the bad pages once
*/
void __init mem_init(void)
{
- int codepages = 0;
- int reservedpages = 0;
- int datapages = 0;
- int initpages = 0, i, min_nr;
+ extern char __init_begin, __init_end, _text, _etext, _end;
+ unsigned int codepages, datapages, initpages;
+ int i;
- max_mapnr = max_low_pfn;
- high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
+ max_mapnr = max_low_pfn;
+ high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
-#ifdef CONFIG_CPU_32
/*
* We may have non-contiguous memory. Setup the PageSkip stuff,
* and mark the areas of mem_map which can be freed
*/
if (meminfo.nr_banks != 1)
create_memmap_holes();
-#endif
/* this will put all unused low memory onto the freelists */
totalram_pages += free_all_bootmem();
for (i = 0; i < meminfo.nr_banks; i++)
num_physpages += meminfo.bank[i].size >> PAGE_SHIFT;
- printk ("Memory: %luk/%luM available (%dk code, %dk reserved, %dk data, %dk init)\n",
- (unsigned long) nr_free_pages << (PAGE_SHIFT-10),
- num_physpages >> (20 - PAGE_SHIFT),
- codepages << (PAGE_SHIFT-10),
- reservedpages << (PAGE_SHIFT-10),
- datapages << (PAGE_SHIFT-10),
- initpages << (PAGE_SHIFT-10));
+ codepages = (int)&_etext - &_text;
+ datapages = (int)&_end - &_etext;
+ initpages = (int)&__init_end - &__init_start;
- /*
- * Correct freepages watermarks
- */
- i = nr_free_pages >> 7;
- if (PAGE_SIZE < 32768)
- min_nr = 10;
- else
- min_nr = 2;
- if (i < min_nr)
- i = min_nr;
- if (i > 256)
- i = 256;
- freepages.min = i;
- freepages.low = i * 2;
- freepages.high = i * 3;
+ printk("Memory: %luk/%luM available (%dK code, %dK data, %dK init)\n",
+ (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
+ num_physpages >> (20 - PAGE_SHIFT),
+ codepages << (PAGE_SHIFT-10),
+ datapages << (PAGE_SHIFT-10),
+ initpages << (PAGE_SHIFT-10));
#ifdef CONFIG_CPU_26
if (max_mapnr <= 128) {
{
val->totalram = totalram_pages;
val->sharedram = 0;
- val->freeram = nr_free_pages;
+ val->freeram = nr_free_pages();
val->bufferram = atomic_read(&buffermem_pages);
val->totalhigh = 0;
val->freehigh = 0;
#include <linux/vmalloc.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/io.h>
static inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
extern struct map_desc io_desc[];
extern unsigned int io_desc_size;
+extern void zonesize_init(unsigned int *);
extern void create_memmap_holes(void);
extern void pagetable_init(void);
#include <linux/bootmem.h>
#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/page.h>
#include <asm/arch/memory.h>
return (pte_t *) pmd_page(*pmd) + offset;
}
+/*
+ * Calculate the size of the DMA, normal and highmem zones.
+ * On 26-bit ARMs, we don't have any real DMA or highmem,
+ * so we allocate the whole memory as being DMA-capable.
+ */
+void __init zonesize_init(unsigned int *zone_size)
+{
+ int i;
+
+ zone_size[0] = max_low_pfn;
+ zone_size[1] = 0;
+ zone_size[2] = 0;
+}
+
/*
* This contains the code to setup the memory map on an ARM2/ARM250/ARM3
* machine. This is both processor & architecture specific, and requires
page_nr = max_low_pfn;
pte = alloc_bootmem_low_pages(PTRS_PER_PTE * sizeof(pte_t));
- memzero(pte, PTRS_PER_PTE * sizeof(pte_t));
pte[0] = mk_pte_phys(PAGE_OFFSET + 491520, PAGE_READONLY);
set_pmd(pmd_offset(swapper_pg_dir, 0), mk_kernel_pmd(pte));
#include <linux/bootmem.h>
#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/setup.h>
pte_t *ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
sizeof(pte_t));
- memzero(ptep, 2 * PTRS_PER_PTE * sizeof(pte_t));
ptep += PTRS_PER_PTE;
set_pmd(pmdp, __mk_pmd(ptep, PMD_TYPE_TABLE | PMD_DOMAIN(domain)));
#define NR_INIT_MAPS (sizeof(init_map) / sizeof(init_map[0]))
+/*
+ * Calculate the size of the DMA, normal and highmem zones.
+ * On ARM, we don't have any problems with DMA, so all memory
+ * is allocated to the DMA zone. We also don't have any
+ * highmem either.
+ */
+void __init zonesize_init(unsigned int *zone_size)
+{
+ int i;
+
+ zone_size[0] = 0;
+ zone_size[1] = 0;
+ zone_size[2] = 0;
+
+ for (i = 0; i < meminfo.nr_banks; i++) {
+ if (meminfo.bank[i].size) {
+ unsigned int end;
+
+ end = (meminfo.bank[i].start +
+ meminfo.bank[i].size) >> PAGE_SHIFT;
+ if (end > zone_size[0])
+ zone_size[0] = end;
+ }
+ }
+}
+
void __init pagetable_init(void)
{
unsigned long address = 0;
set_bit(PG_skip, &pg->flags);
pg->next_hash = NULL;
}
-
-#if 0
- /*
- * setup address validity map
- * - don't think this is used anymore?
- */
- sz = meminfo.end >> (PAGE_SHIFT + 8); /* in MB */
- sz = (sz + 31) >> 3;
-
- valid_addr_bitmap = alloc_bootmem(sz);
- memzero(valid_addr_bitmap, sz);
-
- for (i = 0; i < meminfo.nr_banks; i++) {
- int idx, end;
-
- idx = meminfo.bank[i].start >> 20;
- end = (meminfo.bank[i].start +
- meminfo.bank[i].size) >> 20;
- do
- set_bit(idx, valid_addr_bitmap);
- while (++idx < end);
- }
-#endif
}
#endif
};
-#define USED_MAP(pg) ((pg)->offset)
-#define TEST_AND_CLEAR_USED(pg,off) (test_and_clear_bit(off, &(pg)->offset))
-#define SET_USED(pg,off) (set_bit(off, &(pg)->offset))
+#define USED_MAP(pg) ((pg)->index)
+#define TEST_AND_CLEAR_USED(pg,off) (test_and_clear_bit(off, &USED_MAP(pg)))
+#define SET_USED(pg,off) (set_bit(off, &USED_MAP(pg)))
static void add_page_to_queue(struct page *page, struct page **p)
{
remove_page_from_queue(page);
restore_flags(flags);
- return page_address(page) + (offset << order->shift);
+ return __page_address(page) + (offset << order->shift);
need_new_page:
page = alloc_page(priority);
bootsect.s: bootsect.S Makefile $(BOOT_INCL)
$(CPP) -traditional $(SVGA_MODE) $(RAMDISK) $< -o $@
-bbootsect: bbootsect.o bbootsect_kludge.o
- $(LD) -Ttext 0x0 -R bbootsect_kludge.o -s -oformat binary $< -o $@
-
-bbootsect_kludge.o: bbootsect.o bsetup.o
- $(LD) -r $^ -o $@
+bbootsect: bbootsect.o
+ $(LD) -Ttext 0x0 -s -oformat binary $< -o $@
bbootsect.o: bbootsect.s
$(AS) -o $@ $<
rm -f tools/build
rm -f setup bootsect zImage compressed/vmlinux.out
rm -f bsetup bbootsect bzImage compressed/bvmlinux.out
- rm -f bbootsect_kludge.o
@$(MAKE) -C compressed clean
xorw %bx, %bx # bx is starting address within segment
rp_read:
#ifdef __BIG_KERNEL__
- lcall bootsect_kludge # in setup.S
+ bootsect_kludge = 0x220 # 0x200 (size of bootsector) + 0x20 (offset
+ lcall bootsect_kludge # of bootsect_kludge in setup.S)
#else
movw %es, %ax
subw $SYSSEG, %ax
# don't have to worry about it later.
kill_motor:
- pushw %dx
movw $0x3f2, %dx
xorb %al, %al
outb %al, %dx
- popw %dx
ret
sectors: .word 0
ramdisk_size: .long 0 # its size in bytes
-.global bootsect_kludge # so that we can see it in bootsect.S
bootsect_kludge:
.word bootsect_helper, SETUPSEG
xorw %bx, %bx
int $0x15 # ignore return code
movw $0x05303, %ax # 32 bit connect
- xorw %ebx, %ebx
+ xorw %bx, %bx
int $0x15
jc no_32_apm_bios # Ack, error.
no_s31: xorw %bp, %bp # Detection failed
s3rest: movb %bh, %ah
movb $0x38, %al # restore old value of CRT register 0x38
- call outidx
+ jmp outidx
idS3: .byte 0x81, 0x82, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95
.byte 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa8, 0xb0
# CONFIG_NET_ISA is not set
CONFIG_NET_EISA=y
# CONFIG_PCNET32 is not set
-# CONFIG_ACENIC is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
CONFIG_EEXPRESS_PRO100=y
# CONFIG_NE2K_PCI is not set
+# CONFIG_SIS900 is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
-# CONFIG_SIS900 is not set
# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_PCMCIA_SERIAL_CB is not set
#
-# USB drivers - not for the faint of heart
+# Support for USB
#
# CONFIG_USB is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
printk(KERN_ERR "PCI: I/O Region %s/%d too large (%ld bytes)\n", dev->slot_name, i, size);
return -EFBIG;
}
- if (allocate_resource(pr, r, size, 0x1000, ~0, 1024)) {
+ if (allocate_resource(pr, r, size, 0x1000, ~0, 1024, dev)) {
printk(KERN_ERR "PCI: Allocation of I/O region %s/%d (%ld bytes) failed\n", dev->slot_name, i, size);
return -EBUSY;
}
} else {
- if (allocate_resource(pr, r, size, 0x10000000, ~0, size)) {
+ if (allocate_resource(pr, r, size, 0x10000000, ~0, size, dev)) {
printk(KERN_ERR "PCI: Allocation of memory region %s/%d (%ld bytes) failed\n", dev->slot_name, i, size);
return -EBUSY;
}
pcibios_assign_resources();
}
+unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
+ unsigned long start, unsigned long size)
+{
+ return start;
+}
+
int pcibios_enable_resources(struct pci_dev *dev)
{
u16 cmd, old_cmd;
{
unsigned int zones_size[MAX_NR_ZONES] = {0, 0, 0};
unsigned int max_dma, high, low;
- unsigned int align = (1 << (MAX_ORDER-1))-1;
max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
- low = (max_low_pfn + align) & ~align;
- high = (highend_pfn + align) & ~align;
+ low = max_low_pfn;
+ high = highend_pfn;
if (low < max_dma)
zones_size[ZONE_DMA] = low;
printk ("Freeing unused kernel memory: %dk freed\n", (&__init_end - &__init_begin) >> 10);
}
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+ for (; start < end; start += PAGE_SIZE) {
+ ClearPageReserved(mem_map + MAP_NR(start));
+ set_page_count(mem_map+MAP_NR(start), 1);
+ free_page(start);
+ totalram_pages++;
+ }
+ printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+}
+#endif
+
void si_meminfo(struct sysinfo *val)
{
val->totalram = totalram_pages;
/* gets the response from the fdc */
static int result(void)
{
- int i, status;
+ int i, status=0;
for(i=0; i < MAX_REPLIES; i++) {
if ((status = wait_til_ready()) < 0)
static int initrd_release(struct inode *inode,struct file *file)
{
+ extern void free_initrd_mem(unsigned long, unsigned long);
+
+ if (--initrd_users) return 0;
+ free_initrd_mem(initrd_start, initrd_end);
initrd_start = 0;
- /* No need to actually release the pages, because that is
- done later by free_all_bootmem. */
return 0;
}
block_fsync /* fsync */
};
-#ifdef MODULE
-#define rd_init init_module
-
/* Before freeing the module, invalidate all of the protected buffers! */
-void cleanup_module(void)
+static void __exit rd_cleanup (void)
{
int i;
blk_dev[MAJOR_NR].request_fn = 0;
}
-#endif /* MODULE */
-
-
/* This is the registration and initialization section of the RAM disk driver */
-int __init rd_init(void)
+int __init rd_init (void)
{
int i;
return 0;
}
-/* loadable module support */
+#ifdef MODULE
+module_init(rd_init);
+#endif
+module_exit(rd_cleanup);
+/* loadable module support */
MODULE_PARM (rd_size, "1i");
MODULE_PARM_DESC(rd_size, "Size of each RAM disk in kbytes.");
MODULE_PARM (rd_blocksize, "i");
tristate '/dev/nvram support' CONFIG_NVRAM
-bool 'Enhanced Real Time Clock Support' CONFIG_RTC
+tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
if [ "$CONFIG_ALPHA_BOOK1" = "y" ]; then
bool 'Tadpole ANA H8 Support' CONFIG_H8
fi
{ 3, 1, 0, 2, 0xc00, { 2, 3, 1, 1},{0, 1, 0x800, 0x400, 0xc00, 0}},
/* Modular Technology MM205 PCTV, bt878 */
{ 2, 1, 0, -1, 7, { 2, 3 }, { 0, 0, 0, 0, 0 }},
+ /* Magic TView CPH061 (bt878) */
+ { 3, 1, 0, 2, 0xe00, { 2, 0, 1, 1}, {0x400, 0, 0, 0, 0}},
};
#define TVCARDS (sizeof(tvcards)/sizeof(tvcard))
case BTTV_PIXVIEWPLAYTV:
case BTTV_AVERMEDIA98:
case BTTV_MODTEC_205:
+ case BTTV_MAGICTVIEW061:
btv->pll.pll_ifreq=28636363;
btv->pll.pll_crystal=BT848_IFORM_XT0;
break;
#define BTTV_CONFERENCETV 0x15
#define BTTV_PHOEBE_TVMAS 0x16
#define BTTV_MODTEC_205 0x17
+#define BTTV_MAGICTVIEW061 0x18
#define AUDIO_TUNER 0x00
#define AUDIO_RADIO 0x01
"Compression routines for zftape. Uses the lzrw3 algorithm by Ross Williams");
#endif
-#if LINUX_VERSION_CODE <= KERNEL_VER(1,2,13)
-char kernel_version[] = UTS_RELEASE;
-#endif
#if LINUX_VERSION_CODE >= KERNEL_VER(2,1,18)
static int can_unload(void)
{
{
int result;
-#if LINUX_VERSION_CODE >= KERNEL_VER(1,1,85)
-# if LINUX_VERSION_CODE < KERNEL_VER(2,1,18)
+#if LINUX_VERSION_CODE < KERNEL_VER(2,1,18)
register_symtab(0); /* remove global ftape symbols */
-# else
+#else
if (!mod_member_present(&__this_module, can_unload))
return -EBUSY;
__this_module.can_unload = can_unload;
EXPORT_NO_SYMBOLS;
-# endif
#endif
result = zft_compressor_init();
keep_module_locked = 0;
TRACE_EXIT 0;
}
-#if LINUX_VERSION_CODE >= KERNEL_VER(1,3,70)
static void ftape_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-#else
-static void ftape_interrupt(int irq, struct pt_regs *regs)
-#endif
{
void (*handler) (void) = *fdc.hook;
TRACE_FUN(ft_t_any);
fdc.irq);
}
if (request_dma(fdc.dma, ftape_id)) {
-#if LINUX_VERSION_CODE >= KERNEL_VER(1,3,70)
free_irq(fdc.irq, ftape_id);
-#else
- free_irq(fdc.irq);
-#endif
TRACE_ABORT(-EIO, ft_t_bug,
"Unable to grab DMA%d for ftape driver",
fdc.dma);
}
/* Display old ftape's end-of-file marks
*/
-#if LINUX_VERSION_CODE >= KERNEL_VER(2,0,0)
while ((sector = get_unaligned(((__u16*)ptr)++)) != 0) {
TRACE(ft_t_noise, "Old ftape eof mark: %4d/%2d",
sector, get_unaligned(((__u16*)ptr)++));
}
-#else
- while ((sector = *((__u16*)ptr)++) != 0) {
- TRACE(ft_t_noise, "Old ftape eof mark: %4d/%2d",
- sector, *((__u16*)ptr)++);
- }
-#endif
} else { /* fixed size format */
for (i = ft_first_data_segment;
i < (int)(ft_segments_per_track * ft_tracks_per_tape); ++i) {
/* history record */
#define ft_history ftape_status.fti_history
-/* compatibility with old kernel versions
- */
-#if LINUX_VERSION_CODE <= KERNEL_VER(1,2,13)
-#define _IOC_SIZE(cmd) (((cmd) & IOCSIZE_MASK) >> IOCSIZE_SHIFT)
-#define _IOC_DIR(cmd) (cmd)
-#define _IOC_WRITE IOC_IN
-#define _IOC_READ IOC_OUT
-#endif
-
/*
* ftape-ctl.c defined global vars.
*/
ft_failure = 1; /* inhibit any operation but open */
ftape_udelay_calibrate(); /* must be before fdc_wait_calibrate ! */
fdc_wait_calibrate();
-#if (LINUX_VERSION_CODE >= KERNEL_VER(1,2,0) && \
- LINUX_VERSION_CODE < KERNEL_VER(2,1,18))
+#if LINUX_VERSION_CODE < KERNEL_VER(2,1,18)
register_symtab(&ftape_symbol_table); /* add global ftape symbols */
#endif
#if defined(CONFIG_PROC_FS) && defined(CONFIG_FT_PROC_FS)
"QIC-117 driver for QIC-40/80/3010/3020 floppy tape drives.");
#endif
-#if LINUX_VERSION_CODE <= KERNEL_VER(1,2,13)
-char kernel_version[] = UTS_RELEASE;
-#endif
-
/* Called by modules package when installing the driver
*/
int init_module(void)
/* ftape-init.c defined global variables.
*/
-#if defined(MODULE) && LINUX_VERSION_CODE <= KERNEL_VER(1,2,13)
-extern char kernel_version[];
-#endif
+
/* ftape-init.c defined global functions not defined in ftape.h
*/
#include "../lowlevel/ftape-init.h"
#include "../lowlevel/ftape-bsm.h"
-#if LINUX_VERSION_CODE >= KERNEL_VER(2,0,0)
#include <asm/unaligned.h>
#define GET2(address, offset) get_unaligned((__u16*)((__u8 *)address + offset))
#define PUT2(address, offset , value) put_unaligned((value), (__u16*)((__u8 *)address + offset))
#define PUT4(address, offset , value) put_unaligned((value), (__u32*)((__u8 *)address + offset))
#define PUT8(address, offset , value) put_unaligned((value), (__u64*)((__u8 *)address + offset))
-#else
-#define GET2(address, offset) *(__u16*)((__u8 *)address + offset)
-#define GET4(address, offset) *(__u32*)((__u8 *)address + offset)
-#define GET8(address, offset) *(__u64*)((__u8 *)address + offset)
-#define PUT2(address, offset , value) *(__u16*)((__u8 *)address + offset) = (__u16)(value)
-#define PUT4(address, offset , value) *(__u32*)((__u8 *)address + offset) = (__u32)(value)
-#define PUT8(address, offset , value) *(__u64*)((__u8 *)address + offset) = (__u32)(value)
-#endif
enum runner_status_enum {
idle = 0,
{
while (ptr + 3 < limit) {
-#if LINUX_VERSION_CODE >= KERNEL_VER(2,0,0)
if (get_unaligned((__u32*)ptr)) {
++(__u32*)ptr;
} else {
return ptr;
}
-#else
- if (*(__u32*)ptr) {
- ++(__u32*)ptr;
- } else {
- return ptr;
- }
-#endif
}
return NULL;
}
#else
static int zft_read (struct inode *ino, struct file *fp, char *buff,
int req_len);
-#if LINUX_VERSION_CODE >= KERNEL_VER(1,3,0)
static int zft_write(struct inode *ino, struct file *fp, const char *buff,
int req_len);
-#else
-static int zft_write(struct inode *ino, struct file *fp, char *buff,
- int req_len);
-#endif
#endif
static struct file_operations zft_cdev =
#elif LINUX_VERSION_CODE >= KERNEL_VER(2,1,0)
static long zft_write(struct inode *ino, struct file *fp, const char *buff,
unsigned long req_len)
-#elif LINUX_VERSION_CODE >= KERNEL_VER(1,3,0)
-static int zft_write(struct inode *ino, struct file *fp, const char *buff,
- int req_len)
#else
-static int zft_write(struct inode *ino, struct file *fp, char *buff,
+static int zft_write(struct inode *ino, struct file *fp, const char *buff,
int req_len)
#endif
{
TRACE(ft_t_info,
"installing zftape VFS interface for ftape driver ...");
TRACE_CATCH(register_chrdev(QIC117_TAPE_MAJOR, "zft", &zft_cdev),);
-#if LINUX_VERSION_CODE >= KERNEL_VER(1,2,0)
-# if LINUX_VERSION_CODE < KERNEL_VER(2,1,18)
+#if LINUX_VERSION_CODE < KERNEL_VER(2,1,18)
register_symtab(&zft_symbol_table); /* add global zftape symbols */
-# endif
#endif
#ifdef CONFIG_ZFT_COMPRESSOR
(void)zft_compressor_init();
#ifdef MODULE
-#if LINUX_VERSION_CODE <= KERNEL_VER(1,2,13) && defined(MODULE)
-char kernel_version[] = UTS_RELEASE;
-#endif
#if LINUX_VERSION_CODE >= KERNEL_VER(2,1,18)
/* Called by modules package before trying to unload the module
*/
extern void acq_init(void);
extern void dtlk_init(void);
extern void pcwatchdog_init(void);
-extern int rtc_init(void);
extern int rtc_sun_init(void); /* Combines MK48T02 and MK48T08 */
extern int rtc_DP8570A_init(void);
extern int rtc_MK48T08_init(void);
#if defined(CONFIG_SUN_MOSTEK_RTC)
rtc_sun_init();
#endif
-#if defined(CONFIG_RTC)
- rtc_init();
-#endif
#ifdef CONFIG_ATARI_DSP56K
dsp56k_init();
#endif
#include <linux/config.h>
#include <linux/version.h>
-#if (defined(CONFIG_PCI) && (LINUX_VERSION_CODE >= 131072))
+#ifdef CONFIG_PCI
#define ENABLE_PCI
#endif
-#if (LINUX_VERSION_CODE > 66304)
#define NEW_MODULES
#ifdef LOCAL_ROCKET_H /* We're building standalone */
#define MODULE
#endif
-#endif
#ifdef NEW_MODULES
#ifdef MODVERSIONS
MODULE_PARM_DESC(support_low_speed, "0 means support 50 baud, 1 means support 460400 baud");
#endif
-/*
- * Provide backwards compatibility for kernels prior to 2.1.8.
- */
-#if (LINUX_VERSION_CODE < 0x20000)
-typedef dev_t kdev_t;
-#endif
-
#if (LINUX_VERSION_CODE < 131336)
int copy_from_user(void *to, const void *from_user, unsigned long len)
{
}
}
-#if (LINUX_VERSION_CODE > 66304)
static int rp_write(struct tty_struct * tty, int from_user,
const unsigned char *buf, int count)
-#else
-static int rp_write(struct tty_struct * tty, int from_user,
- unsigned char *buf, int count)
-#endif
{
struct r_port * info = (struct r_port *)tty->driver_data;
CHANNEL_t *cp;
* DEC Alpha as the CMOS clock is also used for other things.
* 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
* 1.09a Pete Zaitcev: Sun SPARC
+ * 1.09b Jeff Garzik: Modularize, init cleanup
*
*/
-#define RTC_VERSION "1.09a"
+#define RTC_VERSION "1.09b"
#define RTC_IRQ 8 /* Can't see this changing soon. */
#define RTC_IO_EXTENT 0x10 /* Only really two ports, but... */
* this driver.)
*/
+#include <linux/module.h>
+#include <linux/kernel.h>
#include <linux/types.h>
-#include <linux/errno.h>
#include <linux/miscdevice.h>
-#include <linux/malloc.h>
#include <linux/ioport.h>
#include <linux/fcntl.h>
#include <linux/mc146818rtc.h>
#include <linux/init.h>
#include <linux/poll.h>
+#include <linux/proc_fs.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/ebus.h>
static unsigned long rtc_port;
+static int rtc_irq;
#endif
/*
static inline unsigned char rtc_is_updating(void);
+static int rtc_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data);
+
/*
* Bits in rtc_status. (6 bits of room for future expansion)
*/
#define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */
#define RTC_TIMER_ON 0x02 /* missed irq timer active */
-unsigned char rtc_status = 0; /* bitmapped status byte. */
-unsigned long rtc_freq = 0; /* Current periodic IRQ rate */
-unsigned long rtc_irq_data = 0; /* our output to the world */
+static unsigned char rtc_status = 0; /* bitmapped status byte. */
+static unsigned long rtc_freq = 0; /* Current periodic IRQ rate */
+static unsigned long rtc_irq_data = 0; /* our output to the world */
/*
* If this driver ever becomes modularised, it will be really nice
static unsigned long epoch = 1900; /* year corresponding to 0x00 */
-unsigned char days_in_mo[] =
+static const unsigned char days_in_mo[] =
{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
/*
if(rtc_status & RTC_IS_OPEN)
return -EBUSY;
+ MOD_INC_USE_COUNT;
+
rtc_status |= RTC_IS_OPEN;
rtc_irq_data = 0;
return 0;
del_timer(&rtc_irq_timer);
}
+ MOD_DEC_USE_COUNT;
+
rtc_irq_data = 0;
rtc_status &= ~RTC_IS_OPEN;
return 0;
&rtc_fops
};
-int __init rtc_init(void)
+static int __init rtc_init(void)
{
unsigned long flags;
#ifdef __alpha__
#ifdef __sparc__
struct linux_ebus *ebus;
struct linux_ebus_device *edev;
- int rtc_irq;
#endif
printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION);
return -EIO;
}
misc_register(&rtc_dev);
+ create_proc_read_entry ("rtc", 0, NULL, rtc_read_proc, NULL);
+
/* Check region? Naaah! Just snarf it up. */
request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
#endif /* __sparc__ vs. others */
return 0;
}
+static void __exit rtc_exit (void)
+{
+ /* interrupts and timer disabled at this point by rtc_release */
+
+ remove_proc_entry ("rtc", NULL);
+ misc_deregister(&rtc_dev);
+
+#ifdef __sparc__
+ free_irq (rtc_irq, &rtc_port);
+#else
+ release_region (RTC_PORT (0), RTC_IO_EXTENT);
+ free_irq (RTC_IRQ, NULL);
+#endif /* __sparc__ */
+}
+
+module_init(rtc_init);
+module_exit(rtc_exit);
+EXPORT_NO_SYMBOLS;
+
/*
* At IRQ rates >= 4096Hz, an interrupt may get lost altogether.
* (usually during an IDE disk interrupt, with IRQ unmasking off)
* Info exported via "/proc/rtc".
*/
-int get_rtc_status(char *buf)
+static int rtc_get_status(char *buf)
{
char *p;
struct rtc_time tm;
return p - buf;
}
+static int rtc_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len = rtc_get_status(page);
+ if (len <= off+count) *eof = 1;
+ *start = page + off;
+ len -= off;
+ if (len>count) len = count;
+ if (len<0) len = 0;
+ return len;
+}
+
/*
* Returns true if a clock update is in progress
*/
#define CONFIG_HUB6
#endif
-#if (defined(CONFIG_PCI) && (LINUX_VERSION_CODE >= 131072))
+#ifdef CONFIG_PCI
#define ENABLE_SERIAL_PCI
#ifndef CONFIG_SERIAL_SHARE_IRQ
#define CONFIG_SERIAL_SHARE_IRQ
* End of serial driver configuration section.
*/
-#if (LINUX_VERSION_CODE > 66304)
#define NEW_MODULES
#ifdef LOCAL_HEADERS /* We're building standalone */
#define MODULE
#endif
-#endif
#ifdef NEW_MODULES
#ifdef MODVERSIONS
}
else
{
- if(m[2]&0x80000000)
+ if(m[2]&0x40000000)
{
int * ptr = (int *)m[3];
if(m[4]>>24)
int *query_done = &dev->done_flag;
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_CFLUSH<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = 60<<16;
i2o_post_wait(dev->controller, msg, 20, 2);
*/
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_MUNLOCK<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = -1;
i2o_post_wait(dev->controller, msg, 20, 2);
*/
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_MMOUNT<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = -1;
msg[5] = 0;
*/
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_MLOCK<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = -1;
i2o_post_wait(dev->controller, msg, 20, 2);
int *query_done = &dev->done_flag;
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_CFLUSH<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = 60<<16;
i2o_post_wait(dev->controller, msg, 20, 2);
*/
msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
msg[1] = I2O_CMD_BLOCK_MUNLOCK<<24|HOST_TID<<12|dev->tid;
- msg[2] = i2ob_context|0x80000000;
+ msg[2] = i2ob_context|0x40000000;
msg[3] = (u32)query_done;
msg[4] = -1;
i2o_post_wait(dev->controller, msg, 20, 2);
#include "i2o_lan.h"
-#define DRIVERDEBUG
+// #define DRIVERDEBUG
// #define DEBUG_IRQ
/*
{
if (msg[4] >> 24)
{
- i2o_report_status(KERN_WARNING, "i2o_core: post_wait reply", msg);
+ /* 0x40000000 is used as an error report supress bit */
+ if((msg[2]&0x40000000)==0)
+ i2o_report_status(KERN_WARNING, "i2o_core: post_wait reply", msg);
status = -(msg[4] & 0xFFFF);
}
else
c->hrt = NULL;
c->lct = NULL;
c->status_block = NULL;
- printk(KERN_INFO "lct @ %p hrt @ %p status @ %p",
- c->lct, c->hrt, c->status_block);
+// printk(KERN_INFO "lct @ %p hrt @ %p status @ %p",
+// c->lct, c->hrt, c->status_block);
sprintf(c->name, "i2o/iop%d", i);
i2o_num_controllers++;
spin_unlock(&i2o_configuration_lock);
*p=c->next;
spin_unlock(&i2o_configuration_lock);
- printk(KERN_INFO "hrt %p lct %p page_frame %p status_block %p\n",
- c->hrt, c->lct, c->page_frame, c->status_block);
+// printk(KERN_INFO "hrt %p lct %p page_frame %p status_block %p\n",
+// c->hrt, c->lct, c->page_frame, c->status_block);
if(c->page_frame)
kfree(c->page_frame);
if(c->hrt)
void i2o_report_controller_unit(struct i2o_controller *c, int unit)
{
char buf[64];
- return;
- if(i2o_query_scalar(c, unit, 0xF100, 3, buf, 16))
+ if(i2o_query_scalar(c, unit, 0xF100, 3, buf, 16)>=0)
{
buf[16]=0;
- printk(KERN_INFO " Vendor: %s\n", buf);
+ printk(KERN_INFO " Vendor: %s", buf);
}
- if(i2o_query_scalar(c, unit, 0xF100, 4, buf, 16))
+ if(i2o_query_scalar(c, unit, 0xF100, 4, buf, 16)>=0)
{
buf[16]=0;
- printk(KERN_INFO " Device: %s\n", buf);
+ printk(" Device: %s", buf);
}
#if 0
- if(i2o_query_scalar(c, unit, 0xF100, 5, buf, 16))
+ if(i2o_query_scalar(c, unit, 0xF100, 5, buf, 16)>=0)
{
buf[16]=0;
printk(KERN_INFO "Description: %s\n", buf);
}
#endif
- if(i2o_query_scalar(c, unit, 0xF100, 6, buf, 8))
+ if(i2o_query_scalar(c, unit, 0xF100, 6, buf, 8)>=0)
{
buf[8]=0;
- printk(KERN_INFO " Rev: %s\n", buf);
+ printk(" Rev: %s\n", buf);
}
}
d->flags = 0;
tid = d->lct_data->tid;
- printk(KERN_INFO "TID %d.\n", tid);
+ printk(KERN_INFO "Task ID %d.\n", tid);
i2o_report_controller_unit(c, tid);
i2o_install_device(c, d);
- printk(KERN_INFO " Class: ");
+ printk(KERN_INFO " Class: ");
sprintf(str, "%-21s", i2o_get_class_name(d->lct_data->class_id));
printk("%s", str);
- printk(" Subclass: 0x%03X Flags: ",
+ printk(" Subclass: 0x%04X Flags: ",
d->lct_data->sub_class);
if(d->lct_data->device_flags&(1<<0))
status_block = (u8*)c->status_block;
- for(i=0;i<5;i++)
- {
- m=i2o_wait_message(c, "StatusGet");
- if(m==0xFFFFFFFF)
- return -ETIMEDOUT;
-
- memset(status_block, 0, sizeof(i2o_status_block));
+ m=i2o_wait_message(c, "StatusGet");
+ if(m==0xFFFFFFFF)
+ return -ETIMEDOUT;
- msg=(u32 *)(c->mem_offset+m);
+ memset(status_block, 0, sizeof(i2o_status_block));
+ msg=(u32 *)(c->mem_offset+m);
__raw_writel(NINE_WORD_MSG_SIZE|SGL_OFFSET_0, &msg[0]);
- __raw_writel(I2O_CMD_STATUS_GET<<24|HOST_TID<<12|ADAPTER_TID, &msg[1]);
- __raw_writel(0, &msg[2]);
- __raw_writel(0, &msg[3]);
- __raw_writel(0, &msg[4]);
- __raw_writel(0, &msg[5]);
- __raw_writel(virt_to_bus(c->status_block), &msg[6]);
- __raw_writel(0, &msg[7]); /* 64bit host FIXME */
- __raw_writel(sizeof(i2o_status_block), &msg[8]);
-
- printk("SB is %d bytes.\n", sizeof(i2o_status_block));
-
- i2o_post_message(c,m);
-
- /* DPT work around */
- mdelay(5);
+ __raw_writel(I2O_CMD_STATUS_GET<<24|HOST_TID<<12|ADAPTER_TID, &msg[1]);
+ __raw_writel(0, &msg[2]);
+ __raw_writel(0, &msg[3]);
+ __raw_writel(0, &msg[4]);
+ __raw_writel(0, &msg[5]);
+ __raw_writel(virt_to_bus(c->status_block), &msg[6]);
+ __raw_writel(0, &msg[7]); /* 64bit host FIXME */
+ __raw_writel(sizeof(i2o_status_block), &msg[8]);
+
+ i2o_post_message(c,m);
+
+ /* DPT work around */
+ mdelay(5);
- /* Wait for a reply */
- time=jiffies;
+ /* Wait for a reply */
+ time=jiffies;
- while((jiffies-time)<=HZ)
+ while((jiffies-time)<=HZ)
+ {
+ if(status_block[87]!=0)
{
- if(status_block[87]!=0)
- {
- /* Ok the reply has arrived. Fill in the important stuff */
- c->inbound_size = (status_block[12]|(status_block[13]<<8))*4;
- return 0;
- }
- schedule();
- barrier();
+ /* Ok the reply has arrived. Fill in the important stuff */
+ c->inbound_size = (status_block[12]|(status_block[13]<<8))*4;
+ return 0;
}
+ schedule();
+ barrier();
+ }
#ifdef DRIVERDEBUG
- printk(KERN_ERR "IOP get status timeout.\n");
+ printk(KERN_ERR "IOP get status timeout.\n");
#endif
- }
- return 0;//-ETIMEDOUT;
+ return -ETIMEDOUT;
}
memset(workspace, 0, 88);
- printk(KERN_INFO "i2o/iop%d: Initializing Outbound Queue\n", c->unit);
+// printk(KERN_INFO "i2o/iop%d: Initializing Outbound Queue\n", c->unit);
m=i2o_wait_message(c, "OutboundInit");
if(m==0xFFFFFFFF)
{
size = i2o_issue_params(I2O_CMD_UTIL_PARAMS_GET, iop, tid,
opblk, sizeof(opblk), resblk, sizeof(resblk));
-
+
if (size < 0)
return size;
{
u8 reply[8];
- if(i2o_query_scalar(c, d->lct_data->tid, 0, 3, reply, 4))
+ if(i2o_query_scalar(c, d->lct_data->tid, 0, 3, reply, 4)<0)
return -1;
*target=reply[0];
- if(i2o_query_scalar(c, d->lct_data->tid, 0, 4, reply, 8))
+ if(i2o_query_scalar(c, d->lct_data->tid, 0, 4, reply, 8)<0)
return -1;
*lun=reply[1];
for(unit=c->devices;unit!=NULL;unit=unit->next)
{
dprintk(("Class %03X, parent %d, want %d.\n",
- unit->lct_data->class_id, unit->lct_data->parent, d->lct_data->tid));
+ unit->lct_data->class_id, unit->lct_data->parent_tid, d->lct_data->tid));
/* Only look at scsi and fc devices */
if ( (unit->lct_data->class_id != I2O_CLASS_SCSI_PERIPHERAL)
continue;
/* On our bus ? */
- dprintk(("Found a disk.\n"));
+ dprintk(("Found a disk (%d).\n", unit->lct_data->tid));
if ((unit->lct_data->parent_tid == d->lct_data->tid)
|| (unit->lct_data->parent_tid == d->lct_data->parent_tid)
)
dprintk(("Its ours.\n"));
if(i2o_find_lun(c, unit, &target, &lun)==-1)
{
- printk(KERN_ERR "i2o_scsi: Unable to get lun for tid %d.\n", d->lct_data->tid);
+ printk(KERN_ERR "i2o_scsi: Unable to get lun for tid %d.\n", unit->lct_data->tid);
continue;
}
dprintk(("Found disk %d %d.\n", target, lun));
* bus_adapter, SCSI (obsolete), or FibreChannel busses only
*/
if( (d->lct_data->class_id!=I2O_CLASS_BUS_ADAPTER_PORT) // bus_adapter
- && (d->lct_data->class_id!=I2O_CLASS_FIBRE_CHANNEL_PORT) // FC_PORT
+// && (d->lct_data->class_id!=I2O_CLASS_FIBRE_CHANNEL_PORT) // FC_PORT
)
continue;
* +1 (416) 297-6433 Facsimile
*/
-#if LINUX_VERSION_CODE < 131072
- #error You cant use this driver on kernels older than 2.0
-#else
- #define REQUEST_IRQ(a,b,c,d,e) request_irq(a,b,c,d,e)
- #define FREE_IRQ(a,b) free_irq(a,b)
-#endif
-
+#define REQUEST_IRQ(a,b,c,d,e) request_irq(a,b,c,d,e)
+#define FREE_IRQ(a,b) free_irq(a,b)
#define DECLARE_WAIT_QUEUE_HEAD(x) struct wait_queue * x = NULL
#endif
-static int acpi_idle_thread(void *context);
+static int acpi_control_thread(void *context);
static int acpi_do_ulong(ctl_table *ctl,
int write,
struct file *file,
struct file *file,
void *buffer,
size_t *len);
+#if 0
static int acpi_do_sleep_wake(ctl_table *ctl,
int write,
struct file *file,
void *buffer,
size_t *len);
+#endif
DECLARE_WAIT_QUEUE_HEAD(acpi_idle_wait);
static spinlock_t acpi_devs_lock = SPIN_LOCK_UNLOCKED;
static LIST_HEAD(acpi_devs);
-/* Make it impossible to enter L2/L3 until after we've initialized */
-static unsigned long acpi_p_lvl2_lat = ~0UL;
-static unsigned long acpi_p_lvl3_lat = ~0UL;
+/* Make it impossible to enter C2/C3 until after we've initialized */
+static unsigned long acpi_p_lvl2_lat = ACPI_INFINITE_LAT;
+static unsigned long acpi_p_lvl3_lat = ACPI_INFINITE_LAT;
+
+static unsigned long acpi_p_blk = 0;
-/* Initialize to guaranteed harmless port read */
-static unsigned long acpi_p_lvl2 = ACPI_P_LVL_DISABLED;
-static unsigned long acpi_p_lvl3 = ACPI_P_LVL_DISABLED;
+static int acpi_p_lvl2_tested = 0;
+static int acpi_p_lvl3_tested = 0;
// bits 8-15 are SLP_TYPa, bits 0-7 are SLP_TYPb
static unsigned long acpi_slp_typ[] =
{ACPI_EVENT, "event", NULL, 0, 0400, NULL, &acpi_do_event},
- {ACPI_P_LVL2, "p_lvl2",
- &acpi_p_lvl2, sizeof(acpi_p_lvl2),
- 0600, NULL, &acpi_do_ulong},
-
- {ACPI_P_LVL3, "p_lvl3",
- &acpi_p_lvl3, sizeof(acpi_p_lvl3),
+ {ACPI_P_BLK, "p_blk",
+ &acpi_p_blk, sizeof(acpi_p_blk),
0600, NULL, &acpi_do_ulong},
{ACPI_P_LVL2_LAT, "p_lvl2_lat",
return value;
}
+/*
+ * Set the value of the PM1 control register (BM_RLD, ...)
+ */
+static void acpi_write_pm1_control(struct acpi_facp *facp, u32 value)
+{
+ if (facp->pm1a_cnt)
+ outw(value, facp->pm1a_cnt);
+ if (facp->pm1b_cnt)
+ outw(value, facp->pm1b_cnt);
+}
+
/*
* Get the value of the fixed event status register
*/
acpi_facp->pm2_cnt_len = ACPI_PIIX4_PM2_CNT_LEN;
acpi_facp->pm_tm_len = ACPI_PIIX4_PM_TM_LEN;
acpi_facp->gpe0_len = ACPI_PIIX4_GPE0_LEN;
- acpi_facp->p_lvl2_lat = ~0;
- acpi_facp->p_lvl3_lat = ~0;
+ acpi_facp->p_lvl2_lat = (__u16) ACPI_INFINITE_LAT;
+ acpi_facp->p_lvl3_lat = (__u16) ACPI_INFINITE_LAT;
acpi_facp_addr = virt_to_phys(acpi_facp);
acpi_dsdt_addr = 0;
- acpi_p_lvl2 = base + ACPI_PIIX4_P_LVL2;
- acpi_p_lvl3 = base + ACPI_PIIX4_P_LVL3;
+ acpi_p_blk = base + ACPI_PIIX4_P_BLK;
return 0;
}
acpi_write_pm1_enable(facp, 0);
acpi_write_pm1_status(facp, acpi_read_pm1_status(facp));
- if (facp->smi_cmd)
- outb(facp->acpi_disable, facp->smi_cmd);
- return (acpi_is_enabled(facp) ? -1:0);
+ /* writing acpi_disable to smi_cmd would be appropriate
+ * here but this causes a nasty crash on many systems
+ */
+
+ return 0;
}
/*
- * Idle loop
+ * Idle loop (uniprocessor only)
*/
static void acpi_idle_handler(void)
{
static int sleep_level = 1;
- u32 timer, pm2_cnt;
- unsigned long time;
+ u32 pm1_cnt, timer, pm2_cnt, bm_active;
+ unsigned long time, usec;
+
+ // return to C0 on bus master request (necessary for C3 only)
+ pm1_cnt = acpi_read_pm1_control(acpi_facp);
+ if (sleep_level == 3) {
+ if (!(pm1_cnt & ACPI_BM_RLD)) {
+ pm1_cnt |= ACPI_BM_RLD;
+ acpi_write_pm1_control(acpi_facp, pm1_cnt);
+ }
+ }
+ else {
+ if (pm1_cnt & ACPI_BM_RLD) {
+ pm1_cnt &= ~ACPI_BM_RLD;
+ acpi_write_pm1_control(acpi_facp, pm1_cnt);
+ }
+ }
+
+ // clear bus master activity flag
+ acpi_write_pm1_status(acpi_facp, ACPI_BM);
// get current time (fallback to CPU cycles if no PM timer)
timer = acpi_facp->pm_tmr;
__asm__ __volatile__("sti ; hlt": : :"memory");
break;
case 2:
- inb(acpi_p_lvl2);
+ inb(acpi_p_blk + ACPI_P_LVL2);
break;
case 3:
pm2_cnt = acpi_facp->pm2_cnt;
if (pm2_cnt) {
- /* Disable PCI arbitration while sleeping,
- to avoid DMA corruption? */
+ /* Disable PCI arbitration while sleeping,
+ to avoid DMA corruption? */
outb(inb(pm2_cnt) | ACPI_ARB_DIS, pm2_cnt);
- inb(acpi_p_lvl3);
+ inb(acpi_p_blk + ACPI_P_LVL3);
outb(inb(pm2_cnt) & ~ACPI_ARB_DIS, pm2_cnt);
}
else {
- inb(acpi_p_lvl3);
+ inb(acpi_p_blk + ACPI_P_LVL3);
}
break;
}
else
time = ACPI_CPU_TO_TMR_TICKS(get_cycles() - time);
- if (time > acpi_p_lvl3_lat)
- sleep_level = 3;
- else if (time > acpi_p_lvl2_lat)
- sleep_level = 2;
- else
- sleep_level = 1;
+ // check for bus master activity
+ bm_active = (acpi_read_pm1_status(acpi_facp) & ACPI_BM);
+
+ // record working C2/C3
+ if (sleep_level == 2 && !acpi_p_lvl2_tested) {
+ acpi_p_lvl2_tested = 1;
+ printk(KERN_INFO "ACPI: C2 works\n");
+ }
+ else if (sleep_level == 3 && !acpi_p_lvl3_tested) {
+ acpi_p_lvl3_tested = 1;
+ printk(KERN_INFO "ACPI: C3 works\n");
+ }
+
+ // pick next C-state based on time spent sleeping,
+ // C-state latencies, and bus master activity
+ sleep_level = 1;
+ if (acpi_p_blk) {
+ usec = ACPI_TMR_TICKS_TO_uS(time);
+ if (usec > acpi_p_lvl3_lat && !bm_active)
+ sleep_level = 3;
+ else if (usec > acpi_p_lvl2_lat)
+ sleep_level = 2;
+ }
}
/*
/*
* Enter system sleep state
*/
-static void acpi_enter_sx(int state)
+static void acpi_enter_sx(acpi_sstate_t state)
{
- unsigned long slp_typ = acpi_slp_typ[state];
+ unsigned long slp_typ = acpi_slp_typ[(int) state];
if (slp_typ != ACPI_SLP_TYP_DISABLED) {
u16 typa, typb, value;
typa = ((typa << ACPI_SLP_TYP_SHIFT) & ACPI_SLP_TYP_MASK);
typb = ((typb << ACPI_SLP_TYP_SHIFT) & ACPI_SLP_TYP_MASK);
+ if (state != ACPI_S0) {
+ acpi_enter_dx(ACPI_D3);
+ }
+
// set SLP_TYPa/b and SLP_EN
if (acpi_facp->pm1a_cnt) {
value = inw(acpi_facp->pm1a_cnt) & ~ACPI_SLP_TYP_MASK;
value = inw(acpi_facp->pm1b_cnt) & ~ACPI_SLP_TYP_MASK;
outw(value | typb | ACPI_SLP_EN, acpi_facp->pm1b_cnt);
}
+
+ if (state == ACPI_S0) {
+ acpi_enter_dx(ACPI_D0);
+ }
}
}
*/
static void acpi_power_off_handler(void)
{
- acpi_enter_sx(5);
+ acpi_enter_sx(ACPI_S5);
}
/*
return 0;
}
+#if 0
/*
* Sleep or wake system
*/
file->f_pos += *len;
return 0;
}
+#endif
/*
* Initialize and enable ACPI
return -ENODEV;
}
+ if (acpi_facp->p_lvl2_lat
+ && acpi_facp->p_lvl2_lat <= ACPI_MAX_P_LVL2_LAT) {
+ acpi_p_lvl2_lat = acpi_facp->p_lvl2_lat;
+ }
+ if (acpi_facp->p_lvl3_lat
+ && acpi_facp->p_lvl3_lat <= ACPI_MAX_P_LVL3_LAT) {
+ acpi_p_lvl3_lat = acpi_facp->p_lvl3_lat;
+ }
+
if (acpi_facp->sci_int
&& request_irq(acpi_facp->sci_int,
acpi_irq,
acpi_claim_ioports(acpi_facp);
acpi_sysctl = register_sysctl_table(acpi_dir_table, 1);
- pid = kernel_thread(acpi_idle_thread,
+ pid = kernel_thread(acpi_control_thread,
NULL,
CLONE_FS | CLONE_FILES | CLONE_SIGHAND);
+ acpi_power_off = acpi_power_off_handler;
+
/*
* Set up the ACPI idle function. Note that we can't really
* do this with multiple CPU's, we'd need a per-CPU ACPI
return 0;
#endif
- acpi_power_off = acpi_power_off_handler;
acpi_idle = acpi_idle_handler;
return 0;
/*
* Manage idle devices
*/
-static int acpi_idle_thread(void *context)
+static int acpi_control_thread(void *context)
{
exit_mm(current);
exit_files(current);
pkt_len, rx_status);
if (skb != NULL) {
skb->dev = dev;
-#if LINUX_VERSION_CODE >= 0x10300
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
/* 'skb_put()' points to the start of sk_buff data area. */
insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
(pkt_len + 3) >> 2);
outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
skb->protocol = eth_type_trans(skb, dev);
-#else
- skb->len = pkt_len;
- /* 'skb->data' points to the start of sk_buff data area. */
- insl(ioaddr + RX_FIFO, skb->data, (pkt_len + 3) >> 2);
- outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
-#endif /* KERNEL_1_3_0 */
netif_rx(skb);
dev->last_rx = jiffies;
vp->stats.rx_packets++;
skb->head, temp);
rx_nocopy++;
}
-#if LINUX_VERSION_CODE > 0x10300
skb->protocol = eth_type_trans(skb, dev);
-#else
- skb->len = pkt_len;
-#endif
netif_rx(skb);
dev->last_rx = jiffies;
vp->stats.rx_packets++;
if (skb == NULL)
break; /* Bad news! */
skb->dev = dev; /* Mark as being used by this device. */
-#if LINUX_VERSION_CODE > 0x10300
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
vp->rx_ring[entry].addr = virt_to_bus(skb->tail);
-#else
- vp->rx_ring[entry].addr = virt_to_bus(skb->data);
-#endif
vp->rx_skbuff[entry] = skb;
}
vp->rx_ring[entry].status = 0; /* Clear complete bit. */
if (skb == NULL)
break; /* Bad news! */
skb->dev = dev; /* Mark as being used by this device. */
-#if LINUX_VERSION_CODE >= 0x10300
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
vp->rx_ring[i].addr = cpu_to_le32(virt_to_bus(skb->tail));
-#else
- vp->rx_ring[i].addr = virt_to_bus(skb->data);
-#endif
}
/* Wrap the ring. */
vp->rx_ring[i-1].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[0]));
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
break;
-#if ! defined(final_version) && LINUX_VERSION_CODE >= 0x10300
+#if ! defined(final_version)
if (vp->full_bus_master_tx) {
int i;
printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d "
tristate ' NI6510 support' CONFIG_NI65
fi
if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
- # tristate ' Packet Engines Hamachi GNIC-II support (EXPERIMENTAL)' CONFIG_HAMACHI
- tristate ' Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)' CONFIG_YELLOWFIN
tristate ' RealTek 8129/8139 (not 8019/8029!) support (EXPERIMENTAL)' CONFIG_RTL8139
tristate ' DM9102 PCI Fast Ethernet Adapter support (EXPERIMENTAL)' CONFIG_DM9102
fi
if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
tristate ' Adaptec Starfire support (EXPERIMENTAL)' CONFIG_ADAPTEC_STARFIRE
fi
- tristate ' Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support' CONFIG_ACENIC
- if [ "$CONFIG_ACENIC" != "n" ]; then
- bool ' Omit support for old Tigon I based AceNICs' CONFIG_ACENIC_OMIT_TIGON_I
- fi
if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
tristate ' Ansel Communications EISA 3200 support (EXPERIMENTAL)' CONFIG_AC3200
fi
endmenu
+#
+# Gigabit Ethernet
+#
+
+mainmenu_option next_comment
+comment 'Ethernet (1000 Mbit)'
+
+ if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
+ # tristate 'Packet Engines Hamachi GNIC-II support (EXPERIMENTAL)' CONFIG_HAMACHI
+ tristate 'Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)' CONFIG_YELLOWFIN
+ fi
+ tristate 'Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support' CONFIG_ACENIC
+ if [ "$CONFIG_ACENIC" != "n" ]; then
+ bool ' Omit support for old Tigon I based AceNICs' CONFIG_ACENIC_OMIT_TIGON_I
+ fi
+ tristate 'SysKonnect SK-98xx support' CONFIG_SK98LIN
+endmenu
+
bool 'FDDI driver support' CONFIG_FDDI
if [ "$CONFIG_FDDI" = "y" ]; then
bool ' Digital DEFEA and DEFPA adapter support' CONFIG_DEFXX
SUB_DIRS :=
MOD_SUB_DIRS :=
MOD_IN_SUB_DIRS :=
-ALL_SUB_DIRS := $(SUB_DIRS) fc hamradio irda pcmcia tokenring wan
+ALL_SUB_DIRS := $(SUB_DIRS) fc hamradio irda pcmcia tokenring wan sk98lin
O_TARGET := net.o
O_OBJS :=
endif
endif
+ifeq ($(CONFIG_SK98LIN),y)
+SUB_DIRS += sk98lin
+MOD_IN_SUB_DIRS += sk98lin
+L_OBJS += sk98lin/sk98lin.o
+else
+ ifeq ($(CONFIG_SK98LIN),m)
+ MOD_IN_SUB_DIRS += sk98lin
+ endif
+endif
+
ifeq ($(CONFIG_TR),y)
SUB_DIRS += tokenring
MOD_IN_SUB_DIRS += tokenring
M_OBJS := $(sort $(filter-out $(export-objs), $(obj-m)))
MX_OBJS := $(sort $(filter $(export-objs), $(obj-m)))
-O_OBJS += $(O_OBJS)
-O_OBJS += $(OX_OBJS)
O_OBJS += auto_irq.o
include $(TOPDIR)/Rules.make
unsigned char *buf;
struct net_device *dev;
- if (dev_get(name) != NULL)
+ if (dev_get(name))
{
printk(KERN_INFO "Z8530drv: device %s already exists.\n", name);
return -EEXIST;
endif
ifeq ($(CONFIG_IRPORT_SIR),y)
-L_OBJS += irport.o
+LX_OBJS += irport.o
else
ifeq ($(CONFIG_IRPORT_SIR),m)
- M_OBJS += irport.o
- endif
-endif
-
-ifeq ($(CONFIG_IRPORT_SIR),y)
-L_OBJS += irport.o
-else
- ifeq ($(CONFIG_IRPORT_SIR),m)
- M_OBJS += irport.o
- endif
-endif
-
-ifeq ($(CONFIG_IRPORT_SIR),y)
-L_OBJS += irport.o
-else
- ifeq ($(CONFIG_IRPORT_SIR),m)
- M_OBJS += irport.o
+ MX_OBJS += irport.o
endif
endif
endif
endif
-ifeq ($(CONFIG_TOSHIBA_FIR),y)
-L_OBJS += toshoboe.o
-else
- ifeq ($(CONFIG_TOSHIBA_FIR),m)
- M_OBJS += toshoboe.o
- endif
-endif
-
-ifeq ($(CONFIG_TOSHIBA_FIR),y)
-L_OBJS += toshoboe.o
-else
- ifeq ($(CONFIG_TOSHIBA_FIR),m)
- M_OBJS += toshoboe.o
- endif
-endif
-
ifeq ($(CONFIG_SMC_IRCC_FIR),y)
-L_OBJS += irport.o smc-ircc.o
+L_OBJS += smc-ircc.o
+LX_OBJS += irport.o
else
ifeq ($(CONFIG_SMC_IRCC_FIR),m)
- M_OBJS += irport.o smc-ircc.o
+ M_OBJS += smc-ircc.o
+ MX_OBJS += irport.o
endif
endif
endif
endif
-ifeq ($(CONFIG_LITELINK_DONGLE),y)
-L_OBJS += litelink.o
-else
- ifeq ($(CONFIG_LITELINK_DONGLE),m)
- M_OBJS += litelink.o
- endif
-endif
-
-ifeq ($(CONFIG_LITELINK_DONGLE),y)
-L_OBJS += litelink.o
-else
- ifeq ($(CONFIG_LITELINK_DONGLE),m)
- M_OBJS += litelink.o
- endif
-endif
-
ifeq ($(CONFIG_AIRPORT_DONGLE),y)
L_OBJS += airport.o
else
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sun Aug 3 13:49:59 1997
- * Modified at: Sat Oct 30 20:03:42 1999
+ * Modified at: Sat Nov 13 23:25:56 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
* Sources: serial.c by Linus Torvalds
*
static int irport_set_dtr_rts(struct net_device *dev, int dtr, int rts);
static int irport_raw_write(struct net_device *dev, __u8 *buf, int len);
static struct net_device_stats *irport_net_get_stats(struct net_device *dev);
+static int irport_change_speed_complete(struct irda_task *task);
+
+EXPORT_SYMBOL(irport_change_speed);
int __init irport_init(void)
{
* State machine for changing speed of the device. We do it this way since
* we cannot use schedule_timeout() when we are in interrupt context
*/
-static int irport_change_speed(struct irda_task *task)
+int irport_change_speed(struct irda_task *task)
{
struct irport_cb *self;
__u32 speed = (__u32) task->param;
IRDA_DEBUG(4, __FUNCTION__ "()\n");
+ iobase = self->io.iobase2;
+
/* Finished with frame? */
if (self->tx_buff.len > 0) {
/* Write data left in transmit buffer */
- actual = irport_write(self->io.iobase2, self->io.fifo_size,
+ actual = irport_write(iobase, self->io.fifo_size,
self->tx_buff.data, self->tx_buff.len);
self->tx_buff.data += actual;
self->tx_buff.len -= actual;
} else {
- iobase = self->io.iobase2;
+
/*
* Now serial buffer is almost free & we can start
- * transmission of another packet
+ * transmission of another packet. But first we must check
+ * if we need to change the speed of the hardware
*/
- self->netdev->tbusy = 0; /* Unlock */
+ if (self->new_speed) {
+ IRDA_DEBUG(5, __FUNCTION__ "(), Changing speed!\n");
+ irda_task_execute(self, irport_change_speed,
+ irport_change_speed_complete,
+ NULL, (void *) self->new_speed);
+ self->new_speed = 0;
+ } else {
+ self->netdev->tbusy = 0; /* Unlock */
+
+ /* Tell network layer that we want more frames */
+ mark_bh(NET_BH);
+ }
self->stats.tx_packets++;
/* Schedule network layer, so we can get some more frames */
mark_bh(NET_BH);
+ /*
+ * Reset Rx FIFO to make sure that all reflected transmit data
+ * is discarded. This is needed for half duplex operation
+ */
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
-
if (self->io.speed < 38400)
fcr |= UART_FCR_TRIGGER_1;
else
fcr |= UART_FCR_TRIGGER_14;
- /*
- * Reset Rx FIFO to make sure that all reflected transmit data
- * will be discarded
- */
outb(fcr, iobase+UART_FCR);
/* Turn on receive interrupts */
- outb(/* UART_IER_RLSI| */UART_IER_RDI, iobase+UART_IER);
+ outb(UART_IER_RDI, iobase+UART_IER);
}
}
}
/* Check if we need to change the speed */
- if ((speed = irda_get_speed(skb)) != self->io.speed) {
- if (irda_task_execute(self, irport_change_speed,
- irport_change_speed_complete, NULL,
- (void *) speed))
- /*
- * Task not finished yet, so make the netdevice
- * layer requeue the frame
- */
- return -EBUSY;
- }
+ if ((speed = irda_get_speed(skb)) != self->io.speed)
+ self->new_speed = speed;
+
spin_lock_irqsave(&self->lock, flags);
/* Init tx buffer */
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Tue Dec 9 21:18:38 1997
- * Modified at: Sun Oct 31 22:24:03 1999
+ * Modified at: Tue Nov 16 02:50:37 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
* Sources: slip.c by Laurence Culhane, <loz@holmes.demon.co.uk>
* Fred N. van Kempen, <waltje@uwalt.nl.mugnet.org>
switch (task->state) {
case IRDA_TASK_INIT:
- case IRDA_TASK_WAIT:
- /* Are we ready to change speed yet? */
+ /*
+ * Make sure all data is sent before changing the speed of the
+ * serial port.
+ */
if (self->tty->driver.chars_in_buffer(self->tty)) {
- task->state = IRDA_TASK_WAIT;
-
- /* Try again later */
- ret = MSECS_TO_JIFFIES(20);
+ /* Keep state, and try again later */
+ ret = MSECS_TO_JIFFIES(10);
break;
+ } else {
+ /* Transmit buffer is now empty, but it may still
+ * take over 13 ms for the FIFO to become empty, so
+ * wait some more to be sure all data is sent
+ */
+ irda_task_next_state(task, IRDA_TASK_WAIT);
+ ret = MSECS_TO_JIFFIES(13);
}
-
+ case IRDA_TASK_WAIT:
if (self->dongle)
irda_task_next_state(task, IRDA_TASK_CHILD_INIT);
else
return -EBUSY;
/* Check if we need to change the speed */
- if ((speed = irda_get_speed(skb)) != self->io.speed) {
- if (irda_task_execute(self, irtty_change_speed,
- irtty_change_speed_complete, NULL,
- (void *) speed))
- /*
- * Task not finished yet, so make the netdevice
- * layer requeue the frame
- */
- return -EBUSY;
- }
+ if ((speed = irda_get_speed(skb)) != self->io.speed)
+ self->new_speed = speed;
/* Init tx buffer*/
self->tx_buff.data = self->tx_buff.head;
actual = self->tty->driver.write(self->tty, 0,
self->tx_buff.data,
self->tx_buff.len);
-
/* Hide the part we just transmitted */
self->tx_buff.data += actual;
self->tx_buff.len -= actual;
self->stats.tx_packets++;
self->stats.tx_bytes += self->tx_buff.len;
-#if 0
- /*
- * Did we transmit the whole frame? Commented out for now since
- * I must check if this optimalization really works. DB.
- */
- if ((self->tx_buff.len) == 0) {
- IRDA_DEBUG( 4, "irtty_xmit_buf: finished with frame!\n");
- self->tty->flags &= ~(1 << TTY_DO_WRITE_WAKEUP);
- irda_unlock( &self->tbusy);
- }
-#endif
+
dev_kfree_skb(skb);
return 0;
tty->flags &= ~(1 << TTY_DO_WRITE_WAKEUP);
- self->netdev->tbusy = 0; /* Unlock */
-
- /* Tell network layer that we want more frames */
- mark_bh(NET_BH);
+ if (self->new_speed) {
+ IRDA_DEBUG(5, __FUNCTION__ "(), Changing speed!\n");
+ irda_task_execute(self, irtty_change_speed,
+ irtty_change_speed_complete,
+ NULL, (void *) self->new_speed);
+ self->new_speed = 0;
+ } else {
+ self->netdev->tbusy = 0; /* Unlock */
+
+ /* Tell network layer that we want more frames */
+ mark_bh(NET_BH);
+ }
}
}
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sat Nov 7 21:43:15 1998
- * Modified at: Sat Oct 30 16:24:17 1999
+ * Modified at: Sat Nov 13 23:54:59 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>
{
struct pc87108 *self;
int iobase;
+ __u32 speed;
__u8 bank;
int mtt;
iobase = self->io.iobase;
- IRDA_DEBUG(4, __FUNCTION__ "(%ld), skb->len=%d\n", jiffies, (int) skb->len);
+ IRDA_DEBUG(4, __FUNCTION__ "(%ld), skb->len=%d\n", jiffies,
+ (int) skb->len);
/* Lock transmit buffer */
if (irda_lock((void *) &dev->tbusy) == FALSE)
return -EBUSY;
+ /* Check if we need to change the speed */
+ if ((speed = irda_get_speed(skb)) != self->io.speed)
+ self->new_speed = speed;
+
/* Save current bank */
bank = inb(iobase+BSR);
self->stats.tx_bytes += self->tx_buff.len;
}
+ if (self->new_speed) {
+ pc87108_change_speed(self, self->new_speed);
+ self->new_speed = 0;
+ }
+
/* Unlock tx_buff and request another frame */
self->netdev->tbusy = 0; /* Unlock */
* Status: Experimental.
* Author: Thomas Davis (tadavis@jps.net)
* Created at:
- * Modified at: Sat Oct 30 14:18:23 1999
+ * Modified at: Fri Nov 12 21:08:09 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Thomas Davis, All Rights Reserved.
serial_out(iobase, UART_MASTER, UART_MASTER_RESET);
serial_out(iobase, UART_MASTER, UART_MASTER_INT_EN);
irport_start(&self->irport, self->io.iobase2);
- irport_change_speed(&self->irport, speed);
+ __irport_change_speed(&self->irport, speed);
return;
break;
/* Check if we need to change the speed */
if ((speed = irda_get_speed(skb)) != self->io.speed)
- toshoboe_setbaud (self, speed);
+ self->new_speed = speed;
if (self->stopped) {
dev_kfree_skb(skb);
self->stats.tx_packets++;
- /* idev->media_busy = FALSE; */
- self->netdev->tbusy = 0;
-
- mark_bh (NET_BH);
+ if (self->new_speed) {
+ toshoboe_setbaud(self, self->new_speed);
+ self->new_speed = 0;
+ }
+ self->netdev->tbusy = 0; /* Unlock */
+
+ /* Tell network layer that we want more frames */
+ mark_bh(NET_BH);
}
if (irqstat & OBOE_ISR_RXDONE)
* Status: Experimental.
* Author: Paul VanderSpek
* Created at: Wed Nov 4 11:46:16 1998
- * Modified at: Sat Oct 30 16:24:32 1999
+ * Modified at: Mon Nov 8 10:05:48 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>
/* Check if we need to change the speed */
if ((speed = irda_get_speed(skb)) != self->io.speed)
- w83977af_change_speed(self, speed);
+ self->new_speed = speed;
/* Save current set */
set = inb(iobase+SSR);
} else
self->stats.tx_packets++;
+
+ if (self->new_speed) {
+ w83977af_change_speed(self, self->new_speed);
+ self->new_speed = 0;
+ }
+
/* Unlock tx_buff and request another frame */
self->netdev->tbusy = 0; /* Unlock */
vortex_interrupt(dev->irq, dev, 0);
}
-#if ! defined(final_version) && LINUX_VERSION_CODE >= 0x10300
+#if ! defined(final_version)
if (vp->full_bus_master_tx) {
int i;
printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d "
extern int rtl8139_probe(void);
extern int sdla_setup(void);
extern int sis900_probe(void);
+extern int skge_probe(void);
extern int sparc_lance_probe(void);
extern int starfire_probe(void);
extern int tc59x_probe(void);
#ifdef CONFIG_ACENIC
{acenic_probe, 0},
#endif
+#ifdef CONFIG_SK98LIN
+ {skge_probe, 0},
+#endif
#ifdef CONFIG_VIA_RHINE
{via_rhine_probe, 0},
#endif
--- /dev/null
+# File: drivers/sk98lin/Makefile
+#
+# Makefile for the SysKonnect SK-98xx device driver.
+#
+
+ifeq ($(CONFIG_SK98LIN),y)
+ O_TARGET := sk98lin.o
+ O_OBJS = skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
+ ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
+ skxmac2.o skcsum.o
+else
+ ifeq ($(CONFIG_SK98LIN),m)
+ MOD_LIST_NAME := SK98LIN_MODULES
+ M_OBJS := sk98lin.o
+ O_TARGET := sk98lin.o
+ O_OBJS = skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
+ ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
+ skxmac2.o skcsum.o
+ endif
+endif
+
+# DBGDEF = \
+# -DDEBUG
+
+ifdef DEBUG
+DBGDEF += \
+-DSK_DEBUG_CHKMOD=0x00000000L \
+-DSK_DEBUG_CHKCAT=0x00000000L
+endif
+
+
+# **** possible debug modules for SK_DEBUG_CHKMOD *****************
+# SK_DBGMOD_MERR 0x00000001L /* general module error indication */
+# SK_DBGMOD_HWM 0x00000002L /* Hardware init module */
+# SK_DBGMOD_RLMT 0x00000004L /* RLMT module */
+# SK_DBGMOD_VPD 0x00000008L /* VPD module */
+# SK_DBGMOD_I2C 0x00000010L /* I2C module */
+# SK_DBGMOD_PNMI 0x00000020L /* PNMI module */
+# SK_DBGMOD_CSUM 0x00000040L /* CSUM module */
+# SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
+# SK_DBGMOD_DRV 0x00010000L /* DRV module */
+
+# **** possible debug categories for SK_DEBUG_CHKCAT **************
+# *** common modules ***
+# SK_DBGCAT_INIT 0x00000001L module/driver initialization
+# SK_DBGCAT_CTRL 0x00000002L controlling: add/rmv MCA/MAC and other controls (IOCTL)
+# SK_DBGCAT_ERR 0x00000004L error handling paths
+# SK_DBGCAT_TX 0x00000008L transmit path
+# SK_DBGCAT_RX 0x00000010L receive path
+# SK_DBGCAT_IRQ 0x00000020L general IRQ handling
+# SK_DBGCAT_QUEUE 0x00000040L any queue management
+# SK_DBGCAT_DUMP 0x00000080L large data output e.g. hex dump
+# SK_DBGCAT_FATAL 0x00000100L large data output e.g. hex dump
+
+# *** driver (file skge.c) ***
+# SK_DBGCAT_DRV_ENTRY 0x00010000 entry points
+# SK_DBGCAT_DRV_??? 0x00020000 not used
+# SK_DBGCAT_DRV_MCA 0x00040000 multicast
+# SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 tx path
+# SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 rx path
+# SK_DBGCAT_DRV_PROGRESS 0x00200000 general runtime
+# SK_DBGCAT_DRV_??? 0x00400000 not used
+# SK_DBGCAT_DRV_PROM 0x00800000 promiscuous mode
+# SK_DBGCAT_DRV_TX_FRAME 0x01000000 display tx frames
+# SK_DBGCAT_DRV_ERROR 0x02000000 error conditions
+# SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
+# SK_DBGCAT_DRV_EVENT 0x08000000 driver events
+
+EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF)
+
+include $(TOPDIR)/Rules.make
+
+clean:
+ rm -f core *.o *.a *.s
+
+
+
+
+
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: lm80.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.2 $
+ * Date: $Date: 1999/03/12 13:26:51 $
+ * Purpose: Contains all defines for the LM80 Chip
+ * (National Semiconductor).
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ * $Log: lm80.h,v $
+ * Revision 1.2 1999/03/12 13:26:51 malthoff
+ * remove __STDC__.
+ *
+ * Revision 1.1 1998/06/19 09:28:31 malthoff
+ * created.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_LM80_H
+#define __INC_LM80_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * LM80 register definition
+ *
+ * All registers are 8 bit wide
+ */
+#define LM80_CFG 0x00 /* Configuration Register */
+#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */
+#define LM80_ISRC_2 0x02 /* Interrupt Status Register 2 */
+#define LM80_IMSK_1 0x03 /* Interrupt Mask Register 1 */
+#define LM80_IMSK_2 0x04 /* Interrupt Mask Register 2 */
+#define LM80_FAN_CTRL 0x05 /* Fan Devisor/RST#/OS# Register */
+#define LM80_TEMP_CTRL 0x06 /* OS# Config, Temp Res. Reg */
+ /* 0x07 - 0x1f reserved */
+ /* current values */
+#define LM80_VT0_IN 0x20 /* current Voltage 0 value */
+#define LM80_VT1_IN 0x21 /* current Voltage 1 value */
+#define LM80_VT2_IN 0x22 /* current Voltage 2 value */
+#define LM80_VT3_IN 0x23 /* current Voltage 3 value */
+#define LM80_VT4_IN 0x24 /* current Voltage 4 value */
+#define LM80_VT5_IN 0x25 /* current Voltage 5 value */
+#define LM80_VT6_IN 0x26 /* current Voltage 6 value */
+#define LM80_TEMP_IN 0x27 /* current temperature value */
+#define LM80_FAN1_IN 0x28 /* current Fan 1 count */
+#define LM80_FAN2_IN 0x29 /* current Fan 2 count */
+ /* limit values */
+#define LM80_VT0_HIGH_LIM 0x2a /* high limit val for Voltage 0 */
+#define LM80_VT0_LOW_LIM 0x2b /* low limit val for Voltage 0 */
+#define LM80_VT1_HIGH_LIM 0x2c /* high limit val for Voltage 1 */
+#define LM80_VT1_LOW_LIM 0x2d /* low limit val for Voltage 1 */
+#define LM80_VT2_HIGH_LIM 0x2e /* high limit val for Voltage 2 */
+#define LM80_VT2_LOW_LIM 0x2f /* low limit val for Voltage 2 */
+#define LM80_VT3_HIGH_LIM 0x30 /* high limit val for Voltage 3 */
+#define LM80_VT3_LOW_LIM 0x31 /* low limit val for Voltage 3 */
+#define LM80_VT4_HIGH_LIM 0x32 /* high limit val for Voltage 4 */
+#define LM80_VT4_LOW_LIM 0x33 /* low limit val for Voltage 4 */
+#define LM80_VT5_HIGH_LIM 0x34 /* high limit val for Voltage 5 */
+#define LM80_VT5_LOW_LIM 0x35 /* low limit val for Voltage 5 */
+#define LM80_VT6_HIGH_LIM 0x36 /* high limit val for Voltage 6 */
+#define LM80_VT6_LOW_LIM 0x37 /* low limit val for Voltage 6 */
+#define LM80_THOT_LIM_UP 0x38 /* hot temperature limit (high) */
+#define LM80_THOT_LIM_LO 0x39 /* hot temperature limit (low) */
+#define LM80_TOS_LIM_UP 0x3a /* OS temperature limit (high) */
+#define LM80_TOS_LIM_LO 0x3b /* OS temperature limit (low) */
+#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */
+#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */
+ /* 0x3e - 0x3f reserved */
+
+/*
+ * LM80 bit definitions
+ */
+
+/* LM80_CFG Configuration Register */
+#define LM80_CFG_START (1<<0) /* start monitoring operation */
+#define LM80_CFG_INT_ENA (1<<1) /* enables the INT# Interrupt output */
+#define LM80_CFG_INT_POL (1<<2) /* INT# pol: 0 act low, 1 act high */
+#define LM80_CFG_INT_CLR (1<<3) /* disables INT#/RST_OUT#/OS# outputs */
+#define LM80_CFG_RESET (1<<4) /* signals a reset */
+#define LM80_CFG_CHASS_CLR (1<<5) /* clears Chassis Intrusion (CI) pin */
+#define LM80_CFG_GPO (1<<6) /* drives the GPO# pin */
+#define LM80_CFG_INIT (1<<7) /* restore power on defaults */
+
+/* LM80_ISRC_1 Interrupt Status Register 1 */
+/* LM80_IMSK_1 Interrupt Mask Register 1 */
+#define LM80_IS_VT0 (1<<0) /* limit exceeded for Voltage 0 */
+#define LM80_IS_VT1 (1<<1) /* limit exceeded for Voltage 1 */
+#define LM80_IS_VT2 (1<<2) /* limit exceeded for Voltage 2 */
+#define LM80_IS_VT3 (1<<3) /* limit exceeded for Voltage 3 */
+#define LM80_IS_VT4 (1<<4) /* limit exceeded for Voltage 4 */
+#define LM80_IS_VT5 (1<<5) /* limit exceeded for Voltage 5 */
+#define LM80_IS_VT6 (1<<6) /* limit exceeded for Voltage 6 */
+#define LM80_IS_INT_IN (1<<7) /* state of INT_IN# */
+
+/* LM80_ISRC_2 Interrupt Status Register 2 */
+/* LM80_IMSK_2 Interrupt Mask Register 2 */
+#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */
+#define LM80_IS_BTI (1<<1) /* state of BTI# pin */
+#define LM80_IS_FAN1 (1<<2) /* count limit exceeded for Fan 1 */
+#define LM80_IS_FAN2 (1<<3) /* count limit exceeded for Fan 2 */
+#define LM80_IS_CI (1<<4) /* Chassis Intrusion occured */
+#define LM80_IS_OS (1<<5) /* OS temperature limit exceeded */
+ /* bit 6 and 7 are reserved in LM80_ISRC_2 */
+#define LM80_IS_HT_IRQ_MD (1<<6) /* Hot temperature interrupt mode */
+#define LM80_IS_OT_IRQ_MD (1<<7) /* OS temperature interrupt mode */
+
+/* LM80_FAN_CTRL Fan Devisor/RST#/OS# Register */
+#define LM80_FAN1_MD_SEL (1<<0) /* Fan 1 mode select */
+#define LM80_FAN2_MD_SEL (1<<1) /* Fan 2 mode select */
+#define LM80_FAN1_PRM_CTL (3<<2) /* Fan 1 speed control */
+#define LM80_FAN2_PRM_CTL (3<<4) /* Fan 2 speed control */
+#define LM80_FAN_OS_ENA (1<<6) /* enable OS mode on RST_OUT#/OS# pins*/
+#define LM80_FAN_RST_ENA (1<<7) /* sets RST_OUT#/OS# pins in RST mode */
+
+/* LM80_TEMP_CTRL OS# Config, Temp Res. Reg */
+#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */
+#define LM80_TEMP_OS_POL (1<<1) /* select OS# polarity */
+#define LM80_TEMP_OS_MODE (1<<2) /* selects Interrupt mode */
+#define LM80_TEMP_RES (1<<3) /* selects 9 or 11 bit temp resulution*/
+#define LM80_TEMP_LSB (0xf<<4)/* 4 LSBs of 11 bit temp data */
+#define LM80_TEMP_LSB_9 (1<<7) /* LSB of 9 bit temperature data */
+
+ /* 0x07 - 0x1f reserved */
+/* LM80_VT0_IN current Voltage 0 value */
+/* LM80_VT1_IN current Voltage 1 value */
+/* LM80_VT2_IN current Voltage 2 value */
+/* LM80_VT3_IN current Voltage 3 value */
+/* LM80_VT4_IN current Voltage 4 value */
+/* LM80_VT5_IN current Voltage 5 value */
+/* LM80_VT6_IN current Voltage 6 value */
+/* LM80_TEMP_IN current temperature value */
+/* LM80_FAN1_IN current Fan 1 count */
+/* LM80_FAN2_IN current Fan 2 count */
+/* LM80_VT0_HIGH_LIM high limit val for Voltage 0 */
+/* LM80_VT0_LOW_LIM low limit val for Voltage 0 */
+/* LM80_VT1_HIGH_LIM high limit val for Voltage 1 */
+/* LM80_VT1_LOW_LIM low limit val for Voltage 1 */
+/* LM80_VT2_HIGH_LIM high limit val for Voltage 2 */
+/* LM80_VT2_LOW_LIM low limit val for Voltage 2 */
+/* LM80_VT3_HIGH_LIM high limit val for Voltage 3 */
+/* LM80_VT3_LOW_LIM low limit val for Voltage 3 */
+/* LM80_VT4_HIGH_LIM high limit val for Voltage 4 */
+/* LM80_VT4_LOW_LIM low limit val for Voltage 4 */
+/* LM80_VT5_HIGH_LIM high limit val for Voltage 5 */
+/* LM80_VT5_LOW_LIM low limit val for Voltage 5 */
+/* LM80_VT6_HIGH_LIM high limit val for Voltage 6 */
+/* LM80_VT6_LOW_LIM low limit val for Voltage 6 */
+/* LM80_THOT_LIM_UP hot temperature limit (high) */
+/* LM80_THOT_LIM_LO hot temperature limit (low) */
+/* LM80_TOS_LIM_UP OS temperature limit (high) */
+/* LM80_TOS_LIM_LO OS temperature limit (low) */
+/* LM80_FAN1_COUNT_LIM Fan 1 count limit (high) */
+/* LM80_FAN2_COUNT_LIM Fan 2 count limit (low) */
+ /* 0x3e - 0x3f reserved */
+
+#define LM80_ADDR 0x28 /* LM80 default addr */
+
+/* typedefs *******************************************************************/
+
+
+/* function prototypes ********************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_LM80_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skaddr.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.19 $
+ * Date: $Date: 1999/05/28 10:56:07 $
+ * Purpose: Header file for Address Management (MC, UC, Prom)
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skaddr.h,v $
+ * Revision 1.19 1999/05/28 10:56:07 rassmann
+ * Editorial changes.
+ *
+ * Revision 1.18 1999/04/06 17:22:04 rassmann
+ * Added private "ActivePort".
+ *
+ * Revision 1.17 1999/01/14 16:18:19 rassmann
+ * Corrected multicast initialization.
+ *
+ * Revision 1.16 1999/01/04 10:30:36 rassmann
+ * SkAddrOverride only possible after SK_INIT_IO phase.
+ *
+ * Revision 1.15 1998/12/29 13:13:11 rassmann
+ * An address override is now preserved in the SK_INIT_IO phase.
+ * All functions return an int now.
+ * Extended parameter checking.
+ *
+ * Revision 1.14 1998/11/24 12:39:45 rassmann
+ * Reserved multicast entry for BPDU address.
+ * 13 multicast entries left for protocol.
+ *
+ * Revision 1.13 1998/11/13 17:24:32 rassmann
+ * Changed return value of SkAddrOverride to int.
+ *
+ * Revision 1.12 1998/11/13 16:56:19 rassmann
+ * Added macro SK_ADDR_COMPARE.
+ * Changed return type of SkAddrOverride to SK_BOOL.
+ *
+ * Revision 1.11 1998/10/28 18:16:35 rassmann
+ * Avoiding I/Os before SK_INIT_RUN level.
+ * Aligning InexactFilter.
+ *
+ * Revision 1.10 1998/10/22 11:39:10 rassmann
+ * Corrected signed/unsigned mismatches.
+ *
+ * Revision 1.9 1998/10/15 15:15:49 rassmann
+ * Changed Flags Parameters from SK_U8 to int.
+ * Checked with lint.
+ *
+ * Revision 1.8 1998/09/24 19:15:12 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.7 1998/09/18 20:22:13 rassmann
+ * Added HW access.
+ *
+ * Revision 1.6 1998/09/04 19:40:20 rassmann
+ * Interface enhancements.
+ *
+ * Revision 1.5 1998/09/04 12:40:57 rassmann
+ * Interface cleanup.
+ *
+ * Revision 1.4 1998/09/04 12:14:13 rassmann
+ * Interface cleanup.
+ *
+ * Revision 1.3 1998/09/02 16:56:40 rassmann
+ * Updated interface.
+ *
+ * Revision 1.2 1998/08/27 14:26:09 rassmann
+ * Updated interface.
+ *
+ * Revision 1.1 1998/08/21 08:31:08 rassmann
+ * First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This module is intended to manage multicast addresses and promiscuous mode
+ * on GEnesis adapters.
+ *
+ * Include File Hierarchy:
+ *
+ * "skdrv1st.h"
+ * ...
+ * "sktypes.h"
+ * "skqueue.h"
+ * "skaddr.h"
+ * ...
+ * "skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKADDR_H
+#define __INC_SKADDR_H
+
+#ifdef __cplusplus
+xxxx /* not supported yet - force error */
+extern "C" {
+#endif /* cplusplus */
+
+/* defines ********************************************************************/
+
+#define SK_MAC_ADDR_LEN 6 /* Length of MAC address. */
+#define SK_MAX_ADDRS 14 /* #Addrs for exact match. */
+
+/* ----- Common return values ----- */
+
+#define SK_ADDR_SUCCESS 0 /* Function returned successfully. */
+#define SK_ADDR_ILLEGAL_PORT 100 /* Port number too high. */
+#define SK_ADDR_TOO_EARLY 101 /* Function called too early. */
+
+/* ----- Clear/Add flag bits ----- */
+
+#define SK_ADDR_PERMANENT 1 /* RLMT Address */
+
+/* ----- Additional Clear flag bits ----- */
+
+#define SK_MC_SW_ONLY 2 /* Do not update HW when clearing. */
+
+/* ----- Override flag bits ----- */
+
+#define SK_ADDR_VIRTUAL_ADDRESS 0
+#define SK_ADDR_PHYSICAL_ADDRESS 1
+
+/* ----- Override return values ----- */
+
+#define SK_ADDR_OVERRIDE_SUCCESS (SK_ADDR_SUCCESS)
+#define SK_ADDR_DUPLICATE_ADDRESS 1
+#define SK_ADDR_MULTICAST_ADDRESS 2
+
+/* ----- Partitioning of excact match table ----- */
+
+#define SK_ADDR_EXACT_MATCHES 16 /* #Exact match entries. */
+
+#define SK_ADDR_FIRST_MATCH_RLMT 1
+#define SK_ADDR_LAST_MATCH_RLMT 2
+#define SK_ADDR_FIRST_MATCH_DRV 3
+#define SK_ADDR_LAST_MATCH_DRV (SK_ADDR_EXACT_MATCHES - 1)
+
+/* ----- SkAddrMcAdd/SkAddrMcUpdate return values ----- */
+
+#define SK_MC_FILTERING_EXACT 0 /* Exact filtering. */
+#define SK_MC_FILTERING_INEXACT 1 /* Inexact filtering. */
+
+/* ----- Additional SkAddrMcAdd return values ----- */
+
+#define SK_MC_ILLEGAL_ADDRESS 2 /* Illegal address. */
+#define SK_MC_ILLEGAL_PORT 3 /* Illegal port (not the active one). */
+#define SK_MC_RLMT_OVERFLOW 4 /* Too many RLMT mc addresses. */
+
+/* Promiscuous mode bits ----- */
+
+#define SK_PROM_MODE_NONE 0 /* Normal receive. */
+#define SK_PROM_MODE_LLC 1 /* Receive all LLC frames. */
+#define SK_PROM_MODE_ALL_MC 2 /* Receive all multicast frames. */
+/* #define SK_PROM_MODE_NON_LLC 4 */ /* Receive all non-LLC frames. */
+
+/* Macros */
+
+#ifndef SK_ADDR_EQUAL
+#ifndef SK_ADDR_DWORD_COMPARE
+#define SK_ADDR_EQUAL(A1,A2) ( \
+ ((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5] && \
+ ((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4] && \
+ ((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3] && \
+ ((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2] && \
+ ((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1] && \
+ ((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])
+#else /* SK_ADDR_DWORD_COMPARE */
+#define SK_ADDR_EQUAL(A1,A2) ( \
+ *(SK_U32 *)&(((SK_U8 *)(A1))[2]) == *(SK_U32 *)&(((SK_U8 *)(A2))[2]) && \
+ *(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))
+#endif /* SK_ADDR_DWORD_COMPARE */
+#endif /* SK_ADDR_EQUAL */
+
+/* typedefs *******************************************************************/
+
+typedef struct s_MacAddr {
+ SK_U8 a[SK_MAC_ADDR_LEN];
+} SK_MAC_ADDR;
+
+/* SK_FILTER is used to ensure alignment of the filter. */
+typedef union s_InexactFilter {
+ SK_U8 Bytes[8];
+ SK_U64 Val; /* Dummy entry for alignment only. */
+} SK_FILTER64;
+
+typedef struct s_AddrPort {
+
+/* ----- Public part (read-only) ----- */
+
+ SK_MAC_ADDR PermanentMacAddress; /* Physical MAC Address. */
+ SK_MAC_ADDR CurrentMacAddress; /* Physical MAC Address. */
+ int PromMode; /* Promiscuous Mode. */
+
+/* ----- Private part ----- */
+
+ SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */
+ SK_MAC_ADDR PreviousMacAddress; /* Prev. phys. MAC Address. */
+ SK_U32 FirstExactMatchRlmt;
+ SK_U32 NextExactMatchRlmt;
+ SK_U32 FirstExactMatchDrv;
+ SK_U32 NextExactMatchDrv;
+ SK_MAC_ADDR Exact[SK_ADDR_EXACT_MATCHES];
+ SK_FILTER64 InexactFilter; /* For 64-bit hash register. */
+} SK_ADDR_PORT;
+
+typedef struct s_Addr {
+
+/* ----- Public part (read-only) ----- */
+
+ SK_ADDR_PORT Port[SK_MAX_MACS];
+ SK_MAC_ADDR PermanentMacAddress; /* Logical MAC Address. */
+ SK_MAC_ADDR CurrentMacAddress; /* Logical MAC Address. */
+
+/* ----- Private part ----- */
+
+#if 0
+ SK_BOOL Initialized; /* Flag: Addr module is initialized. */
+#endif /* 0 */
+ SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */
+ SK_U32 ActivePort; /* Vie of module ADDR. */
+} SK_ADDR;
+
+/* function prototypes ********************************************************/
+
+#ifndef SK_KR_PROTO
+
+/* Functions provided by SkRlmt */
+
+/* ANSI/C++ compliant function prototypes */
+
+extern int SkAddrInit(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Level);
+
+extern int SkAddrMcClear(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 PortIdx,
+ int Flags);
+
+extern int SkAddrMcAdd(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 PortIdx,
+ SK_MAC_ADDR *pMc,
+ int Flags);
+
+extern int SkAddrMcUpdate(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 PortIdx);
+
+extern int SkAddrOverride(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 PortIdx,
+ SK_MAC_ADDR *pNewAddr,
+ int Flags);
+
+extern int SkAddrPromiscuousChange(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 PortIdx,
+ int NewPromMode);
+
+extern int SkAddrSwap(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 FromPortIdx,
+ SK_U32 ToPortIdx);
+
+#else /* defined(SK_KR_PROTO)) */
+
+/* Non-ANSI/C++ compliant function prototypes */
+
+xxxx /* not supported yet - force error */
+
+#endif /* defined(SK_KR_PROTO)) */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_SKADDR_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skcsum.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.2 $
+ * Date: $Date: 1998/09/04 12:16:34 $
+ * Purpose: Store/verify Internet checksum in send/receive packets.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skcsum.h,v $
+ * Revision 1.2 1998/09/04 12:16:34 mhaveman
+ * Checked in for Stephan to allow compilation.
+ * -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic
+ * -Added prototype for SkCsEvent()
+ *
+ * Revision 1.1 1998/09/01 15:36:53 swolf
+ * initial revision
+ *
+ * 01-Sep-1998 sw Created.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * Public header file for the "GEnesis" common module "CSUM".
+ *
+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
+ * and is the code name of this SysKonnect project.
+ *
+ * Compilation Options:
+ *
+ * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
+ * empty module.
+ *
+ * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
+ * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
+ * external.
+ *
+ * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
+ * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
+ * external.
+ *
+ * Include File Hierarchy:
+ *
+ * "h/skcsum.h"
+ * "h/sktypes.h"
+ * "h/skqueue.h"
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKCSUM_H
+#define __INC_SKCSUM_H
+
+#include "h/sktypes.h"
+#include "h/skqueue.h"
+
+/* defines ********************************************************************/
+
+/*
+ * Define the default bit flags for 'SKCS_PACKET_INFO.ProtocolFlags' if no user
+ * overwrite.
+ */
+#ifndef SKCS_OVERWRITE_PROTO /* User overwrite? */
+#define SKCS_PROTO_IP 0x1 /* IP (Internet Protocol version 4) */
+#define SKCS_PROTO_TCP 0x2 /* TCP (Transmission Control Protocol) */
+#define SKCS_PROTO_UDP 0x4 /* UDP (User Datagram Protocol) */
+
+/* Indices for protocol statistics. */
+#define SKCS_PROTO_STATS_IP 0
+#define SKCS_PROTO_STATS_UDP 1
+#define SKCS_PROTO_STATS_TCP 2
+#define SKCS_NUM_PROTOCOLS 3 /* Number of supported protocols. */
+#endif /* !SKCS_OVERWRITE_PROTO */
+
+/*
+ * Define the default SKCS_STATUS type and values if no user overwrite.
+ *
+ * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
+ * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
+ * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
+ * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
+ * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
+ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
+ * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
+ * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
+ */
+#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */
+#define SKCS_STATUS int /* Define status type. */
+
+#define SKCS_STATUS_UNKNOWN_IP_VERSION 1
+#define SKCS_STATUS_IP_CSUM_ERROR 2
+#define SKCS_STATUS_IP_FRAGMENT 3
+#define SKCS_STATUS_IP_CSUM_OK 4
+#define SKCS_STATUS_TCP_CSUM_ERROR 5
+#define SKCS_STATUS_UDP_CSUM_ERROR 6
+#define SKCS_STATUS_TCP_CSUM_OK 7
+#define SKCS_STATUS_UDP_CSUM_OK 8
+#endif /* !SKCS_OVERWRITE_STATUS */
+
+/* Clear protocol statistics event. */
+#define SK_CSUM_EVENT_CLEAR_PROTO_STATS 1
+
+/*
+ * Add two values in one's complement.
+ *
+ * Note: One of the two input values may be "longer" than 16-bit, but then the
+ * resulting sum may be 17 bits long. In this case, add zero to the result using
+ * SKCS_OC_ADD() again.
+ *
+ * Result = Value1 + Value2
+ */
+#define SKCS_OC_ADD(Result, Value1, Value2) { \
+ unsigned long Sum; \
+ \
+ Sum = (unsigned long) (Value1) + (unsigned long) (Value2); \
+ /* Add-in any carry. */ \
+ (Result) = (Sum & 0xffff) + (Sum >> 16); \
+}
+
+/*
+ * Subtract two values in one's complement.
+ *
+ * Result = Value1 - Value2
+ */
+#define SKCS_OC_SUB(Result, Value1, Value2) \
+ SKCS_OC_ADD((Result), (Value1), ~(Value2) & 0xffff)
+
+/* typedefs *******************************************************************/
+
+/*
+ * SKCS_PROTO_STATS - The CSUM protocol statistics structure.
+ *
+ * There is one instance of this structure for each protocol supported.
+ */
+typedef struct s_CsProtocolStatistics {
+ SK_U64 RxOkCts; /* Receive checksum ok. */
+ SK_U64 RxUnableCts; /* Unable to verify receive checksum. */
+ SK_U64 RxErrCts; /* Receive checksum error. */
+ SK_U64 TxOkCts; /* Transmit checksum ok. */
+ SK_U64 TxUnableCts; /* Unable to verify transmit checksum. */
+} SKCS_PROTO_STATS;
+
+/*
+ * s_Csum - The CSUM module context structure.
+ */
+typedef struct s_Csum {
+ /* Enabled receive SK_PROTO_XXX bit flags. */
+ unsigned ReceiveFlags;
+
+ /* The protocol statistics structure; one per supported protocol. */
+ SKCS_PROTO_STATS ProtoStats[SKCS_NUM_PROTOCOLS];
+} SK_CSUM;
+
+/*
+ * SKCS_PACKET_INFO - The packet information structure.
+ */
+typedef struct s_CsPacketInfo {
+ /* Bit field specifiying the desired/found protocols. */
+ unsigned ProtocolFlags;
+
+ /* Length of complete IP header, including any option fields. */
+ unsigned IpHeaderLength;
+
+ /* IP header checksum. */
+ unsigned IpHeaderChecksum;
+
+ /* TCP/UDP pseudo header checksum. */
+ unsigned PseudoHeaderChecksum;
+} SKCS_PACKET_INFO;
+
+/* function prototypes ********************************************************/
+
+#ifndef SkCsCalculateChecksum
+extern unsigned SkCsCalculateChecksum(
+ void *pData,
+ unsigned Length);
+#endif
+
+extern int SkCsEvent(
+ SK_AC *pAc,
+ SK_IOC Ioc,
+ SK_U32 Event,
+ SK_EVPARA Param);
+
+extern SKCS_STATUS SkCsGetReceiveInfo(
+ SK_AC *pAc,
+ void *pIpHeader,
+ unsigned Checksum1,
+ unsigned Checksum2);
+
+extern void SkCsGetSendInfo(
+ SK_AC *pAc,
+ void *pIpHeader,
+ SKCS_PACKET_INFO *pPacketInfo);
+
+extern void SkCsSetReceiveFlags(
+ SK_AC *pAc,
+ unsigned ReceiveFlags,
+ unsigned *pChecksum1Offset,
+ unsigned *pChecksum2Offset);
+
+#endif /* __INC_SKCSUM_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skdebug.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.9 $
+ * Date: $Date: 1999/09/14 14:02:43 $
+ * Purpose: SK specific DEBUG support
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ * $Log: skdebug.h,v $
+ * Revision 1.9 1999/09/14 14:02:43 rwahl
+ * Added SK_DBGMOD_PECP.
+ *
+ * Revision 1.8 1998/11/25 08:31:54 gklug
+ * fix: no C++ comments allowed in common sources
+ *
+ * Revision 1.7 1998/11/24 16:47:24 swolf
+ * Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h").
+ *
+ * Revision 1.6 1998/10/28 10:23:55 rassmann
+ * ADDED SK_DBGMOD_ADDR.
+ *
+ * Revision 1.5 1998/10/22 09:43:55 gklug
+ * add: CSUM module
+ *
+ * Revision 1.4 1998/10/01 07:54:44 gklug
+ * add: PNMI debug module
+ *
+ * Revision 1.3 1998/09/18 08:32:34 afischer
+ * Macros changed according ssr-spec.:
+ * SK_DBG_MODCHK -> SK_DBG_CHKMOD
+ * SK_DBG_CATCHK -> SK_DBG_CHKCAT
+ *
+ * Revision 1.2 1998/07/03 14:38:25 malthoff
+ * Add category SK_DBGCAT_FATAL.
+ *
+ * Revision 1.1 1998/06/19 13:39:01 malthoff
+ * created.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDEBUG_H
+#define __INC_SKDEBUG_H
+
+#ifdef DEBUG
+#ifndef SK_DBG_MSG
+#define SK_DBG_MSG(pAC,comp,cat,arg) \
+ if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
+ ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
+ SK_DBG_PRINTF arg ; \
+ }
+#endif
+#else
+#define SK_DBG_MSG(pAC,comp,lev,arg)
+#endif
+
+/* PLS NOTE:
+ * =========
+ * Due to any restrictions of kernel printf routines do not use other
+ * format identifiers as: %x %d %c %s .
+ * Never use any combined format identifiers such as: %lx %ld in your
+ * printf - argument (arg) because some OS specific kernel printfs may
+ * only support some basic identifiers.
+ */
+
+/* Debug modules */
+
+#define SK_DBGMOD_MERR 0x00000001L /* general module error indication */
+#define SK_DBGMOD_HWM 0x00000002L /* Hardware init module */
+#define SK_DBGMOD_RLMT 0x00000004L /* RLMT module */
+#define SK_DBGMOD_VPD 0x00000008L /* VPD module */
+#define SK_DBGMOD_I2C 0x00000010L /* I2C module */
+#define SK_DBGMOD_PNMI 0x00000020L /* PNMI module */
+#define SK_DBGMOD_CSUM 0x00000040L /* CSUM module */
+#define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
+#define SK_DBGMOD_PECP 0x00000100L /* PECP module */
+
+/* Debug events */
+
+#define SK_DBGCAT_INIT 0x00000001L /* module/driver initialization */
+#define SK_DBGCAT_CTRL 0x00000002L /* controlling: add/rmv MCA/MAC
+ * and other controls (IOCTL)
+ */
+#define SK_DBGCAT_ERR 0x00000004L /* error handling paths */
+#define SK_DBGCAT_TX 0x00000008L /* transmit path */
+#define SK_DBGCAT_RX 0x00000010L /* receive path */
+#define SK_DBGCAT_IRQ 0x00000020L /* general IRQ handling */
+#define SK_DBGCAT_QUEUE 0x00000040L /* any queue management */
+#define SK_DBGCAT_DUMP 0x00000080L /* large data output e.g. hex dump */
+#define SK_DBGCAT_FATAL 0x00000100L /* large data output e.g. hex dump */
+
+#endif /* __INC_SKDEBUG_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skdrv1st.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.6 $
+ * Date: $Date: 1999/07/27 08:03:33 $
+ * Purpose: First header file for driver and all other modules
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skdrv1st.h,v $
+ * Revision 1.6 1999/07/27 08:03:33 cgoos
+ * Changed SK_IN/OUT macros to readX/writeX instead of memory
+ * accesses (necessary for ALPHA).
+ *
+ * Revision 1.5 1999/07/23 12:10:21 cgoos
+ * Removed SK_RLMT_SLOW_LOOKAHEAD define.
+ *
+ * Revision 1.4 1999/07/14 12:31:13 cgoos
+ * Added SK_RLMT_SLOW_LOOKAHEAD define.
+ *
+ * Revision 1.3 1999/04/07 10:12:54 cgoos
+ * Added check for KERNEL and OPTIMIZATION defines.
+ *
+ * Revision 1.2 1999/03/01 08:51:47 cgoos
+ * Fixed pcibios_read/write definitions.
+ *
+ * Revision 1.1 1999/02/16 07:40:49 cgoos
+ * First version.
+ *
+ *
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the first include file of the driver, which includes all
+ * neccessary system header files and some of the GEnesis header files.
+ * It also defines some basic items.
+ *
+ * Include File Hierarchy:
+ *
+ * see skge.c
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDRV1ST_H
+#define __INC_SKDRV1ST_H
+
+
+typedef struct s_AC SK_AC;
+
+/* override some default functions with optimized linux functions */
+
+#define SK_PNMI_STORE_U16(p,v) memcpy((char*)(p),(char*)&(v),2)
+#define SK_PNMI_STORE_U32(p,v) memcpy((char*)(p),(char*)&(v),4)
+#define SK_PNMI_STORE_U64(p,v) memcpy((char*)(p),(char*)&(v),8)
+#define SK_PNMI_READ_U16(p,v) memcpy((char*)&(v),(char*)(p),2)
+#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),2)
+#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),2)
+
+#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
+
+#define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
+
+
+#if !defined(__OPTIMIZE__) || !defined(__KERNEL__)
+#warning You must compile this file with the correct options!
+#warning See the last lines of the source file.
+#error You must compile this driver with "-O".
+#endif
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/malloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <asm/byteorder.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <linux/init.h>
+#include <asm/uaccess.h>
+#include <net/checksum.h>
+
+#include "h/sktypes.h"
+#include "h/skerror.h"
+#include "h/skdebug.h"
+#include "h/lm80.h"
+#include "h/xmac_ii.h"
+
+#ifdef __LITTLE_ENDIAN
+#define SK_LITTLE_ENDIAN
+#else
+#define SK_BIG_ENDIAN
+#endif
+
+
+/* we use gethrtime(), return unit: nanoseconds */
+#define SK_TICKS_PER_SEC HZ
+
+#define SK_MEM_MAPPED_IO
+
+// #define SK_RLMT_SLOW_LOOKAHEAD
+
+#define SK_MAX_MACS 2
+
+#define SK_IOC char*
+
+typedef struct s_DrvRlmtMbuf SK_MBUF;
+
+#define SK_CONST64 INT64_C
+#define SK_CONSTU64 UINT64_C
+
+#define SK_MEMCPY(dest,src,size) memcpy(dest,src,size)
+#define SK_MEMCMP(s1,s2,size) memcmp(s1,s2,size)
+#define SK_MEMSET(dest,val,size) memset(dest,val,size)
+#define SK_STRLEN(pStr) strlen((char*)pStr)
+#define SK_STRNCPY(pDest,pSrc,size) strncpy((char*)pDest,(char*)pSrc,size)
+#define SK_STRCMP(pStr1,pStr2) strcmp((char*)pStr1,(char*)pStr2)
+
+/* macros to access the adapter */
+#define SK_OUT8(b,a,v) writeb(v, (b+a))
+#define SK_OUT16(b,a,v) writew(v, (b+a))
+#define SK_OUT32(b,a,v) writel(v, (b+a))
+#define SK_IN8(b,a,pv) (*(pv) = readb(b+a))
+#define SK_IN16(b,a,pv) (*(pv) = readw(b+a))
+#define SK_IN32(b,a,pv) (*(pv) = readl(b+a))
+
+#define int8_t char
+#define int16_t short
+#define int32_t long
+#define int64_t long long
+#define uint8_t u_char
+#define uint16_t u_short
+#define uint32_t u_long
+#define uint64_t unsigned long long
+#define t_scalar_t int
+#define t_uscalar_t unsigned int
+#define uintptr_t unsigned long
+
+#define __CONCAT__(A,B) A##B
+
+#define INT32_C(a) __CONCAT__(a,L)
+#define INT64_C(a) __CONCAT__(a,LL)
+#define UINT32_C(a) __CONCAT__(a,UL)
+#define UINT64_C(a) __CONCAT__(a,ULL)
+
+#ifdef DEBUG
+#define SK_DBG_PRINTF printk
+/* those come from the makefile */
+#define SK_DBG_CHKMOD(pAC) (SK_DEBUG_CHKMOD)
+#define SK_DBG_CHKCAT(pAC) (SK_DEBUG_CHKCAT)
+
+extern void SkDbgPrintf(const char *format,...);
+
+#define SK_DBGMOD_DRV 0x00010000
+
+/**** possible driver debug categories ********************************/
+#define SK_DBGCAT_DRV_ENTRY 0x00010000
+#define SK_DBGCAT_DRV_SAP 0x00020000
+#define SK_DBGCAT_DRV_MCA 0x00040000
+#define SK_DBGCAT_DRV_TX_PROGRESS 0x00080000
+#define SK_DBGCAT_DRV_RX_PROGRESS 0x00100000
+#define SK_DBGCAT_DRV_PROGRESS 0x00200000
+#define SK_DBGCAT_DRV_MSG 0x00400000
+#define SK_DBGCAT_DRV_PROM 0x00800000
+#define SK_DBGCAT_DRV_TX_FRAME 0x01000000
+#define SK_DBGCAT_DRV_ERROR 0x02000000
+#define SK_DBGCAT_DRV_INT_SRC 0x04000000
+#define SK_DBGCAT_DRV_EVENT 0x08000000
+
+#endif /* DEBUG */
+
+#define SK_ERR_LOG SkErrorLog
+
+extern void SkErrorLog(SK_AC*, int, int, char*);
+
+#endif /* __INC_SKDRV1ST_H */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skdrv2nd.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.7 $
+ * Date: $Date: 1999/09/28 12:38:21 $
+ * Purpose: Second header file for driver and all other modules
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skdrv2nd.h,v $
+ * Revision 1.7 1999/09/28 12:38:21 cgoos
+ * Added CheckQueue to SK_AC.
+ *
+ * Revision 1.6 1999/07/27 08:04:05 cgoos
+ * Added checksumming variables to SK_AC.
+ *
+ * Revision 1.5 1999/03/29 12:33:26 cgoos
+ * Rreversed to fine lock granularity.
+ *
+ * Revision 1.4 1999/03/15 12:14:02 cgoos
+ * Added DriverLock to SK_AC.
+ * Removed other locks.
+ *
+ * Revision 1.3 1999/03/01 08:52:27 cgoos
+ * Changed pAC->PciDev declaration.
+ *
+ * Revision 1.2 1999/02/18 10:57:14 cgoos
+ * Removed SkDrvTimeStamp prototype.
+ * Fixed SkGeOsGetTime prototype.
+ *
+ * Revision 1.1 1999/02/16 07:41:01 cgoos
+ * First version.
+ *
+ *
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the second include file of the driver, which includes all other
+ * neccessary files and defines all structures and constants used by the
+ * driver and the common modules.
+ *
+ * Include File Hierarchy:
+ *
+ * see skge.c
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDRV2ND_H
+#define __INC_SKDRV2ND_H
+
+#include "h/skqueue.h"
+#include "h/skgehwt.h"
+#include "h/sktimer.h"
+#include "h/ski2c.h"
+#include "h/skgepnmi.h"
+#include "h/skvpd.h"
+#include "h/skgehw.h"
+#include "h/skgeinit.h"
+#include "h/skaddr.h"
+#include "h/skgesirq.h"
+#include "h/skcsum.h"
+#include "h/skrlmt.h"
+#include "h/skgedrv.h"
+
+/* global function prototypes ******************************************/
+extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
+extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
+extern SK_U64 SkOsGetTime(SK_AC*);
+extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
+extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
+extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
+extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
+extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
+extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
+extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
+
+struct s_DrvRlmtMbuf {
+ SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
+ SK_U8 *pData; /* Data buffer (virtually contig.). */
+ unsigned Size; /* Data buffer size. */
+ unsigned Length; /* Length of packet (<= Size). */
+ SK_U32 PortIdx; /* Receiving/transmitting port. */
+#ifdef SK_RLMT_MBUF_PRIVATE
+ SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
+#endif /* SK_RLMT_MBUF_PRIVATE */
+ struct sk_buff *pOs; /* Pointer to message block */
+};
+
+
+
+/*
+ * ioctl definitions
+ */
+#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
+#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
+#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
+#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
+
+typedef struct s_IOCTL SK_GE_IOCTL;
+
+struct s_IOCTL {
+ char* pData;
+ unsigned int Len;
+};
+
+
+/*
+ * define sizes of descriptor rings in bytes
+ */
+
+#define TX_RING_SIZE (8*1024)
+#define RX_RING_SIZE (24*1024)
+
+/*
+ * Buffer size for ethernet packets
+ */
+#define ETH_BUF_SIZE 1540
+#define ETH_MAX_MTU 1514
+#define ETH_MIN_MTU 60
+#define ETH_MULTICAST_BIT 0x01
+#define SK_JUMBO_MTU 9000
+
+/*
+ * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
+ */
+#define TX_PRIO_LOW 0
+#define TX_PRIO_HIGH 1
+
+/*
+ * alignment of rx/tx descriptors
+ */
+#define DESCR_ALIGN 8
+
+/*
+ * definitions for pnmi. TODO
+ */
+#define SK_DRIVER_RESET(pAC, IoC) 0
+#define SK_DRIVER_SENDEVENT(pAC, IoC) 0
+#define SK_DRIVER_SELFTEST(pAC, IoC) 0
+
+/* TX and RX descriptors *****************************************************/
+
+typedef struct s_RxD RXD; /* the receive descriptor */
+
+struct s_RxD {
+ volatile SK_U32 RBControl; /* Receive Buffer Control */
+ SK_U32 VNextRxd; /* Next receive descriptor,low dword */
+ SK_U32 VDataLow; /* Receive buffer Addr, low dword */
+ SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
+ SK_U32 FrameStat; /* Receive Frame Status word */
+ SK_U32 TimeStamp; /* Time stamp from XMAX */
+ SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
+ SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
+ RXD *pNextRxd; /* Pointer to next Rxd */
+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
+};
+
+typedef struct s_TxD TXD; /* the transmit descriptor */
+
+struct s_TxD {
+ volatile SK_U32 TBControl; /* Transmit Buffer Control */
+ SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
+ SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
+ SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
+ SK_U32 FrameStat; /* Transmit Frame Status Word */
+ SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
+ SK_U32 TcpSumStWr; /* TCP Sum Start / TCP Sum Write */
+ SK_U32 TcpReserved; /* not used */
+ TXD *pNextTxd; /* Pointer to next Txd */
+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
+};
+
+
+/* definition of flags in descriptor control field */
+#define RX_CTRL_OWN_BMU UINT32_C(0x80000000)
+#define RX_CTRL_STF UINT32_C(0x40000000)
+#define RX_CTRL_EOF UINT32_C(0x20000000)
+#define RX_CTRL_EOB_IRQ UINT32_C(0x10000000)
+#define RX_CTRL_EOF_IRQ UINT32_C(0x08000000)
+#define RX_CTRL_DEV_NULL UINT32_C(0x04000000)
+#define RX_CTRL_STAT_VALID UINT32_C(0x02000000)
+#define RX_CTRL_TIME_VALID UINT32_C(0x01000000)
+#define RX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000)
+#define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000)
+#define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
+
+#define TX_CTRL_OWN_BMU UINT32_C(0x80000000)
+#define TX_CTRL_STF UINT32_C(0x40000000)
+#define TX_CTRL_EOF UINT32_C(0x20000000)
+#define TX_CTRL_EOB_IRQ UINT32_C(0x10000000)
+#define TX_CTRL_EOF_IRQ UINT32_C(0x08000000)
+#define TX_CTRL_ST_FWD UINT32_C(0x04000000)
+#define TX_CTRL_DISAB_CRC UINT32_C(0x02000000)
+#define TX_CTRL_SOFTWARE UINT32_C(0x01000000)
+#define TX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000)
+#define TX_CTRL_CHECK_CSUM UINT32_C(0x00560000)
+#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
+
+
+
+/* The offsets of registers in the TX and RX queue control io area ***********/
+
+#define RX_Q_BUF_CTRL_CNT 0x00
+#define RX_Q_NEXT_DESCR_LOW 0x04
+#define RX_Q_BUF_ADDR_LOW 0x08
+#define RX_Q_BUF_ADDR_HIGH 0x0c
+#define RX_Q_FRAME_STAT 0x10
+#define RX_Q_TIME_STAMP 0x14
+#define RX_Q_CSUM_1_2 0x18
+#define RX_Q_CSUM_START_1_2 0x1c
+#define RX_Q_CUR_DESCR_LOW 0x20
+#define RX_Q_DESCR_HIGH 0x24
+#define RX_Q_CUR_ADDR_LOW 0x28
+#define RX_Q_CUR_ADDR_HIGH 0x2c
+#define RX_Q_CUR_BYTE_CNT 0x30
+#define RX_Q_CTRL 0x34
+#define RX_Q_FLAG 0x38
+#define RX_Q_TEST1 0x3c
+#define RX_Q_TEST2 0x40
+#define RX_Q_TEST3 0x44
+
+#define TX_Q_BUF_CTRL_CNT 0x00
+#define TX_Q_NEXT_DESCR_LOW 0x04
+#define TX_Q_BUF_ADDR_LOW 0x08
+#define TX_Q_BUF_ADDR_HIGH 0x0c
+#define TX_Q_FRAME_STAT 0x10
+#define TX_Q_CSUM_START 0x14
+#define TX_Q_CSUM_START_POS 0x18
+#define TX_Q_RESERVED 0x1c
+#define TX_Q_CUR_DESCR_LOW 0x20
+#define TX_Q_DESCR_HIGH 0x24
+#define TX_Q_CUR_ADDR_LOW 0x28
+#define TX_Q_CUR_ADDR_HIGH 0x2c
+#define TX_Q_CUR_BYTE_CNT 0x30
+#define TX_Q_CTRL 0x34
+#define TX_Q_FLAG 0x38
+#define TX_Q_TEST1 0x3c
+#define TX_Q_TEST2 0x40
+#define TX_Q_TEST3 0x44
+
+/* definition of flags in the queue control field */
+#define RX_Q_CTRL_POLL_ON 0x00000080
+#define RX_Q_CTRL_POLL_OFF 0x00000040
+#define RX_Q_CTRL_STOP 0x00000020
+#define RX_Q_CTRL_START 0x00000010
+#define RX_Q_CTRL_CLR_I_PAR 0x00000008
+#define RX_Q_CTRL_CLR_I_EOB 0x00000004
+#define RX_Q_CTRL_CLR_I_EOF 0x00000002
+#define RX_Q_CTRL_CLR_I_ERR 0x00000001
+
+#define TX_Q_CTRL_POLL_ON 0x00000080
+#define TX_Q_CTRL_POLL_OFF 0x00000040
+#define TX_Q_CTRL_STOP 0x00000020
+#define TX_Q_CTRL_START 0x00000010
+#define TX_Q_CTRL_CLR_I_EOB 0x00000004
+#define TX_Q_CTRL_CLR_I_EOF 0x00000002
+#define TX_Q_CTRL_CLR_I_ERR 0x00000001
+
+
+/* Interrupt bits in the interrupts source register **************************/
+#define IRQ_HW_ERROR 0x80000000
+#define IRQ_RESERVED 0x40000000
+#define IRQ_PKT_TOUT_RX1 0x20000000
+#define IRQ_PKT_TOUT_RX2 0x10000000
+#define IRQ_PKT_TOUT_TX1 0x08000000
+#define IRQ_PKT_TOUT_TX2 0x04000000
+#define IRQ_I2C_READY 0x02000000
+#define IRQ_SW 0x01000000
+#define IRQ_EXTERNAL_REG 0x00800000
+#define IRQ_TIMER 0x00400000
+#define IRQ_MAC1 0x00200000
+#define IRQ_LINK_SYNC_C_M1 0x00100000
+#define IRQ_MAC2 0x00080000
+#define IRQ_LINK_SYNC_C_M2 0x00040000
+#define IRQ_EOB_RX1 0x00020000
+#define IRQ_EOF_RX1 0x00010000
+#define IRQ_CHK_RX1 0x00008000
+#define IRQ_EOB_RX2 0x00004000
+#define IRQ_EOF_RX2 0x00002000
+#define IRQ_CHK_RX2 0x00001000
+#define IRQ_EOB_SY_TX1 0x00000800
+#define IRQ_EOF_SY_TX1 0x00000400
+#define IRQ_CHK_SY_TX1 0x00000200
+#define IRQ_EOB_AS_TX1 0x00000100
+#define IRQ_EOF_AS_TX1 0x00000080
+#define IRQ_CHK_AS_TX1 0x00000040
+#define IRQ_EOB_SY_TX2 0x00000020
+#define IRQ_EOF_SY_TX2 0x00000010
+#define IRQ_CHK_SY_TX2 0x00000008
+#define IRQ_EOB_AS_TX2 0x00000004
+#define IRQ_EOF_AS_TX2 0x00000002
+#define IRQ_CHK_AS_TX2 0x00000001
+
+#define DRIVER_IRQS (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \
+ IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \
+ IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2)
+
+#define SPECIAL_IRQS (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
+ IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
+ IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
+ IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \
+ IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \
+ IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
+ IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
+ IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
+
+#define IRQ_MASK (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \
+ IRQ_EOB_RX2 | IRQ_EOF_RX2 | \
+ IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \
+ IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \
+ IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \
+ IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \
+ IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
+ IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
+ IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
+ IRQ_MAC1 | \
+ IRQ_MAC2 | \
+ IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
+ IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
+ IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)
+
+#define IRQ_HWE_MASK 0x00000FFF /* enable all HW irqs */
+
+typedef struct s_TxPort TX_PORT;
+
+struct s_TxPort {
+ /* the transmit descriptor rings */
+ caddr_t pTxDescrRing; /* descriptor area memory */
+ SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
+ TXD *pTxdRingHead; /* Head of Tx rings */
+ TXD *pTxdRingTail; /* Tail of Tx rings */
+ TXD *pTxdRingPrev; /* descriptor sent previously */
+ int TxdRingFree; /* # of free entrys */
+ spinlock_t TxDesRingLock; /* serialize descriptor accesses */
+ caddr_t HwAddr; /* bmu registers address */
+ int PortIndex; /* index number of port (0 or 1) */
+};
+
+typedef struct s_RxPort RX_PORT;
+
+struct s_RxPort {
+ /* the receive descriptor rings */
+ caddr_t pRxDescrRing; /* descriptor area memory */
+ SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
+ RXD *pRxdRingHead; /* Head of Rx rings */
+ RXD *pRxdRingTail; /* Tail of Rx rings */
+ RXD *pRxdRingPrev; /* descriptor given to BMU previously */
+ int RxdRingFree; /* # of free entrys */
+ spinlock_t RxDesRingLock; /* serialize descriptor accesses */
+ int RxFillLimit; /* limit for buffers in ring */
+ caddr_t HwAddr; /* bmu registers address */
+ int PortIndex; /* index number of port (0 or 1) */
+};
+
+typedef struct s_PerStrm PER_STRM;
+
+#define SK_ALLOC_IRQ 0x00000001
+
+/****************************************************************************
+ * Per board structure / Adapter Context structure:
+ * Allocated within attach(9e) and freed within detach(9e).
+ * Contains all 'per device' necessary handles, flags, locks etc.:
+ */
+struct s_AC {
+ SK_GEINIT GIni; /* GE init struct */
+ SK_PNMI Pnmi; /* PNMI data struct */
+ SK_VPD vpd; /* vpd data struct */
+ SK_QUEUE Event; /* Event queue */
+ SK_HWT Hwt; /* Hardware Timer control struct */
+ SK_TIMCTRL Tim; /* Software Timer control struct */
+ SK_I2C I2c; /* I2C relevant data structure */
+ SK_ADDR Addr; /* for Address module */
+ SK_CSUM Csum; /* for checksum module */
+ SK_RLMT Rlmt; /* for rlmt module */
+ spinlock_t SlowPathLock; /* Normal IRQ lock */
+ SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
+ int RlmtMode; /* link check mode to set */
+
+ SK_IOC IoBase; /* register set of adapter */
+ int BoardLevel; /* level of active hw init (0-2) */
+ char DeviceStr[80]; /* adapter string from vpd */
+ SK_U32 AllocFlag; /* flag allocation of resources */
+ struct pci_dev PciDev; /* for access to pci config space */
+ SK_U32 PciDevId; /* pci device id */
+ struct net_device *dev; /* pointer to device struct */
+ char Name[30]; /* driver name */
+ struct net_device *Next; /* link all devices (for clearing) */
+ int RxBufSize; /* length of receive buffers */
+ struct net_device_stats stats; /* linux 'netstat -i' statistics */
+ int Index; /* internal board index number */
+
+ /* adapter RAM sizes for queues of active port */
+ int RxQueueSize; /* memory used for receive queue */
+ int TxSQueueSize; /* memory used for sync. tx queue */
+ int TxAQueueSize; /* memory used for async. tx queue */
+
+ int PromiscCount; /* promiscuous mode counter */
+ int AllMultiCount; /* allmulticast mode counter */
+ int MulticCount; /* number of different MC */
+ /* addresses for this board */
+ /* (may be more than HW can)*/
+
+ int ActivePort; /* the active XMAC port */
+ int TxDescrPerRing; /* # of descriptors per tx ring */
+ int RxDescrPerRing; /* # of descriptors per rx ring */
+
+
+ caddr_t pDescrMem; /* Pointer to the descriptor area */
+ /* the port structures with descriptor rings */
+ TX_PORT TxPort[SK_MAX_MACS][2];
+ RX_PORT RxPort[SK_MAX_MACS];
+
+ unsigned int CsOfs1; /* for checksum calculation */
+ unsigned int CsOfs2; /* for checksum calculation */
+ SK_U32 CsOfs; /* for checksum calculation */
+
+ SK_BOOL CheckQueue; /* check event queue soon */
+};
+
+
+#endif /* __INC_SKDRV2ND_H */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skerror.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.3 $
+ * Date: $Date: 1999/09/14 14:04:42 $
+ * Purpose: SK specific Error log support
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ * $Log: skerror.h,v $
+ * Revision 1.3 1999/09/14 14:04:42 rwahl
+ * Added error base SK_ERRBASE_PECP.
+ * Changed error base for driver.
+ *
+ * Revision 1.2 1998/08/11 11:15:41 gklug
+ * chg: comments
+ *
+ * Revision 1.1 1998/08/11 11:09:38 gklug
+ * add: error bases
+ * add: error Classes
+ * first version
+ *
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _INC_SKERROR_H_
+#define _INC_SKERROR_H_
+
+/*
+ * Define the Error Classes
+ */
+#define SK_ERRCL_OTHER (0) /* Other error */
+#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */
+#define SK_ERRCL_INIT (1L<<1) /* Initialization error */
+#define SK_ERRCL_NORES (1L<<2) /* Out of resources error */
+#define SK_ERRCL_SW (1L<<3) /* internal Software error */
+#define SK_ERRCL_HW (1L<<4) /* Hardware failure */
+#define SK_ERRCL_COMM (1L<<5) /* Communication error */
+
+
+/*
+ * Define Error code bases
+ */
+#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */
+#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */
+#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */
+#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */
+#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */
+#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */
+#define SK_ERRBASE_I2C 700 /* Base Error number for i2C module */
+#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
+#define SK_ERRBASE_ADDR 900 /* Base Error number for Address mod. */
+#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
+#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
+
+#endif /* _INC_SKERROR_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgedrv.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.3 $
+ * Date: $Date: 1998/12/01 13:31:39 $
+ * Purpose: Interface with the driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgedrv.h,v $
+ * Revision 1.3 1998/12/01 13:31:39 cgoos
+ * SWITCH INTERN Event added.
+ *
+ * Revision 1.2 1998/11/25 08:28:38 gklug
+ * rmv: PORT SWITCH Event
+ *
+ * Revision 1.1 1998/09/29 06:14:07 gklug
+ * add: driver events (initial version)
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEDRV_H_
+#define __INC_SKGEDRV_H_
+
+/* defines ********************************************************************/
+
+/*
+ * Define the driver events.
+ * Usually the events are defined by the destination module. In case of the
+ * driver we put the definition of the events here.
+ */
+#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
+#define SK_DRV_NET_UP 2 /* The net is now operational */
+#define SK_DRV_NET_DOWN 3 /* The net is now down */
+#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links conn */
+#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
+#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */
+#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */
+#define SK_DRV_PORT_FAIL 8 /* One port fails */
+#define SK_DRV_SWITCH_INTERN 9 /* Port switch from driver to itself */
+
+#endif /* __INC_SKGEDRV_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgehw.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.33 $
+ * Date: $Date: 1999/08/27 11:17:10 $
+ * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product
+ * Family
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ * $Log: skgehw.h,v $
+ * Revision 1.33 1999/08/27 11:17:10 malthoff
+ * It's more savely to put bracket around marco parameters.
+ * Brackets added for PHY_READ and PHY_WRITE.
+ *
+ * Revision 1.32 1999/05/19 07:31:01 cgoos
+ * Changes for 1000Base-T.
+ * Added HWAC_LINK_LED macro.
+ *
+ * Revision 1.31 1999/03/12 13:27:40 malthoff
+ * Remove __STDC__.
+ *
+ * Revision 1.30 1999/02/09 09:28:20 malthoff
+ * Add PCI_ERRBITS.
+ *
+ * Revision 1.29 1999/01/26 08:55:48 malthoff
+ * Bugfix: The 16 bit field releations inside the descriptor are
+ * endianess dependend if the descriptor reversal feature
+ * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
+ * Drivers which use this feature has to set the define
+ * SK_USE_REV_DESC.
+ *
+ * Revision 1.28 1998/12/10 11:10:22 malthoff
+ * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
+ *
+ * Revision 1.27 1998/11/13 14:19:21 malthoff
+ * Bug Fix: The bit definition of B3_PA_CTRL has completely
+ * changed from HW Spec v1.3 to v1.5.
+ *
+ * Revision 1.26 1998/11/04 08:31:48 cgoos
+ * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros.
+ *
+ * Revision 1.25 1998/11/04 07:16:25 cgoos
+ * Changed byte ordering in XM_INADDR/XM_INHASH again.
+ *
+ * Revision 1.24 1998/11/02 11:08:43 malthoff
+ * RxCtrl and TxCtrl must be volatile.
+ *
+ * Revision 1.23 1998/10/28 13:50:45 malthoff
+ * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros.
+ *
+ * Revision 1.22 1998/10/26 08:01:36 malthoff
+ * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1,
+ * RX_MFF_STAT_TO, and RX_MFF_TIST_TO.
+ * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF.
+ *
+ * Revision 1.21 1998/10/20 07:43:10 malthoff
+ * Fix: XM_IN/OUT/ADDR/HASH macros:
+ * The pointer must be casted.
+ *
+ * Revision 1.20 1998/10/19 15:53:59 malthoff
+ * Remove ML proto definitions.
+ *
+ * Revision 1.19 1998/10/16 14:40:17 gklug
+ * fix: typo B0_XM_IMSK regs
+ *
+ * Revision 1.18 1998/10/16 09:46:54 malthoff
+ * Remove temp defines for ML diag prototyp.
+ * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA
+ * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR,
+ * B0_XS2_CSR, and B0_XA2_CSR.
+ *
+ * Revision 1.17 1998/10/14 06:03:14 cgoos
+ * Changed shifted constant to ULONG.
+ *
+ * Revision 1.16 1998/10/09 07:05:41 malthoff
+ * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL.
+ *
+ * Revision 1.15 1998/10/05 07:54:23 malthoff
+ * Split up RB_CTRL and it's bit definition into
+ * RB_CTRL, RB_TST1, and RB_TST2.
+ * Rename RB_RX_HTPP to RB_RX_LTPP.
+ * Add ALL_PA_ENA_TO. Modify F_WATER_MARK
+ * according to HW Spec. v1.5.
+ * Add MFF_TX_CTRL_DEF.
+ *
+ * Revision 1.14 1998/09/28 13:31:16 malthoff
+ * bug fix: B2_MAC_3 is 0x110 not 0x114
+ *
+ * Revision 1.13 1998/09/24 14:42:56 malthoff
+ * Split the RX_MFF_TST into RX_MFF_CTRL2,
+ * RX_MFF_TST1, and RX_MFF_TST2.
+ * Rename RX_MFF_CTRL to RX_MFF_CTRL1.
+ * Add BMU bit CSR_SV_IDLE.
+ * Add macros PHY_READ() and PHY_WRITE().
+ * Rename macro SK_ADDR() to SK_HW_ADDR()
+ * because of conflicts with the Address Module.
+ *
+ * Revision 1.12 1998/09/16 07:25:33 malthoff
+ * Change the parameter order in the XM_INxx and XM_OUTxx macros,
+ * to have the IoC as first parameter.
+ *
+ * Revision 1.11 1998/09/03 09:58:41 malthoff
+ * Rework the XM_xxx macros. Use {} instead of () to
+ * be compatible with SK_xxx macros which are defined
+ * with {}.
+ *
+ * Revision 1.10 1998/09/02 11:16:39 malthoff
+ * Temporary modify B2_I2C_SW to make tests with
+ * the GE/ML prototyp.
+ *
+ * Revision 1.9 1998/08/19 09:11:49 gklug
+ * fix: struct are removed from c-source (see CCC)
+ * add: typedefs for all structs
+ *
+ * Revision 1.8 1998/08/18 08:27:27 malthoff
+ * Add some temporary workarounds to test GE
+ * sources with the ML.
+ *
+ * Revision 1.7 1998/07/03 14:42:26 malthoff
+ * bug fix: Correct macro XMA().
+ * Add temporary workaround to access the PCI config space over IO
+ *
+ * Revision 1.6 1998/06/23 11:30:36 malthoff
+ * Remove ';' with ',' in macors.
+ *
+ * Revision 1.5 1998/06/22 14:20:57 malthoff
+ * Add macro SK_ADDR(Base,Addr).
+ *
+ * Revision 1.4 1998/06/19 13:35:43 malthoff
+ * change 'pGec' with 'pAC'
+ *
+ * Revision 1.3 1998/06/17 14:58:16 cvs
+ * Lost keywords reinserted.
+ *
+ * Revision 1.1 1998/06/17 14:16:36 cvs
+ * created
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEHW_H
+#define __INC_SKGEHW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * Configuration Space header
+ * Since this module is used for different OS', those may be
+ * duplicate on some of them (e.g. Linux). But to keep the
+ * common source, we have to live with this...
+ */
+#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
+#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
+#define PCI_COMMAND 0x04 /* 16 bit Command */
+#define PCI_STATUS 0x06 /* 16 bit Status */
+#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
+#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
+#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
+#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
+#define PCI_HEADER_T 0x0e /* 8 bit Header Type */
+#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
+#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
+#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
+ /* Byte 18..2b: reserved */
+#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
+#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
+#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
+ /* Byte 34..33: reserved */
+#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
+ /* Byte 35..3b: reserved */
+#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
+#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
+#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
+#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
+ /* Device Dependent Region */
+#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
+#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
+ /* Power Management Region */
+#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
+#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
+#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
+#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
+ /* Byte 0x4e: reserved */
+#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
+ /* VPD Region */
+#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
+#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
+#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
+#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
+ /* Byte 58..ff: reserved */
+
+/*
+ * I2C Address (PCI Config)
+ *
+ * Note: The temperature and voltage sensors are relocated on a different
+ * I2C bus.
+ */
+#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
+
+/*
+ * Define Bits and Values of the registers
+ */
+/* PCI_VENDOR_ID 16 bit Vendor ID */
+/* PCI_DEVICE_ID 16 bit Device ID */
+/* Values for Vendor ID and Device ID shall be patched into the code */
+/* PCI_COMMAND 16 bit Command */
+ /* Bit 15..10: reserved */
+#define PCI_FBTEN (1<<9) /* Bit 9: Fast Back-To-Back enable */
+#define PCI_SERREN (1<<8) /* Bit 8: SERR enable */
+#define PCI_ADSTEP (1<<7) /* Bit 7: Address Stepping */
+#define PCI_PERREN (1<<6) /* Bit 6: Parity Report Response enable */
+#define PCI_VGA_SNOOP (1<<5) /* Bit 5: VGA palette snoop */
+#define PCI_MWIEN (1<<4) /* Bit 4: Memory write an inv cycl ena */
+#define PCI_SCYCEN (1<<3) /* Bit 3: Special Cycle enable */
+#define PCI_BMEN (1<<2) /* Bit 2: Bus Master enable */
+#define PCI_MEMEN (1<<1) /* Bit 1: Memory Space Access enable */
+#define PCI_IOEN (1<<0) /* Bit 0: IO Space Access enable */
+
+/* PCI_STATUS 16 bit Status */
+#define PCI_PERR (1<<15) /* Bit 15: Parity Error */
+#define PCI_SERR (1<<14) /* Bit 14: Signaled SERR */
+#define PCI_RMABORT (1<<13) /* Bit 13: Received Master Abort */
+#define PCI_RTABORT (1<<12) /* Bit 12: Received Target Abort */
+ /* Bit 11: reserved */
+#define PCI_DEVSEL (3<<9) /* Bit 10..9: DEVSEL Timing */
+#define PCI_DEV_FAST (0<<9) /* fast */
+#define PCI_DEV_MEDIUM (1<<9) /* medium */
+#define PCI_DEV_SLOW (2<<9) /* slow */
+#define PCI_DATAPERR (1<<8) /* Bit 8: DATA Parity error detected */
+#define PCI_FB2BCAP (1<<7) /* Bit 7: Fast Back-to-Back Capability */
+#define PCI_UDF (1<<6) /* Bit 6: User Defined Features */
+#define PCI_66MHZCAP (1<<5) /* Bit 5: 66 MHz PCI bus clock capable */
+#define PCI_NEWCAP (1<<4) /* Bit 4: New cap. list implemented */
+ /* Bit 3..0: reserved */
+
+#define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
+ PCI_DATAPERR)
+
+/* PCI_CLASS_CODE 24 bit Class Code */
+/* Byte 2: Base Class (02) */
+/* Byte 1: SubClass (00) */
+/* Byte 0: Programming Interface (00) */
+
+/* PCI_CACHE_LSZ 8 bit Cache Line Size */
+/* Possible values: 0,2,4,8,16,32,64,128 */
+
+/* PCI_HEADER_T 8 bit Header Type */
+#define PCI_HD_MF_DEV (1<<7) /* Bit 7: 0= single, 1= multi-func dev */
+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
+
+/* PCI_BIST 8 bit Built-in selftest */
+/* Built-in Self test not supported (optional) */
+
+/* PCI_BASE_1ST 32 bit 1st Base address */
+#define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
+#define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
+#define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
+#define PCI_PREFEN (1L<<3) /* Bit 3: Prefetchable */
+#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
+#define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
+#define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
+#define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
+#define PCI_MEMSPACE (1L<<0) /* Bit 0: Memory Space Indic. */
+
+/* PCI_BASE_2ND 32 bit 2nd Base address */
+#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
+#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
+ /* Bit 1: reserved */
+#define PCI_IOSPACE (1L<<0) /* Bit 0: I/O Space Indicator */
+
+/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
+#define PCI_ROMBASE (0xfffeL<<17) /* Bit 31..17: ROM BASE address (1st)*/
+#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */
+#define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
+ /* Bit 10.. 1: reserved */
+#define PCI_ROMEN (0x1L<<0) /* Bit 0: Address Decode enable */
+
+/* Device Dependent Region */
+/* PCI_OUR_REG_1 32 bit Our Register 1 */
+ /* Bit 31..26: reserved */
+#define PCI_VIO (1L<<25) /* Bit 25: PCI IO Voltage, */
+ /* 0 = 3.3V / 1 = 5V */
+#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
+ /* 1 = Don't boot wth ROM*/
+ /* 0 = Boot with ROM */
+#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
+#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
+ /* 1 = Map Flash to Mem */
+ /* 0 = Disable addr. dec*/
+#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
+#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
+#define PCI_PAGE_32K (1L<<20) /* 32 k pages */
+#define PCI_PAGE_64K (2L<<20) /* 64 k pages */
+#define PCI_PAGE_128K (3L<<20) /* 128 k pages */
+ /* Bit 19: reserved */
+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
+#define PCI_NOTAR (1L<<15) /* Bit 15: No turnaround cycle */
+#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
+#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
+#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
+#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
+#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
+#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
+#define PCI_DIS_PCI_CLK (1L<<8) /* Bit 8: Disable PCI clock driv*/
+#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */
+#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
+
+
+/* PCI_OUR_REG_2 32 bit Our Register 2 */
+#define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
+#define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
+#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
+ /* Bit 13..12: reserved */
+#define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patchs dir 3..0 */
+#define PCI_PATCH_DIR_0 (1L<<8)
+#define PCI_PATCH_DIR_1 (1L<<9)
+#define PCI_PATCH_DIR_2 (1L<<10)
+#define PCI_PATCH_DIR_3 (1L<<11)
+#define PCI_EXT_PATCHS (0xfL<<4) /* Bit 7..4: Extended Patches 3..0 */
+#define PCI_EXT_PATCH_0 (1L<<4)
+#define PCI_EXT_PATCH_1 (1L<<5)
+#define PCI_EXT_PATCH_2 (1L<<6)
+#define PCI_EXT_PATCH_3 (1L<<7)
+#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3: Enable Dummy Read */
+#define PCI_REV_DESC (1L<<2) /* Bit 2: Reverse Desc. Bytes */
+ /* Bit 1: reserved */
+#define PCI_USEDATA64 (1L<<0) /* Bit 0: Use 64Bit Data bus ext*/
+
+
+/* Power Management Region */
+/* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
+#define PCI_PME_SUP (0x1f<<11) /* Bit 15..11: PM Manag. Event Sup */
+#define PCI_PM_D2_SUB (1<<10) /* Bit 10: D2 Support Bit */
+#define PCI_PM_D1_SUB (1<<9) /* Bit 9: D1 Support Bit */
+ /* Bit 8..6: reserved */
+#define PCI_PM_DSI (1<<5) /* Bit 5: Device Specific Init.*/
+#define PCI_PM_APS (1<<4) /* Bit 4: Auxialiary Power Src */
+#define PCI_PME_CLOCK (1<<3) /* Bit 3: PM Event Clock */
+#define PCI_PM_VER (7<<0) /* Bit 2..0: PM PCI Spec. version */
+
+/* PCI_PM_CTL_STS 16 bit Power Manag. Control/Status */
+#define PCI_PME_STATUS (1<<15) /* Bit 15: PGA doesn't sup. PME# */
+#define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: dat reg Scaling factor*/
+#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field*/
+#define PCI_PME_EN (1<<8) /* Bit 8: PGA doesn't sup. PME# */
+ /* Bit 7.. 2: reserved */
+#define PCI_PM_STATE (3<<0) /* Bit 1.. 0: Power Management State*/
+#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
+#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
+#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */
+#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */
+
+/* VPD Region */
+/* PCI_VPD_ADR_REG 16 bit VPD Address Register */
+#define PCI_VPD_FLAG (1L<<15) /* Bit 15: starts VPD rd/wd cycle*/
+#define PCI_VPD_ADDR (0x3fffL<<0) /* Bit 14..0: VPD address */
+
+/*
+ * Control Register File:
+ * Bank 0
+ */
+#define B0_RAP 0x0000 /* 8 bit Register Address Port */
+ /* 0x0001 - 0x0003: reserved */
+#define B0_CTST 0x0004 /* 16 bit Control/Status register */
+#define B0_LED 0x0006 /* 8 Bit LED register */
+ /* 0x0007: reserved */
+#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
+#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
+#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
+#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
+#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
+ /* 0x001c: reserved */
+
+/* B0 XMAC 1 registers */
+#define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
+ /* 0x0022 - 0x0027 reserved */
+#define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */
+ /* 0x002a - 0x002f reserved */
+#define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */
+ /* 0x0032 - 0x0033 reserved */
+#define B0_XM1_PHY_DATA 0x0034 /* 16 bit r/w XMAC 1 PHY Data Register */
+ /* 0x0036 - 0x003f reserved */
+
+/* B0 XMAC 2 registers */
+#define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/
+ /* 0x0042 - 0x0047 reserved */
+#define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */
+ /* 0x004a - 0x004f reserved */
+#define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */
+ /* 0x0052 - 0x0053 reserved */
+#define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
+ /* 0x0056 - 0x005f reserved */
+
+/* BMU Control Status Registers */
+#define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
+#define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
+#define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
+#define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/
+#define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
+#define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/
+ /* x0078 - 0x007f reserved */
+
+/*
+ * Bank 1
+ * - completely empty (this is the RAP Block window)
+ * Note: if RAP = 1 this page is reserved
+ */
+
+/*
+ * Bank 2
+ */
+/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
+
+#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
+ /* 0x0106 - 0x0107 reserved */
+#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
+ /* 0x010e - 0x010f reserved */
+#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
+ /* 0x0116 - 0x0117 reserved */
+#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
+#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
+#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration */
+#define B2_CHIP_REV 0x011b /* 8 bit Queen Chip Revision Number */
+ /* Eprom registers are currently of no use */
+#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 */
+#define B2_E_1 0x011d /* 8 bit EPROM Byte 1 */
+#define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
+#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
+#define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
+#define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
+ /* 0x0125 - 0x0127: reserved */
+#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */
+#define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
+ /* 0x012a - 0x012f: reserved */
+#define B2_TI_INI 0x0130 /* 32 bit Timer init value */
+#define B2_TI_VAL 0x0134 /* 32 bit Timer value */
+#define B2_TI_CRTL 0x0138 /* 8 bit Timer control */
+#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
+ /* 0x013a - 0x013f: reserved */
+#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
+#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
+#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
+#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
+#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
+#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
+ /* 0x0154 - 0x0157: reserved */
+#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
+#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
+ /* 0x015a - 0x015b: reserved */
+#define B2_GP_IO 0x015c /* 32 bit General Purpose IO Register */
+#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
+#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
+#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
+#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
+#define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */
+#define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */
+#define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
+#define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
+#define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
+ /* 0x017c - 0x017f: reserved */
+
+/*
+ * Bank 3
+ */
+#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
+#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
+#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
+ /* 0x018c - 0x018f: reserved */
+/* RAM Interface Registers */
+/*
+ * The HW-Spec. call this registers Timeout Value 0..11. But this names are
+ * not usable in SW. Please notice these are NOT real timeouts, these are
+ * the number of qWords transfered continously.
+ */
+#define B3_RI_WTO_R1 0x0190 /* 8 bit RAM Iface WR Timeout Queue R1 (TO0) */
+#define B3_RI_WTO_XA1 0x0191 /* 8 bit RAM Iface WR Timeout Queue XA1 (TO1) */
+#define B3_RI_WTO_XS1 0x0192 /* 8 bit RAM Iface WR Timeout Queue XS1 (TO2) */
+#define B3_RI_RTO_R1 0x0193 /* 8 bit RAM Iface RD Timeout Queue R1 (TO3) */
+#define B3_RI_RTO_XA1 0x0194 /* 8 bit RAM Iface RD Timeout Queue XA1 (TO4) */
+#define B3_RI_RTO_XS1 0x0195 /* 8 bit RAM Iface RD Timeout Queue XS1 (TO5) */
+#define B3_RI_WTO_R2 0x0196 /* 8 bit RAM Iface WR Timeout Queue R2 (TO6) */
+#define B3_RI_WTO_XA2 0x0197 /* 8 bit RAM Iface WR Timeout Queue XA2 (TO7) */
+#define B3_RI_WTO_XS2 0x0198 /* 8 bit RAM Iface WR Timeout Queue XS2 (TO8) */
+#define B3_RI_RTO_R2 0x0199 /* 8 bit RAM Iface RD Timeout Queue R2 (TO9) */
+#define B3_RI_RTO_XA2 0x019a /* 8 bit RAM Iface RD Timeout Queue XA2 (TO10)*/
+#define B3_RI_RTO_XS2 0x019b /* 8 bit RAM Iface RD Timeout Queue XS2 (TO11)*/
+#define B3_RI_TO_VAL 0x019c /* 8 bit RAM Iface Current Timeout Count Val */
+ /* 0x019d - 0x019f reserved */
+#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Iface Control Register */
+#define B3_RI_TEST 0x01a2 /* 8 bit RAM Iface Test Register */
+ /* 0x01a3 - 0x01af reserved */
+/* MAC Arbiter Registers */
+/* Please notice these are the number of qWord tranfered continously and */
+/* NOT real timeouts */
+#define B3_MA_TOINI_RX1 0x01b0 /* 8 bit Timeout Init Value Rx Path MAC 1 */
+#define B3_MA_TOINI_RX2 0x01b1 /* 8 bit Timeout Init Value Rx Path MAC 2 */
+#define B3_MA_TOINI_TX1 0x01b2 /* 8 bit Timeout Init Value Tx Path MAC 1 */
+#define B3_MA_TOINI_TX2 0x01b3 /* 8 bit Timeout Init Value Tx Path MAC 2 */
+#define B3_MA_TOVAL_RX1 0x01b4 /* 8 bit Timeout Value Rx Path MAC 1 */
+#define B3_MA_TOVAL_RX2 0x01b5 /* 8 bit Timeout Value Rx Path MAC 1 */
+#define B3_MA_TOVAL_TX1 0x01b6 /* 8 bit Timeout Value Tx Path MAC 2 */
+#define B3_MA_TOVAL_TX2 0x01b7 /* 8 bit Timeout Value Tx Path MAC 2 */
+#define B3_MA_TO_CTRL 0x01b8 /* 16 bit MAC Arbiter Timeout Ctrl Reg */
+#define B3_MA_TO_TEST 0x01ba /* 16 bit MAC Arbiter Timeout Test Reg */
+ /* 0x01bc - 0x01bf reserved */
+#define B3_MA_RCINI_RX1 0x01c0 /* 8 bit Recovery Init Value Rx Path MAC 1 */
+#define B3_MA_RCINI_RX2 0x01c1 /* 8 bit Recovery Init Value Rx Path MAC 2 */
+#define B3_MA_RCINI_TX1 0x01c2 /* 8 bit Recovery Init Value Tx Path MAC 1 */
+#define B3_MA_RCINI_TX2 0x01c3 /* 8 bit Recovery Init Value Tx Path MAC 2 */
+#define B3_MA_RCVAL_RX1 0x01c4 /* 8 bit Recovery Value Rx Path MAC 1 */
+#define B3_MA_RCVAL_RX2 0x01c5 /* 8 bit Recovery Value Rx Path MAC 1 */
+#define B3_MA_RCVAL_TX1 0x01c6 /* 8 bit Recovery Value Tx Path MAC 2 */
+#define B3_MA_RCVAL_TX2 0x01c7 /* 8 bit Recovery Value Tx Path MAC 2 */
+#define B3_MA_RC_CTRL 0x01c8 /* 16 bit MAC Arbiter Recovery Ctrl Reg */
+#define B3_MA_RC_TEST 0x01ca /* 16 bit MAC Arbiter Recovery Test Reg */
+ /* 0x01cc - 0x01cf reserved */
+/* Packet Arbiter Registers, This are real timeouts */
+#define B3_PA_TOINI_RX1 0x01d0 /* 16 bit Timeout Init Val Rx Path MAC 1*/
+ /* 0x01d2 - 0x01d3: reserved */
+#define B3_PA_TOINI_RX2 0x01d4 /* 16 bit Timeout Init Val Rx Path MAC 2*/
+ /* 0x01d6 - 0x01d7: reserved */
+#define B3_PA_TOINI_TX1 0x01d8 /* 16 bit Timeout Init Val Tx Path MAC 1*/
+ /* 0x01da - 0x01db: reserved */
+#define B3_PA_TOINI_TX2 0x01dc /* 16 bit Timeout Init Val Tx Path MAC 2*/
+ /* 0x01de - 0x01df: reserved */
+#define B3_PA_TOVAL_RX1 0x01e0 /* 16 bit Timeout Val Rx Path MAC 1 */
+ /* 0x01e2 - 0x01e3: reserved */
+#define B3_PA_TOVAL_RX2 0x01e4 /* 16 bit Timeout Val Rx Path MAC 2 */
+ /* 0x01e6 - 0x01e7: reserved */
+#define B3_PA_TOVAL_TX1 0x01e8 /* 16 bit Timeout Val Tx Path MAC 1 */
+ /* 0x01ea - 0x01eb: reserved */
+#define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
+ /* 0x01ee - 0x01ef: reserved */
+#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
+#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
+ /* 0x01f4 - 0x01ff: reserved */
+
+/*
+ * Bank 4 - 5
+ */
+
+/* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
+#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
+#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
+#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
+#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
+#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
+#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
+#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
+ /* 0x0213 - 0x027f: reserved */
+
+/*
+ * Bank 6
+ */
+/* External registers */
+#define B6_EXT_REG 0x0300
+
+/*
+ * Bank 7
+ */
+/* This is a copy of the Configuration register file (lower half) */
+#define B7_CFG_SPC 0x0380
+
+/*
+ * Bank 8 - 15
+ */
+/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
+#define B8_Q_REGS 0x0400
+
+/* Queue Register Offsets, use Q_ADDR() to access */
+#define Q_D 0x00 /* 8*32 bit Current Descriptor */
+#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
+#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
+#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
+#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
+#define Q_BC 0x30 /* 32 bit Current Byte Counter */
+#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
+#define Q_F 0x38 /* 32 bit Flag Register */
+#define Q_T1 0x3c /* 32 bit Test Register 1 */
+#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
+#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
+#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
+#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
+#define Q_T2 0x40 /* 32 bit Test Register 2 */
+#define Q_T3 0x44 /* 32 bit Test Register 3 */
+ /* 0x48 - 0x7f: reserved */
+
+/*
+ * Bank 16 - 23
+ */
+/* RAM Buffer Registers */
+#define B16_RAM_REGS 0x0800
+
+/* RAM Buffer Register Offsets */
+/* use RB_ADDR(Queue,Offs) to address */
+#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
+#define RB_END 0x04 /* 32 bit RAM Buffer End Address */
+#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
+#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
+#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack*/
+#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack*/
+#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
+#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
+ /* 0x10 - 0x1f: reserved for Tx RAM Buffer Registers */
+#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
+#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
+#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
+#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
+#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
+ /* 0x2c - 0x7f: reserved */
+
+/*
+ * Bank 24 - 25
+ */
+/* Receive MAC FIFO, Receive LED, and Link Sync regs, use MR_ADDR() to address*/
+#define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
+#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer*/
+ /* 0x0c08 - 0x0c0b reserved */
+#define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
+#define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
+#define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */
+#define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/
+#define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */
+#define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Timestamp Timeout */
+#define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/
+#define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */
+#define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */
+ /* 0x0c1f reserved */
+#define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */
+#define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */
+#define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */
+#define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */
+ /* 0x0c2a - 0x0c2f reserved */
+#define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */
+#define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */
+#define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register*/
+#define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */
+ /* 0x0c3a - 0x0c3b reserved */
+#define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
+ /* 0x0c3d - 0x0c7f reserved */
+
+/*
+ * Bank 26 - 27
+ */
+/* Transmit MAC FIFO and Transmit LED Registers, use MR_ADDR() to address */
+#define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
+#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
+#define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Pt*/
+#define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
+#define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
+#define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */
+#define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
+#define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush*/
+ /* 0x0c1b reserved */
+#define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
+#define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */
+#define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */
+ /* 0x0d1f reserved */
+#define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */
+#define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */
+#define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */
+#define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Register*/
+ /* 0x0d2a - 0x0d7f reserved */
+
+/*
+ * Bank 28
+ */
+/* Descriptor Poll Timer Registers */
+#define B28_DPT_INI 0x0e00 /* 32 bit Descriptor Poll Timer Init Val*/
+#define B28_DPT_VAL 0x0e04 /* 32 bit Descriptor Poll Timer Curr Val*/
+#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg*/
+ /* 0x0e09: reserved */
+#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg*/
+ /* 0x0e0b - 0x0e8f: reserved */
+
+/*
+ * Bank 29 - 31
+ */
+/* 0x0e90 - 0x0fff: reserved */
+
+/*
+ * Bank 0x20 - 0x3f
+ */
+/* 0x1000 - 0x1fff: reserved */
+
+/*
+ * Bank 0x40 - 0x4f
+ */
+/* XMAC 1 registers */
+#define B40_XMAC1 0x2000
+
+/*
+ * Bank 0x50 - 0x5f
+ */
+/* 0x2800 - 0x2fff: reserved */
+
+/*
+ * Bank 0x60 - 0x6f
+ */
+/* XMAC 2 registers */
+#define B40_XMAC2 0x3000
+
+/*
+ * Bank 0x70 - 0x7f
+ */
+/* 0x3800 - 0x3fff: reserved */
+
+/*
+ * Control Register Bit Definitions:
+ */
+/* B0_RAP 8 bit Register Address Port */
+ /* Bit 7: reserved */
+#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0, .., 6f = block 6f*/
+
+/* B0_CTST 16 bit Control/Status register */
+ /* Bit 15..10: reserved */
+#define CS_BUS_CLOCK (1<<9) /* Bit 9: Bus Clock 0/1 = 33/66MHz */
+#define CS_BUS_SLOT_SZ (1<<8) /* Bit 8: Slot Size 0/1 = 32/64 bit slot*/
+#define CS_ST_SW_IRQ (1<<7) /* Bit 7: Set IRQ SW Request */
+#define CS_CL_SW_IRQ (1<<6) /* Bit 6: Clear IRQ SW Request */
+#define CS_STOP_DONE (1<<5) /* Bit 5: Stop Master is finished */
+#define CS_STOP_MAST (1<<4) /* Bit 4: Command Bit to stop the master*/
+#define CS_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
+#define CS_MRST_SET (1<<2) /* Bit 2: Set Master reset */
+#define CS_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
+#define CS_RST_SET (1<<0) /* Bit 0: Set Software reset */
+
+/* B0_LED 8 Bit LED register */
+ /* Bit 7..2: reserved */
+#define LED_STAT_ON (1<<1) /* Bit 1: Status LED on */
+#define LED_STAT_OFF (1<<0) /* Bit 0: Status LED off */
+
+/* B0_ISRC 32 bit Interrupt Source Register */
+/* B0_IMSK 32 bit Interrupt Mask Register */
+/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
+/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
+#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */
+#define IS_HW_ERR (1UL<<31) /* Bit 31: Interrupt HW Error */
+ /* Bit 30: reserved */
+#define IS_PA_TO_RX1 (1L<<29) /* Bit 29: Packet Arb Timeout Rx1*/
+#define IS_PA_TO_RX2 (1L<<28) /* Bit 28: Packet Arb Timeout Rx2*/
+#define IS_PA_TO_TX1 (1L<<27) /* Bit 27: Packet Arb Timeout Tx1*/
+#define IS_PA_TO_TX2 (1L<<26) /* Bit 26: Packet Arb Timeout Tx2*/
+#define IS_I2C_READY (1L<<25) /* Bit 25: IRQ on end of I2C tx */
+#define IS_IRQ_SW (1L<<24) /* Bit 24: SW forced IRQ */
+#define IS_EXT_REG (1L<<23) /* Bit 23: IRQ from external reg */
+#define IS_TIMINT (1L<<22) /* Bit 22: IRQ from Timer */
+#define IS_MAC1 (1L<<21) /* Bit 21: IRQ from MAC 1 */
+#define IS_LNK_SYNC_M1 (1L<<20) /* Bit 20: Link Sync Cnt wrap M1 */
+#define IS_MAC2 (1L<<19) /* Bit 19: IRQ from MAC 2 */
+#define IS_LNK_SYNC_M2 (1L<<18) /* Bit 18: Link Sync Cnt wrap M2 */
+/* Receive Queue 1 */
+#define IS_R1_B (1L<<17) /* Bit 17: Q_R1 End of Buffer */
+#define IS_R1_F (1L<<16) /* Bit 16: Q_R1 End of Frame */
+#define IS_R1_C (1L<<15) /* Bit 15: Q_R1 Encoding Error */
+/* Receive Queue 2 */
+#define IS_R2_B (1L<<14) /* Bit 14: Q_R2 End of Buffer */
+#define IS_R2_F (1L<<13) /* Bit 13: Q_R2 End of Frame */
+#define IS_R2_C (1L<<12) /* Bit 12: Q_R2 Encoding Error */
+/* Synchronous Transmit Queue 1 */
+#define IS_XS1_B (1L<<11) /* Bit 11: Q_XS1 End of Buffer */
+#define IS_XS1_F (1L<<10) /* Bit 10: Q_XS1 End of Frame */
+#define IS_XS1_C (1L<<9) /* Bit 9: Q_XS1 Encoding Error */
+/* Asynchronous Transmit Queue 1 */
+#define IS_XA1_B (1L<<8) /* Bit 8: Q_XA1 End of Buffer */
+#define IS_XA1_F (1L<<7) /* Bit 7: Q_XA1 End of Frame */
+#define IS_XA1_C (1L<<6) /* Bit 6: Q_XA1 Encoding Error */
+/* Synchronous Transmit Queue 2 */
+#define IS_XS2_B (1L<<5) /* Bit 5: Q_XS2 End of Buffer */
+#define IS_XS2_F (1L<<4) /* Bit 4: Q_XS2 End of Frame */
+#define IS_XS2_C (1L<<3) /* Bit 3: Q_XS2 Encoding Error */
+/* Asynchronous Transmit Queue 2 */
+#define IS_XA2_B (1L<<2) /* Bit 2: Q_XA2 End of Buffer */
+#define IS_XA2_F (1L<<1) /* Bit 1: Q_XA2 End of Frame */
+#define IS_XA2_C (1L<<0) /* Bit 0: Q_XA2 Encoding Error */
+
+
+/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
+/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
+/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
+#define IS_ERR_MSK 0x00000fffL /* All Error bits */
+ /* Bit 31..12: reserved */
+#define IS_IRQ_MST_ERR (1L<<11) /* Bit 11: IRQ master error */
+ /* PERR,RMABORT,RTABORT,DATAPERR */
+#define IS_IRQ_STAT (1L<<10) /* Bit 10: IRQ status execption */
+ /* RMABORT, RTABORT, DATAPERR */
+#define IS_NO_STAT_M1 (1L<<9) /* Bit 9: No Rx Status from MAC1*/
+#define IS_NO_STAT_M2 (1L<<8) /* Bit 8: No Rx Status from MAC2*/
+#define IS_NO_TIST_M1 (1L<<7) /* Bit 7: No Timestamp from MAC1*/
+#define IS_NO_TIST_M2 (1L<<6) /* Bit 6: No Timestamp from MAC2*/
+#define IS_RAM_RD_PAR (1L<<5) /* Bit 5: RAM Read Parity Error */
+#define IS_RAM_WR_PAR (1L<<4) /* Bit 4: RAM Write Parity Error*/
+#define IS_M1_PAR_ERR (1L<<3) /* Bit 3: MAC 1 Parity Error */
+#define IS_M2_PAR_ERR (1L<<2) /* Bit 2: MAC 2 Parity Error */
+#define IS_R1_PAR_ERR (1L<<1) /* Bit 1: Queue R1 Parity Error */
+#define IS_R2_PAR_ERR (1L<<0) /* Bit 0: Queue R2 Parity Error */
+
+/* B2_CONN_TYP 8 bit Connector type */
+/* B2_PMD_TYP 8 bit PMD type */
+/* Values of connector and PMD type comply to SysKonnect internal std */
+
+/* B2_MAC_CFG 8 bit MAC Configuration */
+ /* Bit 7..2: reserved */
+#define CFG_DIS_M2_CLK (1<<1) /* Bit 1: Disable Clock for 2nd MAC */
+#define CFG_SNG_MAC (1<<0) /* Bit 0: MAC Config: 1=2 MACs / 0=1 MAC*/
+
+/* B2_CHIP_REV 8 bit Queen Chip Revision Number */
+#define FIRST_CHIP_REV 0x0a /* Initial Revision Value */
+
+/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
+#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
+
+/* B2_LD_CRTL 8 bit EPROM loader control register */
+/* Bits are currently reserved */
+
+/* B2_LD_TEST 8 bit EPROM loader test register */
+ /* Bit 7..4: reserved */
+#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
+#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
+#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
+#define LD_START (1<<0) /* Bit 0: Start loading FPROM */
+
+/*
+ * Timer Section
+ */
+/* B2_TI_CRTL 8 bit Timer control */
+/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
+ /* Bit 7..3: reserved */
+#define TIM_START (1<<2) /* Bit 2: Start Timer */
+#define TIM_STOP (1<<1) /* Bit 1: Stop Timer */
+#define TIM_CLR_IRQ (1<<0) /* Bit 0: Clear Timer IRQ, (!IRQM) */
+
+/* B2_TI_TEST 8 Bit Timer Test */
+/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
+/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
+ /* Bit 7..3: reserved */
+#define TIM_T_ON (1<<2) /* Bit 2: Test mode on */
+#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off */
+#define TIM_T_STEP (1<<0) /* Bit 0: Test step */
+
+/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
+/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
+ /* Bit 31..24: reserved */
+#define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */
+
+/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
+ /* Bit 7..2: reserved */
+#define DPT_START (1<<1) /* Bit 1: Start Desciptor Poll Timer */
+#define DPT_STOP (1<<0) /* Bit 0: Stop Desciptor Poll Timer */
+
+
+/* B2_TST_CTRL1 8 bit Test Control Register 1 */
+#define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RD */
+#define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR */
+#define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RD */
+#define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR */
+#define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */
+#define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */
+#define TST_CFG_WRITE_ON (1<<1) /* Bit 1: Enable Config Reg WR */
+#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: Disable Config Reg WR */
+
+/* B2_TST_CTRL2 8 bit Test Control Register 2 */
+ /* Bit 7..4: reserved */
+ /* force the following error on */
+ /* the next master read/write */
+#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */
+#define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */
+#define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */
+#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
+
+/* B2_GP_IO 32 bit General Purpose IO Register */
+ /* Bit 31..26: reserved */
+#define GP_DIR_9 (1L<<25) /* Bit 25: IO_9 direct, 0=I/1=O */
+#define GP_DIR_8 (1L<<24) /* Bit 24: IO_8 direct, 0=I/1=O */
+#define GP_DIR_7 (1L<<23) /* Bit 23: IO_7 direct, 0=I/1=O */
+#define GP_DIR_6 (1L<<22) /* Bit 22: IO_6 direct, 0=I/1=O */
+#define GP_DIR_5 (1L<<21) /* Bit 21: IO_5 direct, 0=I/1=O */
+#define GP_DIR_4 (1L<<20) /* Bit 20: IO_4 direct, 0=I/1=O */
+#define GP_DIR_3 (1L<<19) /* Bit 19: IO_3 direct, 0=I/1=O */
+#define GP_DIR_2 (1L<<18) /* Bit 18: IO_2 direct, 0=I/1=O */
+#define GP_DIR_1 (1L<<17) /* Bit 17: IO_1 direct, 0=I/1=O */
+#define GP_DIR_0 (1L<<16) /* Bit 16: IO_0 direct, 0=I/1=O */
+ /* Bit 15..10: reserved */
+#define GP_IO_9 (1L<<9) /* Bit 9: IO_9 pin */
+#define GP_IO_8 (1L<<8) /* Bit 8: IO_8 pin */
+#define GP_IO_7 (1L<<7) /* Bit 7: IO_7 pin */
+#define GP_IO_6 (1L<<6) /* Bit 6: IO_6 pin */
+#define GP_IO_5 (1L<<5) /* Bit 5: IO_5 pin */
+#define GP_IO_4 (1L<<4) /* Bit 4: IO_4 pin */
+#define GP_IO_3 (1L<<3) /* Bit 3: IO_3 pin */
+#define GP_IO_2 (1L<<2) /* Bit 2: IO_2 pin */
+#define GP_IO_1 (1L<<1) /* Bit 1: IO_1 pin */
+#define GP_IO_0 (1L<<0) /* Bit 0: IO_0 pin */
+
+/* B2_I2C_CTRL 32 bit I2C HW Control Register */
+#define I2C_FLAG (1UL<<31) /* Bit 31: Start read/write if WR*/
+#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
+#define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
+ /* Bit 8.. 5: reserved */
+#define I2C_BURST_LEN (1L<<4) /* Bit 4: Burst Len, 1/4 bytes */
+#define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */
+#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */
+#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
+#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
+#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
+#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
+#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
+#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
+#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
+#define I2C_STOP (1L<<0) /* Bit 0: Interrupt I2C transfer*/
+
+/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
+ /* Bit 31..1 reserved */
+#define I2C_CLR_IRQ (1<<0) /* Bit 0: Clear I2C IRQ */
+
+/* B2_I2C_SW 32 bit I2C HW SW Port Register */
+ /* Bit 7..3: reserved */
+#define I2C_DATA_DIR (1<<2) /* Bit 2: direction of I2C_DATA */
+#define I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
+#define I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
+
+/*
+ * I2C Address
+ */
+#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
+
+
+/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
+ /* Bit 7..2: reserved */
+#define BSC_START (1<<1) /* Bit 1: Start Blink Source Counter */
+#define BSC_STOP (1<<0) /* Bit 0: Stop Blink Source Counter */
+
+/* B2_BSC_STAT 8 bit Blink Source Counter Status */
+ /* Bit 7..1: reserved */
+#define BSC_SRC (1<<0) /* Bit 0: Blink Source, 0=Off / 1=On */
+
+/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
+#define BSC_T_ON (1<<2) /* Bit 2: Test mode on */
+#define BSC_T_OFF (1<<1) /* Bit 1: Test mode off */
+#define BSC_T_STEP (1<<0) /* Bit 0: Test step */
+
+
+/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
+ /* Bit 31..19: reserved */
+#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
+
+/* RAM Interface Registers */
+/* B3_RI_CTRL 16 bit RAM Iface Control Register */
+ /* Bit 15..10: reserved */
+#define RI_CLR_RD_PERR (1<<9) /* Bit 9: Clear IRQ RAM Read Parity Err */
+#define RI_CLR_WR_PERR (1<<8) /* Bit 8: Clear IRQ RAM Write Parity Err*/
+ /* Bit 7..2: reserved */
+#define RI_RST_CLR (1<<1) /* Bit 1: Clear RAM Interface Reset */
+#define RI_RST_SET (1<<0) /* Bit 0: Set RAM Interface Reset */
+
+/* B3_RI_TEST 8 bit RAM Iface Test Register */
+ /* Bit 15..4: reserved */
+#define RI_T_EV (1<<3) /* Bit 3: Timeout Event occured */
+#define RI_T_ON (1<<2) /* Bit 2: Timeout Timer Test On */
+#define RI_T_OFF (1<<1) /* Bit 1: Timeout Timer Test Off */
+#define RI_T_STEP (1<<0) /* Bit 0: Timeout Timer Step */
+
+/* MAC Arbiter Registers */
+/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
+ /* Bit 15..4: reserved */
+#define MA_FOE_ON (1<<3) /* Bit 3: XMAC Fast Output Enable ON */
+#define MA_FOE_OFF (1<<2) /* Bit 2: XMAC Fast Output Enable OFF */
+#define MA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
+#define MA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
+
+/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
+ /* Bit 15..8: reserved */
+#define MA_ENA_REC_TX2 (1<<7) /* Bit 7: Enable Recovery Timer TX2 */
+#define MA_DIS_REC_TX2 (1<<6) /* Bit 6: Disable Recovery Timer TX2 */
+#define MA_ENA_REC_TX1 (1<<5) /* Bit 5: Enable Recovery Timer TX1 */
+#define MA_DIS_REC_TX1 (1<<4) /* Bit 4: Disable Recovery Timer TX1 */
+#define MA_ENA_REC_RX2 (1<<3) /* Bit 3: Enable Recovery Timer RX2 */
+#define MA_DIS_REC_RX2 (1<<2) /* Bit 2: Disable Recovery Timer RX2 */
+#define MA_ENA_REC_RX1 (1<<1) /* Bit 1: Enable Recovery Timer RX1 */
+#define MA_DIS_REC_RX1 (1<<0) /* Bit 0: Disable Recovery Timer RX1 */
+
+/* Packet Arbiter Registers */
+/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
+ /* Bit 15..14: reserved */
+#define PA_CLR_TO_TX2 (1<<13) /* Bit 13: Clear IRQ Packet Timeout TX2 */
+#define PA_CLR_TO_TX1 (1<<12) /* Bit 12: Clear IRQ Packet Timeout TX1 */
+#define PA_CLR_TO_RX2 (1<<11) /* Bit 11: Clear IRQ Packet Timeout RX2 */
+#define PA_CLR_TO_RX1 (1<<10) /* Bit 10: Clear IRQ Packet Timeout RX1 */
+#define PA_ENA_TO_TX2 (1<<9) /* Bit 9: Enable Timeout Timer TX2 */
+#define PA_DIS_TO_TX2 (1<<8) /* Bit 8: Disable Timeout Timer TX2 */
+#define PA_ENA_TO_TX1 (1<<7) /* Bit 7: Enable Timeout Timer TX1 */
+#define PA_DIS_TO_TX1 (1<<6) /* Bit 6: Disable Timeout Timer TX1 */
+#define PA_ENA_TO_RX2 (1<<5) /* Bit 5: Enable Timeout Timer RX2 */
+#define PA_DIS_TO_RX2 (1<<4) /* Bit 4: Disable Timeout Timer RX2 */
+#define PA_ENA_TO_RX1 (1<<3) /* Bit 3: Enable Timeout Timer RX1 */
+#define PA_DIS_TO_RX1 (1<<2) /* Bit 2: Disable Timeout Timer RX1 */
+#define PA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
+#define PA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
+
+#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
+ PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
+
+/* Rx/Tx Path related Arbiter Test Registers */
+/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
+/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
+/* B3_PA_TEST 16 bit Packet Arbiter Test Register */
+/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
+#define TX2_T_EV (1<<15) /* Bit 15: TX2 Timeout/Recv Event occured*/
+#define TX2_T_ON (1<<14) /* Bit 14: TX2 Timeout/Recv Timer Test On*/
+#define TX2_T_OFF (1<<13) /* Bit 13: TX2 Timeout/Recv Timer Tst Off*/
+#define TX2_T_STEP (1<<12) /* Bit 12: TX2 Timeout/Recv Timer Step */
+#define TX1_T_EV (1<<11) /* Bit 11: TX1 Timeout/Recv Event occured*/
+#define TX1_T_ON (1<<10) /* Bit 10: TX1 Timeout/Recv Timer Test On*/
+#define TX1_T_OFF (1<<9) /* Bit 9: TX1 Timeout/Recv Timer Tst Off*/
+#define TX1_T_STEP (1<<8) /* Bit 8: TX1 Timeout/Recv Timer Step */
+#define RX2_T_EV (1<<7) /* Bit 7: RX2 Timeout/Recv Event occured*/
+#define RX2_T_ON (1<<6) /* Bit 6: RX2 Timeout/Recv Timer Test On*/
+#define RX2_T_OFF (1<<5) /* Bit 5: RX2 Timeout/Recv Timer Tst Off*/
+#define RX2_T_STEP (1<<4) /* Bit 4: RX2 Timeout/Recv Timer Step */
+#define RX1_T_EV (1<<3) /* Bit 3: RX1 Timeout/Recv Event occured*/
+#define RX1_T_ON (1<<2) /* Bit 2: RX1 Timeout/Recv Timer Test On*/
+#define RX1_T_OFF (1<<1) /* Bit 1: RX1 Timeout/Recv Timer Tst Off*/
+#define RX1_T_STEP (1<<0) /* Bit 0: RX1 Timeout/Recv Timer Step */
+
+
+/* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
+/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
+/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
+/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
+/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
+ /* Bit 31..24: reserved */
+#define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
+
+/* TXA_CTRL 8 bit Tx Arbiter Control Register */
+#define TXA_ENA_FSYNC (1<<7) /* Bit 7: Enable force of sync tx queue */
+#define TXA_DIS_FSYNC (1<<6) /* Bit 6: Disable force of sync tx queue*/
+#define TXA_ENA_ALLOC (1<<5) /* Bit 5: Enable alloc of free bandwidth*/
+#define TXA_DIS_ALLOC (1<<4) /* Bit 4: Disabl alloc of free bandwidth*/
+#define TXA_START_RC (1<<3) /* Bit 3: Start sync Rate Control */
+#define TXA_STOP_RC (1<<2) /* Bit 2: Stop sync Rate Control */
+#define TXA_ENA_ARB (1<<1) /* Bit 1: Enable Tx Arbiter */
+#define TXA_DIS_ARB (1<<0) /* Bit 0: Disable Tx Arbiter */
+
+/* TXA_TEST 8 bit Tx Arbiter Test Register */
+ /* Bit 7..6: reserved */
+#define TXA_INT_T_ON (1<<5) /* Bit 5: Tx Arb Interval Timer Test On */
+#define TXA_INT_T_OFF (1<<4) /* Bit 4: Tx Arb Interval Timer Test Off*/
+#define TXA_INT_T_STEP (1<<3) /* Bit 3: Tx Arb Interval Timer Step */
+#define TXA_LIM_T_ON (1<<2) /* Bit 2: Tx Arb Limit Timer Test On */
+#define TXA_LIM_T_OFF (1<<1) /* Bit 1: Tx Arb Limit Timer Test Off */
+#define TXA_LIM_T_STEP (1<<0) /* Bit 0: Tx Arb Limit Timer Step */
+
+/* TXA_STAT 8 bit Tx Arbiter Status Register */
+ /* Bit 7..1: reserved */
+#define TXA_PRIO_XS (1<<0) /* Bit 0: sync queue has prio to send */
+
+/* Q_BC 32 bit Current Byte Counter */
+ /* Bit 31..16: reserved */
+#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
+
+/* BMU Control Status Registers */
+/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
+/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
+/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
+/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
+/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
+/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
+/* Q_CSR 32 bit BMU Control/Status Register */
+ /* Bit 31..25: reserved */
+#define CSR_SV_IDLE (1L<<24) /* Bit 24: BMU SM Idle */
+ /* Bit 23..22: reserved */
+#define CSR_DESC_CLR (1L<<21) /* Bit 21: Clear Reset for Descr */
+#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
+#define CSR_FIFO_CLR (1L<<19) /* Bit 19: Clear Reset for FIFO */
+#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
+#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
+#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
+#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
+#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
+#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
+#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
+#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
+#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
+#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
+#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
+#define CSR_ENA_POL (1L<<7) /* Bit 7: Enable Descr Polling */
+#define CSR_DIS_POL (1L<<6) /* Bit 6: Disable Descr Polling */
+#define CSR_STOP (1L<<5) /* Bit 5: Stop Rx/Tx Queue */
+#define CSR_START (1L<<4) /* Bit 4: Start Rx/Tx Queue */
+#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: (Rx) Clear Parity IRQ */
+#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
+#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
+#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
+
+#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
+ CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
+#define CSR_CLR_RESET (CSR_DESC_CLR|CSR_FIFO_CLR|CSR_HPI_RUN|CSR_SV_RUN|\
+ CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
+
+
+/* Q_F 32 bit Flag Register */
+ /* Bit 28..31: reserved */
+#define F_ALM_FULL (1L<<27) (Rx) /* Bit 27: (Rx) FIFO almost full */
+#define F_EMPTY (1L<<27) (Tx) /* Bit 27: (Tx) FIFO empty flag */
+#define F_FIFO_EOF (1L<<26) /* Bit 26: Fag bit in FIFO */
+#define F_WM_REACHED (1L<<25) /* Bit 25: Watermark reached */
+ /* Bit 24: reserved */
+#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
+ /* Bit 15..11: reserved */
+#define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
+
+/* Q_T1 32 bit Test Register 1 */
+/* Holds four State Machine control Bytes */
+#define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
+#define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
+#define SM_CRTL_WR (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */
+#define SM_CRTL_TR (0xffL<<0) /* Bit 7.. 0: Control Transfer SM */
+
+/* Q_T1_TR 8 bit Test Register 1 Transfer SM */
+/* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */
+/* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */
+/* Q_T1_SV 8 bit Test Register 1 Supervisor SM */
+/* The control status byte of each machine looks like ... */
+#define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */
+#define SM_LOAD (1<<3) /* Bit 3: Load the SM with SM_STATE */
+#define SM_TEST_ON (1<<2) /* Bit 2: Switch on SM Test Mode */
+#define SM_TEST_OFF (1<<1) /* Bit 1: Go off the Test Mode */
+#define SM_STEP (1<<0) /* Bit 0: Step the State Machine */
+/* The encoding of the states is not supported by the Diagnostics Tool */
+
+/* Q_T2 32 bit Test Register 2 */
+ /* Bit 31..8: reserved */
+#define T2_AC_T_ON (1<<7) /* Bit 7: Address Counter Test Mode on */
+#define T2_AC_T_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/
+#define T2_BC_T_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */
+#define T2_BC_T_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */
+#define T2_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */
+#define T2_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */
+#define T2_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */
+#define T2_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
+
+/* Q_T3 32 bit Test Register 3 */
+ /* Bit 31..7: reserved */
+#define T3_MUX (7<<4) /* Bit 6.. 4: Mux Position */
+ /* Bit 3: reserved */
+#define T3_VRAM (7<<0) /* Bit 2.. 0: Virtual RAM Buffer Address */
+
+/* RAM Buffer Register Offsets */
+/* use RB_ADDR(Queue,Offs) to address */
+/* RB_START 32 bit RAM Buffer Start Address */
+/* RB_END 32 bit RAM Buffer End Address */
+/* RB_WP 32 bit RAM Buffer Write Pointer */
+/* RB_RP 32 bit RAM Buffer Read Pointer */
+/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
+/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pasue Pack */
+/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
+/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
+/* RB_PC 32 bit RAM Buffer Packet Counter */
+/* RB_LEV 32 bit RAM Buffer Level Register */
+ /* Bit 31..19: reserved */
+#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
+
+/* RB_TST2 8 bit RAM Buffer Test Register 2 */
+ /* Bit 4..7: reserved */
+#define RB_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
+#define RB_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
+#define RB_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
+#define RB_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
+
+/* RB_TST1 8 bit RAM Buffer Test Register 1 */
+ /* Bit 7: reserved */
+#define RB_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
+#define RB_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
+#define RB_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
+ /* Bit 3: reserved */
+#define RB_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
+#define RB_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
+#define RB_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
+
+/* RB_CTRL 8 bit RAM Buffer Control Register */
+ /* Bit 7..6: reserved */
+#define RB_ENA_STFWD (1<<5) /* Bit 5: Enable Store & Forward */
+#define RB_DIS_STFWD (1<<4) /* Bit 4: Disab. Store & Forward */
+#define RB_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
+#define RB_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
+#define RB_RST_CLR (1<<1) /* Bit 1: Clr RAM Buf STM Reset */
+#define RB_RST_SET (1<<0) /* Bit 0: Set RAM Buf STM Reset */
+
+
+/* Receive and Transmit MAC FIFO Registers, use MR_ADDR() to address */
+/* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
+/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
+/* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
+/* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter*/
+/* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
+/* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
+/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer*/
+/* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pt*/
+/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
+/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
+/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */
+ /* Bit 31..6: reserved */
+#define MFF_MSK 0x007fL /* Bit 5..0: MAC FIFO Address/Pointer Bits */
+
+/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
+ /* Bit 15..14: reserved */
+#define MFF_ENA_RDY_PAT (1<<13) /* Bit 13: Enable Ready Patch */
+#define MFF_DIS_RDY_PAT (1<<12) /* Bit 12: Disable Ready Patch */
+#define MFF_ENA_TIM_PAT (1<<11) /* Bit 11: Enable Timing Patch */
+#define MFF_DIS_TIM_PAT (1<<10) /* Bit 10: Disable Timing Patch */
+#define MFF_ENA_ALM_FUL (1<<9) /* Bit 9: Enable AlmostFull Sign*/
+#define MFF_DIS_ALM_FUL (1<<8) /* Bit 8: Disab. AlmostFull Sign*/
+#define MFF_ENA_PAUSE (1<<7) /* Bit 7: Enable Pause Signaling*/
+#define MFF_DIS_PAUSE (1<<6) /* Bit 6: Disab. Pause Signaling*/
+#define MFF_ENA_FLUSH (1<<5) /* Bit 5: Enable Frame Flushing */
+#define MFF_DIS_FLUSH (1<<4) /* Bit 4: Disab. Frame Flushing */
+#define MFF_ENA_TIST (1<<3) /* Bit 3: Enable Timestamp Gener*/
+#define MFF_DIS_TIST (1<<2) /* Bit 2: Disab. Timestamp Gener*/
+#define MFF_CLR_INTIST (1<<1) /* Bit 1: Clear IRQ No Timestamp*/
+#define MFF_CLR_INSTAT (1<<0) /* Bit 0: Clear IRQ No Status */
+
+#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
+
+/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
+#define MFF_CLR_PERR (1<<15) /* Bit 15: Clear Parity Error IRQ*/
+ /* Bit 14: reserved */
+#define MFF_ENA_PKT_REC (1<<13) /* Bit 13: Enable Packet Recovery*/
+#define MFF_DIS_PKT_REC (1<<12) /* Bit 12: Disable Packet Recov. */
+/* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1)Bit 11: Enable Timing Patch */
+/* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1)Bit 10: Disable Timing Patch */
+/* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1)Bit 9: Enable AlmostFull Sign*/
+/* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1)Bit 8: Disab. AlmostFull Sign*/
+#define MFF_ENA_W4E (1<<7) /* Bit 7: Enable Wait for Empty */
+#define MFF_DIS_W4E (1<<6) /* Bit 6: Disab. Wait for Empty */
+/* MFF_ENA_FLUSH (see RX_MFF_CTRL1)Bit 5: Enable Frame Flushing */
+/* MFF_DIS_FLUSH (see RX_MFF_CTRL1)Bit 4: Disab. Frame Flushing */
+#define MFF_ENA_LOOPB (1<<3) /* Bit 3: Enable Loopback */
+#define MFF_DIS_LOOPB (1<<2) /* Bit 2: Disable Loopback */
+#define MFF_CLR_MAC_RST (1<<1) /* Bit 1: Clear XMAC Reset */
+#define MFF_SET_MAC_RST (1<<0) /* Bit 0: Set XMAC Reset */
+
+#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
+
+/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
+/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
+ /* Bit 7: reserved */
+#define MFF_WSP_T_ON (1<<6) /* Bit 6: (Tx) Write Shadow Pt TestOn */
+#define MFF_WSP_T_OFF (1<<5) /* Bit 5: (Tx) Write Shadow Pt TstOff */
+#define MFF_WSP_INC (1<<4) /* Bit 4: (Tx) Write Shadow Pt Increm */
+#define MFF_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
+#define MFF_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
+#define MFF_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
+#define MFF_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
+
+/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
+/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
+ /* Bit 7: reserved */
+#define MFF_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
+#define MFF_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
+#define MFF_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
+ /* Bit 3: reserved */
+#define MFF_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
+#define MFF_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
+#define MFF_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
+
+/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
+/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
+ /* Bit 7..4: reserved */
+#define MFF_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
+#define MFF_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
+#define MFF_RST_CLR (1<<1) /* Bit 1: Clear MAC FIFO Reset */
+#define MFF_RST_SET (1<<0) /* Bit 0: Set MAC FIFO Reset */
+
+
+/* Receive, Transmit, and Link LED Counter Registers */
+/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
+/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
+/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
+ /* Bit 7..3: reserved */
+#define LED_START (1<<2) /* Bit 2: Start Timer */
+#define LED_STOP (1<<1) /* Bit 1: Stop Timer */
+#define LED_STATE (1<<0) /* Bit 0:(Rx/Tx)LED State, 1=LED on */
+#define LED_CLR_IRQ (1<<0) /* Bit 0:(Lnk) Clear Link IRQ */
+
+/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
+/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
+/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
+ /* Bit 7..3: reserved */
+#define LED_T_ON (1<<2) /* Bit 2: LED Counter Testmode On */
+#define LED_T_OFF (1<<1) /* Bit 1: LED Counter Testmode Off */
+#define LED_T_STEP (1<<0) /* Bit 0: LED Counter Step */
+
+/* LNK_LED_REG 8 bit Link LED Register */
+ /* Bit 7..6: reserved */
+#define LED_BLK_ON (1<<5) /* Bit 5: Link LED Blinking On */
+#define LED_BLK_OFF (1<<4) /* Bit 4: Link LED Blinking Off */
+#define LED_SYNC_ON (1<<3) /* Bit 3: Use Sync Wire to switch LED */
+#define LED_SYNC_OFF (1<<2) /* Bit 2: Disable Sync Wire Input */
+#define LED_ON (1<<1) /* Bit 1: switch LED on */
+#define LED_OFF (1<<0) /* Bit 0: switch LED off */
+
+
+/* Receive and Transmit Descriptors ******************************************/
+
+/* Transmit Descriptor struct */
+typedef struct s_HwTxd {
+ SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
+ SK_U32 TxNext ; /* Physical Address Pointer to the next TxD */
+ SK_U32 TxAdrLo ; /* Physical Tx Buffer Address lower dword */
+ SK_U32 TxAdrHi ; /* Physical Tx Buffer Address upper dword */
+ SK_U32 TxStat ; /* Transmit Frame Status Word */
+#ifndef SK_USE_REV_DESC
+ SK_U16 TxTcpOffs ; /* TCP Checksum Calculation Start Value */
+ SK_U16 TxRes1 ; /* 16 bit reserved field */
+ SK_U16 TxTcpWp ; /* TCP Checksum Write Position */
+ SK_U16 TxTcpSp ; /* TCP Checksum Calculation Start Position */
+#else /* SK_USE_REV_DESC */
+ SK_U16 TxRes1 ; /* 16 bit reserved field */
+ SK_U16 TxTcpOffs ; /* TCP Checksum Calculation Start Value */
+ SK_U16 TxTcpSp ; /* TCP Checksum Calculation Start Position */
+ SK_U16 TxTcpWp ; /* TCP Checksum Write Position */
+#endif /* SK_USE_REV_DESC */
+ SK_U32 TxRes2; /* 32 bit reserved field */
+} SK_HWTXD;
+
+/* Receive Descriptor struct */
+typedef struct s_HwRxd {
+ SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
+ SK_U32 RxNext ; /* Physical Address Pointer to the next TxD */
+ SK_U32 RxAdrLo ; /* Physical Receive Buffer Address lower dword*/
+ SK_U32 RxAdrHi ; /* Physical Receive Buffer Address upper dword*/
+ SK_U32 RxStat ; /* Receive Frame Status Word */
+ SK_U32 RxTiSt ; /* Receive Timestamp provided by the XMAC */
+#ifndef SK_USE_REV_DESC
+ SK_U16 RxTcpSum1 ; /* TCP Checksum 1 */
+ SK_U16 RxTcpSum2 ; /* TCP Checksum 2 */
+ SK_U16 RxTcpSp1 ; /* TCP Checksum Calculation Start Position 1 */
+ SK_U16 RxTcpSp2 ; /* TCP Checksum Calculation Start Position 2 */
+#else /* SK_USE_REV_DESC */
+ SK_U16 RxTcpSum2 ; /* TCP Checksum 2 */
+ SK_U16 RxTcpSum1 ; /* TCP Checksum 1 */
+ SK_U16 RxTcpSp2 ; /* TCP Checksum Calculation Start Position 2 */
+ SK_U16 RxTcpSp1 ; /* TCP Checksum Calculation Start Position 1 */
+#endif /* SK_USE_REV_DESC */
+} SK_HWRXD;
+
+/*
+ * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
+ * should set the define SK_USE_REV_DESC.
+ * Structures are 'normaly' not endianess dependent. But in
+ * this case the SK_U16 fields are bound to bit positions inside the
+ * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
+ * The bit positions inside a DWord are of course endianess dependent and
+ * swaps if the DWord is swaped by the hardware.
+ */
+
+
+/* Descriptor Bit Definition */
+/* TxCtrl Transmit Buffer Control Field */
+/* RxCtrl Receive Buffer Control Field */
+#define BMU_OWN (1UL<<31) /* Bit 31: OWN bit: 0=host/1=BMU */
+#define BMU_STF (1L<<30) /* Bit 30: Start of Frame ? */
+#define BMU_EOF (1L<<29) /* Bit 29: End of Frame ? */
+#define BMU_IRQ_EOB (1L<<28) /* Bit 28: Req "End of Buff" IRQ */
+#define BMU_IRQ_EOF (1L<<27) /* Bit 27: Req "End of Frame" IRQ*/
+/* TxCtrl specific bits */
+#define BMU_STFWD (1L<<26) /* Bit 26: (Tx) Store&Forward Frame */
+#define BMU_NO_FCS (1L<<25) /* Bit 25: (Tx) disable XMAC FCS gener*/
+#define BMU_SW (1L<<24) /* Bit 24: (Tx) 1 bit res. for SW use */
+/* RxCtrl specific bits */
+#define BMU_DEV_0 (1L<<26) /* Bit 26: (Rx) transfer data to Dev0 */
+#define BMU_STAT_VAL (1L<<25) /* Bit 25: (Rx) RxStat Valid */
+#define BMU_TIST_VAL (1L<<24) /* Bit 24: (Rx) RxTiSt Valid */
+ /* Bit 23..16: BMU Check Opcodes */
+#define BMU_CHECK 0x00550000L /* Default BMU check */
+#define BMU_TCP_CHECK 0x00560000L /* Descr with TCP ext */
+#define BMU_BBC 0x0000FFFFL /* Bit 15..0: Buffer Byte Counter */
+
+/* TxStat Transmit Frame Status Word */
+/* RxStat Receive Frame Status Word */
+/*
+ *Note: TxStat is reserved for ASIC loopback mode only
+ *
+ * The Bits of the Status words are defined in xmac_ii.h
+ * (see XMR_FS bits)
+ */
+
+/* other defines *************************************************************/
+
+/*
+ * FlashProm specification
+ */
+#define MAX_PAGES 0x20000L /* Every byte has a single page */
+#define MAX_FADDR 1 /* 1 byte per page */
+#define SKFDDI_PSZ 8 /* address PROM size */
+
+/* macros ********************************************************************/
+
+/*
+ * Receive and Transmit Queues
+ */
+#define Q_R1 0x0000 /* Receive Queue 1 */
+#define Q_R2 0x0080 /* Receive Queue 2 */
+#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
+#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
+#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
+#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
+
+/*
+ * Macro Q_ADDR()
+ *
+ * Use this macro to address the Receive and Transmit Queue Registers.
+ *
+ * para Queue Queue to address.
+ * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
+ * Offs Queue register offset.
+ * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
+ *
+ * usage SK_IN32(pAC,Q_ADDR(Q_R2,Q_BC),pVal)
+ */
+#define Q_ADDR(Queue,Offs) (B8_Q_REGS + (Queue) + (Offs))
+
+/*
+ * Macro RB_ADDR()
+ *
+ * Use this macro to address the RAM Buffer Registers.
+ *
+ * para Queue Queue to address.
+ * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
+ * Offs Queue register offset.
+ * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
+ *
+ * usage SK_IN32(pAC,RB_ADDR(Q_R2,RB_RP),pVal)
+ */
+#define RB_ADDR(Queue,Offs) (B16_RAM_REGS + (Queue) + (Offs))
+
+
+/*
+ * MAC Related Registers
+ */
+#define MAC_1 0 /* belongs to the port near the slot */
+#define MAC_2 1 /* belongs to the port far away from the slot */
+
+/*
+ * Macro MR_ADDR()
+ *
+ * Use this macro to address a MAC Related Registers in side the ASIC.
+ *
+ * para Queue Queue to address.
+ * Values: TXA_ITI_INI ... TXA_TEST,
+ * RX_MFF_EA ... RX_LED_TST,
+ * LNK_SYNC_INI ... LNK_LED_REG, and
+ * TX_MFF_EA ... TX_LED_TST
+ * Mac MAC to address.
+ * Values: MAC_1, MAC_2
+ *
+ * usage SK_IN32(pAC,MR_ADDR(MAC_1,TX_MFF_EA),pVal)
+ */
+#define MR_ADDR(Mac,Offs) (((Mac) << 7) + (Offs))
+
+
+
+/*
+ * macros to access the XMAC
+ *
+ * XM_IN16(), to read a 16 bit register (e.g. XM_MMU_CMD)
+ * XM_OUT16(), to write a 16 bit register (e.g. XM_MMU_CMD)
+ * XM_IN32(), to read a 32 bit register (e.g. XM_TX_EV_CNT)
+ * XM_OUT32(), to write a 32 bit register (e.g. XM_TX_EV_CNT)
+ * XM_INADDR(), to read a network address register (e.g. XM_SRC_CHK)
+ * XM_OUTADDR(), to write a network address register (e.g. XM_SRC_CHK)
+ * XM_INHASH(), to read the XM_HSM_CHK register
+ * XM_OUTHASH() to write the XM_HSM_CHK register
+ *
+ * para: Mac XMAC to address values: MAC_1 or MAC_2
+ * IoC I/O context needed for SK IO macros
+ * Reg XMAC Register to read or write
+ * (p)Val Value or pointer to the value which should be read or
+ * written.
+ *
+ * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value) ;
+ */
+
+#ifdef SK_LITTLE_ENDIAN
+#define XM_WORD_LO 0
+#define XM_WORD_HI 1
+#else /* !SK_LITTLE_ENDIAN */
+#define XM_WORD_LO 1
+#define XM_WORD_HI 0
+#endif /* !SK_LITTLE_ENDIAN */
+
+#define XMA(Mac,Reg) (((0x1000 << (Mac)) + 0x1000) | ((Reg) << 1))
+
+#define XM_IN16(IoC,Mac,Reg,pVal) SK_IN16((IoC),XMA((Mac),(Reg)),(pVal))
+#define XM_OUT16(IoC,Mac,Reg,Val) SK_OUT16((IoC),XMA((Mac),(Reg)),(Val))
+
+#define XM_IN32(IoC,Mac,Reg,pVal) { \
+ SK_IN16((IoC),XMA((Mac),(Reg)), \
+ (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \
+ SK_IN16((IoC),XMA((Mac),(Reg+2)), \
+ (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \
+}
+
+#define XM_OUT32(IoC,Mac,Reg,Val) { \
+ SK_OUT16((IoC),XMA((Mac),(Reg)), (SK_U16)((Val) & 0x0000ffffL));\
+ SK_OUT16((IoC),XMA((Mac),(Reg+2)),(SK_U16)(((Val)>>16) & 0x0000ffffL));\
+}
+
+/*
+ * Remember: we are always writing to / reading from LITTLE ENDIAN memory
+ */
+
+#define XM_INADDR(IoC, Mac, Reg, pVal) { \
+ SK_U16 Word; \
+ SK_U8 *pByte; \
+ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
+ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
+ pByte[0] = (SK_U8) (Word & 0x00ff); \
+ pByte[1] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
+ pByte[2] = (SK_U8) (Word & 0x00ff); \
+ pByte[3] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
+ pByte[4] = (SK_U8) (Word & 0x00ff); \
+ pByte[5] = (SK_U8) ((Word >> 8) & 0x00ff); \
+}
+
+#define XM_OUTADDR(IoC, Mac, Reg, pVal) { \
+ SK_U8 *pByte; \
+ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
+ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
+ (((SK_U16)(pByte[0]) & 0x00ff)| \
+ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
+ (((SK_U16)(pByte[2]) & 0x00ff)| \
+ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
+ (((SK_U16)(pByte[4]) & 0x00ff)| \
+ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
+}
+
+#define XM_INHASH(IoC, Mac, Reg, pVal) { \
+ SK_U16 Word; \
+ SK_U8 *pByte; \
+ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
+ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
+ pByte[0] = (SK_U8) (Word & 0x00ff); \
+ pByte[1] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
+ pByte[2] = (SK_U8) (Word & 0x00ff); \
+ pByte[3] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
+ pByte[4] = (SK_U8) (Word & 0x00ff); \
+ pByte[5] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
+ pByte[6] = (SK_U8) (Word & 0x00ff); \
+ pByte[7] = (SK_U8) ((Word >> 8) & 0x00ff); \
+}
+
+#define XM_OUTHASH(IoC, Mac, Reg, pVal) { \
+ SK_U8 *pByte; \
+ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
+ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
+ (((SK_U16)(pByte[0]) & 0x00ff)| \
+ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
+ (((SK_U16)(pByte[2]) & 0x00ff)| \
+ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
+ (((SK_U16)(pByte[4]) & 0x00ff)| \
+ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
+ (((SK_U16)(pByte[6]) & 0x00ff)| \
+ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
+}
+
+/*
+ * Different PHY Types
+ */
+#define SK_PHY_XMAC 0 /* integrated in Xmac II*/
+#define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
+#define SK_PHY_LONE 2 /* Level One LXT1000 */
+#define SK_PHY_NAT 3 /* National DP83891 */
+
+/*
+ * PHY addresses (bits 8..12 of PHY address reg)
+ */
+#define PHY_ADDR_XMAC (0<<8)
+#define PHY_ADDR_BCOM (1<<8)
+#define PHY_ADDR_LONE (3<<8)
+#define PHY_ADDR_NAT (0<<8)
+
+/*
+ * macros to access the PHY
+ *
+ * PHY_READ() read a 16 bit value from the PHY
+ * PHY_WIRTE() write a 16 bit value to the PHY
+ *
+ * para: IoC I/O context needed for SK IO macros
+ * pPort Pointer to port struct for PhyAddr
+ * Mac XMAC to address values: MAC_1 or MAC_2
+ * PhyReg PHY Register to read or write
+ * (p)Val Value or pointer to the value which should be read or
+ * written.
+ *
+ * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
+ */
+#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
+ SK_U16 Mmu; \
+ \
+ XM_OUT16((IoC),(Mac), XM_PHY_ADDR, (PhyReg)|(pPort)->PhyAddr); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ } \
+}
+
+#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \
+ SK_U16 Mmu; \
+ \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
+ } \
+ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg)|(pPort)->PhyAddr); \
+ XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
+ } \
+}
+
+/*
+ * Macro PCI_C()
+ *
+ * Use this macro to address PCI config register from the IO space.
+ *
+ * para Addr PCI configuration register to address.
+ * Values: PCI_VENDOR_ID ... PCI_VPD_ADDR,
+ *
+ * usage SK_IN16(pAC,PCI_C(PCI_VENDOR_ID),pVal);
+ */
+#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
+
+/*
+ * Macro SK_ADDR(Base,Addr)
+ *
+ * Calculates the effective HW address
+ *
+ * para Base IO- or memory base address
+ * Addr Address offset
+ *
+ * usage: May be used in SK_INxx and SK_OUTxx macros
+ * #define SK_IN8(pAC,Addr,pVal) ...\
+ * *pVal = (SK_U8) inp(SK_ADDR(pAC->Hw.Iop,Addr)))
+ */
+#ifdef SK_MEM_MAPPED_IO
+#define SK_HW_ADDR(Base,Addr) ((Base)+(Addr))
+#else /* SK_MEM_MAPPED_IO */
+#define SK_HW_ADDR(Base,Addr) ((Base)+(((Addr)&0x7F)|((Addr)>>7 ? 0x80:0)))
+#endif /* SK_MEM_MAPPED_IO */
+
+#define SZ_LONG (sizeof(SK_U32))
+
+/*
+ * Macro SK_HWAC_LINK_LED()
+ *
+ * Use this macro to set the link LED mode.
+ * para pAC Pointer to adapter context struct
+ * IoC I/O context needed for SK IO macros
+ * Port Port number
+ * Mode Mode to set for this LED
+ */
+#define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
+SK_OUT8(IoC, MR_ADDR(Port,LNK_LED_REG), Mode);
+
+
+/* typedefs *******************************************************************/
+
+
+/* function prototypes ********************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_SKGEHW_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skhwt.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.4 $
+ * Date: $Date: 1998/08/19 09:50:58 $
+ * Purpose: Defines for the hardware timer functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgehwt.h,v $
+ * Revision 1.4 1998/08/19 09:50:58 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.3 1998/08/14 07:09:29 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.2 1998/08/07 12:54:21 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.1 1998/08/07 09:32:58 gklug
+ * first version
+ *
+ *
+ *
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * SKGEHWT.H contains all defines and types for the timer functions
+ */
+
+#ifndef _SKGEHWT_H_
+#define _SKGEHWT_H_
+
+/*
+ * SK Hardware Timer
+ * - needed wherever the HWT module is used
+ * - use in Adapters context name pAC->Hwt
+ */
+typedef struct s_Hwt {
+ SK_U32 TStart ; /* HWT start */
+ SK_U32 TStop ; /* HWT stop */
+ int TActive ; /* HWT: flag : active/inactive */
+} SK_HWT;
+
+extern void SkHwtInit(SK_AC *pAC, SK_IOC Ioc);
+extern void SkHwtStart(SK_AC *pAC, SK_IOC Ioc, SK_U32 Time);
+extern void SkHwtStop(SK_AC *pAC, SK_IOC Ioc);
+extern SK_U32 SkHwtRead(SK_AC *pAC,SK_IOC Ioc);
+extern void SkHwtIsr(SK_AC *pAC, SK_IOC Ioc);
+#endif /* _SKGEHWT_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgei2c.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.16 $
+ * Date: $Date: 1999/11/12 08:24:10 $
+ * Purpose: Special genesis defines for I2C
+ * (taken from Monalisa (taken from Concentrator))
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgei2c.h,v $
+ * Revision 1.16 1999/11/12 08:24:10 malthoff
+ * Change voltage warning and error limits
+ * (warning +-5%, error +-10%).
+ *
+ * Revision 1.15 1999/09/14 14:14:43 malthoff
+ * The 1000BT Dual Link adapter has got only one Fan.
+ * The second Fan has been removed.
+ *
+ * Revision 1.14 1999/05/27 13:40:50 malthoff
+ * Fan Divisor = 1. Assuming fan with 6500 rpm.
+ *
+ * Revision 1.13 1999/05/20 14:56:55 malthoff
+ * Bug Fix: Missing brace in SK_LM80_FAN_FAKTOR.
+ *
+ * Revision 1.12 1999/05/20 09:22:00 cgoos
+ * Changes for 1000Base-T (Fan sensors).
+ *
+ * Revision 1.11 1998/10/14 05:57:22 cgoos
+ * Fixed compilation warnings.
+ *
+ * Revision 1.10 1998/09/04 08:37:00 malthoff
+ * bugfix: correct the SK_I2C_GET_CTL() macro.
+ *
+ * Revision 1.9 1998/08/25 06:10:03 gklug
+ * add: thresholds for all sensors
+ *
+ * Revision 1.8 1998/08/20 11:37:42 gklug
+ * chg: change Ioc to IoC
+ *
+ * Revision 1.7 1998/08/20 08:53:11 gklug
+ * fix: compiler errors
+ * add: Threshold values
+ *
+ * Revision 1.6 1998/08/17 11:37:09 malthoff
+ * Bugfix in SK_I2C_CTL macro. The parameter 'dev'
+ * has to be shifted 9 bits.
+ *
+ * Revision 1.5 1998/08/17 06:52:21 malthoff
+ * Remove unrequired macros.
+ * Add macros for accessing I2C SW register.
+ *
+ * Revision 1.4 1998/08/13 08:30:18 gklug
+ * add: conversion factors for read values
+ * add: new state SEN_VALEXT to read extension value of temperature sensor
+ *
+ * Revision 1.3 1998/08/12 13:37:56 gklug
+ * rmv: error numbers and messages
+ *
+ * Revision 1.2 1998/08/11 07:54:38 gklug
+ * add: sensor states for GE sensors
+ * add: Macro to access I2c hardware register
+ * chg: Error messages for I2c errors
+ *
+ * Revision 1.1 1998/07/17 11:27:56 gklug
+ * Created.
+ *
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * SKGEI2C.H contains all SK-98xx specific defines for the I2C handling
+ */
+
+#ifndef _INC_SKGEI2C_H_
+#define _INC_SKGEI2C_H_
+
+/*
+ * Macros to access the B2_I2C_CTRL
+ */
+#define SK_I2C_CTL(IoC,flag,dev,reg,burst) \
+ SK_OUT32(IoC,B2_I2C_CTRL,\
+ (flag ? 0x80000000UL : 0x0L ) | \
+ (((SK_U32) reg << 16) & I2C_ADDR) | \
+ (((SK_U32) dev << 9) & I2C_DEV_SEL) | \
+ (( burst << 4) & I2C_BURST_LEN) )
+
+#define SK_I2C_STOP(IoC) { \
+ SK_U32 I2cCtrl; \
+ SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
+ SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
+}
+
+#define SK_I2C_GET_CTL(Ioc,pI2cCtrl) SK_IN32(Ioc,B2_I2C_CTRL,pI2cCtrl)
+
+/*
+ * Macros to access the I2C SW Registers
+ */
+#define SK_I2C_SET_BIT(IoC, SetBits) { \
+ SK_U8 OrgBits; \
+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
+ SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SetBits)); \
+}
+
+#define SK_I2C_CLR_BIT(IoC,ClrBits) { \
+ SK_U8 OrgBits; \
+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
+ SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~(ClrBits)); \
+}
+
+#define SK_I2C_GET_SW(IoC,pI2cSw) SK_IN8(IoC,B2_I2C_SW,pI2cSw)
+
+/*
+ * define the possible sensor states
+ */
+#define SK_SEN_IDLE 0 /* Idle: sensor not read */
+#define SK_SEN_VALUE 1 /* Value Read cycle */
+#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
+
+/*
+ * Conversion factor to convert read Voltage sensor to milli Volt
+ * Conversion factor to convert read Temperature sensor to 10th degree Celsius
+ */
+#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
+#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
+#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for the
+ * extension value
+ */
+#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
+/* formula: counter = (22500*60)/(rpm * divisor * pulses/2)
+ * assuming: 6500rpm, 4 pulses, divisor 1
+ */
+
+/*
+ * Define sensor management data
+ * Maximum is reached on copperfield with dual Broadcom.
+ * Board specific maximum is in pAC->I2c.MaxSens
+ */
+#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
+#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
+
+/*
+ * Defines for the individual Thresholds
+ */
+
+/* Temperature sensor */
+#define SK_SEN_ERRHIGH0 800 /* Temperature High Err Threshold */
+#define SK_SEN_WARNHIGH0 700 /* Temperature High Warn Threshold */
+#define SK_SEN_WARNLOW0 100 /* Temperature Low Err Threshold */
+#define SK_SEN_ERRLOW0 0 /* Temperature Low Warn Threshold */
+
+/* VCC which should be 5 V */
+#define SK_SEN_ERRHIGH1 5588 /* Voltage PCI High Err Threshold */
+#define SK_SEN_WARNHIGH1 5346 /* Voltage PCI High Warn Threshold */
+#define SK_SEN_WARNLOW1 4664 /* Voltage PCI Low Err Threshold */
+#define SK_SEN_ERRLOW1 4422 /* Voltage PCI Low Warn Threshold */
+
+/*
+ * VIO may be 5 V or 3.3 V. Initialization takes two parts:
+ * 1. Initialize lowest lower limit and highest higher limit.
+ * 2. After the first value is read correct the upper or the lower limit to
+ * the appropriate C constant.
+ *
+ * Warning limits are +-5% of the exepected voltage.
+ * Error limits are +-10% of the expected voltage.
+ */
+#define SK_SEN_ERRHIGH2 5588 /* Voltage PCI-IO High Err Threshold */
+#define SK_SEN_WARNHIGH2 5346 /* Voltage PCI-IO High Warn Threshold */
+#define SK_SEN_WARNLOW2 3146 /* Voltage PCI-IO Low Err Threshold */
+#define SK_SEN_ERRLOW2 2970 /* Voltage PCI-IO Low Warn Threshold */
+
+/* correction values for the second pass */
+#define SK_SEN_ERRHIGH2C 3630 /* Voltage PCI-IO High Err Threshold */
+#define SK_SEN_WARNHIGH2C 3476 /* Voltage PCI-IO High Warn Threshold */
+#define SK_SEN_WARNLOW2C 4664 /* Voltage PCI-IO Low Err Threshold */
+#define SK_SEN_ERRLOW2C 4422 /* Voltage PCI-IO Low Warn Threshold */
+
+/*
+ * VDD voltage
+ */
+#define SK_SEN_ERRHIGH3 3630 /* Voltage ASIC High Err Threshold */
+#define SK_SEN_WARNHIGH3 3476 /* Voltage ASIC High Warn Threshold */
+#define SK_SEN_WARNLOW3 3146 /* Voltage ASIC Low Err Threshold */
+#define SK_SEN_ERRLOW3 2970 /* Voltage ASIC Low Warn Threshold */
+
+/*
+ * PLC_3V3 voltage
+ * PHY_PLL_A_3V3 voltage
+ */
+#define SK_SEN_ERRHIGH4 3630 /* Voltage PMA High Err Threshold */
+#define SK_SEN_WARNHIGH4 3476 /* Voltage PMA High Warn Threshold */
+#define SK_SEN_WARNLOW4 3146 /* Voltage PMA Low Err Threshold */
+#define SK_SEN_ERRLOW4 2970 /* Voltage PMA Low Warn Threshold */
+
+/*
+ * PHY_2V5 voltage
+ */
+#define SK_SEN_ERRHIGH5 2750 /* Voltage PHY High Err Threshold */
+#define SK_SEN_WARNHIGH5 2640 /* Voltage PHY High Warn Threshold */
+#define SK_SEN_WARNLOW5 2376 /* Voltage PHY Low Err Threshold */
+#define SK_SEN_ERRLOW5 2222 /* Voltage PHY Low Warn Threshold */
+
+/*
+ * PHY_PLL_B_3V3 voltage
+ */
+#define SK_SEN_ERRHIGH6 3630 /* Voltage PMA High Err Threshold */
+#define SK_SEN_WARNHIGH6 3476 /* Voltage PMA High Warn Threshold */
+#define SK_SEN_WARNLOW6 3146 /* Voltage PMA Low Err Threshold */
+#define SK_SEN_ERRLOW6 2970 /* Voltage PMA Low Warn Threshold */
+
+/*
+ * FAN 1 speed
+ */
+/* assuming: 6500rpm +-15%, 4 pulses,
+ * warning at: 80 %
+ * error at: 70 %
+ * no upper limit
+ */
+#define SK_SEN_ERRHIGH 20000 /* FAN Speed High Err Threshold */
+#define SK_SEN_WARNHIGH 20000 /* FAN Speed High Warn Threshold */
+#define SK_SEN_WARNLOW 5200 /* FAN Speed Low Err Threshold */
+#define SK_SEN_ERRLOW 4550 /* FAN Speed Low Warn Threshold */
+
+extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
+#endif /* n_INC_SKGEI2C_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgeinit.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.44 $
+ * Date: $Date: 1999/10/26 07:34:15 $
+ * Purpose: Structures and prototypes for the GE Init Module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgeinit.h,v $
+ * Revision 1.44 1999/10/26 07:34:15 malthoff
+ * The define SK_LNK_ON has been lost in v1.41.
+ *
+ * Revision 1.43 1999/10/06 09:30:16 cgoos
+ * Changed SK_XM_THR_JUMBO.
+ *
+ * Revision 1.42 1999/09/16 12:58:26 cgoos
+ * Changed SK_LED_STANDY macro to be independent of HW link sync.
+ *
+ * Revision 1.41 1999/07/30 06:56:14 malthoff
+ * Correct comment for SK_MS_STAT_UNSET.
+ *
+ * Revision 1.40 1999/05/27 13:38:46 cgoos
+ * Added SK_BMU_TX_WM.
+ * Made SK_BMU_TX_WM and SK_BMU_RX_WM user-definable.
+ * Changed XMAC Tx treshold to max. values.
+ *
+ * Revision 1.39 1999/05/20 14:35:26 malthoff
+ * Remove prototypes for SkGeLinkLED().
+ *
+ * Revision 1.38 1999/05/19 11:59:12 cgoos
+ * Added SK_MS_CAP_INDETERMINATED define.
+ *
+ * Revision 1.37 1999/05/19 07:32:33 cgoos
+ * Changes for 1000Base-T.
+ * LED-defines for HWAC_LINK_LED macro.
+ *
+ * Revision 1.36 1999/04/08 14:00:24 gklug
+ * add:Port struct field PLinkResCt
+ *
+ * Revision 1.35 1999/03/25 07:43:07 malthoff
+ * Add error string for SKERR_HWI_E018MSG.
+ *
+ * Revision 1.34 1999/03/12 16:25:57 malthoff
+ * Remove PPollRxD and PPollTxD.
+ * Add SKERR_HWI_E017MSG. and SK_DPOLL_MAX.
+ *
+ * Revision 1.33 1999/03/12 13:34:41 malthoff
+ * Add Autonegotiation error codes.
+ * Change defines for parameter Mode in SkXmSetRxCmd().
+ * Replace __STDC__ by SK_KR_PROTO.
+ *
+ * Revision 1.32 1999/01/25 14:40:20 mhaveman
+ * Added new return states for the virtual management port if multiple
+ * ports are active but differently configured.
+ *
+ * Revision 1.31 1998/12/11 15:17:02 gklug
+ * add: Link partnet autoneg states : Unknown Manual and Autonegotiation
+ *
+ * Revision 1.30 1998/12/07 12:17:04 gklug
+ * add: Link Partner autonegotiation flag
+ *
+ * Revision 1.29 1998/12/01 10:54:42 gklug
+ * add: variables for XMAC Errata
+ *
+ * Revision 1.28 1998/12/01 10:14:15 gklug
+ * add: PIsave saves the Interrupt status word
+ *
+ * Revision 1.27 1998/11/26 15:24:52 mhaveman
+ * Added link status states SK_LMODE_STAT_AUTOHALF and
+ * SK_LMODE_STAT_AUTOFULL which are used by PNMI.
+ *
+ * Revision 1.26 1998/11/26 14:53:01 gklug
+ * add:autoNeg Timeout variable
+ *
+ * Revision 1.25 1998/11/26 08:58:50 gklug
+ * add: Link Mode configuration (AUTO Sense mode)
+ *
+ * Revision 1.24 1998/11/24 13:30:27 gklug
+ * add: PCheckPar to port struct
+ *
+ * Revision 1.23 1998/11/18 13:23:26 malthoff
+ * Add SK_PKT_TO_MAX.
+ *
+ * Revision 1.22 1998/11/18 13:19:54 gklug
+ * add: PPrevShorts and PLinkBroken to port struct for WA XMAC Errata #C1
+ *
+ * Revision 1.21 1998/10/26 08:02:57 malthoff
+ * Add GIRamOffs.
+ *
+ * Revision 1.20 1998/10/19 07:28:37 malthoff
+ * Add prototyp for SkGeInitRamIface().
+ *
+ * Revision 1.19 1998/10/14 14:47:48 malthoff
+ * SK_TIMER should not be defined for Diagnostics.
+ * Add SKERR_HWI_E015MSG and SKERR_HWI_E016MSG.
+ *
+ * Revision 1.18 1998/10/14 14:00:03 gklug
+ * add: timer to port struct for workaround of Errata #2
+ *
+ * Revision 1.17 1998/10/14 11:23:09 malthoff
+ * Add prototype for SkXmAutoNegDone().
+ * Fix SkXmSetRxCmd() prototype statement.
+ *
+ * Revision 1.16 1998/10/14 05:42:29 gklug
+ * add: HWLinkUp flag to Port struct
+ *
+ * Revision 1.15 1998/10/09 08:26:33 malthoff
+ * Rename SK_RB_ULPP_B to SK_RB_LLPP_B.
+ *
+ * Revision 1.14 1998/10/09 07:11:13 malthoff
+ * bug fix: SK_FACT_53 is 85 not 117.
+ * Rework time out init values.
+ * Add GIPortUsage and corresponding defines.
+ * Add some error log messages.
+ *
+ * Revision 1.13 1998/10/06 14:13:14 malthoff
+ * Add prototyp for SkGeLoadLnkSyncCnt().
+ *
+ * Revision 1.12 1998/10/05 11:29:53 malthoff
+ * bug fix: A comment was not closed.
+ *
+ * Revision 1.11 1998/10/05 08:01:59 malthoff
+ * Add default Timeout- Threshold- and
+ * Watermark constants. Add QRam start and end
+ * variables. Also add vars to store the polling
+ * mode and receive command. Add new Error Log
+ * Messages and function prototypes.
+ *
+ * Revision 1.10 1998/09/28 13:34:48 malthoff
+ * Add mode bits for LED functions.
+ * Move Autoneg and Flow Ctrl bits from shgesirq.h
+ * Add the required Error Log Entries
+ * and Function Prototypes.
+ *
+ * Revision 1.9 1998/09/16 14:38:41 malthoff
+ * Rework the SK_LNK_xxx defines.
+ * Add error log message defines.
+ * Add prototypes for skxmac2.c
+ *
+ * Revision 1.8 1998/09/11 05:29:18 gklug
+ * add: init state of a port
+ *
+ * Revision 1.7 1998/09/08 08:35:52 gklug
+ * add: defines of the Init Levels
+ *
+ * Revision 1.6 1998/09/03 13:48:42 gklug
+ * add: Link strati, capabilities to Port struct
+ *
+ * Revision 1.5 1998/09/03 13:30:59 malthoff
+ * Add SK_LNK_BLINK and SK_LNK_PERM.
+ *
+ * Revision 1.4 1998/09/03 09:55:31 malthoff
+ * Add constants for parameters Dir and RstMode
+ * when calling SkGeStopPort().
+ * Rework the prototyp section.
+ * Add Queue Address offsets PRxQOff, PXsQOff, and PXaQOff.
+ * Remove Ioc with IoC.
+ *
+ * Revision 1.3 1998/08/19 09:11:54 gklug
+ * fix: struct are removed from c-source (see CCC)
+ * add: typedefs for all structs
+ *
+ * Revision 1.2 1998/07/28 12:38:26 malthoff
+ * The prototypes got the parameter 'IoC'.
+ *
+ * Revision 1.1 1998/07/23 09:50:24 malthoff
+ * Created.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEINIT_H_
+#define __INC_SKGEINIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * defines for modifying Link LED behaviour (has been used with SkGeLinkLED())
+ */
+#define SK_LNK_OFF LED_OFF
+#define SK_LNK_ON (LED_ON | LED_BLK_OFF| LED_SYNC_OFF)
+#define SK_LNK_BLINK (LED_ON | LED_BLK_ON | LED_SYNC_ON)
+#define SK_LNK_PERM (LED_ON | LED_BLK_OFF| LED_SYNC_ON)
+#define SK_LNK_TST (LED_ON | LED_BLK_ON | LED_SYNC_OFF)
+
+/*
+ * defines for parameter 'Mode' when calling SK_HWAC_LINK_LED()
+ */
+#define SK_LED_OFF LED_OFF
+#define SK_LED_ACTIVE (LED_ON | LED_BLK_OFF| LED_SYNC_OFF)
+#define SK_LED_STANDBY (LED_ON | LED_BLK_ON| LED_SYNC_OFF)
+
+/*
+ * defines for parameter 'Mode' when calling SkGeXmitLED()
+ */
+#define SK_LED_DIS 0
+#define SK_LED_ENA 1
+#define SK_LED_TST 2
+
+/*
+ * Counter and Timer constants, for a host clock of 62.5 MHz
+ */
+#define SK_XMIT_DUR 0x002faf08L /* 50 ms */
+#define SK_BLK_DUR 0x01dcd650L /* 500 ms */
+
+#define SK_DPOLL_DEF 0x00EE6B28L /* 250 ms */
+#define SK_DPOLL_MAX 0x00FFFFFFL /* ca. 268ms */
+
+#define SK_FACT_62 100 /* is given in percent */
+#define SK_FACT_53 85
+
+/*
+ * Timeout values
+ */
+#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
+#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
+#define SK_PKT_TO_MAX 0xffff /* Maximum value */
+#define SK_RI_TO_53 36 /* RAM interface timeout */
+
+/*
+ * RAM Buffer High Pause Threshold values
+ */
+#define SK_RB_ULPP ( 8 * 1024) /* Upper Level in kB/8 */
+#define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
+#define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
+
+#ifndef SK_BMU_RX_WM
+#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
+#endif
+#ifndef SK_BMU_TX_WM
+#define SK_BMU_TX_WM 0x600 /* BMU Rx Watermark */
+#endif
+
+/* XMAC II Tx Threshold */
+#define SK_XM_THR_REDL 0x01fb /* .. for redundant link usage */
+#define SK_XM_THR_SL 0x01fb /* .. for single link adapters */
+#define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
+#define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
+
+/* values for GIPortUsage */
+#define SK_RED_LINK 1 /* redundant link usage */
+#define SK_MUL_LINK 2 /* multiple link usage */
+#define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
+
+/* Minimum RAM Buffer Receive Queue Size */
+#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
+/*
+ * defines for parameter 'Dir' when calling SkGeStopPort()
+ */
+#define SK_STOP_TX 1 /* Stops the transmit path, resets the XMAC */
+#define SK_STOP_RX 2 /* Stops the receive path */
+#define SK_STOP_ALL 3 /* Stops rx and tx path, resets the XMAC */
+
+/*
+ * defines for parameter 'RstMode' when calling SkGeStopPort()
+ */
+#define SK_SOFT_RST 1 /* perform a software reset */
+#define SK_HARD_RST 2 /* perform a hardware reset */
+
+/*
+ * Define Init Levels
+ */
+#define SK_INIT_DATA 0 /* Init level 0: init data structures */
+#define SK_INIT_IO 1 /* Init level 1: init with IOs */
+#define SK_INIT_RUN 2 /* Init level 2: init for run time */
+
+/*
+ * Set Link Mode Parameter
+ */
+#define SK_LMODE_HALF 1 /* Half Duplex Mode */
+#define SK_LMODE_FULL 2 /* Full Duplex Mode */
+#define SK_LMODE_AUTOHALF 3 /* AutoHalf Duplex Mode */
+#define SK_LMODE_AUTOFULL 4 /* AutoFull Duplex Mode */
+#define SK_LMODE_AUTOBOTH 5 /* AutoBoth Duplex Mode */
+#define SK_LMODE_AUTOSENSE 6 /* configured mode auto sensing */
+#define SK_LMODE_INDETERMINATED 7 /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+
+/*
+ * Autonegotiation timeout in 100ms granularity.
+ */
+#define SK_AND_MAX_TO 6 /* Wait 600 msec before link comes up */
+
+/*
+ * Define Autonegotiation error codes here
+ */
+#define SK_AND_OK 0 /* no error */
+#define SK_AND_OTHER 1 /* other error than below */
+#define SK_AND_DUP_CAP 2 /* Duplex capabilities error */
+
+/*
+ * Link Capability value
+ */
+#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
+#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
+#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
+#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
+#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+
+/*
+ * Link mode current state
+ */
+#define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
+#define SK_LMODE_STAT_HALF 2 /* Half Duplex Mode */
+#define SK_LMODE_STAT_FULL 3 /* Full Duplex Mode */
+#define SK_LMODE_STAT_AUTOHALF 4 /* Half Duplex Mode obtained by AutoNeg */
+#define SK_LMODE_STAT_AUTOFULL 5 /* Half Duplex Mode obtained by AutoNeg */
+#define SK_LMODE_STAT_INDETERMINATED 6 /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+/*
+ * Set Flow Control Mode Parameter (and capabilities)
+ */
+#define SK_FLOW_MODE_NONE 1 /* No Flow Control */
+#define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */
+#define SK_FLOW_MODE_SYMMETRIC 3 /* Both station may send PAUSE */
+#define SK_FLOW_MODE_SYM_OR_REM 4 /* Both station may send PAUSE or
+ * just the remote station may send
+ * PAUSE
+ */
+#define SK_FLOW_MODE_INDETERMINATED 5 /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+
+/*
+ * Flow Control Status Parameter
+ */
+#define SK_FLOW_STAT_NONE 1 /* No Flow Control */
+#define SK_FLOW_STAT_REM_SEND 2 /* Remote Station sends PAUSE */
+#define SK_FLOW_STAT_LOC_SEND 3 /* Local station sends PAUSE */
+#define SK_FLOW_STAT_SYMMETRIC 4 /* Both station may send PAUSE */
+#define SK_FLOW_STAT_INDETERMINATED 5 /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+/*
+ * Master/Slave Mode capabilities
+ */
+#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
+#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
+#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
+#define SK_MS_CAP_INDETERMINATED (1<<3) /* Return value for virtual port if
+ * multiple ports are differently
+ * configured.
+ */
+
+/*
+ * Set Master/Slave Mode Parameter (and capabilities)
+ */
+#define SK_MS_MODE_AUTO 1 /* Automatic resolution */
+#define SK_MS_MODE_MASTER 2 /* This station is master */
+#define SK_MS_MODE_SLAVE 3 /* This station is slave */
+#define SK_MS_MODE_INDETERMINATED 4 /* Return value for virtual port if
+ * multiple ports are differently
+ */
+
+/*
+ * Master/Slave Status Parameter
+ */
+#define SK_MS_STAT_UNSET 1 /* The MS status is never been determ*/
+#define SK_MS_STAT_MASTER 2 /* This station is master */
+#define SK_MS_STAT_SLAVE 3 /* This station is slave */
+#define SK_MS_STAT_FAULT 4 /* MS resolution failed */
+#define SK_MS_STAT_INDETERMINATED 5 /* Return value for virtual port if
+ * multiple ports are differently
+ */
+
+/*
+ * defines for parameter 'Mode' when calling SkXmSetRxCmd()
+ */
+#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of rx frames */
+#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of rx frames */
+#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of rx f */
+#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of rx f */
+#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error*/
+#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error*/
+#define SK_BIG_PK_OK_ON (1<<6) /* Don't set rcvError bit for big fr */
+#define SK_BIG_PK_OK_OFF (1<<7) /* Set rcvError bit for big frames */
+
+/*
+ * States of PState
+ */
+#define SK_PRT_RESET 0 /* the port is reset */
+#define SK_PRT_STOP 1 /* the port is stopped (similar to sw reset) */
+#define SK_PRT_INIT 2 /* the port is initialized */
+#define SK_PRT_RUN 3 /* the port has an active link */
+
+/*
+ * Default receive frame limit for Workaround of XMAC Errata
+ */
+#define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
+
+/*
+ * Define link partner Status
+ */
+#define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
+#define SK_LIPA_MANUAL 1 /* Link partner is in detected manual state */
+#define SK_LIPA_AUTO 2 /* Link partner is in autonegotiation state */
+
+/*
+ * Define Maximum Restarts before restart is ignored (3com WA)
+ */
+#define SK_MAX_LRESTART 3 /* Max. 3 times the link is restarted */
+
+/* structures *****************************************************************/
+
+/*
+ * Port Structure
+ */
+typedef struct s_GePort {
+#ifndef SK_DIAG
+ SK_TIMER PWaTimer; /* Workaround Timer */
+#endif
+ SK_U64 PPrevShorts; /* Previous short Counter checking */
+ SK_U64 PPrevRx; /* Previous RxOk Counter checking */
+ SK_U64 PPrevFcs; /* Previous FCS Error Counter checking */
+ SK_U64 PRxLim; /* Previous RxOk Counter checking */
+ int PLinkResCt; /* Link Restart Counter */
+ int PAutoNegTimeOut;/* AutoNegotiation timeout current value */
+ int PRxQSize; /* Port Rx Queue Size in kB */
+ int PXSQSize; /* Port Synchronous Transmit Queue Size in kB */
+ int PXAQSize; /* Port Asynchronous Transmit Queue Size in kB*/
+ SK_U32 PRxQRamStart; /* Receive Queue RAM Buffer Start Address */
+ SK_U32 PRxQRamEnd; /* Receive Queue RAM Buffer End Address */
+ SK_U32 PXsQRamStart; /* Sync Tx Queue RAM Buffer Start Address */
+ SK_U32 PXsQRamEnd; /* Sync Tx Queue RAM Buffer End Address */
+ SK_U32 PXaQRamStart; /* Async Tx Queue RAM Buffer Start Address */
+ SK_U32 PXaQRamEnd; /* Async Tx Queue RAM Buffer End Address */
+ int PRxQOff; /* Rx Queue Address Offset */
+ int PXsQOff; /* Synchronous Tx Queue Address Offset */
+ int PXaQOff; /* Asynchronous Tx Queue Address Offset */
+ SK_U16 PRxCmd; /* Port Receive Command Configuration Value */
+ SK_U16 PIsave; /* Saved Interrupt status word */
+ SK_U16 PSsave; /* Saved PHY status word */
+ SK_BOOL PHWLinkUp; /* The hardware Link is up (wireing) */
+ SK_BOOL PState; /* Is port initialized ? */
+ SK_BOOL PLinkBroken; /* Is Link broken ? */
+ SK_BOOL PCheckPar; /* Do we check for parity errors ? */
+ SK_U8 PLinkCap; /* Link Capabilities */
+ SK_U8 PLinkModeConf; /* Link Mode configured */
+ SK_U8 PLinkMode; /* Link Mode currently used */
+ SK_U8 PLinkModeStatus; /* Link Mode Status */
+ SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */
+ SK_U8 PFlowCtrlMode; /* Flow Control Mode */
+ SK_U8 PFlowCtrlStatus; /* Flow Control Status */
+ SK_U8 PMSCap; /* Master/Slave Capabilities */
+ SK_U8 PMSMode; /* Master/Slave Mode */
+ SK_U8 PMSStatus; /* Master/Slave Status */
+ SK_U8 PAutoNegFail; /* Autonegotiation fail flag */
+ SK_U8 PLipaAutoNeg; /* Autonegotiation possible with Link Partner */
+ int PhyType; /* PHY used on this port */
+ SK_U16 PhyAddr; /* MDIO/MDC PHY address */
+} SK_GEPORT;
+
+/*
+ * Gigabit Ethernet Initalization Struct
+ * (has to be included in the adapter context
+ */
+typedef struct s_GeInit {
+ int GIMacsFound; /* Number of MACs found on this adapter */
+ int GIPciHwRev; /* PCI HW Revision Number */
+ SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
+ int GIRamSize; /* The RAM size of the adapter in kB */
+ int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
+ int GIPortUsage; /* driver port usage: SK_RED_LINK/SK_MUL_LINK */
+ SK_U32 GIPollTimerVal; /* Descriptor Poll Timer Init Val in clk ticks*/
+ int GILevel; /* Initialization Level Completed */
+ SK_BOOL GIAnyPortAct; /* Is True if one or more port is initialized */
+ SK_GEPORT GP[SK_MAX_MACS]; /* Port Dependent Information */
+} SK_GEINIT;
+
+/*
+ * Define the error numbers and messages for xmac_ii.c and skgeinit.c
+ */
+#define SKERR_HWI_E001 (SK_ERRBASE_HWINIT)
+#define SKERR_HWI_E001MSG "SkXmClrExactAddr() has got illegal parameters"
+#define SKERR_HWI_E002 (SKERR_HWI_E001+1)
+#define SKERR_HWI_E002MSG "SkGeInit() Level 1 call missing"
+#define SKERR_HWI_E003 (SKERR_HWI_E002+1)
+#define SKERR_HWI_E003MSG "SkGeInit() called with illegal init Level"
+#define SKERR_HWI_E004 (SKERR_HWI_E003+1)
+#define SKERR_HWI_E004MSG "SkGeInitPort() Queue size illegal configured"
+#define SKERR_HWI_E005 (SKERR_HWI_E004+1)
+#define SKERR_HWI_E005MSG "SkGeInitPort() cannot init running ports"
+#define SKERR_HWI_E006 (SKERR_HWI_E005+1)
+#define SKERR_HWI_E006MSG "SkGeXmInit(): PState does not match HW state"
+#define SKERR_HWI_E007 (SKERR_HWI_E006+1)
+#define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
+#define SKERR_HWI_E008 (SKERR_HWI_E007+1)
+#define SKERR_HWI_E008MSG "SkXmSetRxCmd() called with invalid Mode"
+#define SKERR_HWI_E009 (SKERR_HWI_E008+1)
+#define SKERR_HWI_E009MSG "SkGeCfgSync() called although PXSQSize zero"
+#define SKERR_HWI_E010 (SKERR_HWI_E009+1)
+#define SKERR_HWI_E010MSG "SkGeCfgSync() called with invalid parameters"
+#define SKERR_HWI_E011 (SKERR_HWI_E010+1)
+#define SKERR_HWI_E011MSG "SkGeInitPort() Receive Queue Size to small"
+#define SKERR_HWI_E012 (SKERR_HWI_E011+1)
+#define SKERR_HWI_E012MSG "SkGeInitPort() invalid Queue Size specified"
+#define SKERR_HWI_E013 (SKERR_HWI_E012+1)
+#define SKERR_HWI_E013MSG "SkGeInitPort() cfg changed for running queue"
+#define SKERR_HWI_E014 (SKERR_HWI_E013+1)
+#define SKERR_HWI_E014MSG "SkGeInitPort() unknown GIPortUsage specified"
+#define SKERR_HWI_E015 (SKERR_HWI_E014+1)
+#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
+#define SKERR_HWI_E016 (SKERR_HWI_E015+1)
+#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
+#define SKERR_HWI_E017 (SKERR_HWI_E016+1)
+#define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
+#define SKERR_HWI_E018 (SKERR_HWI_E017+1)
+#define SKERR_HWI_E018MSG "FATAL: SkGeStopPort() does not terminate"
+#define SKERR_HWI_E019 (SKERR_HWI_E018+1)
+#define SKERR_HWI_E019MSG ""
+
+/* function prototypes ********************************************************/
+
+#ifndef SK_KR_PROTO
+
+/*
+ * public functions in skgeinit.c
+ */
+extern void SkGePollRxD(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_BOOL PollRxD);
+
+extern void SkGePollTxD(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_BOOL PollTxD);
+
+extern void SkGeYellowLED(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int State);
+
+extern int SkGeCfgSync(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U32 IntTime,
+ SK_U32 LimCount,
+ int SyncMode);
+
+extern void SkGeLoadLnkSyncCnt(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U32 CntVal);
+
+extern void SkGeStopPort(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ int Dir,
+ int RstMode);
+
+extern int SkGeInit(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Level);
+
+extern void SkGeDeInit(
+ SK_AC *pAC,
+ SK_IOC IoC);
+
+extern int SkGeInitPort(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkGeXmitLED(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Led,
+ int Mode);
+
+extern void SkGeInitRamIface(
+ SK_AC *pAC,
+ SK_IOC IoC);
+
+/*
+ * public functions in skxmac2.c
+ */
+extern void SkXmSetRxCmd(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ int Mode);
+
+extern void SkXmClrExactAddr(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ int StartNum,
+ int StopNum);
+
+extern void SkXmFlushTxFifo(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmFlushRxFifo(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmSoftRst(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmHardRst(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmInitMac(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmInitDupMd(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmInitPauseMd(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern int SkXmAutoNegDone(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port);
+
+extern void SkXmAutoNegLipaXmac(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U16 IStatus);
+
+extern void SkXmAutoNegLipaBcom(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U16 IStatus);
+
+extern void SkXmAutoNegLipaLone(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U16 IStatus);
+
+extern void SkXmIrq(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Port,
+ SK_U16 IStatus);
+
+#else /* SK_KR_PROTO */
+
+/*
+ * public functions in skgeinit.c
+ */
+extern void SkGePollRxD();
+extern void SkGePollTxD();
+extern void SkGeYellowLED();
+extern int SkGeCfgSync();
+extern void SkGeLoadLnkSyncCnt();
+extern void SkGeStopPort();
+extern int SkGeInit();
+extern void SkGeDeInit();
+extern int SkGeInitPort();
+extern void SkGeXmitLED();
+extern void SkGeInitRamIface();
+
+/*
+ * public functions in skxmac2.c
+ */
+extern void SkXmSetRxCmd();
+extern void SkXmClrExactAddr();
+extern void SkXmFlushTxFifo();
+extern void SkXmFlushRxFifo();
+extern void SkXmSoftRst();
+extern void SkXmHardRst();
+extern void SkXmInitMac();
+extern void SkXmInitDupMd();
+extern void SkXmInitPauseMd();
+extern int SkXmAutoNegDone();
+extern void SkXmAutoNegLipa();
+extern void SkXmIrq();
+
+#endif /* SK_KR_PROTO */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_SKGEINIT_H_ */
--- /dev/null
+/*****************************************************************************
+ *
+ * Name: skgepnm2.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.24 $
+ * Date: $Date: 1999/04/13 15:11:11 $
+ * Purpose: Defines for Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgepnm2.h,v $
+ * Revision 1.24 1999/04/13 15:11:11 mhaveman
+ * Changed copyright.
+ *
+ * Revision 1.23 1999/01/28 15:07:12 mhaveman
+ * Changed default threshold for port switches per hour from 10
+ * to 240 which means 4 switches per minute. This fits better
+ * the granularity of 32 for the port switch estimate
+ * counter.
+ *
+ * Revision 1.22 1999/01/05 12:52:30 mhaveman
+ * Removed macro SK_PNMI_MICRO_SEC.
+ *
+ * Revision 1.21 1999/01/05 12:50:34 mhaveman
+ * Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit
+ * arithmetic is necessary if SK_TICKS_PER_SEC is 100.
+ *
+ * Revision 1.20 1998/12/09 14:02:53 mhaveman
+ * Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch
+ * threshold.
+ *
+ * Revision 1.19 1998/12/03 11:28:41 mhaveman
+ * Removed SK_PNMI_CHECKPTR macro.
+ *
+ * Revision 1.18 1998/12/03 11:21:00 mhaveman
+ * -Added pointer check macro SK_PNMI_CHECKPTR
+ * -Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for
+ * VPD key evaluation.
+ *
+ * Revision 1.17 1998/11/20 13:20:33 mhaveman
+ * Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set.
+ *
+ * Revision 1.16 1998/11/20 08:08:49 mhaveman
+ * Macro SK_PNMI_CHECKFLAGS has got a if clause.
+ *
+ * Revision 1.15 1998/11/03 13:53:40 mhaveman
+ * Fixed alignment problem in macor SK_PNMI_SET_STAT macro.
+ *
+ * Revision 1.14 1998/10/30 15:50:13 mhaveman
+ * Added macro SK_PNMI_MICRO_SEC()
+ *
+ * Revision 1.13 1998/10/30 12:32:20 mhaveman
+ * Added forgotten cast in SK_PNMI_READ_U32 macro.
+ *
+ * Revision 1.12 1998/10/29 15:40:26 mhaveman
+ * -Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now
+ * variable string length.
+ * -Defined SK_PNMI_CHECKFLAGS macro
+ *
+ * Revision 1.11 1998/10/29 08:53:34 mhaveman
+ * Removed SK_PNMI_RLM_XXX table indexed because these counters need
+ * not been saved over XMAC resets.
+ *
+ * Revision 1.10 1998/10/28 08:48:20 mhaveman
+ * -Added macros for storage according to alignment
+ * -Changed type of Instance to SK_U32 because of VPD
+ * -Removed trap structures. Not needed because of alignment problem
+ * -Changed type of Action form SK_U8 to int
+ *
+ * Revision 1.9 1998/10/21 13:34:45 mhaveman
+ * Shit, mismatched calculation of SK_PNMI_HUNDREDS_SEC. Corrected.
+ *
+ * Revision 1.8 1998/10/21 13:24:58 mhaveman
+ * Changed calculation of hundreds of seconds.
+ *
+ * Revision 1.7 1998/10/20 07:31:41 mhaveman
+ * Made type changes to unsigned int where possible.
+ *
+ * Revision 1.6 1998/09/04 17:04:05 mhaveman
+ * Added Sync counters to offset storage to provided settled values on
+ * port switch.
+ *
+ * Revision 1.5 1998/09/04 12:45:35 mhaveman
+ * Removed dummies for SK_DRIVER_ macros. They should be added by driver
+ * writer in skdrv2nd.h.
+ *
+ * Revision 1.4 1998/09/04 11:59:50 mhaveman
+ * Everything compiles now. Driver Macros for counting still missing.
+ *
+ * Revision 1.3 1998/08/24 12:01:35 mhaveman
+ * Intermediate state.
+ *
+ * Revision 1.2 1998/08/17 07:51:40 mhaveman
+ * Intermediate state.
+ *
+ * Revision 1.1 1998/08/11 09:08:40 mhaveman
+ * Intermediate state.
+ *
+ ****************************************************************************/
+
+#ifndef _SKGEPNM2_H_
+#define _SKGEPNM2_H_
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE !(FALSE)
+#endif
+
+/*
+ * General definitions
+ */
+#define SK_PNMI_CHIPSET 1 /* XMAC11800FP */
+
+#define SK_PNMI_BUS_PCI 1 /* PCI bus*/
+
+/*
+ * Actions
+ */
+#define SK_PNMI_ACT_IDLE 1
+#define SK_PNMI_ACT_RESET 2
+#define SK_PNMI_ACT_SELFTEST 3
+#define SK_PNMI_ACT_RESETCNT 4
+
+/*
+ * VPD releated defines
+ */
+#define SK_PNMI_VPD_ARR_SIZE 40
+#define SK_PNMI_VPD_STR_SIZE 5
+
+#define SK_PNMI_VPD_RW 1
+#define SK_PNMI_VPD_RO 2
+
+#define SK_PNMI_VPD_OK 0
+#define SK_PNMI_VPD_NOTFOUND 1
+#define SK_PNMI_VPD_CUT 2
+#define SK_PNMI_VPD_TIMEOUT 3
+#define SK_PNMI_VPD_FULL 4
+#define SK_PNMI_VPD_NOWRITE 5
+#define SK_PNMI_VPD_FATAL 6
+
+#define SK_PNMI_VPD_IGNORE 0
+#define SK_PNMI_VPD_CREATE 1
+#define SK_PNMI_VPD_DELETE 2
+
+
+/*
+ * RLMT related defines
+ */
+#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */
+
+/*
+ * Internal table definitions
+ */
+#define SK_PNMI_GET 0
+#define SK_PNMI_PRESET 1
+#define SK_PNMI_SET 2
+
+#define SK_PNMI_RO 0
+#define SK_PNMI_RW 1
+
+typedef struct s_OidTabEntry {
+ SK_U32 Id;
+ SK_U32 InstanceNo;
+ unsigned int StructSize;
+ unsigned int Offset;
+ int Access;
+ int (* Func)(SK_AC *pAc, SK_IOC pIo, int action,
+ SK_U32 Id, char* pBuf, unsigned int* pLen,
+ SK_U32 Instance, unsigned int TableIndex);
+ SK_U16 Param;
+} SK_PNMI_TAB_ENTRY;
+
+
+/*
+ * Trap lengths
+ */
+#define SK_PNMI_TRAP_SIMPLE_LEN 17
+#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46
+#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23
+#define SK_PNMI_TRAP_RLMT_PORT_LEN 23
+
+
+/*
+ * MAC statistic data structures
+ */
+#define SK_PNMI_HTX 0
+#define SK_PNMI_HTX_OCTET 1
+#define SK_PNMI_HTX_OCTETHIGH 1
+#define SK_PNMI_HTX_OCTETLOW 2
+#define SK_PNMI_HTX_BROADCAST 3
+#define SK_PNMI_HTX_MULTICAST 4
+#define SK_PNMI_HTX_UNICAST 5
+#define SK_PNMI_HTX_LONGFRAMES 6
+#define SK_PNMI_HTX_BURST 7
+#define SK_PNMI_HTX_PMACC 8
+#define SK_PNMI_HTX_MACC 9
+#define SK_PNMI_HTX_SINGLE_COL 10
+#define SK_PNMI_HTX_MULTI_COL 11
+#define SK_PNMI_HTX_EXCESS_COL 12
+#define SK_PNMI_HTX_LATE_COL 13
+#define SK_PNMI_HTX_DEFFERAL 14
+#define SK_PNMI_HTX_EXCESS_DEF 15
+#define SK_PNMI_HTX_UNDERRUN 16
+#define SK_PNMI_HTX_CARRIER 17
+#define SK_PNMI_HTX_UTILUNDER 18
+#define SK_PNMI_HTX_UTILOVER 19
+#define SK_PNMI_HTX_64 20
+#define SK_PNMI_HTX_127 21
+#define SK_PNMI_HTX_255 22
+#define SK_PNMI_HTX_511 23
+#define SK_PNMI_HTX_1023 24
+#define SK_PNMI_HTX_MAX 25
+#define SK_PNMI_HTX_RESERVED26 26
+#define SK_PNMI_HTX_RESERVED27 27
+#define SK_PNMI_HTX_RESERVED28 28
+#define SK_PNMI_HTX_RESERVED29 29
+#define SK_PNMI_HTX_RESERVED30 30
+#define SK_PNMI_HTX_RESERVED31 31
+#define SK_PNMI_HRX (32 + 0)
+#define SK_PNMI_HRX_OCTET (32 + 1)
+#define SK_PNMI_HRX_OCTETHIGH (32 + 1)
+#define SK_PNMI_HRX_OCTETLOW (32 + 2)
+#define SK_PNMI_HRX_BROADCAST (32 + 3)
+#define SK_PNMI_HRX_MULTICAST (32 + 4)
+#define SK_PNMI_HRX_UNICAST (32 + 5)
+#define SK_PNMI_HRX_PMACC (32 + 6)
+#define SK_PNMI_HRX_MACC (32 + 7)
+#define SK_PNMI_HRX_PMACC_ERR (32 + 8)
+#define SK_PNMI_HRX_MACC_UNKWN (32 + 9)
+#define SK_PNMI_HRX_BURST (32 + 10)
+#define SK_PNMI_HRX_MISSED (32 + 11)
+#define SK_PNMI_HRX_FRAMING (32 + 12)
+#define SK_PNMI_HRX_OVERFLOW (32 + 13)
+#define SK_PNMI_HRX_JABBER (32 + 14)
+#define SK_PNMI_HRX_CARRIER (32 + 15)
+#define SK_PNMI_HRX_IRLENGTH (32 + 16)
+#define SK_PNMI_HRX_SYMBOL (32 + 17)
+#define SK_PNMI_HRX_SHORTS (32 + 18)
+#define SK_PNMI_HRX_RUNT (32 + 19)
+#define SK_PNMI_HRX_TOO_LONG (32 + 20)
+#define SK_PNMI_HRX_FCS (32 + 21)
+#define SK_PNMI_HRX_RESERVED22 (32 + 22)
+#define SK_PNMI_HRX_CEXT (32 + 23)
+#define SK_PNMI_HRX_UTILUNDER (32 + 24)
+#define SK_PNMI_HRX_UTILOVER (32 + 25)
+#define SK_PNMI_HRX_64 (32 + 26)
+#define SK_PNMI_HRX_127 (32 + 27)
+#define SK_PNMI_HRX_255 (32 + 28)
+#define SK_PNMI_HRX_511 (32 + 29)
+#define SK_PNMI_HRX_1023 (32 + 30)
+#define SK_PNMI_HRX_MAX (32 + 31)
+
+#define SK_PNMI_HTX_SYNC 64
+#define SK_PNMI_HTX_SYNC_OCTET 65
+
+#define SK_PNMI_MAX_IDX (SK_PNMI_CNT_NO)
+
+/*
+ * MAC specific data
+ */
+typedef struct s_PnmiStatAddr {
+ SK_BOOL GetOffset; /* TRUE: Call GetStatVal function */
+ SK_U16 Param; /* XMAC register containing value */
+} SK_PNMI_STATADDR;
+
+
+/*
+ * SK_PNMI_STRUCT_DATA copy offset evaluation macros
+ */
+#define SK_PNMI_OFF(e) ((SK_U32)&(((SK_PNMI_STRUCT_DATA *)0)->e))
+#define SK_PNMI_MAI_OFF(e) ((SK_U32)&(((SK_PNMI_STRUCT_DATA *)0)->e))
+#define SK_PNMI_VPD_OFF(e) ((SK_U32)&(((SK_PNMI_VPD *)0)->e))
+#define SK_PNMI_SEN_OFF(e) ((SK_U32)&(((SK_PNMI_SENSOR *)0)->e))
+#define SK_PNMI_CHK_OFF(e) ((SK_U32)&(((SK_PNMI_CHECKSUM *)0)->e))
+#define SK_PNMI_STA_OFF(e) ((SK_U32)&(((SK_PNMI_STAT *)0)->e))
+#define SK_PNMI_CNF_OFF(e) ((SK_U32)&(((SK_PNMI_CONF *)0)->e))
+#define SK_PNMI_RLM_OFF(e) ((SK_U32)&(((SK_PNMI_RLMT *)0)->e))
+#define SK_PNMI_MON_OFF(e) ((SK_U32)&(((SK_PNMI_RLMT_MONITOR *)0)->e))
+#define SK_PNMI_TRP_OFF(e) ((SK_U32)&(((SK_PNMI_TRAP *)0)->e))
+
+#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \
+ Val32 = (s); \
+ pVal = (char *)(b) + ((SK_U32) \
+ &(((SK_PNMI_STRUCT_DATA *)0)-> \
+ ReturnStatus.ErrorStatus)); \
+ SK_PNMI_STORE_U32(pVal, Val32); \
+ Val32 = (o); \
+ pVal = (char *)(b) + ((SK_U32) \
+ &(((SK_PNMI_STRUCT_DATA *)0)-> \
+ ReturnStatus.ErrorOffset)); \
+ SK_PNMI_STORE_U32(pVal, Val32);}
+
+/*
+ * Time macros
+ */
+#if SK_TICKS_PER_SEC == 100
+#define SK_PNMI_HUNDREDS_SEC(t) (t)
+#else
+#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC))
+#endif
+
+/*
+ * Macros to work around alignment problems
+ */
+#ifndef SK_PNMI_STORE_U16
+#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \
+ *((char *)(p) + 1) = \
+ *(((char *)&(v)) + 1);}
+#endif
+
+#ifndef SK_PNMI_STORE_U32
+#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \
+ *((char *)(p) + 1) = \
+ *(((char *)&(v)) + 1); \
+ *((char *)(p) + 2) = \
+ *(((char *)&(v)) + 2); \
+ *((char *)(p) + 3) = \
+ *(((char *)&(v)) + 3);}
+#endif
+
+#ifndef SK_PNMI_STORE_U64
+#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \
+ *((char *)(p) + 1) = \
+ *(((char *)&(v)) + 1); \
+ *((char *)(p) + 2) = \
+ *(((char *)&(v)) + 2); \
+ *((char *)(p) + 3) = \
+ *(((char *)&(v)) + 3); \
+ *((char *)(p) + 4) = \
+ *(((char *)&(v)) + 4); \
+ *((char *)(p) + 5) = \
+ *(((char *)&(v)) + 5); \
+ *((char *)(p) + 6) = \
+ *(((char *)&(v)) + 6); \
+ *((char *)(p) + 7) = \
+ *(((char *)&(v)) + 7);}
+#endif
+
+#ifndef SK_PNMI_READ_U16
+#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \
+ *(((char *)&(v)) + 1) = \
+ *((char *)(p) + 1);}
+#endif
+
+#ifndef SK_PNMI_READ_U32
+#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \
+ *(((char *)&(v)) + 1) = \
+ *((char *)(p) + 1); \
+ *(((char *)&(v)) + 2) = \
+ *((char *)(p) + 2); \
+ *(((char *)&(v)) + 3) = \
+ *((char *)(p) + 3);}
+#endif
+
+#ifndef SK_PNMI_READ_U64
+#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \
+ *(((char *)&(v)) + 1) = \
+ *((char *)(p) + 1); \
+ *(((char *)&(v)) + 2) = \
+ *((char *)(p) + 2); \
+ *(((char *)&(v)) + 3) = \
+ *((char *)(p) + 3); \
+ *(((char *)&(v)) + 4) = \
+ *((char *)(p) + 4); \
+ *(((char *)&(v)) + 5) = \
+ *((char *)(p) + 5); \
+ *(((char *)&(v)) + 6) = \
+ *((char *)(p) + 6); \
+ *(((char *)&(v)) + 7) = \
+ *((char *)(p) + 7);}
+#endif
+
+/*
+ * Macros for Debug
+ */
+#ifdef DEBUG
+
+#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \
+ pAC->Pnmi.RlmtUpdatedFlag > 0 || \
+ pAC->Pnmi.SirqUpdatedFlag > 0) { \
+ SK_DBG_MSG(pAC, \
+ SK_DBGMOD_PNMI, \
+ SK_DBGCAT_CTRL, \
+ ("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \
+ vSt, \
+ pAC->Pnmi.MacUpdatedFlag, \
+ pAC->Pnmi.RlmtUpdatedFlag, \
+ pAC->Pnmi.SirqUpdatedFlag))}}
+
+#else /* !DEBUG */
+
+#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */
+
+#endif /* !DEBUG */
+
+#endif /* _SKGEPNM2_H_ */
--- /dev/null
+/*****************************************************************************
+ *
+ * Name: skgepnmi.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.37 $
+ * Date: $Date: 1999/09/14 14:25:32 $
+ * Purpose: Defines for Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgepnmi.h,v $
+ * Revision 1.37 1999/09/14 14:25:32 rwahl
+ * Set MDB version for 1000Base-T (sensors, Master/Slave) changes.
+ *
+ * Revision 1.36 1999/05/20 09:24:56 cgoos
+ * Changes for 1000Base-T (sensors, Master/Slave).
+ *
+ * Revision 1.35 1999/04/13 15:10:51 mhaveman
+ * Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to
+ * grant unified interface. But PNMI macros will store the same
+ * value as RLMT macros.
+ *
+ * Revision 1.34 1999/04/13 15:03:49 mhaveman
+ * -Changed copyright
+ * -Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be
+ * used.
+ *
+ * Revision 1.33 1999/03/23 10:41:02 mhaveman
+ * Changed comments.
+ *
+ * Revision 1.32 1999/01/25 15:01:33 mhaveman
+ * Added support for multiple simultaniously active ports.
+ *
+ * Revision 1.31 1999/01/19 10:06:26 mhaveman
+ * Added new error log message.
+ *
+ * Revision 1.30 1999/01/05 10:34:49 mhaveman
+ * Fixed little error in RlmtChangeEstimate calculation.
+ *
+ * Revision 1.29 1999/01/05 09:59:41 mhaveman
+ * Redesigned port switch average calculation to avoid 64bit
+ * arithmetic.
+ *
+ * Revision 1.28 1998/12/08 10:05:48 mhaveman
+ * Defined macro SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Revision 1.27 1998/12/03 14:39:35 mhaveman
+ * Fixed problem that LSTAT was enumerated wrong.
+ *
+ * Revision 1.26 1998/12/03 11:19:51 mhaveman
+ * Changed contents of errlog message SK_PNMI_ERR016MSG
+ *
+ * Revision 1.25 1998/12/01 10:40:04 mhaveman
+ * Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in
+ * SK_PNMI_STRUCT_DATA to be conform with OID definition.
+ *
+ * Revision 1.24 1998/11/20 08:09:27 mhaveman
+ * Added macros to convert between logical, physical port indexes and
+ * instances.
+ *
+ * Revision 1.23 1998/11/10 13:41:13 mhaveman
+ * Needed to change interface, because NT driver needs a return value
+ * of needed buffer space on TOO_SHORT errors. Therefore all
+ * SkPnmiGet/Preset/Set functions now have a pointer to the length
+ * parameter, where the needed space on error is returned.
+ *
+ * Revision 1.22 1998/11/03 12:05:51 mhaveman
+ * Added pAC parameter to counter macors.
+ *
+ * Revision 1.21 1998/11/02 10:47:36 mhaveman
+ * Added syslog messages for internal errors.
+ *
+ * Revision 1.20 1998/10/30 15:49:36 mhaveman
+ * -Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt.
+ * -Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds.
+ *
+ * Revision 1.19 1998/10/29 15:38:44 mhaveman
+ * Changed string lengths of PNMI_STRUCT_DATA structure because
+ * string OIDs are now encoded with leading length ocetet.
+ *
+ * Revision 1.18 1998/10/29 08:52:27 mhaveman
+ * -Added byte to strings in PNMI_STRUCT_DATA structure.
+ * -Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements.
+ *
+ * Revision 1.17 1998/10/28 08:49:50 mhaveman
+ * -Changed type of Instance back to SK_U32 because of VPD
+ * -Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD,
+ * and Connector.
+ *
+ * Revision 1.16 1998/10/22 10:42:31 mhaveman
+ * -Removed (SK_U32) casts for OIDs
+ * -excluded NDIS OIDs when they are already defined with ifndef _NDIS_
+ *
+ * Revision 1.15 1998/10/20 13:56:28 mhaveman
+ * Headerfile includes now directly other header files to comile correctly.
+ *
+ * Revision 1.14 1998/10/20 07:31:09 mhaveman
+ * Made type changes to unsigned int where possible.
+ *
+ * Revision 1.13 1998/10/19 10:53:13 mhaveman
+ * -Casted OID definitions to SK_U32
+ * -Renamed RlmtMAC... to RlmtPort...
+ * -Changed wrong type of VpdEntriesList from SK_U32 to char *
+ *
+ * Revision 1.12 1998/10/13 07:42:27 mhaveman
+ * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA
+ * -Removed old cvs history entries
+ * -Renamed MacNumber to PortNumber
+ *
+ * Revision 1.11 1998/10/07 10:55:24 mhaveman
+ * -Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs
+ * necessary.
+ * -Added OID_GEN_ Ids to support the windows driver.
+ *
+ * Revision 1.10 1998/09/30 13:41:10 mhaveman
+ * Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'.
+ *
+ * Revision 1.9 1998/09/04 17:06:17 mhaveman
+ * -Added SyncCounter as macro.
+ * -Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS.
+ * -Added macros for driver description and version strings.
+ *
+ * Revision 1.8 1998/09/04 14:36:52 mhaveman
+ * Added OIDs and Structure to access value of macro counters which are
+ * counted by the driver.
+ *
+ * Revision 1.7 1998/09/04 11:59:36 mhaveman
+ * Everything compiles now. Driver Macros for counting still missing.
+ *
+ ****************************************************************************/
+
+#ifndef _SKGEPNMI_H_
+#define _SKGEPNMI_H_
+
+/*
+ * Include dependencies
+ */
+#include "h/sktypes.h"
+#include "h/skerror.h"
+#include "h/sktimer.h"
+#include "h/ski2c.h"
+#include "h/skaddr.h"
+#include "h/skrlmt.h"
+
+
+/*
+ * Management Database Version
+ */
+#define SK_PNMI_MDB_VERSION 0x00030000 /* 3.0 */
+
+
+/*
+ * Event definitions
+ */
+#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */
+#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */
+#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */
+#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */
+#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
+#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
+#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
+
+#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
+#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
+#define SK_PNMI_EVT_RLMT_PORT_SWITCH 12 /* Switched active port */
+#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
+#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
+#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
+
+/*
+ * Return values
+ */
+#define SK_PNMI_ERR_OK 0
+#define SK_PNMI_ERR_GENERAL 1
+#define SK_PNMI_ERR_TOO_SHORT 2
+#define SK_PNMI_ERR_BAD_VALUE 3
+#define SK_PNMI_ERR_READ_ONLY 4
+#define SK_PNMI_ERR_UNKNOWN_OID 5
+#define SK_PNMI_ERR_UNKNOWN_INST 6
+
+
+/*
+ * Return values of driver reset function SK_DRIVER_RESET() and
+ * driver event function SK_DRIVER_EVENT()
+ */
+#define SK_PNMI_ERR_OK 0
+#define SK_PNMI_ERR_FAIL 1
+
+
+/*
+ * Return values of driver test function SK_DRIVER_SELFTEST()
+ */
+#define SK_PNMI_TST_UNKNOWN (1 << 0)
+#define SK_PNMI_TST_TRANCEIVER (1 << 1)
+#define SK_PNMI_TST_ASIC (1 << 2)
+#define SK_PNMI_TST_SENSOR (1 << 3)
+#define SK_PNMI_TST_POWERMGMT (1 << 4)
+#define SK_PNMI_TST_PCI (1 << 5)
+#define SK_PNMI_TST_MAC (1 << 6)
+
+
+/*
+ * RLMT specific definitions
+ */
+#define SK_PNMI_RLMT_STATUS_STANDBY 1
+#define SK_PNMI_RLMT_STATUS_ACTIVE 2
+#define SK_PNMI_RLMT_STATUS_ERROR 3
+
+#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1
+#define SK_PNMI_RLMT_LSTAT_AUTONEG 2
+#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3
+#define SK_PNMI_RLMT_LSTAT_LOG_UP 4
+#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5
+
+#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK)
+#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK)
+#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG)
+/* #define SK_PNMI_RLMT_MODE_CHK_EX */
+
+/*
+ * OID definition
+ */
+#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */
+
+#define OID_GEN_XMIT_OK 0x00020101
+#define OID_GEN_RCV_OK 0x00020102
+#define OID_GEN_XMIT_ERROR 0x00020103
+#define OID_GEN_RCV_ERROR 0x00020104
+#define OID_GEN_RCV_NO_BUFFER 0x00020105
+
+/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */
+#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
+/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */
+#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
+/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */
+#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
+/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */
+#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
+/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */
+#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
+/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */
+#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
+#define OID_GEN_RCV_CRC_ERROR 0x0002020D
+#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
+
+#define OID_802_3_PERMANENT_ADDRESS 0x01010101
+#define OID_802_3_CURRENT_ADDRESS 0x01010102
+/* #define OID_802_3_MULTICAST_LIST 0x01010103 */
+/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */
+/* #define OID_802_3_MAC_OPTIONS 0x01010105 */
+
+#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
+#define OID_802_3_XMIT_ONE_COLLISION 0x01020102
+#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
+#define OID_802_3_XMIT_DEFERRED 0x01020201
+#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
+#define OID_802_3_RCV_OVERRUN 0x01020203
+#define OID_802_3_XMIT_UNDERRUN 0x01020204
+#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
+#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
+
+#endif /* _NDIS_ */
+
+#define OID_SKGE_MDB_VERSION 0xFF010100
+#define OID_SKGE_SUPPORTED_LIST 0xFF010101
+#define OID_SKGE_VPD_FREE_BYTES 0xFF010102
+#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103
+#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104
+#define OID_SKGE_VPD_KEY 0xFF010105
+#define OID_SKGE_VPD_VALUE 0xFF010106
+#define OID_SKGE_VPD_ACCESS 0xFF010107
+#define OID_SKGE_VPD_ACTION 0xFF010108
+
+#define OID_SKGE_PORT_NUMBER 0xFF010110
+#define OID_SKGE_DEVICE_TYPE 0xFF010111
+#define OID_SKGE_DRIVER_DESCR 0xFF010112
+#define OID_SKGE_DRIVER_VERSION 0xFF010113
+#define OID_SKGE_HW_DESCR 0xFF010114
+#define OID_SKGE_HW_VERSION 0xFF010115
+#define OID_SKGE_CHIPSET 0xFF010116
+#define OID_SKGE_ACTION 0xFF010117
+#define OID_SKGE_RESULT 0xFF010118
+#define OID_SKGE_BUS_TYPE 0xFF010119
+#define OID_SKGE_BUS_SPEED 0xFF01011A
+#define OID_SKGE_BUS_WIDTH 0xFF01011B
+
+/*#define OID_SKGE_MULTICAST_LIST 0xFF01011C*/
+
+#define OID_SKGE_SENSOR_NUMBER 0xFF020100
+#define OID_SKGE_SENSOR_INDEX 0xFF020101
+#define OID_SKGE_SENSOR_DESCR 0xFF020102
+#define OID_SKGE_SENSOR_TYPE 0xFF020103
+#define OID_SKGE_SENSOR_VALUE 0xFF020104
+#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105
+#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106
+#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107
+#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108
+#define OID_SKGE_SENSOR_STATUS 0xFF020109
+#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A
+#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B
+#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C
+#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D
+
+#define OID_SKGE_CHKSM_NUMBER 0xFF020110
+#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111
+#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112
+#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113
+#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114
+#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115
+
+#define OID_SKGE_STAT_TX 0xFF020120
+#define OID_SKGE_STAT_TX_OCTETS 0xFF020121
+#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122
+#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123
+#define OID_SKGE_STAT_TX_UNICAST 0xFF020124
+#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125
+#define OID_SKGE_STAT_TX_BURST 0xFF020126
+#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127
+#define OID_SKGE_STAT_TX_FLOWC 0xFF020128
+#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129
+#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A
+#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B
+#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C
+#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D
+#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E
+#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F
+#define OID_SKGE_STAT_TX_CARRIER 0xFF020130
+/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */
+#define OID_SKGE_STAT_TX_64 0xFF020132
+#define OID_SKGE_STAT_TX_127 0xFF020133
+#define OID_SKGE_STAT_TX_255 0xFF020134
+#define OID_SKGE_STAT_TX_511 0xFF020135
+#define OID_SKGE_STAT_TX_1023 0xFF020136
+#define OID_SKGE_STAT_TX_MAX 0xFF020137
+#define OID_SKGE_STAT_TX_SYNC 0xFF020138
+#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139
+#define OID_SKGE_STAT_RX 0xFF02013A
+#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B
+#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C
+#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D
+#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E
+#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F
+#define OID_SKGE_STAT_RX_FLOWC 0xFF020140
+#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141
+#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142
+#define OID_SKGE_STAT_RX_BURST 0xFF020143
+#define OID_SKGE_STAT_RX_MISSED 0xFF020144
+#define OID_SKGE_STAT_RX_FRAMING 0xFF020145
+#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146
+#define OID_SKGE_STAT_RX_JABBER 0xFF020147
+#define OID_SKGE_STAT_RX_CARRIER 0xFF020148
+#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149
+#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A
+#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B
+#define OID_SKGE_STAT_RX_RUNT 0xFF02014C
+#define OID_SKGE_STAT_RX_CEXT 0xFF02014D
+#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E
+#define OID_SKGE_STAT_RX_FCS 0xFF02014F
+/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */
+#define OID_SKGE_STAT_RX_64 0xFF020151
+#define OID_SKGE_STAT_RX_127 0xFF020152
+#define OID_SKGE_STAT_RX_255 0xFF020153
+#define OID_SKGE_STAT_RX_511 0xFF020154
+#define OID_SKGE_STAT_RX_1023 0xFF020155
+#define OID_SKGE_STAT_RX_MAX 0xFF020156
+
+#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120
+#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121
+#define OID_SKGE_PMD 0xFF010122
+#define OID_SKGE_CONNECTOR 0xFF010123
+#define OID_SKGE_LINK_CAP 0xFF010124
+#define OID_SKGE_LINK_MODE 0xFF010125
+#define OID_SKGE_LINK_MODE_STATUS 0xFF010126
+#define OID_SKGE_LINK_STATUS 0xFF010127
+#define OID_SKGE_FLOWCTRL_CAP 0xFF010128
+#define OID_SKGE_FLOWCTRL_MODE 0xFF010129
+#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A
+#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B
+#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C
+#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D
+
+#define OID_SKGE_TRAP 0xFF010130
+#define OID_SKGE_TRAP_NUMBER 0xFF010131
+
+#define OID_SKGE_RLMT_MODE 0xFF010140
+#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
+#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
+#define OID_SKGE_RLMT_PORT_PREFERED 0xFF010143
+#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160
+#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161
+#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162
+#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163
+
+#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164
+#define OID_SKGE_RLMT_STATUS 0xFF020165
+#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166
+#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167
+#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
+#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
+
+#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
+#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
+#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
+#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
+#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
+#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
+
+#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
+#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
+#define OID_SKGE_TX_RETRY 0xFF020172
+#define OID_SKGE_RX_INTR_CTS 0xFF020173
+#define OID_SKGE_TX_INTR_CTS 0xFF020174
+#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175
+#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176
+#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177
+#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178
+#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179
+#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A
+#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B
+#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C
+#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D
+#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E
+#define OID_SKGE_SYSUPTIME 0xFF02017F
+
+#define OID_SKGE_ALL_DATA 0xFF020190
+
+
+#define OID_SKGE_TRAP_SEN_WAR_LOW 500
+#define OID_SKGE_TRAP_SEN_WAR_UPP 501
+#define OID_SKGE_TRAP_SEN_ERR_LOW 502
+#define OID_SKGE_TRAP_SEN_ERR_UPP 503
+#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520
+#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521
+#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522
+#define OID_SKGE_TRAP_RLMT_PORT_UP 523
+#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524
+
+
+/*
+ * Define error numbers and messages for syslog
+ */
+#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1)
+#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID"
+#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2)
+#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys"
+#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3)
+#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID"
+#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4)
+#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action"
+#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5)
+#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver"
+#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6)
+#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command"
+#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7)
+#define SK_PNMI_ERR007MSG "General: Driver description not initialized"
+#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8)
+#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID"
+#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9)
+#define SK_PNMI_ERR009MSG "Addr: Unknown OID"
+#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10)
+#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID"
+#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11)
+#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long"
+#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12)
+#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID"
+#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13)
+#define SK_PNMI_ERR013MSG "SensorStat: Unknown OID should be errored before"
+#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
+#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
+#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
+#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
+#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
+#define SK_PNMI_ERR016MSG "Vpd: Key string too long"
+#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
+#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer"
+#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18)
+#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid"
+#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19)
+#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long"
+#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21)
+#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long"
+#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22)
+#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before"
+#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23)
+#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action"
+#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24)
+#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action"
+#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25)
+#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry"
+#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26)
+#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD"
+#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27)
+#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry"
+#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28)
+#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry"
+#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29)
+#define SK_PNMI_ERR029MSG "General: Driver description string too long"
+#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30)
+#define SK_PNMI_ERR030MSG "General: Driver version not initialized"
+#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31)
+#define SK_PNMI_ERR031MSG "General: Driver version string too long"
+#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32)
+#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr"
+#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33)
+#define SK_PNMI_ERR033MSG "General: HW description string too long"
+#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34)
+#define SK_PNMI_ERR034MSG "General: Unknown OID"
+#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35)
+#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID"
+#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
+#define SK_PNMI_ERR036MSG "Rlmt: Unknown OID should be errored before"
+#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
+#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
+#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
+#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
+#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
+#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
+#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
+#define SK_PNMI_ERR040MSG "RlmtStat: Unknown OID should be errored before"
+#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41)
+#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID"
+#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42)
+#define SK_PNMI_ERR042MSG "MacPrivateConf: Unknown OID should be errored before"
+#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43)
+#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0"
+#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44)
+#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0"
+#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45)
+#define SK_PNMI_ERR045MSG "MacPrivateConf: Unknown OID in set action"
+#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
+#define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
+#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
+#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
+#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
+#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
+#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
+#define SK_PNMI_ERR049MSG ""
+#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
+#define SK_PNMI_ERR050MSG "MacUpdate: Cannot update statistic counter"
+#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51)
+#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious"
+
+/*
+ * Management counter macros called by the driver
+ */
+#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \
+ (char *)(v))
+
+#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \
+ (char *)(v))
+
+#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v) \
+ { \
+ (pAC)->Pnmi.TxSwQueueLen = (SK_U64)(v); \
+ if ((pAC)->Pnmi.TxSwQueueLen > (pAC)->Pnmi.TxSwQueueMax) { \
+ (pAC)->Pnmi.TxSwQueueMax = (pAC)->Pnmi.TxSwQueueLen; \
+ } \
+ }
+#define SK_PNMI_CNT_TX_RETRY(pAC) (((pAC)->Pnmi.TxRetryCts)++)
+#define SK_PNMI_CNT_RX_INTR(pAC) (((pAC)->Pnmi.RxIntrCts)++)
+#define SK_PNMI_CNT_TX_INTR(pAC) (((pAC)->Pnmi.TxIntrCts)++)
+#define SK_PNMI_CNT_NO_RX_BUF(pAC) (((pAC)->Pnmi.RxNoBufCts)++)
+#define SK_PNMI_CNT_NO_TX_BUF(pAC) (((pAC)->Pnmi.TxNoBufCts)++)
+#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v) \
+ ((pAC)->Pnmi.TxUsedDescrNo=(SK_U64)(v));
+#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v) \
+ { \
+ ((pAC)->Pnmi.RxDeliveredCts)++; \
+ (pAC)->Pnmi.RxOctetsDeliveredCts += (SK_U64)(v); \
+ }
+#define SK_PNMI_CNT_ERR_RECOVERY(pAC) (((pAC)->Pnmi.ErrRecoveryCts)++);
+
+#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \
+ { \
+ if (((p) >= 0) && ((p) < SK_MAX_MACS)) { \
+ ((pAC)->Pnmi.StatSyncCts[p])++; \
+ (pAC)->Pnmi.StatSyncOctetsCts[p] += (SK_U64)(v); \
+ } \
+ }
+
+/*
+ * Conversion Macros
+ */
+#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1)
+#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1)
+#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1)
+#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1)
+#define SK_PNMI_PORT_PHYS2INST(p) ((unsigned int)(p) + 2)
+#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2)
+
+/*
+ * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
+ */
+#define SK_PNMI_VPD_ENTRIES 20
+#define SK_PNMI_VPD_DATALEN 128
+#define SK_PNMI_MULTICAST_LISTLEN 64
+#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS)
+#define SK_PNMI_CHECKSUM_ENTRIES 3
+#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1)
+#define SK_PNMI_MONITOR_ENTRIES 20
+#define SK_PNMI_TRAP_ENTRIES 10
+#define SK_PNMI_TRAPLEN 128
+#define SK_PNMI_STRINGLEN1 80
+#define SK_PNMI_STRINGLEN2 25
+#define SK_PNMI_TRAP_QUEUE_LEN 512
+
+typedef struct s_PnmiVpd {
+ char VpdKey[5];
+ char VpdValue[SK_PNMI_VPD_DATALEN];
+ SK_U8 VpdAccess;
+ SK_U8 VpdAction;
+} SK_PNMI_VPD;
+
+typedef struct s_PnmiSensor {
+ SK_U8 SensorIndex;
+ char SensorDescr[SK_PNMI_STRINGLEN2];
+ SK_U8 SensorType;
+ SK_U32 SensorValue;
+ SK_U32 SensorWarningThresholdLow;
+ SK_U32 SensorWarningThresholdHigh;
+ SK_U32 SensorErrorThresholdLow;
+ SK_U32 SensorErrorThresholdHigh;
+ SK_U8 SensorStatus;
+ SK_U64 SensorWarningCts;
+ SK_U64 SensorErrorCts;
+ SK_U64 SensorWarningTimestamp;
+ SK_U64 SensorErrorTimestamp;
+} SK_PNMI_SENSOR;
+
+typedef struct s_PnmiChecksum {
+ SK_U64 ChecksumRxOkCts;
+ SK_U64 ChecksumRxUnableCts;
+ SK_U64 ChecksumRxErrCts;
+ SK_U64 ChecksumTxOkCts;
+ SK_U64 ChecksumTxUnableCts;
+} SK_PNMI_CHECKSUM;
+
+typedef struct s_PnmiStat {
+ SK_U64 StatTxOkCts;
+ SK_U64 StatTxOctetsOkCts;
+ SK_U64 StatTxBroadcastOkCts;
+ SK_U64 StatTxMulticastOkCts;
+ SK_U64 StatTxUnicastOkCts;
+ SK_U64 StatTxLongFramesCts;
+ SK_U64 StatTxBurstCts;
+ SK_U64 StatTxPauseMacCtrlCts;
+ SK_U64 StatTxMacCtrlCts;
+ SK_U64 StatTxSingleCollisionCts;
+ SK_U64 StatTxMultipleCollisionCts;
+ SK_U64 StatTxExcessiveCollisionCts;
+ SK_U64 StatTxLateCollisionCts;
+ SK_U64 StatTxDeferralCts;
+ SK_U64 StatTxExcessiveDeferralCts;
+ SK_U64 StatTxFifoUnderrunCts;
+ SK_U64 StatTxCarrierCts;
+ SK_U64 Dummy1; /* StatTxUtilization */
+ SK_U64 StatTx64Cts;
+ SK_U64 StatTx127Cts;
+ SK_U64 StatTx255Cts;
+ SK_U64 StatTx511Cts;
+ SK_U64 StatTx1023Cts;
+ SK_U64 StatTxMaxCts;
+ SK_U64 StatTxSyncCts;
+ SK_U64 StatTxSyncOctetsCts;
+ SK_U64 StatRxOkCts;
+ SK_U64 StatRxOctetsOkCts;
+ SK_U64 StatRxBroadcastOkCts;
+ SK_U64 StatRxMulticastOkCts;
+ SK_U64 StatRxUnicastOkCts;
+ SK_U64 StatRxPauseMacCtrlCts;
+ SK_U64 StatRxMacCtrlCts;
+ SK_U64 StatRxPauseMacCtrlErrorCts;
+ SK_U64 StatRxMacCtrlUnknownCts;
+ SK_U64 StatRxBurstCts;
+ SK_U64 StatRxMissedCts;
+ SK_U64 StatRxFramingCts;
+ SK_U64 StatRxFifoOverflowCts;
+ SK_U64 StatRxJabberCts;
+ SK_U64 StatRxCarrierCts;
+ SK_U64 StatRxIRLengthCts;
+ SK_U64 StatRxSymbolCts;
+ SK_U64 StatRxShortsCts;
+ SK_U64 StatRxRuntCts;
+ SK_U64 StatRxCextCts;
+ SK_U64 StatRxTooLongCts;
+ SK_U64 StatRxFcsCts;
+ SK_U64 Dummy2; /* StatRxUtilization */
+ SK_U64 StatRx64Cts;
+ SK_U64 StatRx127Cts;
+ SK_U64 StatRx255Cts;
+ SK_U64 StatRx511Cts;
+ SK_U64 StatRx1023Cts;
+ SK_U64 StatRxMaxCts;
+} SK_PNMI_STAT;
+
+typedef struct s_PnmiConf {
+ char ConfMacCurrentAddr[6];
+ char ConfMacFactoryAddr[6];
+ SK_U8 ConfPMD;
+ SK_U8 ConfConnector;
+ SK_U8 ConfLinkCapability;
+ SK_U8 ConfLinkMode;
+ SK_U8 ConfLinkModeStatus;
+ SK_U8 ConfLinkStatus;
+ SK_U8 ConfFlowCtrlCapability;
+ SK_U8 ConfFlowCtrlMode;
+ SK_U8 ConfFlowCtrlStatus;
+ SK_U8 ConfPhyOperationCapability;
+ SK_U8 ConfPhyOperationMode;
+ SK_U8 ConfPhyOperationStatus;
+} SK_PNMI_CONF;
+
+typedef struct s_PnmiRlmt {
+ SK_U32 RlmtIndex;
+ SK_U32 RlmtStatus;
+ SK_U64 RlmtTxHelloCts;
+ SK_U64 RlmtRxHelloCts;
+ SK_U64 RlmtTxSpHelloReqCts;
+ SK_U64 RlmtRxSpHelloCts;
+} SK_PNMI_RLMT;
+
+typedef struct s_PnmiRlmtMonitor {
+ SK_U32 RlmtMonitorIndex;
+ char RlmtMonitorAddr[6];
+ SK_U64 RlmtMonitorErrorCts;
+ SK_U64 RlmtMonitorTimestamp;
+ SK_U8 RlmtMonitorAdmin;
+} SK_PNMI_RLMT_MONITOR;
+
+typedef struct s_PnmiRequestStatus {
+ SK_U32 ErrorStatus;
+ SK_U32 ErrorOffset;
+} SK_PNMI_REQUEST_STATUS;
+
+typedef struct s_PnmiStrucData {
+ SK_U32 MgmtDBVersion;
+ SK_PNMI_REQUEST_STATUS ReturnStatus;
+ SK_U32 VpdFreeBytes;
+ char VpdEntriesList[SK_PNMI_VPD_DATALEN];
+ SK_U32 VpdEntriesNumber;
+ SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES];
+ SK_U32 PortNumber;
+ SK_U32 DeviceType;
+ char DriverDescr[SK_PNMI_STRINGLEN1];
+ char DriverVersion[SK_PNMI_STRINGLEN2];
+ char HwDescr[SK_PNMI_STRINGLEN1];
+ char HwVersion[SK_PNMI_STRINGLEN2];
+ SK_U16 Chipset;
+ SK_U32 Action;
+ SK_U32 TestResult;
+ SK_U8 BusType;
+ SK_U8 BusSpeed;
+ SK_U8 BusWidth;
+ SK_U8 SensorNumber;
+ SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES];
+ SK_U8 ChecksumNumber;
+ SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES];
+ SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES];
+ SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES];
+ SK_U8 RlmtMode;
+ SK_U32 RlmtPortNumber;
+ SK_U8 RlmtPortActive;
+ SK_U8 RlmtPortPreferred;
+ SK_U64 RlmtChangeCts;
+ SK_U64 RlmtChangeTime;
+ SK_U64 RlmtChangeEstimate;
+ SK_U64 RlmtChangeThreshold;
+ SK_PNMI_RLMT Rlmt[SK_MAX_MACS];
+ SK_U32 RlmtMonitorNumber;
+ SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES];
+ SK_U32 TrapNumber;
+ SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN];
+ SK_U64 TxSwQueueLen;
+ SK_U64 TxSwQueueMax;
+ SK_U64 TxRetryCts;
+ SK_U64 RxIntrCts;
+ SK_U64 TxIntrCts;
+ SK_U64 RxNoBufCts;
+ SK_U64 TxNoBufCts;
+ SK_U64 TxUsedDescrNo;
+ SK_U64 RxDeliveredCts;
+ SK_U64 RxOctetsDeliveredCts;
+ SK_U64 RxHwErrorsCts;
+ SK_U64 TxHwErrorsCts;
+ SK_U64 InErrorsCts;
+ SK_U64 OutErrorsCts;
+ SK_U64 ErrRecoveryCts;
+ SK_U64 SysUpTime;
+} SK_PNMI_STRUCT_DATA;
+
+#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
+#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)&(((SK_PNMI_STRUCT_DATA *)0)->\
+ VpdFreeBytes)) /*
+ * ReturnStatus field
+ * must be located
+ * before VpdFreeBytes
+ */
+
+/*
+ * Various definitions
+ */
+#define SK_PNMI_MAX_PROTOS 3
+
+#define SK_PNMI_SCNT_NOT 64
+#define SK_PNMI_CNT_NO 66
+
+/*
+ * Estimate data structure
+ */
+typedef struct s_PnmiEstimate {
+ unsigned int EstValueIndex;
+ SK_U64 EstValue[7];
+ SK_U64 Estimate;
+ SK_TIMER EstTimer;
+} SK_PNMI_ESTIMATE;
+
+
+/*
+ * PNMI specific adatper context structure
+ */
+typedef struct s_PnmiPort {
+ SK_U32 CounterHigh[SK_PNMI_SCNT_NOT];
+ SK_U64 CounterOffset[SK_PNMI_CNT_NO];
+ SK_U64 StatSyncCts;
+ SK_U64 StatSyncOctetsCts;
+ SK_BOOL ActiveFlag;
+} SK_PNMI_PORT;
+
+typedef struct s_PnmiData {
+ SK_PNMI_PORT Port[SK_MAX_MACS];
+ SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO];
+ SK_U32 TestResult;
+ char HwVersion[10];
+
+ char *pDriverDescription;
+ char *pDriverVersion;
+
+ char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN];
+ unsigned int TrapBufFree;
+ unsigned int TrapQueueBeg;
+ unsigned int TrapQueueEnd;
+ unsigned int TrapBufPad;
+ unsigned int TrapUnique;
+
+ int MacUpdatedFlag;
+ int RlmtUpdatedFlag;
+ int SirqUpdatedFlag;
+
+ SK_U64 RlmtChangeCts;
+ SK_U64 RlmtChangeTime;
+ SK_PNMI_ESTIMATE RlmtChangeEstimate;
+ SK_U64 RlmtChangeThreshold;
+
+ SK_U32 DeviceType;
+ char PciBusSpeed;
+ char PciBusWidth;
+ char PMD;
+ char Connector;
+
+ SK_U64 TxSwQueueLen;
+ SK_U64 TxSwQueueMax;
+ SK_U64 TxRetryCts;
+ SK_U64 RxIntrCts;
+ SK_U64 TxIntrCts;
+ SK_U64 RxNoBufCts;
+ SK_U64 TxNoBufCts;
+ SK_U64 TxUsedDescrNo;
+ SK_U64 RxDeliveredCts;
+ SK_U64 RxOctetsDeliveredCts;
+ SK_U64 ErrRecoveryCts;
+ SK_U64 StartUpTime;
+} SK_PNMI;
+
+
+/*
+ * Function prototypes
+ */
+extern int SkPnmiInit(SK_AC *pAc, SK_IOC IoC, int level);
+extern int SkPnmiGetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf,
+ unsigned int* pLen, SK_U32 Instance);
+extern int SkPnmiPreSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id,
+ void* pBuf, unsigned int *pLen, SK_U32 Instance);
+extern int SkPnmiSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf,
+ unsigned int *pLen, SK_U32 Instance);
+extern int SkPnmiGetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf,
+ unsigned int *pLen);
+extern int SkPnmiPreSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf,
+ unsigned int *pLen);
+extern int SkPnmiSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf,
+ unsigned int *pLen);
+extern int SkPnmiEvent(SK_AC *pAc, SK_IOC IoC, SK_U32 Event,
+ SK_EVPARA Param);
+
+#endif
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgesirq.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.18 $
+ * Date: $Date: 1999/05/19 07:32:59 $
+ * Purpose: SK specific Gigabit Ethernet special IRQ functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ * $Log: skgesirq.h,v $
+ * Revision 1.18 1999/05/19 07:32:59 cgoos
+ * Changes for 1000Base-T.
+ *
+ * Revision 1.17 1999/03/12 13:29:31 malthoff
+ * Move Autonegotiation Error Codes to skgeinit.h.
+ *
+ * Revision 1.16 1999/03/08 10:11:28 gklug
+ * add: AutoNegDone return codes
+ *
+ * Revision 1.15 1998/11/18 13:20:53 gklug
+ * add: different timeouts for active and non-active links
+ *
+ * Revision 1.14 1998/11/04 07:18:14 cgoos
+ * Added prototype for SkXmRxTxEnable.
+ *
+ * Revision 1.13 1998/10/21 05:52:23 gklug
+ * add: parameter DoLoop to InitPhy function
+ *
+ * Revision 1.12 1998/10/19 06:45:03 cgoos
+ * Added prototype for SkXmInitPhy.
+ *
+ * Revision 1.11 1998/10/15 14:34:10 gklug
+ * add: WA_TIME is 500 msec
+ *
+ * Revision 1.10 1998/10/14 14:49:41 malthoff
+ * Remove err log defines E021 and E022. They are
+ * defined in skgeinit.h now.
+ *
+ * Revision 1.9 1998/10/14 14:00:39 gklug
+ * add: eroor logs for init phys
+ *
+ * Revision 1.8 1998/10/14 05:44:05 gklug
+ * add: E020
+ *
+ * Revision 1.7 1998/10/02 06:24:58 gklug
+ * add: error messages
+ *
+ * Revision 1.6 1998/10/01 07:54:45 gklug
+ * add: PNMI debug module
+ *
+ * Revision 1.5 1998/09/28 13:36:31 malthoff
+ * Move the bit definitions for Autonegotiation
+ * and Flow Control to skgeinit.h.
+ *
+ * Revision 1.4 1998/09/15 12:29:34 gklug
+ * add: error logs
+ *
+ * Revision 1.3 1998/09/03 13:54:02 gklug
+ * add: function prototypes
+ *
+ * Revision 1.2 1998/09/03 10:24:36 gklug
+ * add: Events send by PNMI
+ * add: parameter definition for Flow Control etc.
+ *
+ * Revision 1.1 1998/08/27 11:50:27 gklug
+ * initial revision
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _INC_SKGESIRQ_H_
+#define _INC_SKGESIRQ_H_
+
+/*
+ * Define the Event the special IRQ/INI module can handle
+ */
+#define SK_HWEV_WATIM 1 /* Timeout for WA errata #2 XMAC */
+#define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */
+#define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */
+#define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */
+#define SK_HWEV_UPDATE_STAT 5 /* Update Statistics by PNMI */
+#define SK_HWEV_SET_LMODE 6 /* Set Link Mode by PNMI */
+#define SK_HWEV_SET_FLOWMODE 7 /* Set Flow Control Mode by PNMI */
+
+#define SK_WA_ACT_TIME (5000000L) /* 5 sec */
+#define SK_WA_INA_TIME (100000L) /* 100 msec */
+
+/*
+ * Define the error numbers and messages
+ */
+#define SKERR_SIRQ_E001 (SK_ERRBASE_SIRQ+0)
+#define SKERR_SIRQ_E001MSG "Unknown event"
+#define SKERR_SIRQ_E002 (SKERR_SIRQ_E001+1)
+#define SKERR_SIRQ_E002MSG "Packet timeout RX1"
+#define SKERR_SIRQ_E003 (SKERR_SIRQ_E002+1)
+#define SKERR_SIRQ_E003MSG "Packet timeout RX2"
+#define SKERR_SIRQ_E004 (SKERR_SIRQ_E003+1)
+#define SKERR_SIRQ_E004MSG "XMAC 1 not correctly initialized"
+#define SKERR_SIRQ_E005 (SKERR_SIRQ_E004+1)
+#define SKERR_SIRQ_E005MSG "XMAC 2 not correctly initialized"
+#define SKERR_SIRQ_E006 (SKERR_SIRQ_E005+1)
+#define SKERR_SIRQ_E006MSG "CHECK failure R1"
+#define SKERR_SIRQ_E007 (SKERR_SIRQ_E006+1)
+#define SKERR_SIRQ_E007MSG "CHECK failure R2"
+#define SKERR_SIRQ_E008 (SKERR_SIRQ_E007+1)
+#define SKERR_SIRQ_E008MSG "CHECK failure XS1"
+#define SKERR_SIRQ_E009 (SKERR_SIRQ_E008+1)
+#define SKERR_SIRQ_E009MSG "CHECK failure XA1"
+#define SKERR_SIRQ_E010 (SKERR_SIRQ_E009+1)
+#define SKERR_SIRQ_E010MSG "CHECK failure XS2"
+#define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
+#define SKERR_SIRQ_E011MSG "CHECK failure XA2"
+#define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
+#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
+#define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
+#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
+#define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
+#define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
+#define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
+#define SKERR_SIRQ_E015MSG "Parity error on RAM (write)"
+#define SKERR_SIRQ_E016 (SKERR_SIRQ_E015+1)
+#define SKERR_SIRQ_E016MSG "Parity error MAC 1"
+#define SKERR_SIRQ_E017 (SKERR_SIRQ_E016+1)
+#define SKERR_SIRQ_E017MSG "Parity error MAC 2"
+#define SKERR_SIRQ_E018 (SKERR_SIRQ_E017+1)
+#define SKERR_SIRQ_E018MSG "Parity error RX 1"
+#define SKERR_SIRQ_E019 (SKERR_SIRQ_E018+1)
+#define SKERR_SIRQ_E019MSG "Parity error RX 2"
+#define SKERR_SIRQ_E020 (SKERR_SIRQ_E019+1)
+#define SKERR_SIRQ_E020MSG "XMAC transmit FIFO underrun"
+#define SKERR_SIRQ_E021 (SKERR_SIRQ_E020+1)
+#define SKERR_SIRQ_E021MSG "Spurious I2C interrupt"
+#define SKERR_SIRQ_E022 (SKERR_SIRQ_E020+1)
+#define SKERR_SIRQ_E022MSG "Cable pair swap error"
+
+extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
+extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
+extern void SkXmInitPhy( SK_AC *pAC, SK_IOC IoC, int Port, SK_BOOL DoLoop);
+extern int SkXmRxTxEnable(SK_AC *pAC, SK_IOC IoC, int Port);
+extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
+extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
+
+#endif /* _INC_SKGESIRQ_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: ski2c.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.27 $
+ * Date: $Date: 1999/05/20 09:23:10 $
+ * Purpose: Defines to access Voltage and Temperature Sensor
+ * (taken from Monalisa (taken from Concentrator))
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: ski2c.h,v $
+ * Revision 1.27 1999/05/20 09:23:10 cgoos
+ * Changes for 1000Base-T (Fan sensors).
+ *
+ * Revision 1.26 1998/12/01 13:45:47 gklug
+ * add: InitLevel to I2c struct
+ *
+ * Revision 1.25 1998/11/03 06:55:16 gklug
+ * add: Dummy Reads to I2c struct
+ *
+ * Revision 1.24 1998/10/02 14:28:59 cgoos
+ * Added prototype for SkI2cIsr.
+ *
+ * Revision 1.23 1998/09/08 12:20:11 gklug
+ * add: prototypes for init and read functions
+ *
+ * Revision 1.22 1998/09/08 07:37:56 gklug
+ * add: log error if PCI_IO voltage sensor could not be initialized
+ *
+ * Revision 1.21 1998/09/04 08:38:05 malthoff
+ * Change the values for I2C_READ and I2C_WRITE
+ *
+ * Revision 1.20 1998/08/25 07:52:22 gklug
+ * chg: Timestamps (last) added for logging
+ *
+ * Revision 1.19 1998/08/25 06:09:00 gklug
+ * rmv: warning and error levels of the individual sensors.
+ * add: timing definitions for sending traps and logging errors
+ *
+ * Revision 1.18 1998/08/20 11:41:15 gklug
+ * chg: omit STRCPY macro by using char * as Sensor Description
+ *
+ * Revision 1.17 1998/08/20 11:37:43 gklug
+ * chg: change Ioc to IoC
+ *
+ * Revision 1.16 1998/08/20 11:30:38 gklug
+ * fix: SenRead declaration
+ *
+ * Revision 1.15 1998/08/20 11:27:53 gklug
+ * fix: Compile bugs with new awrning constants
+ *
+ * Revision 1.14 1998/08/20 08:53:12 gklug
+ * fix: compiler errors
+ * add: Threshold values
+ *
+ * Revision 1.13 1998/08/19 12:21:16 gklug
+ * fix: remove struct from C files (see CCC)
+ * add: typedefs for all structs
+ *
+ * Revision 1.12 1998/08/19 10:57:41 gklug
+ * add: Warning levels
+ *
+ * Revision 1.11 1998/08/18 08:37:02 malthoff
+ * Prototypes not required for SK_DIAG.
+ *
+ * Revision 1.10 1998/08/17 13:54:00 gklug
+ * fix: declaration of event function
+ *
+ * Revision 1.9 1998/08/17 06:48:39 malthoff
+ * Remove some unrequired macros.
+ * Fix the compiler errors.
+ *
+ * Revision 1.8 1998/08/14 06:47:19 gklug
+ * fix: Values are intergers
+ *
+ * Revision 1.7 1998/08/14 06:26:05 gklug
+ * add: Init error message
+ *
+ * Revision 1.6 1998/08/13 08:31:08 gklug
+ * add: Error message
+ *
+ * Revision 1.5 1998/08/12 14:32:04 gklug
+ * add: new error code/message
+ *
+ * Revision 1.4 1998/08/12 13:39:08 gklug
+ * chg: names of error messages
+ * add: defines for Sensor type and thresholds
+ *
+ * Revision 1.3 1998/08/11 07:57:16 gklug
+ * add: sensor struct
+ * add: Timeout defines
+ * add: I2C control struct for pAC
+ *
+ * Revision 1.2 1998/07/17 11:29:02 gklug
+ * rmv: Microwire and SMTPANIC
+ *
+ * Revision 1.1 1998/06/19 14:30:10 malthoff
+ * Created. Sources taken from ML Project.
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * SKI2C.H contains all I2C specific defines
+ */
+
+#ifndef _SKI2C_H_
+#define _SKI2C_H_
+
+typedef struct s_Sensor SK_SENSOR;
+
+#include "h/skgei2c.h"
+
+/*
+ * Define the I2c events.
+ */
+#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
+#define SK_I2CEV_TIM 2 /* Timeout event */
+#define SK_I2CEV_CLEAR 3 /* Clear Mib Values */
+
+/*
+ * Define READ and WRITE Constants.
+ */
+#define I2C_READ 0
+#define I2C_WRITE 1
+#define I2C_BURST 1
+#define I2C_SIGLE 0
+
+#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
+#define SKERR_I2C_E001MSG "Sensor index unknown"
+#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
+#define SKERR_I2C_E002MSG "I2C: transfer does not complete.\n"
+#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
+#define SKERR_I2C_E003MSG "lm80: NAK on device send.\n"
+#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
+#define SKERR_I2C_E004MSG "lm80: NAK on register send.\n"
+#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
+#define SKERR_I2C_E005MSG "lm80: NAK on device (2) send.\n"
+#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
+#define SKERR_I2C_E006MSG "Unknown event"
+#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
+#define SKERR_I2C_E007MSG "LM80 read out of state"
+#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
+#define SKERR_I2C_E008MSG "unexpected sensor read completed"
+#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
+#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
+#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
+#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
+#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
+#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
+#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
+#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
+#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
+#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
+#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
+#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
+#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
+#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
+
+/*
+ * Define Timeout values
+ */
+#define SK_I2C_TIM_LONG 2000000L /* 2 second */
+#define SK_I2C_TIM_SHORT 100000L /* 100 milli second */
+
+/*
+ * Define trap and error log hold times
+ */
+#ifndef SK_SEN_ERR_TR_HOLD
+#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
+#endif
+#ifndef SK_SEN_ERR_LOG_HOLD
+#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
+#endif
+#ifndef SK_SEN_WARN_TR_HOLD
+#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
+#endif
+#ifndef SK_SEN_WARN_LOG_HOLD
+#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
+#endif
+
+/*
+ * Defines for SenType
+ */
+#define SK_SEN_TEMP 1
+#define SK_SEN_VOLT 2
+#define SK_SEN_FAN 3
+
+/*
+ * Define for the ErrorFlag
+ */
+#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
+#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
+#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
+
+/*
+ * Define the Sensor struct
+ */
+struct s_Sensor {
+ char *SenDesc; /* Description */
+ int SenType; /* Voltage or Temperature */
+ SK_I32 SenValue; /* Current value of the sensor */
+ SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
+ SK_I32 SenThreWarnHigh;/* High warning Threshhold of this sensor */
+ SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
+ SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
+ int SenErrFlag; /* Sensor indicated an error */
+ SK_BOOL SenInit; /* Is sensor initialized? */
+ SK_U64 SenErrCts; /* Error trap counter */
+ SK_U64 SenWarnCts; /* Warning trap counter */
+ SK_U64 SenBegErrTS; /* Begin error timestamp */
+ SK_U64 SenBegWarnTS; /* Begin warning timestamp */
+ SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
+ SK_U64 SenLastErrLogTS; /* Last error log timestamp */
+ SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
+ SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
+ int SenState; /* Sensor State (see HW specific include) */
+ int (*SenRead)(SK_AC *pAC, SK_IOC IoC,struct s_Sensor *pSen) ;
+ /* Sensors read function */
+ SK_U16 SenReg; /* Register Address for this sensor */
+ SK_U8 SenDev; /* DeviceSelection for this sensor */
+} ;
+
+
+typedef struct s_I2c {
+ SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
+ int CurrSens; /* Which sensor is currently queried */
+ int MaxSens; /* Max. number of sensors */
+ int InitLevel; /* Initialized Level */
+#ifndef SK_DIAG
+ int DummyReads; /* Number of non-checked dummy reads */
+ SK_TIMER SenTimer; /* Sensors timer */
+#endif /* !SK_DIAG */
+} SK_I2C;
+
+extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
+#ifndef SK_DIAG
+extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event,
+ SK_EVPARA Para);
+extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
+extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
+
+#endif
+#endif /* n_SKI2C_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skqueue.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.12 $
+ * Date: $Date: 1998/09/08 08:48:01 $
+ * Purpose: Defines for the Event queue
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skqueue.h,v $
+ * Revision 1.12 1998/09/08 08:48:01 gklug
+ * add: init level handling
+ *
+ * Revision 1.11 1998/09/03 14:15:11 gklug
+ * add: CSUM and HWAC Eventclass and function.
+ * fix: pParaPtr according to CCC
+ *
+ * Revision 1.10 1998/08/20 12:43:03 gklug
+ * add: typedef SK_QUEUE
+ *
+ * Revision 1.9 1998/08/19 09:50:59 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.8 1998/08/18 07:00:01 gklug
+ * fix: SK_PTR not defined use void * instead.
+ *
+ * Revision 1.7 1998/08/17 13:43:19 gklug
+ * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ * Revision 1.6 1998/08/14 07:09:30 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.5 1998/08/11 14:26:44 gklug
+ * chg: Event Dispatcher returns now int.
+ *
+ * Revision 1.4 1998/08/11 12:15:21 gklug
+ * add: Error numbers of skqueue module
+ *
+ * Revision 1.3 1998/08/07 12:54:23 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.2 1998/08/07 09:34:00 gklug
+ * adapt structure defs to CCC
+ * add: prototypes for functions
+ *
+ * Revision 1.1 1998/07/30 14:52:12 gklug
+ * Initial version.
+ * Defines Event Classes, Event structs and queue management variables.
+ *
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * SKQUEUE.H contains all defines and types for the event queue
+ */
+
+#ifndef _SKQUEUE_H_
+#define _SKQUEUE_H_
+
+
+/*
+ * define the event classes to be served
+ */
+#define SKGE_DRV 1 /* Driver Event Class */
+#define SKGE_RLMT 2 /* RLMT Event Class */
+#define SKGE_I2C 3 /* i2C Event Class */
+#define SKGE_PNMI 4 /* PNMI Event Class */
+#define SKGE_CSUM 5 /* Checksum Event Class */
+#define SKGE_HWAC 6 /* Hardware Access Event Class */
+
+/*
+ * define event queue as circular buffer
+ */
+#define SK_MAX_EVENT 64
+
+/*
+ * Parameter union for the Para stuff
+ */
+typedef union u_EvPara {
+ void *pParaPtr; /* Parameter Pointer */
+ SK_U64 Para64; /* Parameter 64bit version */
+ SK_U32 Para32[2]; /* Parameter Array of 32bit parameters */
+} SK_EVPARA;
+
+/*
+ * Event Queue
+ * skqueue.c
+ * events are class/value pairs
+ * class is addressee, e.g. RMT, PCM etc.
+ * value is command, e.g. line state change, ring op change etc.
+ */
+typedef struct s_EventElem {
+ SK_U32 Class ; /* Event class */
+ SK_U32 Event ; /* Event value */
+ SK_EVPARA Para ; /* Event parameter */
+} SK_EVENTELEM;
+
+typedef struct s_Queue {
+ SK_EVENTELEM EvQueue[SK_MAX_EVENT];
+ SK_EVENTELEM *EvPut ;
+ SK_EVENTELEM *EvGet ;
+} SK_QUEUE;
+
+extern void SkEventInit(SK_AC *pAC, SK_IOC Ioc, int Level);
+extern void SkEventQueue(SK_AC *pAC, SK_U32 Class, SK_U32 Event,
+ SK_EVPARA Para);
+extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc);
+
+
+/* Define Error Numbers and messages */
+#define SKERR_Q_E001 (SK_ERRBASE_QUEUE+0)
+#define SKERR_Q_E001MSG "Event queue overflow"
+#define SKERR_Q_E002 (SKERR_Q_E001+1)
+#define SKERR_Q_E002MSG "Undefined event class"
+#endif /* _SKQUEUE_H_ */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skrlmt.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.26 $
+ * Date: $Date: 1999/10/04 14:01:19 $
+ * Purpose: Header file for Redundant Link ManagemenT.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skrlmt.h,v $
+ * Revision 1.26 1999/10/04 14:01:19 rassmann
+ * Corrected reaction to reception of BPDU frames.
+ * Added parameter descriptions to "For Readme" section skrlmt.txt.
+ * Clarified usage of lookahead result *pForRlmt.
+ * Requested driver to present RLMT packets as soon as poosible.
+ *
+ * Revision 1.25 1999/07/20 12:53:39 rassmann
+ * Fixed documentation errors for lookahead macros.
+ *
+ * Revision 1.24 1999/05/28 11:15:56 rassmann
+ * Changed behaviour to reflect Design Spec v1.2.
+ * Controlling Link LED(s).
+ * Introduced RLMT Packet Version field in RLMT Packet.
+ * Newstyle lookahead macros (checking meta-information before looking at
+ * the packet).
+ *
+ * Revision 1.23 1999/01/28 12:50:42 rassmann
+ * Not using broadcast time stamps in CheckLinkState mode.
+ *
+ * Revision 1.22 1999/01/27 14:13:04 rassmann
+ * Monitoring broadcast traffic.
+ * Switching more reliably and not too early if switch is
+ * configured for spanning tree.
+ *
+ * Revision 1.21 1998/12/08 13:11:25 rassmann
+ * Stopping SegTimer at RlmtStop.
+ *
+ * Revision 1.20 1998/11/24 12:37:33 rassmann
+ * Implemented segmentation check.
+ *
+ * Revision 1.19 1998/11/17 13:43:06 rassmann
+ * Handling (logical) tx failure.
+ * Sending packet on logical address after PORT_SWITCH.
+ *
+ * Revision 1.18 1998/11/13 16:56:56 rassmann
+ * Added macro version of SkRlmtLookaheadPacket.
+ *
+ * Revision 1.17 1998/11/06 18:06:05 rassmann
+ * Corrected timing when RLMT checks fail.
+ * Clearing tx counter earlier in periodical checks.
+ *
+ * Revision 1.16 1998/11/03 13:53:50 rassmann
+ * RLMT should switch now (at least in mode 3).
+ *
+ * Revision 1.15 1998/10/22 11:39:52 rassmann
+ * Corrected signed/unsigned mismatches.
+ * Corrected receive list handling and address recognition.
+ *
+ * Revision 1.14 1998/10/15 15:16:36 rassmann
+ * Finished Spanning Tree checking.
+ * Checked with lint.
+ *
+ * Revision 1.13 1998/09/24 19:16:08 rassmann
+ * Code cleanup.
+ * Introduced Timer for PORT_DOWN due to no RX.
+ *
+ * Revision 1.12 1998/09/16 11:09:52 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.11 1998/09/15 11:28:50 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.10 1998/09/14 17:07:38 rassmann
+ * Added code for port checking via LAN.
+ * Changed Mbuf definition.
+ *
+ * Revision 1.9 1998/09/07 11:14:15 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.8 1998/09/07 09:06:08 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.7 1998/09/04 19:41:34 rassmann
+ * Syntax corrections.
+ * Started entering code for checking local links.
+ *
+ * Revision 1.6 1998/09/04 12:14:28 rassmann
+ * Interface cleanup.
+ *
+ * Revision 1.5 1998/09/02 16:55:29 rassmann
+ * Updated to reflect new DRV/HWAC/RLMT interface.
+ *
+ * Revision 1.4 1998/09/02 07:26:02 afischer
+ * typedef for SK_RLMT_PORT
+ *
+ * Revision 1.3 1998/08/27 14:29:03 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.2 1998/08/27 14:26:25 rassmann
+ * Updated interface.
+ *
+ * Revision 1.1 1998/08/21 08:29:10 rassmann
+ * First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the header file for Redundant Link ManagemenT.
+ *
+ * Include File Hierarchy:
+ *
+ * "skdrv1st.h"
+ * ...
+ * "sktypes.h"
+ * "skqueue.h"
+ * "skaddr.h"
+ * "skrlmt.h"
+ * ...
+ * "skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKRLMT_H
+#define __INC_SKRLMT_H
+
+#ifdef __cplusplus
+xxxx /* not supported yet - force error */
+extern "C" {
+#endif /* cplusplus */
+
+/* defines ********************************************************************/
+
+#define SK_RLMT_NET_DOWN_TEMP 1 /* NET_DOWN due to last port down. */
+#define SK_RLMT_NET_DOWN_FINAL 2 /* NET_DOWN due to RLMT_STOP. */
+
+/* ----- Default queue sizes - must be multiples of 8 KB ----- */
+
+/* Less than 8 KB free in RX queue => pause frames. */
+#define SK_RLMT_STANDBY_QRXSIZE 128 /* Size of rx standby queue in KB. */
+#define SK_RLMT_STANDBY_QXASIZE 32 /* Size of async standby queue in KB. */
+#define SK_RLMT_STANDBY_QXSSIZE 0 /* Size of sync standby queue in KB. */
+
+#define SK_RLMT_MAX_TX_BUF_SIZE 60 /* Maximum RLMT transmit size. */
+
+/* ----- PORT states ----- */
+
+#define SK_RLMT_PS_INIT 0 /* Port state: Init. */
+#define SK_RLMT_PS_LINK_DOWN 1 /* Port state: Link down. */
+#define SK_RLMT_PS_DOWN 2 /* Port state: Port down. */
+#define SK_RLMT_PS_GOING_UP 3 /* Port state: Going up. */
+#define SK_RLMT_PS_UP 4 /* Port state: Up. */
+
+/* ----- RLMT states ----- */
+
+#define SK_RLMT_RS_INIT 0 /* RLMT state: Init. */
+#define SK_RLMT_RS_NET_DOWN 1 /* RLMT state: Net down. */
+#define SK_RLMT_RS_NET_UP 2 /* RLMT state: Net up. */
+
+/* ----- PORT events ----- */
+
+#define SK_RLMT_LINK_UP 1001 /* Link came up. */
+#define SK_RLMT_LINK_DOWN 1002 /* Link went down. */
+#define SK_RLMT_PORT_ADDR 1003 /* Port address changed. */
+
+/* ----- RLMT events ----- */
+
+#define SK_RLMT_START 2001 /* Start RLMT. */
+#define SK_RLMT_STOP 2002 /* Stop RLMT. */
+#define SK_RLMT_PACKET_RECEIVED 2003 /* Packet was received for RLMT. */
+#define SK_RLMT_STATS_CLEAR 2004 /* Clear statistics. */
+#define SK_RLMT_STATS_UPDATE 2005 /* Update statistics. */
+#define SK_RLMT_PREFPORT_CHANGE 2006 /* Change preferred port. */
+#define SK_RLMT_MODE_CHANGE 2007 /* New RlmtMode. */
+
+/* ----- RLMT mode bits ----- */
+
+#define SK_RLMT_CHECK_LINK 1 /* Check Link. */
+#define SK_RLMT_CHECK_LOC_LINK 2 /* Check other link on same adapter. */
+#define SK_RLMT_CHECK_SEG 4 /* Check segmentation. */
+
+#ifndef RLMT_CHECK_REMOTE
+#define SK_RLMT_CHECK_OTHERS SK_RLMT_CHECK_LOC_LINK
+#else /* RLMT_CHECK_REMOTE */
+#define SK_RLMT_CHECK_REM_LINK 8 /* Check link(s) on other adapter(s). */
+#define SK_RLMT_MAX_REMOTE_PORTS_CHECKED 3
+#define SK_RLMT_CHECK_OTHERS (SK_RLMT_CHECK_LOC_LINK | \
+ SK_RLMT_CHECK_REM_LINK)
+#endif /* RLMT_CHECK_REMOTE */
+
+/* ----- RLMT modes ----- */
+
+/* Check Link State. */
+#define SK_RLMT_MODE_CLS (SK_RLMT_CHECK_LINK)
+
+/* Check Local Ports: check other links on the same adapter. */
+#define SK_RLMT_MODE_CLP (SK_RLMT_CHECK_LINK | \
+ SK_RLMT_CHECK_LOC_LINK)
+
+/* Check Local Ports and Segmentation Status. */
+#define SK_RLMT_MODE_CLPSS (SK_RLMT_CHECK_LINK | \
+ SK_RLMT_CHECK_LOC_LINK | \
+ SK_RLMT_CHECK_SEG)
+
+#ifdef RLMT_CHECK_REMOTE
+/* Check Local and Remote Ports: check links (local or remote). */
+ Name of define TBD!
+#define SK_RLMT_MODE_CRP (SK_RLMT_CHECK_LINK | \
+ SK_RLMT_CHECK_LOC_LINK | \
+ SK_RLMT_CHECK_REM_LINK)
+
+/* Check Local and Remote Ports and Segmentation Status. */
+ Name of define TBD!
+#define SK_RLMT_MODE_CRPSS (SK_RLMT_CHECK_LINK | \
+ SK_RLMT_CHECK_LOC_LINK | \
+ SK_RLMT_CHECK_REM_LINK | \
+ SK_RLMT_CHECK_SEG)
+#endif /* RLMT_CHECK_REMOTE */
+
+/* ----- RLMT lookahead result bits ----- */
+
+#define SK_RLMT_RX_RLMT 1 /* Give packet to RLMT. */
+#define SK_RLMT_RX_PROTOCOL 2 /* Give packet to protocol. */
+
+/* Macros */
+
+#if 0
+SK_AC *pAC /* adapter context */
+SK_U32 PortIdx /* receiving port */
+unsigned PacketLength /* received packet's length */
+SK_BOOL IsBc /* Flag: broadcast received */
+unsigned *pOffset /* Result: offset of bytes to present
+ to SK_RLMT_LOOKAHEAD */
+unsigned *pNumBytes /* Result: #Bytes to present
+ to SK_RLMT_LOOKAHEAD */
+#endif /* 0 */
+
+
+#define SK_RLMT_PRE_LOOKAHEAD(pAC,PortIdx,PacketLength,IsBc,pOffset,pNumBytes) { \
+ SK_AC *_pAC; \
+ SK_U32 _PortIdx; \
+ _pAC = (pAC); \
+ _PortIdx = (SK_U32)(PortIdx); \
+ _pAC->Rlmt.Port[_PortIdx].PacketsRx++; \
+ _pAC->Rlmt.Port[_PortIdx].PacketsPerTimeSlot++; \
+ if ((IsBc) && _pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS) { \
+ *(pOffset) = 6; \
+ *(pNumBytes) = 6; \
+ } \
+ else { \
+ *(pOffset) = 0; \
+ if ((PacketLength) > SK_RLMT_MAX_TX_BUF_SIZE) { \
+ _pAC->Rlmt.Port[_PortIdx].DataPacketsPerTimeSlot++; \
+ *(pNumBytes) = 0; \
+ } \
+ else { \
+ *(pNumBytes) = 6; \
+ } \
+ } \
+}
+
+#if 0
+SK_AC *pAC /* adapter context */
+SK_U32 PortIdx /* receiving port */
+SK_U8 *pLaPacket, /* received packet's data (points to pOffset) */
+SK_BOOL IsBc /* Flag: broadcast received */
+SK_BOOL IsMc /* Flag: multicast received */
+unsigned *pForRlmt /* Result: bits SK_RLMT_RX_RLMT,
+ SK_RLMT_RX_PROTOCOL */
+SK_RLMT_LOOKAHEAD() expects *pNumBytes from
+packet offset *pOffset (s.a.) at *pLaPacket.
+
+If you use SK_RLMT_LOOKAHEAD in a path where you already know if the packet is
+BC, MC, or UC, you should use constants for IsBc and IsMc, so that your compiler
+can trash unneeded parts of the if construction.
+#endif /* 0 */
+#define SK_RLMT_LOOKAHEAD(pAC,PortIdx,pLaPacket,IsBc,IsMc,pForRlmt) { \
+ SK_AC *_pAC; \
+ SK_U32 _PortIdx; \
+ SK_U8 *_pLaPacket; \
+ _pAC = (pAC); \
+ _PortIdx = (SK_U32)(PortIdx); \
+ _pLaPacket = (SK_U8 *)(pLaPacket); \
+ if (IsBc) {\
+ if (!SK_ADDR_EQUAL( \
+ _pLaPacket, \
+ _pAC->Addr.CurrentMacAddress.a)) { \
+ _pAC->Rlmt.Port[_PortIdx].BcTimeStamp = \
+ SkOsGetTime(_pAC); \
+ } \
+ _pAC->Rlmt.Port[_PortIdx].DataPacketsPerTimeSlot++; \
+ *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
+ } \
+ else if (IsMc) { \
+ if (SK_ADDR_EQUAL(_pLaPacket, BridgeMcAddr.a)) { \
+ _pAC->Rlmt.Port[_PortIdx].BpduPacketsPerTimeSlot++; \
+ if (_pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) { \
+ *(pForRlmt) = SK_RLMT_RX_RLMT | \
+ SK_RLMT_RX_PROTOCOL; \
+ } \
+ else { \
+ *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
+ } \
+ } \
+ else if (SK_ADDR_EQUAL(_pLaPacket, SkRlmtMcAddr.a)) { \
+ *(pForRlmt) = SK_RLMT_RX_RLMT; \
+ } \
+ else { \
+ _pAC->Rlmt.Port[_PortIdx].DataPacketsPerTimeSlot++; \
+ *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
+ } \
+ } \
+ else { \
+ if (SK_ADDR_EQUAL( \
+ _pLaPacket, \
+ _pAC->Addr.Port[_PortIdx].CurrentMacAddress.a)) { \
+ *(pForRlmt) = SK_RLMT_RX_RLMT; \
+ } \
+ else { \
+ _pAC->Rlmt.Port[_PortIdx].DataPacketsPerTimeSlot++; \
+ *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
+ } \
+ } \
+}
+
+#ifdef SK_RLMT_FAST_LOOKAHEAD
+Error: SK_RLMT_FAST_LOOKAHEAD no longer used. Use new macros for lookahead.
+#endif /* SK_RLMT_FAST_LOOKAHEAD */
+
+/* typedefs *******************************************************************/
+
+typedef struct s_RootId {
+ SK_U8 Id[8]; /* Root Bridge Id. */
+} SK_RLMT_ROOT_ID;
+
+typedef struct s_port {
+ SK_MAC_ADDR CheckAddr;
+ SK_BOOL SuspectTx;
+} SK_PORT_CHECK;
+
+typedef struct s_RlmtPort {
+
+/* ----- Public part (read-only) ----- */
+
+ SK_U8 PortState; /* Current state of this port. */
+
+ /* For PNMI */
+
+ SK_BOOL LinkDown;
+ SK_BOOL PortDown;
+
+ SK_U64 TxHelloCts;
+ SK_U64 RxHelloCts;
+ SK_U64 TxSpHelloReqCts;
+ SK_U64 RxSpHelloCts;
+
+/* ----- Private part ----- */
+
+ SK_BOOL PortStarted; /* Port is started. */
+ SK_BOOL PortNoRx; /* NoRx for >= 1 time slot. */
+ SK_U32 CheckingState; /* Checking State. */
+
+ SK_U64 PacketsRx; /* Total packets received. */
+ SK_U32 PacketsPerTimeSlot; /* Packets rxed between TOs. */
+ SK_U32 DataPacketsPerTimeSlot; /* Data packets ... */
+#if 0
+ SK_U32 RlmtAcksPerTimeSlot; /* RLMT Acks rxed in TS. */
+ SK_U32 RlmtChksPerTimeSlot; /* RLMT Chks rxed in TS. */
+#endif /* 0 */
+ SK_U32 BpduPacketsPerTimeSlot; /* BPDU packets rxed in TS. */
+ SK_U64 BcTimeStamp; /* Time of last BC receive. */
+ SK_U64 GuTimeStamp; /* Time of entering GOING_UP. */
+
+ SK_TIMER UpTimer; /* Timer struct Link/Port up. */
+ SK_TIMER DownRxTimer; /* Timer struct down rx. */
+ SK_TIMER DownTxTimer; /* Timer struct down tx. */
+
+ SK_U8 Random[4]; /* Random value. */
+ unsigned PortsChecked; /* #ports checked. */
+ unsigned PortsSuspect; /* #ports checked that are s. */
+ SK_PORT_CHECK PortCheck[1];
+/* SK_PORT_CHECK PortCheck[SK_MAX_MACS - 1]; */
+
+ SK_BOOL RootIdSet;
+ SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */
+} SK_RLMT_PORT;
+
+#ifdef SK_RLMT_MBUF_PRIVATE
+typedef struct s_RlmtMbuf {
+ some content
+} SK_RLMT_MBUF;
+#endif /* SK_RLMT_MBUF_PRIVATE */
+
+#ifdef SK_LA_INFO
+typedef struct s_Rlmt_PacketInfo {
+ unsigned PacketLength; /* Length of packet. */
+ unsigned PacketType; /* Directed/Multicast/Broadcast. */
+} SK_RLMT_PINFO;
+#endif /* SK_LA_INFO */
+
+typedef struct s_Rlmt {
+
+/* ----- Public part (read-only) ----- */
+
+ SK_U8 RlmtState; /* Current RLMT state. */
+ SK_RLMT_PORT Port[SK_MAX_MACS]; /* Array of available ports. */
+ SK_U32 PrefPort; /* Preferred port. */
+
+ /* For PNMI */
+
+ SK_U32 RlmtMode; /* Check ... */
+ SK_U32 MacActive; /* Active port. */
+ SK_U32 MacPreferred; /* 0xFFFFFFFF: Automatic. */
+
+/* ----- Private part ----- */
+
+ int LinksUp; /* #Links up. */
+ int PortsUp; /* #Ports up. */
+ SK_U32 TimeoutValue; /* RLMT timeout value. */
+ SK_TIMER LocTimer; /* Timer struct. */
+
+ SK_U32 CheckingState; /* Checking State. */
+ SK_BOOL RootIdSet;
+ SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */
+ SK_TIMER SegTimer; /* Timer struct. */
+} SK_RLMT;
+
+extern SK_MAC_ADDR BridgeMcAddr;
+extern SK_MAC_ADDR SkRlmtMcAddr;
+
+/* function prototypes ********************************************************/
+
+
+#ifndef SK_KR_PROTO
+
+/* Functions provided by SkRlmt */
+
+/* ANSI/C++ compliant function prototypes */
+
+extern void SkRlmtInit(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int Level);
+
+#ifdef SK_RLMT_SLOW_LOOKAHEAD
+extern SK_BOOL SkRlmtLookaheadPacket(
+ SK_AC *pAC,
+ SK_U32 PortIdx,
+ SK_U8 *pLaPacket,
+ unsigned PacketLength,
+ unsigned LaLength);
+#endif /* SK_RLMT_SLOW_LOOKAHEAD */
+
+extern int SkRlmtEvent(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ SK_U32 Event,
+ SK_EVPARA Para);
+
+#else /* defined(SK_KR_PROTO)) */
+
+/* Non-ANSI/C++ compliant function prototypes */
+
+xxxx /* not supported yet - force error */
+
+#endif /* defined(SK_KR_PROTO)) */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_SKRLMT_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: sktimer.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.8 $
+ * Date: $Date: 1998/09/08 08:48:02 $
+ * Purpose: Defines for the timer functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: sktimer.h,v $
+ * Revision 1.8 1998/09/08 08:48:02 gklug
+ * add: init level handling
+ *
+ * Revision 1.7 1998/08/20 12:31:29 gklug
+ * fix: SK_TIMCTRL needs to be defined
+ *
+ * Revision 1.6 1998/08/19 09:51:00 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.5 1998/08/17 13:43:21 gklug
+ * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ * Revision 1.4 1998/08/14 07:09:31 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.3 1998/08/07 12:54:24 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.2 1998/08/07 09:35:29 gklug
+ * add: Timer control struct for Adapters context
+ * add: function prototypes
+ *
+ * Revision 1.1 1998/08/05 11:27:01 gklug
+ * First version: adapted from SMT
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * SKTIMER.H contains all defines and types for the timer functions
+ */
+
+#ifndef _SKTIMER_H_
+#define _SKTIMER_H_
+
+#include "h/skqueue.h"
+
+/*
+ * SK timer
+ * - needed wherever a timer is used. Put this in your data structure
+ * wherever you want.
+ */
+typedef struct s_Timer SK_TIMER;
+
+struct s_Timer {
+ SK_TIMER *TmNext ; /* linked list */
+ SK_U32 TmClass ; /* Timer Event class */
+ SK_U32 TmEvent ; /* Timer Event value */
+ SK_EVPARA TmPara ; /* Timer Event parameter */
+ SK_U32 TmDelta ; /* delta time */
+ int TmActive ; /* flag : active/inactive */
+} ;
+
+/*
+ * Timer control struct.
+ * - use in Adapters context name pAC->Tim
+ */
+typedef struct s_TimCtrl {
+ SK_TIMER *StQueue ; /* Head of Timer queue */
+} SK_TIMCTRL ;
+
+extern void SkTimerInit(SK_AC *pAC,SK_IOC Ioc, int Level);
+extern void SkTimerStop(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer);
+extern void SkTimerStart(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer,
+ SK_U32 Time,SK_U32 Class,SK_U32 Event,SK_EVPARA Para);
+extern void SkTimerDone(SK_AC *pAC,SK_IOC Ioc);
+#endif /* _SKTIMER_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: sktypes.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.1 $
+ * Date: $Date: 1999/02/16 07:41:40 $
+ * Purpose: Define data types for Linux
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+ /*****************************************************************************
+ *
+ * History:
+ *
+ * $Log: sktypes.h,v $
+ * Revision 1.1 1999/02/16 07:41:40 cgoos
+ * First version.
+ *
+ *
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * In this file, all data types that are needed by the common modules
+ * are mapped to Linux data types.
+ *
+ *
+ * Include File Hierarchy:
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKTYPES_H
+#define __INC_SKTYPES_H
+
+
+/* defines *******************************************************************/
+
+/*
+ * Data types with a specific size. 'I' = signed, 'U' = unsigned.
+ */
+#define SK_I8 s8
+#define SK_U8 u8
+#define SK_I16 s16
+#define SK_U16 u16
+#define SK_I32 s32
+#define SK_U32 u32
+#define SK_I64 s64
+#define SK_U64 u64
+
+#define SK_UPTR ulong /* casting pointer <-> integral */
+
+/*
+* Boolean type.
+*/
+#define SK_BOOL SK_U8
+#define SK_FALSE 0
+#define SK_TRUE (!SK_FALSE)
+
+/* typedefs *******************************************************************/
+
+/* function prototypes ********************************************************/
+
+#endif /* __INC_SKTYPES_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skvpd.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.8 $
+ * Date: $Date: 1999/03/11 14:26:40 $
+ * Purpose: Defines and Macros for VPD handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skvpd.h,v $
+ * Revision 1.8 1999/03/11 14:26:40 malthoff
+ * Replace __STDC__ with SK_KR_PROTO.
+ *
+ * Revision 1.7 1998/10/28 07:27:17 gklug
+ * rmv: SWAP macros
+ * add: VPD_IN/OUT8 macros
+ * chg: interface definition
+ *
+ * Revision 1.6 1998/10/22 10:03:44 gklug
+ * fix: use SK_OUT16 instead of SK_OUTW
+ *
+ * Revision 1.5 1998/10/14 07:05:31 cgoos
+ * Changed constants in SK_SWAP_32 to UL.
+ *
+ * Revision 1.4 1998/08/19 08:14:09 gklug
+ * fix: remove struct keyword as much as possible from the c-code (see CCC)
+ *
+ * Revision 1.3 1998/08/18 08:18:56 malthoff
+ * Modify VPD in and out macros for SK_DIAG
+ *
+ * Revision 1.2 1998/07/03 14:49:08 malthoff
+ * Add VPD_INxx() and VPD_OUTxx() macros for the Diagnostics tool.
+ *
+ * Revision 1.1 1998/06/19 14:08:03 malthoff
+ * Created.
+ *
+ *
+ ******************************************************************************/
+
+/*
+ * skvpd.h contains Diagnostic specific defines for VPD handling
+ */
+
+#ifndef __INC_SKVPD_H_
+#define __INC_SKVPD_H_
+
+/*
+ * Define Resource Type Identifiers and VPD keywords
+ */
+#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
+#define RES_VPD_R 0x90 /* start of VPD read only area */
+#define RES_VPD_W 0x91 /* start of VPD read/write area */
+#define RES_END 0x78 /* Resource Type End Tag */
+
+#ifndef VPD_NAME
+#define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
+#endif /* VPD_NAME */
+#define VPD_PN "PN" /* Adapter Part Number */
+#define VPD_EC "EC" /* Adapter Engineering Level */
+#define VPD_MN "MN" /* Manufacture ID */
+#define VPD_SN "SN" /* Serial Number */
+#define VPD_CP "CP" /* Extended Capability */
+#define VPD_RV "RV" /* Checksum and Reserved */
+#define VPD_YA "YA" /* Asset Tag Identifier */
+#define VPD_VL "VL" /* First Error Log Message (SK specific) */
+#define VPD_VF "VF" /* Second Error Log Message (SK specific) */
+#define VPD_RW "RW" /* Remaining Read / Write Area */
+
+/* 'type' values for vpd_setup_para() */
+#define VPD_RO_KEY 1 /* RO keys are "PN", "EC", "MN", "SN", "RV" */
+#define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
+
+/* 'op' values for vpd_setup_para() */
+#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
+#define OWR_KEY 2 /* overwrite key if already exists */
+
+/*
+ * Define READ and WRITE Constants.
+ */
+#define VPD_SIZE 512
+#define VPD_READ 0x0000
+#define VPD_WRITE 0x8000
+
+#define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
+
+#define VPD_GET_RES_LEN(p) ((unsigned int) \
+ (* (SK_U8 *)&(p)[1]) |\
+ ((* (SK_U8 *)&(p)[2]) << 8))
+#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
+#define VPD_GET_VAL(p) ((char *)&(p)[3])
+
+#define VPD_MAX_LEN 50
+
+/* VPD status */
+ /* bit 7..1 reserved */
+#define VPD_VALID (1<<0) /* VPD data buffer, vpd_free_ro, */
+ /* and vpd_free_rw valid */
+
+/*
+ * VPD structs
+ */
+typedef struct s_vpd_status {
+ unsigned short vpd_status ; /* VPD status, description see above */
+ int vpd_free_ro ; /* unused bytes in read only area */
+ int vpd_free_rw ; /* bytes available in read/write area */
+} SK_VPD_STATUS;
+
+typedef struct s_vpd {
+ SK_VPD_STATUS v ; /* VPD status structure */
+ char vpd_buf[VPD_SIZE] ; /* VPD buffer */
+} SK_VPD;
+
+typedef struct s_vpd_para {
+ unsigned int p_len ; /* parameter length */
+ char *p_val ; /* points to the value */
+} SK_VPD_PARA;
+
+/*
+ * structure of Large Resource Type Identifiers
+ */
+/* was removed, because of alignment problems */
+
+/*
+ * sturcture of VPD keywords
+ */
+typedef struct s_vpd_key {
+ char p_key[2] ; /* 2 bytes ID string */
+ unsigned char p_len ; /* 1 byte length */
+ char p_val ; /* start of the value string */
+} SK_VPD_KEY;
+
+
+/*
+ * System specific VPD macros
+ */
+#ifndef SKDIAG
+#ifndef VPD_DO_IO
+#define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
+#define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
+#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val)
+#define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
+#define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
+#define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
+#else /* VPD_DO_IO */
+#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
+#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
+#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(Addr),Val)
+#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
+#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
+#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
+#endif /* VPD_DO_IO */
+#else /* SKDIAG */
+#define VPD_OUT8(pAC,Ioc,Addr,Val) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciWriteCfgByte(pAC,Addr,Val) ; \
+ else \
+ SK_OUT8(pAC,PCI_C(Addr),Val); \
+ }
+#define VPD_OUT16(pAC,Ioc,Addr,Val) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciWriteCfgWord(pAC,Addr,Val) ; \
+ else \
+ SK_OUT16(pAC,PCI_C(Addr),Val); \
+ }
+#define VPD_OUT32(pAC,Ioc,Addr,Val) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciWriteCfgDWord(pAC,Addr,Val) ; \
+ else \
+ SK_OUT32(pAC,PCI_C(Addr),Val); \
+ }
+#define VPD_IN8(pAC,Ioc,Addr,pVal) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciReadCfgByte(pAC,Addr,pVal) ; \
+ else \
+ SK_IN8(pAC,PCI_C(Addr),pVal); \
+ }
+#define VPD_IN16(pAC,Ioc,Addr,pVal) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciReadCfgWord(pAC,Addr,pVal) ; \
+ else \
+ SK_IN16(pAC,PCI_C(Addr),pVal); \
+ }
+#define VPD_IN32(pAC,Ioc,Addr,pVal) { \
+ if ((pAC)->DgT.DgUseCfgCycle) \
+ SkPciReadCfgDWord(pAC,Addr,pVal) ; \
+ else \
+ SK_IN32(pAC,PCI_C(Addr),pVal); \
+ }
+#endif /* nSKDIAG */
+
+/* function prototypes ********************************************************/
+
+#ifndef SK_KR_PROTO
+extern SK_U32 VpdReadDWord(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ int addr) ;
+
+extern int VpdSetupPara(
+ SK_AC *pAC,
+ char *key,
+ char *buf,
+ int len,
+ int type,
+ int op) ;
+
+extern SK_VPD_STATUS *VpdStat(
+ SK_AC *pAC,
+ SK_IOC IoC) ;
+
+extern int VpdKeys(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *buf,
+ int *len,
+ int *elements) ;
+
+extern int VpdRead(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *key,
+ char *buf,
+ int *len) ;
+
+extern SK_BOOL VpdMayWrite(
+ char *key) ;
+
+extern int VpdWrite(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *key,
+ char *buf) ;
+
+extern int VpdDelete(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *key) ;
+
+extern int VpdUpdate(
+ SK_AC *pAC,
+ SK_IOC IoC);
+
+extern void VpdErrLog(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *msg) ;
+
+#ifdef SKDIAG
+extern int VpdReadBlock(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *buf,
+ int addr,
+ int len) ;
+
+extern int VpdWriteBlock(
+ SK_AC *pAC,
+ SK_IOC IoC,
+ char *buf,
+ int addr,
+ int len) ;
+#endif /* SKDIAG */
+#else /* SK_KR_PROTO */
+extern SK_U32 VpdReadDWord() ;
+extern int VpdSetupPara() ;
+extern SK_VPD_STATUS *VpdStat() ;
+extern int VpdKeys() ;
+extern int VpdRead() ;
+extern SK_BOOL VpdMayWrite() ;
+extern int VpdWrite() ;
+extern int VpdDelete() ;
+extern int VpdUpdate() ;
+extern void VpdErrLog() ;
+#endif /* SK_KR_PROTO */
+
+#endif /* __INC_SKVPD_H_ */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: xmac_ii.h
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.25 $
+ * Date: $Date: 1999/08/12 19:19:38 $
+ * Purpose: Defines and Macros for XaQti's Gigabit Ethernet Controller
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: xmac_ii.h,v $
+ * Revision 1.25 1999/08/12 19:19:38 malthoff
+ * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet.
+ *
+ * Revision 1.24 1999/07/30 11:27:21 cgoos
+ * Fixed a missing end-of-comment.
+ *
+ * Revision 1.23 1999/07/30 07:03:31 malthoff
+ * Cut some long comments.
+ * Correct the XMAC PHY ID definitions.
+ *
+ * Revision 1.22 1999/05/19 07:33:18 cgoos
+ * Changes for 1000Base-T.
+ *
+ * Revision 1.21 1999/03/25 07:46:11 malthoff
+ * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers.
+ *
+ * Revision 1.20 1999/03/12 13:36:09 malthoff
+ * Remove __STDC__.
+ *
+ * Revision 1.19 1998/12/10 12:22:54 gklug
+ * fix: RX_PAGE must be in interrupt mask
+ *
+ * Revision 1.18 1998/12/10 10:36:36 gklug
+ * fix: swap of pause bits
+ *
+ * Revision 1.17 1998/11/18 13:21:45 gklug
+ * fix: Default interrupt mask
+ *
+ * Revision 1.16 1998/10/29 15:53:21 gklug
+ * fix: Default mask uses ASS (GP0) signal
+ *
+ * Revision 1.15 1998/10/28 13:52:52 malthoff
+ * Add new bits in RX_CMD register.
+ *
+ * Revision 1.14 1998/10/19 15:34:53 gklug
+ * fix: typos
+ *
+ * Revision 1.13 1998/10/14 07:19:03 malthoff
+ * bug fix: Every define which describes bit 31
+ * must be declared as unsigned long 'UL'.
+ * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE.
+ * Remove ANP defines. Rework the RFB defines.
+ *
+ * Revision 1.12 1998/10/14 06:22:44 cgoos
+ * Changed shifted constant to ULONG.
+ *
+ * Revision 1.11 1998/10/14 05:43:26 gklug
+ * add: shift pause codeing
+ * fix: PAUSE bits definition
+ *
+ * Revision 1.10 1998/10/13 09:19:21 malthoff
+ * Again change XMR_FS_ANY_ERR because of new info from XaQti.
+ *
+ * Revision 1.9 1998/10/09 07:58:30 malthoff
+ * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR.
+ *
+ * Revision 1.8 1998/10/09 07:18:17 malthoff
+ * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE
+ * are not inverted! Bug XM_DEF_MSK is inverted.
+ *
+ * Revision 1.7 1998/10/05 08:04:32 malthoff
+ * bug fix: XM_PAUSE_MODE and XM_DEF_MODE
+ * must be inverted declarations.
+ *
+ * Revision 1.6 1998/09/28 13:38:18 malthoff
+ * Add default modes and masks XM_DEF_MSK,
+ * XM_PAUSE_MODE and XM_DEF_MODE
+ *
+ * Revision 1.5 1998/09/16 14:42:04 malthoff
+ * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register.
+ *
+ * Revision 1.4 1998/08/20 14:59:47 malthoff
+ * Rework this file after reading the XaQti data sheet
+ * "Differences between Rev. B2 & Rev. C XMAC II".
+ * This file is now 100% XMAC II Rev. C complained.
+ *
+ * Revision 1.3 1998/06/29 12:18:23 malthoff
+ * Correct XMR_FS_ANY_ERR definition.
+ *
+ * Revision 1.2 1998/06/29 12:10:56 malthoff
+ * Add define XMR_FS_ANY_ERR.
+ *
+ * Revision 1.1 1998/06/19 13:37:17 malthoff
+ * created.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __INC_XMAC_H
+#define __INC_XMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * XMAC II registers
+ *
+ * The XMAC registers are 16 or 32 bits wide. The XMACs host processor
+ * interface is set to 16 bit mode, therefore ALL registers will be
+ * addressed with 16 bit accesses.
+ *
+ * The following macros are provided to access the XMAC registers
+ * XM_IN16(), XM_OUT16, XM_IN32(), MX_OUT32(), XM_INADR(), XM_OUTADR(),
+ * XM_INHASH(), and XM_OUTHASH().
+ * The macros are defined in SkGeHw.h.
+ *
+ * Note: NA reg = Network Address e.g DA, SA etc.
+ *
+ */
+#define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */
+ /* 0x0004: reserved */
+#define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */
+#define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/
+#define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */
+#define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */
+ /* 0x0018 - 0x001e: reserved */
+#define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */
+#define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */
+#define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */
+#define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */
+#define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */
+#define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */
+#define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */
+ /* 0x003c: reserved */
+#define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */
+#define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */
+#define XM_ISRC 0x0048 /* 16 bit ro Interrupt Status Register */
+#define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */
+ /* 0x0050 - 0x005e: reserved */
+#define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */
+#define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */
+#define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */
+#define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */
+#define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */
+ /* 0x006e: reserved */
+#define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */
+#define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */
+#define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/
+#define XM_TX_STAT 0x0078 /* 32 bit ro Tx Status LIFO Register */
+
+ /* 0x0080 - 0x00fc: 16 NA reg r/w Exakt Match Address Registers */
+ /* use the XM_EMX() macro to address */
+#define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */
+
+ /*
+ * XM_EXM(Reg)
+ *
+ * returns the XMAC address offset off specified Exakt Match Addr Reg
+ *
+ * para: Reg EXM register to addr (0 .. 15)
+ *
+ * usage: XM_INADDR(XMAC_1,pAC,XM_EXM(i),&val[i]) ;
+ */
+#define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3))
+
+#define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */
+#define XM_SA 0x0108 /* NA reg r/w Station Address Register */
+#define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */
+#define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */
+#define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */
+#define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */
+#define XM_DEV_ID 0x0120 /* 32 bit ro Device ID Register */
+#define XM_MODE 0x0124 /* 32 bit r/w Mode Register */
+#define XM_LSA 0x0128 /* NA reg ro Last Source Register */
+ /* 0x012e: reserved */
+#define XM_TS_READ 0x0130 /* 32 bit ro TimeStamp Read Regeister */
+#define XM_TS_LOAD 0x0134 /* 32 bit ro TimeStamp Load Value */
+ /* 0x0138 - 0x01fe: reserved */
+#define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */
+#define XM_RX_CNT_EV 0x0204 /* 32 bit ro Rx Counter Event Register */
+#define XM_TX_CNT_EV 0x0208 /* 32 bit ro Tx Counter Event Register */
+#define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */
+#define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */
+ /* 0x0204 - 0x027e: reserved */
+#define XM_TXF_OK 0x0280 /* 32 bit ro Frames Transmitted OK Conuter */
+#define XM_TXO_OK_HI 0x0284 /* 32 bit ro Octets Transmitted OK High Cnt*/
+#define XM_TXO_OK_LO 0x0288 /* 32 bit ro Octets Transmitted OK Low Cnt */
+#define XM_TXF_BC_OK 0x028c /* 32 bit ro Broadcast Frames Xmitted OK */
+#define XM_TXF_MC_OK 0x0290 /* 32 bit ro Multicast Frames Xmitted OK */
+#define XM_TXF_UC_OK 0x0294 /* 32 bit ro Unicast Frames Xmitted OK */
+#define XM_TXF_LONG 0x0298 /* 32 bit ro Tx Long Frame Counter */
+#define XM_TXE_BURST 0x029c /* 32 bit ro Tx Burst Event Counter */
+#define XM_TXF_MPAUSE 0x02a0 /* 32 bit ro Tx Pause MAC Ctrl Frame Cnt */
+#define XM_TXF_MCTRL 0x02a4 /* 32 bit ro Tx MAC Ctrl Frame Counter */
+#define XM_TXF_SNG_COL 0x02a8 /* 32 bit ro Tx Single Colliosion Counter */
+#define XM_TXF_MUL_COL 0x02ac /* 32 bit ro Tx Multiple Collision Counter */
+#define XM_TXF_ABO_COL 0x02b0 /* 32 bit ro Tx aborted due to Exessive Col*/
+#define XM_TXF_LAT_COL 0x02b4 /* 32 bit ro Tx Late Collision Counter */
+#define XM_TXF_DEF 0x02b8 /* 32 bit ro Tx Deferred Frame Counter */
+#define XM_TXF_EX_DEF 0x02bc /* 32 bit ro Tx Excessive Deferall Counter */
+#define XM_TXE_FIFO_UR 0x02c0 /* 32 bit ro Tx FIFO Underrun Event Cnt */
+#define XM_TXE_CS_ERR 0x02c4 /* 32 bit ro Tx Carrier Sence Error Cnt */
+#define XM_TXP_UTIL 0x02c8 /* 32 bit ro Tx Utilization in % */
+ /* 0x02cc - 0x02ce: reserved */
+#define XM_TXF_64B 0x02d0 /* 32 bit ro 64 Byte Tx Frame Counter */
+#define XM_TXF_127B 0x02d4 /* 32 bit ro 65-127 Byte Tx Frame Counter */
+#define XM_TXF_255B 0x02d8 /* 32 bit ro 128-255 Byte Tx Frame Counter */
+#define XM_TXF_511B 0x02dc /* 32 bit ro 256-511 Byte Tx Frame Counter */
+#define XM_TXF_1023B 0x02e0 /* 32 bit ro 512-1023 Byte Tx Frame Counter*/
+#define XM_TXF_MAX_SZ 0x02e4 /* 32 bit ro 1024-MaxSize Byte Tx Frame Cnt*/
+ /* 0x02e8 - 0x02fe: reserved */
+#define XM_RXF_OK 0x0300 /* 32 bit ro Frames Received OK */
+#define XM_RXO_OK_HI 0x0304 /* 32 bit ro Octets Received OK High Cnt */
+#define XM_RXO_OK_LO 0x0308 /* 32 bit ro Octets Received OK Low Counter*/
+#define XM_RXF_BC_OK 0x030c /* 32 bit ro Broadcast Frames Received OK */
+#define XM_RXF_MC_OK 0x0310 /* 32 bit ro Multicast Frames Received OK */
+#define XM_RXF_UC_OK 0x0314 /* 32 bit ro Unicast Frames Received OK */
+#define XM_RXF_MPAUSE 0x0318 /* 32 bit ro Rx Pause MAC Ctrl Frame Cnt */
+#define XM_RXF_MCTRL 0x031c /* 32 bit ro Rx MAC Ctrl Frame Counter */
+#define XM_RXF_INV_MP 0x0320 /* 32 bit ro Rx invalid Pause Frame Cnt */
+#define XM_RXF_INV_MOC 0x0324 /* 32 bit ro Rx Frames with inv. MAC Opcode*/
+#define XM_RXE_BURST 0x0328 /* 32 bit ro Rx Burst Event Counter */
+#define XM_RXE_FMISS 0x032c /* 32 bit ro Rx Missed Frames Event Cnt */
+#define XM_RXF_FRA_ERR 0x0330 /* 32 bit ro Rx Framing Error Counter */
+#define XM_RXE_FIFO_OV 0x0334 /* 32 bit ro Rx FIFO overflow Event Cnt */
+#define XM_RXF_JAB_PKT 0x0338 /* 32 bit ro Rx Jabber Packet Frame Cnt */
+#define XM_RXE_CAR_ERR 0x033c /* 32 bit ro Rx Carrier Event Error Cnt */
+#define XM_RXF_LEN_ERR 0x0340 /* 32 bit ro Rx in Range Length Error */
+#define XM_RXE_SYM_ERR 0x0344 /* 32 bit ro Rx Symbol Error Counter */
+#define XM_RXE_SHT_ERR 0x0348 /* 32 bit ro Rx Short Event Error Cnt */
+#define XM_RXE_RUNT 0x034c /* 32 bit ro Rx Runt Event Counter */
+#define XM_RXF_LNG_ERR 0x0350 /* 32 bit ro Rx Frame too Long Error Cnt */
+#define XM_RXF_FCS_ERR 0x0354 /* 32 bit ro Rx Frame Check Seq. Error Cnt */
+ /* 0x0358 - 0x035a: reserved */
+#define XM_RXF_CEX_ERR 0x035c /* 32 bit ro Rx Carrier Ext Error Frame Cnt*/
+#define XM_RXP_UTIL 0x0360 /* 32 bit ro Rx Utilization in % */
+ /* 0x0364 - 0x0366: reserved */
+#define XM_RXF_64B 0x0368 /* 32 bit ro 64 Byte Rx Frame Counter */
+#define XM_RXF_127B 0x036c /* 32 bit ro 65-127 Byte Rx Frame Counter */
+#define XM_RXF_255B 0x0370 /* 32 bit ro 128-255 Byte Rx Frame Counter */
+#define XM_RXF_511B 0x0374 /* 32 bit ro 256-511 Byte Rx Frame Counter */
+#define XM_RXF_1023B 0x0378 /* 32 bit ro 512-1023 Byte Rx Frame Counter*/
+#define XM_RXF_MAX_SZ 0x037c /* 32 bit ro 1024-MaxSize Byte Rx Frame Cnt*/
+ /* 0x02e8 - 0x02fe: reserved */
+
+
+/*----------------------------------------------------------------------------*/
+/*
+ * XMAC Bit Definitions
+ *
+ * If the bit access behaviour differs from the register access behaviour
+ * (r/w, ro) this is docomented after the bit number. The following bit
+ * access behaviours are used:
+ * (sc) self clearing
+ * (ro) read only
+ */
+
+/* XM_MMU_CMD 16 bit r/w MMU Comamnd Register */
+ /* Bit 15..13: reserved */
+#define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */
+#define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */
+#define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */
+#define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */
+ /* Bit 8: reserved */
+#define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */
+#define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */
+#define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */
+#define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */
+#define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */
+#define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Lookback Mode */
+#define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */
+#define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */
+
+
+/* XM_TX_CMD 16 bit r/w Transmit Command Register */
+ /* Bit 15..7: reserved */
+#define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (tx Bk2Bk)*/
+#define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */
+#define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */
+#define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */
+#define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */
+#define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */
+#define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */
+
+
+/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
+ /* Bit 15..5: reserved */
+#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
+
+
+/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
+ /* Bit 15..7: reserved */
+#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
+
+
+/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
+ /* Bit 15..8: reserved */
+#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
+
+
+/* XM_RX_CMD 16 bit r/w Receive Command Register */
+ /* Bit 15..9: reserved */
+#define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */
+ /* inrange error packets */
+#define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */
+ /* jumbo packets */
+#define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */
+#define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */
+#define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */
+#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */
+#define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */
+#define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of rx frames */
+#define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */
+
+
+/* XM_PHY_ADDR 16 bit r/w PHY Address Register */
+ /* Bit 15..5: reserved */
+#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
+
+
+/* XM_GP_PORT 32 bit r/w General Purpose Port Register */
+ /* Bit 31..7: reserved */
+#define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto Negotiation in Progress */
+#define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */
+ /* Bit 4: reserved */
+#define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */
+#define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */
+ /* Bit 1: reserved */
+#define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */
+
+
+/* XM_IMSK 16 bit r/w Interrupt Mask Register */
+/* XM_ISRC 16 bit ro Interrupt Status Register */
+ /* Bit 15: reserved */
+#define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */
+#define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */
+#define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */
+#define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */
+#define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */
+#define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */
+#define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */
+#define XM_IS_AND (1<<7) /* Bit 7: Auto Negotiation Done */
+#define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */
+#define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */
+#define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */
+#define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */
+#define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */
+#define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */
+#define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */
+
+#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
+ XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV |\
+ XM_IS_TXF_UR))
+
+
+/* XM_HW_CFG 16 bit r/w Hardware Config Register */
+ /* Bit 15.. 4: reserved */
+#define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */
+#define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/
+ /* Bit 1: reserved */
+#define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */
+
+
+/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
+/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
+ /* Bit 15..10 reserved */
+#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
+
+/* XM_TX_THR 16 bit r/w Tx Request Threshold */
+/* XM_HT_THR 16 bit r/w Host Request Threshold */
+/* XM_RX_THR 16 bit r/w Receive Request Threshold */
+ /* Bit 15..11 reserved */
+#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Tx FIFO Watermark bits */
+
+
+/* XM_TX_STAT 32 bit ro Tx Status LIFO Register */
+#define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */
+#define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */
+#define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */
+#define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */
+#define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */
+#define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/
+#define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */
+#define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */
+#define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */
+#define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */
+#define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */
+#define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */
+#define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */
+#define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */
+#define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */
+
+/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
+/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
+ /* Bit 15..11: reserved */
+#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
+
+
+/* XM_DEV_ID 32 bit ro Device ID Register */
+#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
+#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
+
+
+/* XM_MODE 32 bit r/w Mode Register */
+ /* Bit 31..27: reserved */
+#define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */
+#define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */
+ /* extern generated */
+#define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode*/
+#define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFOfull*/
+ /* intern generated */
+#define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Lit En*/
+#define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */
+#define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */
+#define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */
+#define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */
+ /* intern generated */
+#define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */
+ /* intern generated */
+#define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */
+#define XM_MD_ENA_HSH (1L<<15) /* Bit 15: Enable Hashing */
+#define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */
+#define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */
+#define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frames */
+#define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */
+#define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err F */
+#define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frames */
+#define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frames */
+#define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frames */
+#define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */
+#define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */
+#define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Boradcast */
+#define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */
+#define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */
+#define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */
+#define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */
+
+#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
+#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
+ XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA |\
+ XM_MD_CAA)
+
+/* XM_STAT_CMD 16 bit r/w Statistics Command Register */
+ /* Bit 16..6: reserved */
+#define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
+#define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
+#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
+#define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
+#define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
+#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
+
+
+/* XM_RX_CNT_EV 32 bit ro Rx Counter Event Register */
+/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
+#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
+#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
+#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
+#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
+#define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
+#define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
+#define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
+#define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */
+#define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
+ /* Bit 22: reserved */
+#define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
+#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
+#define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
+#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
+#define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
+ /* Bit 16: reserved */
+#define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
+#define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */
+#define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
+#define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
+#define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
+#define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
+#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
+#define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
+#define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
+#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
+#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
+#define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
+#define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
+#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
+#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
+#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
+
+#define XMR_DEF_MSK 0x00000006L /* all bits excepting 1 and 2 */
+
+/* XM_TX_CNT_EV 32 bit ro Tx Counter Event Register */
+/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
+ /* Bit 31..26: reserved */
+#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
+#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
+#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
+#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
+#define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
+#define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
+#define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
+#define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
+#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
+#define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
+#define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
+#define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
+#define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
+#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
+#define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
+#define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
+#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
+#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
+#define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
+#define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
+#define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
+#define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
+#define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
+#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
+#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
+#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
+
+#define XMT_DEF_MSK 0x00000006L /* all bits excepting 1 and 2 */
+
+/*
+ * Receive Frame Status Encoding
+ */
+#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
+#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
+#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
+#define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
+#define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
+#define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
+ /* Bit 12: reserved */
+#define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */
+#define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */
+#define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */
+#define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */
+#define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */
+#define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */
+#define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */
+#define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Error */
+#define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Gaint Error */
+#define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */
+#define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
+#define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
+
+/*
+ * XMR_FS_ERR will be set if
+ * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
+ * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
+ * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
+ * XMR_FS_ERR unless the corresponding bit in the Receive Command
+ * Register is set.
+ */
+#define XMR_FS_ANY_ERR XMR_FS_ERR
+
+/*----------------------------------------------------------------------------*/
+/*
+ * XMAC-PHY Registers, indirect addressed over the XMAC
+ */
+#define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */
+#define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */
+#define PHY_XMAC_ID0 0x02 /* 16 bit ro PHY ID0 Register */
+#define PHY_XMAC_ID1 0x03 /* 16 bit ro PHY ID1 Register */
+#define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */
+#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit ro Link Partner Abi Reg */
+#define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */
+#define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
+#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit ro Next Page Link P Reg */
+ /* 0x09 - 0x0e: reserved */
+#define PHY_XMAC_EXT_STAT 0x0f /* 16 bit ro Ext Status Register */
+#define PHY_XMAC_RES_ABI 0x10 /* 16 bit ro PHY Resolved Ability */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Broadcom-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */
+#define PHY_BCOM_STAT 0x01 /* 16 bit ro PHY Status Register */
+#define PHY_BCOM_ID0 0x02 /* 16 bit ro PHY ID0 Register */
+#define PHY_BCOM_ID1 0x03 /* 16 bit ro PHY ID1 Register */
+#define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */
+#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit ro Link Part Ability Reg */
+#define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */
+#define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
+#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit ro Next Page Link P Reg */
+ /* Broadcom-specific registers */
+#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
+#define PHY_BCOM_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */
+ /* 0x0b - 0x0e: reserved */
+#define PHY_BCOM_EXT_STAT 0x0f /* 16 bit ro Extended Status Reg */
+#define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */
+#define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit ro PHY Extended Stat Reg */
+#define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */
+#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */
+#define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */
+ /* 0x15 - 0x17: reserved */
+#define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */
+#define PHY_BCOM_AUX_STAT 0x19 /* 16 bit ro Auxiliary Stat Summary*/
+#define PHY_BCOM_INT_STAT 0x1a /* 16 bit ro Interrupt Status Reg */
+#define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */
+ /* 0x1c: reserved */
+ /* 0x1d - 0x1f: test registers */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Level One-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */
+#define PHY_LONE_STAT 0x01 /* 16 bit ro PHY Status Register */
+#define PHY_LONE_ID0 0x02 /* 16 bit ro PHY ID0 Register */
+#define PHY_LONE_ID1 0x03 /* 16 bit ro PHY ID1 Register */
+#define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */
+#define PHY_LONE_AUNE_LP 0x05 /* 16 bit ro Link Part Ability Reg */
+#define PHY_LONE_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */
+#define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
+#define PHY_LONE_NEPG_LP 0x08 /* 16 bit ro Next Page Link Partner*/
+ /* Level One-specific registers */
+#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
+#define PHY_LONE_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */
+ /* 0x0b -0x0e: reserved */
+#define PHY_LONE_EXT_STAT 0x0f /* 16 bit ro Extended Status Reg */
+#define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
+#define PHY_LONE_Q_STAT 0x11 /* 16 bit ro Quick Status Reg */
+#define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */
+#define PHY_LONE_INT_STAT 0x13 /* 16 bit ro Interrupt Status Reg */
+#define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
+#define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
+#define PHY_LONE_CIM 0x16 /* 16 bit ro CIM Reg */
+ /* 0x17 -0x1c: reserved */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * National-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */
+#define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */
+#define PHY_NAT_ID0 0x02 /* 16 bit ro PHY ID0 Register */
+#define PHY_NAT_ID1 0x03 /* 16 bit ro PHY ID1 Register */
+#define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Autonegotiation Advertisement */
+#define PHY_NAT_AUNE_LP 0x05 /* 16 bit ro Link Partner Ability Reg */
+#define PHY_NAT_AUNE_EXP 0x06 /* 16 bit ro Autonegotiation Expansion Reg */
+#define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */
+#define PHY_NAT_NEPG_LP 0x08 /* 16 bit ro Next Page Link Partner Reg */
+ /* National-specific registers */
+#define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
+#define PHY_NAT_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */
+ /* 0x0b -0x0e: reserved */
+#define PHY_NAT_EXT_STAT 0x0f /* 16 bit ro Extended Status Register */
+#define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit ro Extended Control Reg1 */
+#define PHY_NAT_Q_STAT1 0x11 /* 16 bit ro Quick Status Reg1 */
+#define PHY_NAT_10B_OP 0x12 /* 16 bit ro 10Base-T Operations Reg */
+#define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit ro Extended Control Reg1 */
+#define PHY_NAT_Q_STAT2 0x14 /* 16 bit ro Quick Status Reg2 */
+ /* 0x15 -0x18: reserved */
+#define PHY_NAT_PHY_ADDR 0x19 /* 16 bit ro PHY Address Register */
+
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * PHY bit definitions
+ * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
+ * Xmac/Broadcom/LevelOne/National-specific.
+ * All other are general.
+ */
+
+/***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/
+/***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/
+/***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
+#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY releated regs */
+#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
+#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
+#define PHY_CT_ANE (1<<12) /* Bit 12: Autonegotiation Enabled */
+#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
+#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
+#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Autonegotiation */
+#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
+#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collsion Test enabled */
+#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
+ /* Bit 5..0: reserved */
+
+#define PHY_B_CT_SP1000 (1<<6) /* Bit 6: enable speed of 1000 MBit/s */
+#define PHY_B_CT_SP100 (1<<13) /* Bit 13: enable speed of 100 MBit/s */
+#define PHY_B_CT_SP10 (0) /* Bit 6/13 not set, speed of 10 MBit/s */
+
+#define PHY_L_CT_SP1000 (1<<6) /* Bit 6: enable speed of 1000 MBit/s */
+#define PHY_L_CT_SP100 (1<<13) /* Bit 13: enable speed of 100 MBit/s */
+#define PHY_L_CT_SP10 (0) /* Bit 6/13 not set, speed of 10 MBit/s */
+
+
+/***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/
+/***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/
+/***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
+ /* Bit 15..9: reserved */
+ /* (BC/L1) 100/10 MBit/s cap bits ignored*/
+#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
+ /* Bit 7: reserved */
+#define PHY_ST_PRE_SUB (1<<6) /* Bit 6: (BC/L1) preamble suppression */
+#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Autonegotiation Over */
+#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remode Fault Condition Occured*/
+#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Autonegotiation Capability */
+#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
+#define PHY_ST_JAP_DET (1<<1) /* Bit 1: (BC/L1) Japper Detected */
+#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
+
+
+/* PHY_XMAC_ID1 16 bit ro PHY ID1 Register */
+/* PHY_BCOM_ID1 16 bit ro PHY ID1 Register */
+/* PHY_LONE_ID1 16 bit ro PHY ID1 Register */
+#define PHY_I1_OUI (0x3f<<10) /* Bit 15..10: Organiz. Unique ID */
+#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
+#define PHY_I1_REV (0x0f<<0) /* Bit 3.. 0: Revision Number */
+
+
+/***** PHY_XMAC_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/
+/***** PHY_XMAC_AUNE_LP 16 bit ro Link Partner Ability Reg *****/
+#define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
+#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
+#define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remode Fault Bits */
+ /* Bit 11.. 9: reserved */
+#define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
+#define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */
+#define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */
+ /* Bit 4.. 0: reserved */
+
+/***** PHY_BCOM_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/
+/***** PHY_BCOM_AUNE_LP 16 bit ro Link Partner Ability Reg *****/
+/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
+ /* Bit 14: reserved */
+#define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */
+ /* Bit 12: reserved */
+#define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymetric Pause */
+#define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */
+ /* Bit 9..5: 100/10 BT cap bits ingnored */
+#define PHY_B_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/
+
+/***** PHY_LONE_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/
+/***** PHY_LONE_AUNE_LP 16 bit ro Link Partner Ability Reg *****/
+/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
+ /* Bit 14: reserved */
+#define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */
+ /* Bit 12: reserved */
+#define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymetric Pause */
+#define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */
+ /* Bit 9..5: 100/10 BT cap bits ingnored */
+#define PHY_L_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/
+
+/***** PHY_NAT_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/
+/***** PHY_NAT_AUNE_LP 16 bit ro Link Partner Ability Reg *****/
+/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
+ /* Bit 14: reserved */
+#define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */
+ /* Bit 12: reserved */
+#define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */
+#define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */
+ /* Bit 9..5: 100/10 BT cap bits ingnored */
+#define PHY_N_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/
+
+/* field type definition for PHY_x_AN_SEL */
+#define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */
+
+/***** PHY_XMAC_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/
+ /* Bit 15..4: reserved */
+#define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */
+#define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */
+#define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */
+ /* Bit 0: reserved */
+
+/***** PHY_BCOM_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/
+ /* Bit 15..5: reserved */
+#define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */
+/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
+/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
+/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
+#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Autoneg Cap. */
+
+/***** PHY_LONE_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/
+#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */
+#define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */
+/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
+/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
+/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
+#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Autoneg Cap. */
+
+
+/***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
+/***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
+/***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/
+/***** PHY_XMAC_NEPG_LP 16 bit ro Next Page Link Partner *****/
+/***** PHY_BCOM_NEPG_LP 16 bit ro Next Page Link Partner *****/
+/***** PHY_LONE_NEPG_LP 16 bit ro Next Page Link Partner *****/
+#define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */
+#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/
+#define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */
+#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/
+#define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */
+#define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */
+
+/*
+ * XMAC-Specific
+ */
+/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
+#define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */
+#define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */
+ /* Bit 13..0: reserved */
+
+/***** PHY_XMAC_RES_ABI 16 bit ro PHY Resolved Ability *****/
+ /* Bit 15..9: reserved */
+#define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */
+#define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */
+#define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */
+#define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */
+#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */
+ /* Bit 2..0: reserved */
+/*
+ * Remote Fault Bits (PHY_X_AN_RFB) encoding
+ */
+#define X_RFB_OK (0<<12) /* Bit 12..13 No errors, Link OK */
+#define X_RFB_LF (1<<12) /* Bit 12..13 Link Failure */
+#define X_RFB_OFF (2<<12) /* Bit 12..13 Offline */
+#define X_RFB_AN_ERR (3<<12) /* Bit 12..13 Autonegotiation Error */
+
+/*
+ * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
+ */
+#define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */
+#define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */
+#define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */
+#define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */
+
+
+/*
+ * Broadcom-Specific
+ */
+/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
+#define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
+#define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
+#define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
+#define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
+#define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
+#define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
+ /* Bit 7..0: reserved */
+
+/***** PHY_BCOM_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/
+#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
+#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
+#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
+#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
+#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
+#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
+ /* Bit 9..8: reserved */
+#define PHY_B_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */
+
+/***** PHY_BCOM_EXT_STAT 16 bit ro Extended Status Register *****/
+#define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
+#define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
+#define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
+#define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
+ /* Bit 11..0: reserved */
+
+/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
+#define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */
+#define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */
+#define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
+#define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */
+#define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */
+#define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */
+#define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */
+#define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
+#define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
+#define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
+#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
+#define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
+#define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
+#define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
+#define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */
+#define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII Fifo Elasticy */
+
+/***** PHY_BCOM_P_EXT_STAT 16 bit ro PHY Extended Status Reg *****/
+ /* Bit 15..14: reserved */
+#define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */
+#define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */
+#define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */
+#define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */
+#define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */
+#define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */
+#define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */
+#define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */
+#define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */
+#define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */
+#define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */
+#define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */
+#define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */
+#define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */
+
+/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
+ /* Bit 15..8: reserved */
+#define PHY_B_FC_CTR (255<<0)/* Bit 7..0: False Carrier Counter */
+
+/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
+#define PHY_B_RC_LOC (255<<8)/* Bit 15..8: Local Rx NOT_OK cnt */
+#define PHY_B_RC_REM (255<<0)/* Bit 7..0: Remote Rx NOT_OK cnt */
+
+/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
+#define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */
+#define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */
+#define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */
+ /* Bit 11: reserved */
+#define PHY_B_AC_TX_TST (1<<10) /* Bit 10: tx test bit, always 1 */
+ /* Bit 9.. 8: reserved */
+#define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */
+ /* Bit 6.. 4: reserved */
+#define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */
+ /* Bit 2.. 0: reserved */
+
+/***** PHY_BCOM_AUX_STAT 16 bit ro Auxiliary Status Reg *****/
+#define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */
+#define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */
+#define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */
+#define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */
+#define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */
+#define PHY_B_AS_AN_RES (7<<8) /* Bit 10..8: AN HDC */
+#define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault*/
+#define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */
+#define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */
+#define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */
+#define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */
+#define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */
+#define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */
+#define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */
+
+/***** PHY_BCOM_INT_STAT 16 bit ro Interrupt Status Reg *****/
+/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
+ /* Bit 15: reserved */
+#define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */
+#define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */
+#define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */
+#define PHY_B_IS_LCT (1<<11) /* Bit 11: all counter below 128 */
+#define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */
+#define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */
+#define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */
+#define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */
+#define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */
+#define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */
+#define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */
+#define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */
+#define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */
+#define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */
+#define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */
+
+#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
+
+
+/*
+ * Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding
+ */
+#define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
+#define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
+#define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
+#define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
+
+/*
+ * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
+ */
+#define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */
+#define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */
+/* others: 100/10: invalid for us */
+
+/*
+ * Level One-Specific
+ */
+/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
+#define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
+#define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
+#define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
+#define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
+#define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
+#define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
+ /* Bit 7..0: reserved */
+
+/***** PHY_LONE_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/
+#define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
+#define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
+#define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
+#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/
+#define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
+#define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
+ /* Bit 9..8: reserved */
+#define PHY_B_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */
+
+/***** PHY_LONE_EXT_STAT 16 bit ro Extended Status Register *****/
+#define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
+#define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
+#define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
+#define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
+ /* Bit 11..0: reserved */
+
+/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
+#define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */
+ /* Bit 14: reserved */
+#define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
+#define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */
+#define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */
+#define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */
+#define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */
+#define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */
+#define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */
+#define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */
+#define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */
+#define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */
+#define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */
+#define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */
+#define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */
+#define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */
+
+/***** PHY_LONE_Q_STAT 16 bit ro Quick Status Reg *****/
+#define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */
+#define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */
+#define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */
+#define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */
+#define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */
+#define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
+#define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
+#define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
+#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
+#define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
+#define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
+#define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
+#define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */
+
+/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
+/***** PHY_LONE_INT_STAT 16 bit ro Interrupt Status Reg *****/
+ /* Bit 15..14: reserved */
+#define PHY_L_IS_AN_F (1<<13) /* Bit 13: Autoneg fault */
+ /* Bit 12: not described */
+#define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */
+#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/
+#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/
+#define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */
+#define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */
+#define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */
+#define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */
+#define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */
+#define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */
+#define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */
+#define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */
+#define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */
+
+#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | \
+ PHY_L_IS_INTEN) /* int. mask */
+
+/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
+#define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */
+#define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */
+#define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */
+#define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */
+#define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */
+#define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */
+#define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */
+#define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */
+#define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */
+
+/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
+#define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */
+ /* Bit 14: reserved */
+#define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */
+#define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */
+ /* Bit 11: reserved */
+#define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/
+ /* Bit 9..0: not described */
+
+/***** PHY_LONE_CIM 16 bit ro CIM Reg *****/
+#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
+#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
+
+
+/*
+ * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
+ */
+#define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
+#define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
+#define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
+#define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
+
+
+/*
+ * National-Specific
+ */
+/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
+#define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
+#define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
+#define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
+#define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
+#define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
+#define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
+#define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymetric Pause Cap. */
+ /* Bit 6..0: reserved */
+
+/***** PHY_NAT_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/
+#define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
+#define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
+#define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
+#define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/
+#define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
+#define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
+#define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */
+ /* Bit 8: reserved */
+#define PHY_N_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */
+
+/***** PHY_NAT_EXT_STAT 16 bit ro Extended Status Register *****/
+#define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
+#define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
+#define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
+#define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
+ /* Bit 11..0: reserved */
+
+/* todo: those are still missing */
+/***** PHY_NAT_EXT_CTRL1 16 bit ro Extended Control Reg1 *****/
+/***** PHY_NAT_Q_STAT1 16 bit ro Quick Status Reg1 *****/
+/***** PHY_NAT_10B_OP 16 bit ro 10Base-T Operations Reg *****/
+/***** PHY_NAT_EXT_CTRL2 16 bit ro Extended Control Reg1 *****/
+/***** PHY_NAT_Q_STAT2 16 bit ro Quick Status Reg2 *****/
+/***** PHY_NAT_PHY_ADDR 16 bit ro PHY Address Register *****/
+
+/* typedefs *******************************************************************/
+
+
+/* function prototypes ********************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_XMAC_H */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skaddr.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.33 $
+ * Date: $Date: 1999/05/28 10:56:06 $
+ * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skaddr.c,v $
+ * Revision 1.33 1999/05/28 10:56:06 rassmann
+ * Editorial changes.
+ *
+ * Revision 1.32 1999/03/31 10:59:20 rassmann
+ * Returning Success instead of DupAddr if address shall be overridden
+ * with same value.
+ *
+ * Revision 1.31 1999/01/14 16:18:17 rassmann
+ * Corrected multicast initialization.
+ *
+ * Revision 1.30 1999/01/04 10:30:35 rassmann
+ * SkAddrOverride only possible after SK_INIT_IO phase.
+ *
+ * Revision 1.29 1998/12/29 13:13:10 rassmann
+ * An address override is now preserved in the SK_INIT_IO phase.
+ * All functions return an int now.
+ * Extended parameter checking.
+ *
+ * Revision 1.28 1998/12/01 11:45:53 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.27 1998/12/01 09:22:49 rassmann
+ * SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT
+ * too often.
+ *
+ * Revision 1.26 1998/11/24 12:39:44 rassmann
+ * Reserved multicast entry for BPDU address.
+ * 13 multicast entries left for protocol.
+ *
+ * Revision 1.25 1998/11/17 16:54:23 rassmann
+ * Using exact match for up to 14 multicast addresses.
+ * Still receiving all multicasts if more addresses are added.
+ *
+ * Revision 1.24 1998/11/13 17:24:31 rassmann
+ * Changed return value of SkAddrOverride to int.
+ *
+ * Revision 1.23 1998/11/13 16:56:18 rassmann
+ * Added macro SK_ADDR_COMPARE.
+ * Changed return type of SkAddrOverride to SK_BOOL.
+ *
+ * Revision 1.22 1998/11/04 17:06:17 rassmann
+ * Corrected McUpdate and PromiscuousChange functions.
+ *
+ * Revision 1.21 1998/10/29 14:34:04 rassmann
+ * Clearing SK_ADDR struct at startup.
+ *
+ * Revision 1.20 1998/10/28 18:16:34 rassmann
+ * Avoiding I/Os before SK_INIT_RUN level.
+ * Aligning InexactFilter.
+ *
+ * Revision 1.19 1998/10/28 11:29:28 rassmann
+ * Programming physical address in SkAddrMcUpdate.
+ * Corrected programming of exact match entries.
+ *
+ * Revision 1.18 1998/10/28 10:34:48 rassmann
+ * Corrected reading of physical addresses.
+ *
+ * Revision 1.17 1998/10/28 10:26:13 rassmann
+ * Getting ports' current MAC addresses from EPROM now.
+ * Added debug output.
+ *
+ * Revision 1.16 1998/10/27 16:20:12 rassmann
+ * Reading MAC address byte by byte.
+ *
+ * Revision 1.15 1998/10/22 11:39:09 rassmann
+ * Corrected signed/unsigned mismatches.
+ *
+ * Revision 1.14 1998/10/19 17:12:35 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.13 1998/10/19 17:02:19 rassmann
+ * Now reading permanent MAC addresses from CRF.
+ *
+ * Revision 1.12 1998/10/15 15:15:48 rassmann
+ * Changed Flags Parameters from SK_U8 to int.
+ * Checked with lint.
+ *
+ * Revision 1.11 1998/09/24 19:15:12 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.10 1998/09/18 20:18:54 rassmann
+ * Added HW access.
+ * Implemented swapping.
+ *
+ * Revision 1.9 1998/09/16 11:32:00 rassmann
+ * Including skdrv1st.h again. :(
+ *
+ * Revision 1.8 1998/09/16 11:09:34 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.7 1998/09/14 17:06:34 rassmann
+ * Minor changes.
+ *
+ * Revision 1.6 1998/09/07 08:45:41 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.5 1998/09/04 19:40:19 rassmann
+ * Interface enhancements.
+ *
+ * Revision 1.4 1998/09/04 12:14:12 rassmann
+ * Interface cleanup.
+ *
+ * Revision 1.3 1998/09/02 16:56:40 rassmann
+ * Updated interface.
+ *
+ * Revision 1.2 1998/08/27 14:26:09 rassmann
+ * Updated interface.
+ *
+ * Revision 1.1 1998/08/21 08:30:22 rassmann
+ * First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This module is intended to manage multicast addresses, address override,
+ * and promiscuous mode on GEnesis adapters.
+ *
+ * Address Layout:
+ * port address: physical MAC address
+ * 1st exact match: logical MAC address
+ * 2nd exact match: RLMT multicast
+ * exact match 3-13: OS-specific multicasts
+ *
+ * Include File Hierarchy:
+ *
+ * "skdrv1st.h"
+ * "skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#ifndef lint
+static const char SysKonnectFileId[] =
+ "@(#) $Id: skaddr.c,v 1.33 1999/05/28 10:56:06 rassmann Exp $ (C) SysKonnect.";
+#endif /* !defined(lint) */
+
+#define __SKADDR_C
+
+#ifdef __cplusplus
+xxxx /* not supported yet - force error */
+extern "C" {
+#endif /* cplusplus */
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+#define SK_ADDR_CHEAT YES /* Cheat. */
+
+/*
+ * G32:
+ * POLY equ 04C11DB6h ; CRC polynominal term
+ * bit-reversed: 6DB88320
+ */
+
+#define CRC32_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */
+#if 0
+#define CRC32_POLY 0x6DB88320UL /* CRC32-Poly - XMAC: Little Endian */
+#endif /* 0 */
+#define HASH_BITS 6 /* #bits in hash */
+#define SK_MC_BIT 0x01
+
+/* Error numbers and messages. */
+
+#define SKERR_ADDR_E001 (SK_ERRBASE_ADDR + 0)
+#define SKERR_ADDR_E001MSG "Bad Flags."
+#define SKERR_ADDR_E002 (SKERR_ADDR_E001 + 1)
+#define SKERR_ADDR_E002MSG "New Error."
+
+/* typedefs *******************************************************************/
+
+/* None. */
+
+/* global variables ***********************************************************/
+
+/* 64-bit hash values with all bits set. */
+
+SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+
+/* local variables ************************************************************/
+
+#ifdef DEBUG
+static int Next0[SK_MAX_MACS] = {0, 0};
+#endif /* DEBUG */
+
+/* functions ******************************************************************/
+
+#if 0
+void SkAddrDummy(void)
+{
+ SkAddrInit(NULL, NULL, 0);
+} /* SkAddrDummy */
+#endif /* 0 */
+
+/******************************************************************************
+ *
+ * SkAddrInit - initialize data, set state to init
+ *
+ * Description:
+ *
+ * SK_INIT_DATA
+ * ============
+ *
+ * This routine clears the multicast tables and resets promiscuous mode.
+ * Some entries are reserved for the "logical board address", the
+ * SK-RLMT multicast address, and the BPDU multicast address.
+ *
+ *
+ * SK_INIT_IO
+ * ==========
+ *
+ * All permanent MAC addresses are read from EPROM.
+ * If the current MAC addresses are not already set in software,
+ * they are set to the values of the permanent addresses.
+ * The current addresses are written to the corresponding XMAC.
+ *
+ *
+ * SK_INIT_RUN
+ * ===========
+ *
+ * Nothing.
+ *
+ * Context:
+ * init, pageable
+ *
+ * Returns:
+ * SK_ADDR_SUCCESS
+ */
+int SkAddrInit(
+SK_AC *pAC, /* the adapter context */
+SK_IOC IoC, /* I/O context */
+int Level) /* initialization level */
+{
+ int j;
+ SK_U32 i;
+ SK_U8 *InAddr;
+ SK_U16 *OutAddr;
+ SK_ADDR_PORT *pAPort;
+
+ switch (Level) {
+ case SK_INIT_DATA:
+ SK_MEMSET((char *)&pAC->Addr, 0, sizeof(SK_ADDR));
+
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ pAPort = &pAC->Addr.Port[i];
+ pAPort->PromMode = SK_PROM_MODE_NONE;
+
+ pAPort->FirstExactMatchRlmt =
+ SK_ADDR_FIRST_MATCH_RLMT;
+ pAPort->FirstExactMatchDrv =
+ SK_ADDR_FIRST_MATCH_DRV;
+ pAPort->NextExactMatchRlmt =
+ SK_ADDR_FIRST_MATCH_RLMT;
+ pAPort->NextExactMatchDrv =
+ SK_ADDR_FIRST_MATCH_DRV;
+
+#if 0
+ /* Not here ... */
+
+ /* Reset Promiscuous mode. */
+
+ (void)SkAddrPromiscuousChange(
+ pAC,
+ IoC,
+ i,
+ SK_PROM_MODE_NONE);
+#endif /* 0 */
+ }
+
+#ifdef DEBUG
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ if (pAC->Addr.Port[i].NextExactMatchRlmt <
+ SK_ADDR_FIRST_MATCH_RLMT) {
+ Next0[i] |= 4;
+ }
+ }
+#endif /* DEBUG */
+
+ /* pAC->Addr.InitDone = SK_INIT_DATA; */
+ break;
+
+ case SK_INIT_IO:
+ pAC->Addr.ActivePort = pAC->Rlmt.MacActive;
+
+#ifdef DEBUG
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ if (pAC->Addr.Port[i].NextExactMatchRlmt <
+ SK_ADDR_FIRST_MATCH_RLMT) {
+ Next0[i] |= 8;
+ }
+ }
+#endif /* DEBUG */
+
+ /* Read permanent virtual address from Control Register File. */
+
+ for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
+ InAddr = (SK_U8 *)&pAC->Addr.PermanentMacAddress.a[j];
+ SK_IN8(IoC, B2_MAC_1 + j, InAddr);
+ }
+
+ if (!pAC->Addr.CurrentMacAddressSet) {
+ /*
+ * Set the current virtual MAC address
+ * to the permanent one.
+ */
+
+ pAC->Addr.CurrentMacAddress =
+ pAC->Addr.PermanentMacAddress;
+ pAC->Addr.CurrentMacAddressSet = SK_TRUE;
+ }
+
+ /* Set the current virtual MAC address. */
+
+ pAC->Addr.Port[pAC->Addr.ActivePort].Exact[0] =
+ pAC->Addr.CurrentMacAddress;
+
+#ifdef xDEBUG
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_INIT,
+ ("Permanent MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAC->Addr.PermanentMacAddress.a[0],
+ pAC->Addr.PermanentMacAddress.a[1],
+ pAC->Addr.PermanentMacAddress.a[2],
+ pAC->Addr.PermanentMacAddress.a[3],
+ pAC->Addr.PermanentMacAddress.a[4],
+ pAC->Addr.PermanentMacAddress.a[5]))
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_INIT,
+ ("Virtual MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAC->Addr.CurrentMacAddress.a[0],
+ pAC->Addr.CurrentMacAddress.a[1],
+ pAC->Addr.CurrentMacAddress.a[2],
+ pAC->Addr.CurrentMacAddress.a[3],
+ pAC->Addr.CurrentMacAddress.a[4],
+ pAC->Addr.CurrentMacAddress.a[5]))
+#endif /* DEBUG */
+
+#if 0
+ /* Not here ... */
+
+ (void)SkAddrMcUpdate(pAC, IoC, pAC->Addr.ActivePort);
+#endif /* 0 */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pAPort = &pAC->Addr.Port[i];
+
+ /*
+ * Read permanent port addresses from
+ * Control Register File.
+ */
+
+ for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
+ InAddr = (SK_U8 *)
+ &pAPort->PermanentMacAddress.a[j];
+ SK_IN8(IoC, B2_MAC_2 + 8 * i + j, InAddr);
+ }
+
+ if (!pAPort->CurrentMacAddressSet) {
+ /*
+ * Set the current and previous physical
+ * MAC address of this port to its permanent
+ * MAC address.
+ */
+
+ pAPort->CurrentMacAddress =
+ pAPort->PermanentMacAddress;
+ pAPort->PreviousMacAddress =
+ pAPort->PermanentMacAddress;
+ pAPort->CurrentMacAddressSet = SK_TRUE;
+ }
+
+ /* Set port's current MAC addresses. */
+
+ OutAddr = (SK_U16 *)&pAPort->CurrentMacAddress.a[0];
+ XM_OUTADDR(IoC, i, XM_SA, OutAddr);
+
+#ifdef xDEBUG
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_INIT,
+ ("Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAPort->PermanentMacAddress.a[0],
+ pAPort->PermanentMacAddress.a[1],
+ pAPort->PermanentMacAddress.a[2],
+ pAPort->PermanentMacAddress.a[3],
+ pAPort->PermanentMacAddress.a[4],
+ pAPort->PermanentMacAddress.a[5]))
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_INIT,
+ ("Phsical MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAPort->CurrentMacAddress.a[0],
+ pAPort->CurrentMacAddress.a[1],
+ pAPort->CurrentMacAddress.a[2],
+ pAPort->CurrentMacAddress.a[3],
+ pAPort->CurrentMacAddress.a[4],
+ pAPort->CurrentMacAddress.a[5]))
+#endif /* DEBUG */
+ }
+ /* pAC->Addr.InitDone = SK_INIT_IO; */
+ break;
+
+ case SK_INIT_RUN:
+#ifdef DEBUG
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ if (pAC->Addr.Port[i].NextExactMatchRlmt <
+ SK_ADDR_FIRST_MATCH_RLMT) {
+ Next0[i] |= 16;
+ }
+ }
+#endif /* DEBUG */
+
+ /* pAC->Addr.InitDone = SK_INIT_RUN; */
+ break;
+
+ default: /* error */
+ break;
+ }
+
+ return (SK_ADDR_SUCCESS);
+} /* SkAddrInit */
+
+
+/******************************************************************************
+ *
+ * SkAddrMcClear - clear the multicast table
+ *
+ * Description:
+ * This routine clears the multicast table
+ * (either entry 2 or entries 3-16 and InexactFilter) of the given port.
+ * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated
+ * immediately.
+ *
+ * Context:
+ * runtime, pageable
+ * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY
+ * may be called after SK_INIT_IO without limitation
+ *
+ * Returns:
+ * SK_ADDR_SUCCESS
+ * SK_ADDR_ILLEGAL_PORT
+ */
+int SkAddrMcClear(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx, /* Index of affected port */
+int Flags) /* permanent/non-perm, sw-only */
+{
+ int i;
+
+ if (PortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ if (Flags & SK_ADDR_PERMANENT) {
+
+ /* Clear RLMT multicast addresses. */
+
+ pAC->Addr.Port[PortIdx].NextExactMatchRlmt =
+ SK_ADDR_FIRST_MATCH_RLMT;
+ }
+ else { /* not permanent => DRV */
+
+ /* Clear InexactFilter. */
+
+ for (i = 0; i < 8; i++) {
+ pAC->Addr.Port[PortIdx].InexactFilter.Bytes[i] = 0;
+ }
+
+ /* Clear DRV multicast addresses. */
+
+ pAC->Addr.Port[PortIdx].NextExactMatchDrv =
+ SK_ADDR_FIRST_MATCH_DRV;
+ }
+
+ if (!(Flags & SK_MC_SW_ONLY)) {
+ (void)SkAddrMcUpdate(pAC, IoC, PortIdx);
+ }
+
+ return (SK_ADDR_SUCCESS);
+} /* SkAddrMcClear */
+
+#ifndef SK_ADDR_CHEAT
+// RA;:;:
+/******************************************************************************
+ *
+ * SkCrc32McHash - hash multicast address
+ *
+ * Description:
+ * This routine computes the hash value for a multicast address.
+ *
+ * Notes:
+ * The code was adapted from the XaQti data sheet.
+ *
+ * Context:
+ * runtime, pageable
+ *
+ * Returns:
+ * Hash value of multicast address.
+ */
+unsigned SkCrc32McHash(
+unsigned char *pMc) /* Multicast address */
+{
+ unsigned Idx;
+ unsigned Bit;
+ unsigned Data;
+ unsigned Crc;
+
+ Crc = 0xFFFFFFFFUL;
+ for (Idx = 0; Idx < SK_MAC_ADDR_LEN; Idx++) {
+ Data = *pMc++;
+ for (Bit = 0; Bit < 8; Bit++, Data >>= 1) {
+ Crc = (Crc >> 1) ^
+ (((Crc ^ Data) & 1) ? CRC32_POLY : 0);
+ }
+ }
+
+ return (Crc & ((1 << HASH_BITS) - 1));
+
+} /* SkCrc32McHash */
+
+#endif /* not SK_ADDR_CHEAT */
+
+/******************************************************************************
+ *
+ * SkAddrMcAdd - add a multicast address to a port
+ *
+ * Description:
+ * This routine enables reception for a given address on the given port.
+ *
+ * Notes:
+ * The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * In the current version, only RLMT may add addresses to the non-active
+ * port.
+ *
+ * The multicast bit is only checked if there are no free exact match
+ * entries.
+ *
+ * Context:
+ * runtime, pageable
+ * may be called after SK_INIT_DATA
+ *
+ * Returns:
+ * SK_MC_FILTERING_EXACT
+ * SK_MC_FILTERING_INEXACT
+ * SK_MC_ILLEGAL_ADDRESS
+ * SK_MC_ILLEGAL_PORT
+ * SK_MC_RLMT_OVERFLOW
+ */
+int SkAddrMcAdd(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx, /* Port Index */
+SK_MAC_ADDR *pMc, /* multicast address to be added */
+int Flags) /* permanent/non-permanent */
+{
+ int i;
+ SK_U8 Inexact;
+#ifndef SK_ADDR_CHEAT
+ unsigned HashBit;
+#endif /* !defined(SK_ADDR_CHEAT) */
+
+ if (PortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ if (Flags & SK_ADDR_PERMANENT) {
+#ifdef DEBUG
+ if (pAC->Addr.Port[PortIdx].NextExactMatchRlmt <
+ SK_ADDR_FIRST_MATCH_RLMT) {
+ Next0[PortIdx] |= 1;
+ return (SK_MC_RLMT_OVERFLOW);
+ }
+#endif /* DEBUG */
+
+ if (pAC->Addr.Port[PortIdx].NextExactMatchRlmt >
+ SK_ADDR_LAST_MATCH_RLMT) {
+ return (SK_MC_RLMT_OVERFLOW);
+ }
+
+ /* Set an RLMT multicast address. */
+
+ pAC->Addr.Port[PortIdx].Exact[
+ pAC->Addr.Port[PortIdx].NextExactMatchRlmt++] = *pMc;
+
+ return (SK_MC_FILTERING_EXACT);
+ }
+
+ /* Not PERMANENT => DRV */
+
+ if (PortIdx != pAC->Addr.ActivePort) {
+
+ /* Only RLMT is allowed to do this. */
+
+ return (SK_MC_ILLEGAL_PORT);
+ }
+
+#ifdef DEBUG
+ if (pAC->Addr.Port[PortIdx].NextExactMatchDrv <
+ SK_ADDR_FIRST_MATCH_DRV) {
+ Next0[PortIdx] |= 2;
+ return (SK_MC_RLMT_OVERFLOW);
+ }
+#endif /* DEBUG */
+
+ if (pAC->Addr.Port[PortIdx].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
+
+ /* Set exact match entry. */
+
+ pAC->Addr.Port[PortIdx].Exact[
+ pAC->Addr.Port[PortIdx].NextExactMatchDrv++] = *pMc;
+
+ /* Clear InexactFilter. */
+
+ for (i = 0; i < 8; i++) {
+ pAC->Addr.Port[PortIdx
+ ].InexactFilter.Bytes[i] = 0;
+ }
+ }
+ else {
+ if (!(pMc->a[0] & SK_MC_BIT)) {
+
+ /*
+ * Hashing only possible with
+ * multicast addresses.
+ */
+
+ return (SK_MC_ILLEGAL_ADDRESS);
+ }
+#ifndef SK_ADDR_CHEAT
+ /* Compute hash value of address. */
+RA;:;: untested
+ HashBit = SkCrc32McHash(&pMc->a[0]);
+
+ /* Add bit to InexactFilter. */
+
+ pAC->Addr.Port[PortIdx].InexactFilter.Bytes[HashBit / 8] |=
+ 1 << (HashBit % 8);
+
+#else /* SK_ADDR_CHEAT */
+
+ /* Set all bits in InexactFilter. */
+
+ for (i = 0; i < 8; i++) {
+ pAC->Addr.Port[PortIdx].InexactFilter.Bytes[i] = 0xFF;
+ }
+#endif /* SK_ADDR_CHEAT */
+ }
+
+ for (Inexact = 0, i = 0; i < 8; i++) {
+ Inexact |= pAC->Addr.Port[PortIdx].InexactFilter.Bytes[i];
+ }
+
+ if (Inexact == 0 && pAC->Addr.Port[PortIdx].PromMode == 0) {
+ return (SK_MC_FILTERING_EXACT);
+ }
+ else {
+ return (SK_MC_FILTERING_INEXACT);
+ }
+} /* SkAddrMcAdd */
+
+
+/******************************************************************************
+ *
+ * SkAddrMcUpdate - update the HW MC address table and set the MAC address
+ *
+ * Description:
+ * This routine enables reception of the addresses contained in a local
+ * table for a given port.
+ * It also programs the port's current physical MAC address.
+ *
+ * Notes:
+ * The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * Context:
+ * runtime, pageable
+ * may be called after SK_INIT_IO
+ *
+ * Returns:
+ * SK_MC_FILTERING_EXACT
+ * SK_MC_FILTERING_INEXACT
+ * SK_ADDR_ILLEGAL_PORT
+ */
+int SkAddrMcUpdate(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx) /* Port Index */
+{
+ SK_U32 i;
+ SK_U8 Inexact;
+ SK_U16 *OutAddr;
+ SK_U16 LoMode; /* Lower 16 bits of XMAC Mode Reg. */
+ SK_ADDR_PORT *pAPort;
+
+ if (PortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_CTRL,
+ ("SkAddrMcUpdate on Port %u.\n", PortIdx))
+
+ pAPort = &pAC->Addr.Port[PortIdx];
+
+#ifdef DEBUG
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_CTRL,
+ ("Next0 on Port %d: %d\n", PortIdx, Next0[PortIdx]))
+#endif /* DEBUG */
+
+ for (i = 0; /* Also program the virtual address. */
+ i < pAPort->NextExactMatchRlmt;
+ i++) {
+
+ /* Set exact match address i on HW. */
+
+ OutAddr = (SK_U16 *)&pAPort->Exact[i].a[0];
+ XM_OUTADDR(IoC, PortIdx, XM_EXM(i), OutAddr);
+ }
+
+ /* Clear other permanent exact match addresses on HW. */
+
+ if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
+ SkXmClrExactAddr(
+ pAC,
+ IoC,
+ PortIdx,
+ pAPort->NextExactMatchRlmt,
+ SK_ADDR_LAST_MATCH_RLMT);
+ }
+
+ for (i = pAPort->FirstExactMatchDrv;
+ i < pAPort->NextExactMatchDrv;
+ i++) {
+
+ OutAddr = (SK_U16 *)&pAPort->Exact[i].a[0];
+ XM_OUTADDR(IoC, PortIdx, XM_EXM(i), OutAddr);
+
+ }
+
+ /* Clear other non-permanent exact match addresses on HW. */
+
+ if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
+ SkXmClrExactAddr(
+ pAC,
+ IoC,
+ PortIdx,
+ pAPort->NextExactMatchDrv,
+ SK_ADDR_LAST_MATCH_DRV);
+ }
+
+ for (Inexact = 0xFF, i = 0; i < 8; i++) {
+ Inexact &= pAPort->InexactFilter.Bytes[i];
+ }
+ if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
+
+ /* Set all bits in 64-bit hash register. */
+
+ XM_OUTHASH(IoC, PortIdx, XM_HSM, &OnesHash);
+
+ /* Set bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode |= XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ else if (Inexact != 0xFF) {
+
+ /* Clear bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode &= ~XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ else {
+ /* Set 64-bit hash register to InexactFilter. */
+
+ XM_OUTHASH(
+ IoC,
+ PortIdx,
+ XM_HSM,
+ &pAPort->InexactFilter.Bytes[0]);
+
+ /* Set bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode |= XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+
+ if (pAPort->PromMode != SK_PROM_MODE_NONE) {
+ (void)SkAddrPromiscuousChange(
+ pAC,
+ IoC,
+ PortIdx,
+ pAPort->PromMode);
+ }
+
+ /* Set port's current MAC address. */
+
+ OutAddr = (SK_U16 *)&pAPort->CurrentMacAddress.a[0];
+ XM_OUTADDR(IoC, PortIdx, XM_SA, OutAddr);
+
+#ifdef DEBUG
+ for (i = 0; /* Also program the virtual address. */
+ i < pAPort->NextExactMatchRlmt;
+ i++) {
+ SK_U8 InAddr8[6];
+ SK_U16 *InAddr;
+
+ /* Get exact match address i from port PortIdx. */
+
+ InAddr = (SK_U16 *)&InAddr8[0];
+ XM_INADDR(IoC, PortIdx, XM_EXM(i), InAddr);
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("MC address %d on Port %u: %02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x.\n",
+ i,
+ PortIdx,
+ InAddr8[0],
+ InAddr8[1],
+ InAddr8[2],
+ InAddr8[3],
+ InAddr8[4],
+ InAddr8[5],
+ pAPort->Exact[i].a[0],
+ pAPort->Exact[i].a[1],
+ pAPort->Exact[i].a[2],
+ pAPort->Exact[i].a[3],
+ pAPort->Exact[i].a[4],
+ pAPort->Exact[i].a[5]))
+ }
+#endif /* DEBUG */
+
+ /* Determine return value. */
+
+ for (Inexact = 0, i = 0; i < 8; i++) {
+ Inexact |= pAPort->InexactFilter.Bytes[i];
+ }
+ if (Inexact == 0 && pAPort->PromMode == 0) {
+ return (SK_MC_FILTERING_EXACT);
+ }
+ else {
+ return (SK_MC_FILTERING_INEXACT);
+ }
+} /* SkAddrMcUpdate */
+
+
+/******************************************************************************
+ *
+ * SkAddrOverride - override a port's MAC address
+ *
+ * Description:
+ * This routine overrides the MAC address of one port.
+ *
+ * Context:
+ * runtime, pageable
+ * may be called after SK_INIT_IO
+ *
+ * Returns:
+ * SK_ADDR_SUCCESS if successful.
+ * SK_ADDR_DUPLICATE_ADDRESS if duplicate MAC address.
+ * SK_ADDR_MULTICAST_ADDRESS if multicast or broadcast address.
+ * SK_ADDR_TOO_EARLY if SK_INIT_IO was not executed before.
+ */
+int SkAddrOverride(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx, /* Port Index */
+SK_MAC_ADDR *pNewAddr, /* new MAC address */
+int Flags) /* logical/physical address */
+{
+ SK_U32 i;
+ SK_U16 *OutAddr;
+ SK_EVPARA Para;
+#if 0
+ SK_MAC_ADDR NewAddr; /* new MAC address */
+ SK_U8 AddrBits;
+#endif /* 0 */
+
+ if (PortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ if (pNewAddr->a[0] & SK_MC_BIT) {
+ return (SK_ADDR_MULTICAST_ADDRESS);
+ }
+
+#if 0
+DANGEROUS!
+ if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical address. */
+ if (!pAC->Addr.Port[PortIdx].CurrentMacAddressSet) {
+ pAC->Addr.Port[PortIdx].PreviousMacAddress = *pNewAddr;
+ pAC->Addr.Port[PortIdx].CurrentMacAddress = *pNewAddr;
+ pAC->Addr.Port[PortIdx].CurrentMacAddressSet = SK_TRUE;
+ return (SK_ADDR_SUCCESS);
+ }
+ }
+ else {
+ if (!pAC->Addr.CurrentMacAddressSet) {
+ pAC->Addr.CurrentMacAddress = *pNewAddr;
+ pAC->Addr.CurrentMacAddressSet = SK_TRUE;
+ return (SK_ADDR_SUCCESS);
+ }
+ }
+DANGEROUS!
+#endif /* 0 */
+
+ if (!pAC->Addr.CurrentMacAddressSet) {
+ return (SK_ADDR_TOO_EARLY);
+ }
+
+ if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical address. */
+ if (SK_ADDR_EQUAL(pNewAddr->a, pAC->Addr.CurrentMacAddress.a)) {
+ return (SK_ADDR_DUPLICATE_ADDRESS);
+ }
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+ return (SK_ADDR_TOO_EARLY);
+ }
+
+ if (SK_ADDR_EQUAL(
+ pNewAddr->a,
+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
+ if (i == PortIdx) {
+ return (SK_ADDR_SUCCESS);
+ }
+ else {
+ return (SK_ADDR_DUPLICATE_ADDRESS);
+ }
+ }
+ }
+
+ pAC->Addr.Port[PortIdx].PreviousMacAddress =
+ pAC->Addr.Port[PortIdx].CurrentMacAddress;
+ pAC->Addr.Port[PortIdx].CurrentMacAddress = *pNewAddr;
+
+ /* Change port's address. */
+
+ OutAddr = (SK_U16 *)pNewAddr;
+ XM_OUTADDR(IoC, PortIdx, XM_SA, OutAddr);
+
+ /* Report address change to RLMT. */
+
+ Para.Para32[0] = PortIdx;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
+ }
+ else { /* Logical Address. */
+ if (SK_ADDR_EQUAL(pNewAddr->a, pAC->Addr.CurrentMacAddress.a)) {
+ return (SK_ADDR_SUCCESS);
+ }
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+ return (SK_ADDR_TOO_EARLY);
+ }
+
+ if (SK_ADDR_EQUAL(
+ pNewAddr->a,
+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
+ return (SK_ADDR_DUPLICATE_ADDRESS);
+ }
+ }
+
+ pAC->Addr.CurrentMacAddress = *pNewAddr;
+ pAC->Addr.Port[PortIdx].Exact[0] = *pNewAddr;
+
+#ifdef DEBUG
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_CTRL,
+ ("Permanent MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAC->Addr.PermanentMacAddress.a[0],
+ pAC->Addr.PermanentMacAddress.a[1],
+ pAC->Addr.PermanentMacAddress.a[2],
+ pAC->Addr.PermanentMacAddress.a[3],
+ pAC->Addr.PermanentMacAddress.a[4],
+ pAC->Addr.PermanentMacAddress.a[5]))
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_ADDR,
+ SK_DBGCAT_CTRL,
+ ("New Virtual MAC Address: %02X %02X %02X %02X %02X %02X\n",
+ pAC->Addr.CurrentMacAddress.a[0],
+ pAC->Addr.CurrentMacAddress.a[1],
+ pAC->Addr.CurrentMacAddress.a[2],
+ pAC->Addr.CurrentMacAddress.a[3],
+ pAC->Addr.CurrentMacAddress.a[4],
+ pAC->Addr.CurrentMacAddress.a[5]))
+#endif /* DEBUG */
+
+ /* Write address to first exact match entry of active port. */
+
+ (void)SkAddrMcUpdate(pAC, IoC, PortIdx);
+ }
+
+ return (SK_ADDR_SUCCESS);
+} /* SkAddrOverride */
+
+
+/******************************************************************************
+ *
+ * SkAddrPromiscuousChange - set promiscuous mode for given port
+ *
+ * Description:
+ * This routine manages promiscuous mode:
+ * - none
+ * - all LLC frames
+ * - all MC frames
+ *
+ * Context:
+ * runtime, pageable
+ * may be called after SK_INIT_IO
+ *
+ * Returns:
+ * SK_ADDR_SUCCESS
+ * SK_ADDR_ILLEGAL_PORT
+ */
+int SkAddrPromiscuousChange(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx, /* port whose promiscuous mode changes */
+int NewPromMode) /* new promiscuous mode */
+{
+ int i;
+ SK_BOOL InexactModeBit;
+ SK_U8 Inexact;
+ SK_U8 HwInexact;
+ SK_FILTER64 HwInexactFilter;
+ SK_U16 LoMode; /* Lower 16 bits of XMAC Mode Register. */
+ int CurPromMode = SK_PROM_MODE_NONE;
+
+ if (PortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ /* Read CurPromMode from Hardware. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+
+ if (LoMode & XM_MD_ENA_PROM) {
+ CurPromMode |= SK_PROM_MODE_LLC;
+ }
+
+ for (Inexact = 0xFF, i = 0; i < 8; i++) {
+ Inexact &= pAC->Addr.Port[PortIdx].InexactFilter.Bytes[i];
+ }
+ if (Inexact == 0xFF) {
+ CurPromMode |= (pAC->Addr.Port[PortIdx].PromMode &
+ SK_PROM_MODE_ALL_MC);
+ }
+ else {
+ /* Read InexactModeBit (bit 15 in mode register). */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+
+ InexactModeBit = (LoMode & XM_MD_ENA_HSH) != 0;
+
+ /* Read 64-bit hash register from HW. */
+
+ XM_INHASH(IoC, PortIdx, XM_HSM, &HwInexactFilter.Bytes[0]);
+
+ for (HwInexact = 0xFF, i = 0; i < 8; i++) {
+ HwInexact &= HwInexactFilter.Bytes[i];
+ }
+
+ if (InexactModeBit && (HwInexact == 0xFF)) {
+ CurPromMode |= SK_PROM_MODE_ALL_MC;
+ }
+ }
+
+ pAC->Addr.Port[PortIdx].PromMode = NewPromMode;
+
+ if (NewPromMode == CurPromMode) {
+ return (SK_ADDR_SUCCESS);
+ }
+
+ if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
+ !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
+
+ /* Set all bits in 64-bit hash register. */
+
+ XM_OUTHASH(IoC, PortIdx, XM_HSM, &OnesHash);
+
+ /* Set bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode |= XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ else if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
+ !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm MC. */
+
+ for (Inexact = 0, i = 0; i < 8; i++) {
+ Inexact |=
+ pAC->Addr.Port[PortIdx].InexactFilter.Bytes[i];
+ }
+ if (Inexact == 0) {
+ /* Clear bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode &= ~XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ else {
+ /* Set 64-bit hash register to InexactFilter. */
+
+ XM_OUTHASH(
+ IoC,
+ PortIdx,
+ XM_HSM,
+ &pAC->Addr.Port[PortIdx
+ ].InexactFilter.Bytes[0]);
+
+ /* Set bit 15 in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+ LoMode |= XM_MD_ENA_HSH;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ }
+
+ if ((NewPromMode & SK_PROM_MODE_LLC) &&
+ !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
+
+ /* Set promiscuous bit in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+#if 0
+ /* Receive MAC frames. */
+
+ LoMode |= XM_MD_RX_MCTRL;
+#endif /* 0 */
+ LoMode |= XM_MD_ENA_PROM;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+ else if ((CurPromMode & SK_PROM_MODE_LLC) &&
+ !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC. */
+
+ /* Clear promiscuous bit in mode register. */
+
+ XM_IN16(IoC, PortIdx, XM_MODE, &LoMode);
+#if 0
+ /* Don't receive MAC frames. */
+
+ LoMode &= ~XM_MD_RX_MCTRL;
+#endif /* 0 */
+ LoMode &= ~XM_MD_ENA_PROM;
+ XM_OUT16(IoC, PortIdx, XM_MODE, LoMode);
+ }
+
+ return (SK_ADDR_SUCCESS);
+} /* SkAddrPromiscuousChange */
+
+
+/******************************************************************************
+ *
+ * SkAddrSwap - swap address info
+ *
+ * Description:
+ * This routine swaps address info of two ports.
+ *
+ * Context:
+ * runtime, pageable
+ * may be called after SK_INIT_IO
+ *
+ * Returns:
+ * SK_ADDR_SUCCESS
+ * SK_ADDR_ILLEGAL_PORT
+ */
+int SkAddrSwap(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 FromPortIdx, /* Port1 Index */
+SK_U32 ToPortIdx) /* Port2 Index */
+{
+ int i;
+ SK_U8 Byte;
+ SK_MAC_ADDR MacAddr;
+ SK_U32 DWord;
+
+ if (FromPortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ if (ToPortIdx >= (SK_U32)pAC->GIni.GIMacsFound) {
+ return (SK_ADDR_ILLEGAL_PORT);
+ }
+
+ /*
+ * Swap
+ * - Exact Match Entries
+ * - FirstExactMatchRlmt;
+ * - NextExactMatchRlmt;
+ * - FirstExactMatchDrv;
+ * - NextExactMatchDrv;
+ * - 64-bit filter
+ * - Promiscuous Mode
+ * of ports.
+ */
+
+ for (i = 0; i < SK_ADDR_EXACT_MATCHES; i++) {
+ MacAddr = pAC->Addr.Port[FromPortIdx].Exact[i];
+ pAC->Addr.Port[FromPortIdx].Exact[i] =
+ pAC->Addr.Port[ToPortIdx].Exact[i];
+ pAC->Addr.Port[ToPortIdx].Exact[i] = MacAddr;
+ }
+
+ for (i = 0; i < 8; i++) {
+ Byte = pAC->Addr.Port[FromPortIdx].InexactFilter.Bytes[i];
+ pAC->Addr.Port[FromPortIdx].InexactFilter.Bytes[i] =
+ pAC->Addr.Port[ToPortIdx].InexactFilter.Bytes[i];
+ pAC->Addr.Port[ToPortIdx].InexactFilter.Bytes[i] = Byte;
+ }
+
+ i = pAC->Addr.Port[FromPortIdx].PromMode;
+ pAC->Addr.Port[FromPortIdx].PromMode =
+ pAC->Addr.Port[ToPortIdx].PromMode;
+ pAC->Addr.Port[ToPortIdx].PromMode = i;
+
+ DWord = pAC->Addr.Port[FromPortIdx].FirstExactMatchRlmt;
+ pAC->Addr.Port[FromPortIdx].FirstExactMatchRlmt =
+ pAC->Addr.Port[ToPortIdx].FirstExactMatchRlmt;
+ pAC->Addr.Port[ToPortIdx].FirstExactMatchRlmt = DWord;
+
+ DWord = pAC->Addr.Port[FromPortIdx].NextExactMatchRlmt;
+ pAC->Addr.Port[FromPortIdx].NextExactMatchRlmt =
+ pAC->Addr.Port[ToPortIdx].NextExactMatchRlmt;
+ pAC->Addr.Port[ToPortIdx].NextExactMatchRlmt = DWord;
+
+ DWord = pAC->Addr.Port[FromPortIdx].FirstExactMatchDrv;
+ pAC->Addr.Port[FromPortIdx].FirstExactMatchDrv =
+ pAC->Addr.Port[ToPortIdx].FirstExactMatchDrv;
+ pAC->Addr.Port[ToPortIdx].FirstExactMatchDrv = DWord;
+
+ DWord = pAC->Addr.Port[FromPortIdx].NextExactMatchDrv;
+ pAC->Addr.Port[FromPortIdx].NextExactMatchDrv =
+ pAC->Addr.Port[ToPortIdx].NextExactMatchDrv;
+ pAC->Addr.Port[ToPortIdx].NextExactMatchDrv = DWord;
+
+ pAC->Addr.ActivePort = ToPortIdx;
+
+ (void)SkAddrMcUpdate(pAC, IoC, FromPortIdx);
+ (void)SkAddrMcUpdate(pAC, IoC, ToPortIdx);
+
+ return (SK_ADDR_SUCCESS);
+} /* SkAddrSwap */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skcsum.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.3 $
+ * Date: $Date: 1999/05/10 08:39:33 $
+ * Purpose: Store/verify Internet checksum in send/receive packets.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skcsum.c,v $
+ * Revision 1.3 1999/05/10 08:39:33 mkarl
+ * prevent overflows in SKCS_HTON16
+ * fixed a bug in pseudo header checksum calculation
+ * added some comments
+ *
+ * Revision 1.2 1998/10/22 11:53:28 swolf
+ * Now using SK_DBG_MSG.
+ *
+ * Revision 1.1 1998/09/01 15:35:41 swolf
+ * initial revision
+ *
+ * 13-May-1998 sw Created.
+ *
+ ******************************************************************************/
+
+#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
+
+#ifndef lint
+static const char SysKonnectFileId[] = "@(#)"
+ "$Id: skcsum.c,v 1.3 1999/05/10 08:39:33 mkarl Exp $"
+ " (C) SysKonnect.";
+#endif /* !lint */
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the "GEnesis" common module "CSUM".
+ *
+ * This module contains the code necessary to calculate, store, and verify the
+ * Internet Checksum of IP, TCP, and UDP frames.
+ *
+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
+ * and is the code name of this SysKonnect project.
+ *
+ * Compilation Options:
+ *
+ * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
+ * empty module.
+ *
+ * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
+ * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
+ * external.
+ *
+ * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
+ * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
+ * external.
+ *
+ * Include File Hierarchy:
+ *
+ * "h/skdrv1st.h"
+ * "h/skcsum.h"
+ * "h/sktypes.h"
+ * "h/skqueue.h"
+ * "h/skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skcsum.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+/* The size of an Ethernet MAC header. */
+#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2)
+
+/* The size of the used topology's MAC header. */
+#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE
+
+/* The size of the IP header without any option fields. */
+#define SKCS_IP_HEADER_SIZE 20
+
+/*
+ * Field offsets within the IP header.
+ */
+
+/* "Internet Header Version" and "Length". */
+#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0
+
+/* "Total Length". */
+#define SKCS_OFS_IP_TOTAL_LENGTH 2
+
+/* "Flags" "Fragment Offset". */
+#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6
+
+/* "Next Level Protocol" identifier. */
+#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9
+
+/* Source IP address. */
+#define SKCS_OFS_IP_SOURCE_ADDRESS 12
+
+/* Destination IP address. */
+#define SKCS_OFS_IP_DESTINATION_ADDRESS 16
+
+/* IP "Next Level Protocol" identifiers (see RFC 790). */
+#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */
+#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */
+
+/* IP "Don't Fragment" bit. */
+#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000)
+
+/* Add a byte offset to a pointer. */
+#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs)))
+
+/*
+ * Macros that convert host to network representation and vice versa, i.e.
+ * little/big endian conversion on little endian machines only.
+ */
+#ifdef SK_LITTLE_ENDIAN
+#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xFF) << 8))
+#endif /* SK_LITTLE_ENDIAN */
+#ifdef SK_BIG_ENDIAN
+#define SKCS_HTON16(Val16) (Val16)
+#endif /* SK_BIG_ENDIAN */
+#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16)
+
+/* typedefs *******************************************************************/
+
+/* function prototypes ********************************************************/
+
+/******************************************************************************
+ *
+ * SkCsGetSendInfo - get checksum information for a send packet
+ *
+ * Description:
+ * Get all checksum information necessary to send a TCP or UDP packet. The
+ * function checks the IP header passed to it. If the high-level protocol
+ * is either TCP or UDP the pseudo header checksum is calculated and
+ * returned.
+ *
+ * The function returns the total length of the IP header (including any
+ * IP option fields), which is the same as the start offset of the IP data
+ * which in turn is the start offset of the TCP or UDP header.
+ *
+ * The function also returns the TCP or UDP pseudo header checksum, which
+ * should be used as the start value for the hardware checksum calculation.
+ * (Note that any actual pseudo header checksum can never calculate to
+ * zero.)
+ *
+ * Note:
+ * There is a bug in the ASIC whic may lead to wrong checksums.
+ *
+ * Arguments:
+ * pAc - A pointer to the adapter context struct.
+ *
+ * pIpHeader - Pointer to IP header. Must be at least the IP header *not*
+ * including any option fields, i.e. at least 20 bytes.
+ *
+ * Note: This pointer will be used to address 8-, 16-, and 32-bit
+ * variables with the respective alignment offsets relative to the pointer.
+ * Thus, the pointer should point to a 32-bit aligned address. If the
+ * target system cannot address 32-bit variables on non 32-bit aligned
+ * addresses, then the pointer *must* point to a 32-bit aligned address.
+ *
+ * pPacketInfo - A pointer to the packet information structure for this
+ * packet. Before calling this SkCsGetSendInfo(), the following field must
+ * be initialized:
+ *
+ * ProtocolFlags - Initialize with any combination of
+ * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
+ * the protocols specified here. Any protocol(s) not specified
+ * here will be ignored.
+ *
+ * Note: Only one checksum can be calculated in hardware. Thus, if
+ * SKCS_PROTO_IP is specified in the 'ProtocolFlags',
+ * SkCsGetSendInfo() must calculate the IP header checksum in
+ * software. It might be a better idea to have the calling
+ * protocol stack calculate the IP header checksum.
+ *
+ * Returns: N/A
+ * On return, the following fields in 'pPacketInfo' may or may not have
+ * been filled with information, depending on the protocol(s) found in the
+ * packet:
+ *
+ * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
+ * that were both requested by the caller and actually found in the packet.
+ * Protocol(s) not specified by the caller and/or not found in the packet
+ * will have their respective SKCS_PROTO_XXX bit flags reset.
+ *
+ * Note: For IP fragments, TCP and UDP packet information is ignored.
+ *
+ * IpHeaderLength - The total length in bytes of the complete IP header
+ * including any option fields is returned here. This is the start offset
+ * of the IP data, i.e. the TCP or UDP header if present.
+ *
+ * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
+ * 16-bit Internet Checksum of the IP header is returned here. This value
+ * is to be stored into the packet's 'IP Header Checksum' field.
+ *
+ * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
+ * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
+ * of the TCP or UDP pseudo header is returned here.
+ */
+void SkCsGetSendInfo(
+SK_AC *pAc, /* Adapter context struct. */
+void *pIpHeader, /* IP header. */
+SKCS_PACKET_INFO *pPacketInfo) /* Packet information struct. */
+{
+ /* Internet Header Version found in IP header. */
+ unsigned InternetHeaderVersion;
+
+ /* Length of the IP header as found in IP header. */
+ unsigned IpHeaderLength;
+
+ /* Bit field specifiying the desired/found protocols. */
+ unsigned ProtocolFlags;
+
+ /* Next level protocol identifier found in IP header. */
+ unsigned NextLevelProtocol;
+
+ /* Length of IP data portion. */
+ unsigned IpDataLength;
+
+ /* TCP/UDP pseudo header checksum. */
+ unsigned long PseudoHeaderChecksum;
+
+ /* Pointer to next level protocol statistics structure. */
+ SKCS_PROTO_STATS *NextLevelProtoStats;
+
+ /* Temporary variable. */
+ unsigned Tmp;
+
+ Tmp = *(SK_U8 *)
+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
+
+ /* Get the Internet Header Version (IHV). */
+ /* Note: The IHV is stored in the upper four bits. */
+
+ InternetHeaderVersion = Tmp >> 4;
+
+ /* Check the Internet Header Version. */
+ /* Note: We currently only support IP version 4. */
+
+ if (InternetHeaderVersion != 4) { /* IPv4? */
+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
+ ("Tx: Unknown Internet Header Version %u.\n",
+ InternetHeaderVersion));
+ pPacketInfo->ProtocolFlags = 0;
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].TxUnableCts++;
+ return;
+ }
+
+ /* Get the IP header length (IHL). */
+ /*
+ * Note: The IHL is stored in the lower four bits as the number of
+ * 4-byte words.
+ */
+
+ IpHeaderLength = (Tmp & 0xf) * 4;
+ pPacketInfo->IpHeaderLength = IpHeaderLength;
+
+ /* Check the IP header length. */
+
+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
+
+ if (IpHeaderLength < 5*4) {
+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
+ ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
+ pPacketInfo->ProtocolFlags = 0;
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].TxUnableCts++;
+ return;
+ }
+
+ /* This is an IPv4 frame with a header of valid length. */
+
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].TxOkCts++;
+
+ /* Check if we should calculate the IP header checksum. */
+
+ ProtocolFlags = pPacketInfo->ProtocolFlags;
+
+ if (ProtocolFlags & SKCS_PROTO_IP) {
+ pPacketInfo->IpHeaderChecksum =
+ SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
+ }
+
+ /* Get the next level protocol identifier. */
+
+ NextLevelProtocol =
+ *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
+
+ /*
+ * Check if this is a TCP or UDP frame and if we should calculate the
+ * TCP/UDP pseudo header checksum.
+ *
+ * Also clear all protocol bit flags of protocols not present in the
+ * frame.
+ */
+
+ if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
+ /* TCP/IP frame. */
+ ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
+ NextLevelProtoStats =
+ &pAc->Csum.ProtoStats[SKCS_PROTO_STATS_TCP];
+ }
+ else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
+ /* UDP/IP frame. */
+ ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
+ NextLevelProtoStats =
+ &pAc->Csum.ProtoStats[SKCS_PROTO_STATS_UDP];
+ }
+ else {
+ /*
+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
+ * specified.
+ */
+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
+ return;
+ }
+
+ /* Check if this is an IP fragment. */
+
+ /*
+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
+ * and the "More Fragments" are zero, it is *not* a fragment. We can
+ * easily check both at the same time since they are in the same 16-bit
+ * word.
+ */
+
+ if ((*(SK_U16 *)
+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
+ /* IP fragment; ignore all other protocols. */
+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
+ NextLevelProtoStats->TxUnableCts++;
+ return;
+ }
+
+ /*
+ * Calculate the TCP/UDP pseudo header checksum.
+ */
+
+ /* Get total length of IP header and data. */
+
+ IpDataLength =
+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
+
+ /* Get length of IP data portion. */
+
+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
+
+ /* Calculate the sum of all pseudo header fields (16-bit). */
+
+ PseudoHeaderChecksum =
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
+ (unsigned long) (NextLevelProtocol << 8) +
+ (unsigned long) SKCS_HTON16(IpDataLength);
+
+ /* Add-in any carries. */
+
+ SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
+
+ /* Add-in any new carry. */
+
+ SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
+
+ NextLevelProtoStats->TxOkCts++; /* Success. */
+}
+
+/******************************************************************************
+ *
+ * SkCsGetReceiveInfo - verify checksum information for a received packet
+ *
+ * Description:
+ * Verify a received frame's checksum. The function returns a status code
+ * reflecting the result of the verification.
+ *
+ * Note:
+ * Before calling this function you have to verify that the frame is
+ * not padded and Checksum1 and Checksum2 are bigger than 1.
+ *
+ * Arguments:
+ * pAc - Pointer to adapter context struct.
+ *
+ * pIpHeader - Pointer to IP header. Must be at least the length in bytes
+ * of the received IP header including any option fields.
+ *
+ * Note: The actual length of the IP header is stored in the lower four
+ * bits of the first octet of the IP header as the number of 4-byte words,
+ * so it must be multiplied by four to get the length in bytes. Thus, the
+ * maximum IP header length is 15 * 4 = 60 bytes.
+ *
+ * Checksum1 - The first 16-bit Internet Checksum calculated by the
+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
+ *
+ * Checksum2 - The second 16-bit Internet Checksum calculated by the
+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
+ *
+ * Returns:
+ * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
+ * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
+ * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
+ * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
+ * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
+ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
+ * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
+ * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
+ *
+ * Note: The SKCS_STATUS_XXX values returned here are *not* defined by
+ * the CSUM module but must be defined in some header file by the module
+ * using CSUM. In this way, the calling module can assign return values
+ * for its own needs, e.g. by assigning bit flags to the individual
+ * protocols.
+ */
+SKCS_STATUS SkCsGetReceiveInfo(
+SK_AC *pAc, /* Adapter context struct. */
+void *pIpHeader, /* IP header. */
+unsigned Checksum1, /* Hardware checksum 1. */
+unsigned Checksum2) /* Hardware checksum 2. */
+{
+ /* Internet Header Version found in IP header. */
+ unsigned InternetHeaderVersion;
+
+ /* Length of the IP header as found in IP header. */
+ unsigned IpHeaderLength;
+
+ /* Length of IP data portion. */
+ unsigned IpDataLength;
+
+ /* IP header checksum. */
+ unsigned IpHeaderChecksum;
+
+ /* IP header options checksum, if any. */
+ unsigned IpOptionsChecksum;
+
+ /* IP data checksum, i.e. TCP/UDP checksum. */
+ unsigned IpDataChecksum;
+
+ /* Next level protocol identifier found in IP header. */
+ unsigned NextLevelProtocol;
+
+ /* The checksum of the "next level protocol", i.e. TCP or UDP. */
+ unsigned long NextLevelProtocolChecksum;
+
+ /* Pointer to next level protocol statistics structure. */
+ SKCS_PROTO_STATS *NextLevelProtoStats;
+
+ /* Temporary variable. */
+ unsigned Tmp;
+
+ Tmp = *(SK_U8 *)
+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
+
+ /* Get the Internet Header Version (IHV). */
+ /* Note: The IHV is stored in the upper four bits. */
+
+ InternetHeaderVersion = Tmp >> 4;
+
+ /* Check the Internet Header Version. */
+ /* Note: We currently only support IP version 4. */
+
+ if (InternetHeaderVersion != 4) { /* IPv4? */
+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+ ("Rx: Unknown Internet Header Version %u.\n",
+ InternetHeaderVersion));
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].RxUnableCts++;
+ return (SKCS_STATUS_UNKNOWN_IP_VERSION);
+ }
+
+ /* Get the IP header length (IHL). */
+ /*
+ * Note: The IHL is stored in the lower four bits as the number of
+ * 4-byte words.
+ */
+
+ IpHeaderLength = (Tmp & 0xf) * 4;
+
+ /* Check the IP header length. */
+
+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
+
+ if (IpHeaderLength < 5*4) {
+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+ ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].RxErrCts++;
+ return (SKCS_STATUS_IP_CSUM_ERROR);
+ }
+
+ /* This is an IPv4 frame with a header of valid length. */
+
+ /* Get the IP header and data checksum. */
+
+ IpDataChecksum = Checksum2;
+
+ /*
+ * The IP header checksum is calculated as follows:
+ *
+ * IpHeaderChecksum = Checksum1 - Checksum2
+ */
+
+ SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
+
+ /* Check if any IP header options. */
+
+ if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
+
+ /* Get the IP options checksum. */
+
+ IpOptionsChecksum = SkCsCalculateChecksum(
+ SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
+ IpHeaderLength - SKCS_IP_HEADER_SIZE);
+
+ /* Adjust the IP header and IP data checksums. */
+
+ SKCS_OC_ADD(IpHeaderChecksum,
+ IpHeaderChecksum, IpOptionsChecksum);
+
+ SKCS_OC_SUB(IpDataChecksum,
+ IpDataChecksum, IpOptionsChecksum);
+ }
+
+ /* Check if the IP header checksum is ok. */
+ /*
+ * NOTE: We must check the IP header checksum even if the caller does
+ * not want us to do so because we cannot do any further processing of
+ * the packet without a valid IP checksum.
+ */
+
+ if (IpHeaderChecksum != 0xFFFF) {
+ pAc->Csum.ProtoStats[SKCS_PROTO_STATS_IP].RxErrCts++;
+ return (SKCS_STATUS_IP_CSUM_ERROR);
+ }
+
+ /* Get the next level protocol identifier. */
+
+ NextLevelProtocol =
+ *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
+
+ /*
+ * Check if this is a TCP or UDP frame and if we should calculate the
+ * TCP/UDP pseudo header checksum.
+ *
+ * Also clear all protocol bit flags of protocols not present in the
+ * frame.
+ */
+
+ if ((pAc->Csum.ReceiveFlags & SKCS_PROTO_TCP) != 0 &&
+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
+ /* TCP/IP frame. */
+ NextLevelProtoStats =
+ &pAc->Csum.ProtoStats[SKCS_PROTO_STATS_TCP];
+ }
+ else if ((pAc->Csum.ReceiveFlags & SKCS_PROTO_UDP) != 0 &&
+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
+ /* UDP/IP frame. */
+ NextLevelProtoStats =
+ &pAc->Csum.ProtoStats[SKCS_PROTO_STATS_UDP];
+ }
+ else {
+ /*
+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
+ * specified.
+ */
+ return (SKCS_STATUS_IP_CSUM_OK);
+ }
+
+ /* Check if this is an IP fragment. */
+
+ /*
+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
+ * and the "More Fragments" are zero, it is *not* a fragment. We can
+ * easily check both at the same time since they are in the same 16-bit
+ * word.
+ */
+
+ if ((*(SK_U16 *)
+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
+ /* IP fragment; ignore all other protocols. */
+ NextLevelProtoStats->RxUnableCts++;
+ return (SKCS_STATUS_IP_FRAGMENT);
+ }
+
+ /*
+ * Calculate the TCP/UDP checksum.
+ */
+
+ /* Get total length of IP header and data. */
+
+ IpDataLength =
+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
+
+ /* Get length of IP data portion. */
+
+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
+
+ NextLevelProtocolChecksum =
+
+ /* Calculate the pseudo header checksum. */
+
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
+ (unsigned long) (NextLevelProtocol << 8) +
+ (unsigned long) SKCS_HTON16(IpDataLength) +
+
+ /* Add the TCP/UDP header checksum. */
+
+ (unsigned long) IpDataChecksum;
+
+ /* Add-in any carries. */
+
+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
+
+ /* Add-in any new carry. */
+
+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
+
+ /* Check if the TCP/UDP checksum is ok. */
+
+ if ((unsigned) NextLevelProtocolChecksum == 0xFFFF) {
+
+ /* TCP/UDP checksum ok. */
+
+ NextLevelProtoStats->RxOkCts++;
+
+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
+ SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
+ }
+
+ /* TCP/UDP checksum error. */
+
+ NextLevelProtoStats->RxErrCts++;
+
+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
+ SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
+}
+
+/******************************************************************************
+ *
+ * SkCsSetReceiveFlags - set checksum receive flags
+ *
+ * Description:
+ * Use this function to set the various receive flags. According to the
+ * protocol flags set by the caller, the start offsets within received
+ * packets of the two hardware checksums are returned. These offsets must
+ * be stored in all receive descriptors.
+ *
+ * Arguments:
+ * pAc - Pointer to adapter context struct.
+ *
+ * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
+ * for which the caller wants checksum information on received frames.
+ *
+ * pChecksum1Offset - The start offset of the first receive descriptor
+ * hardware checksum to be calculated for received frames is returned
+ * here.
+ *
+ * pChecksum2Offset - The start offset of the second receive descriptor
+ * hardware checksum to be calculated for received frames is returned
+ * here.
+ *
+ * Returns: N/A
+ * Returns the two hardware checksum start offsets.
+ */
+void SkCsSetReceiveFlags(
+SK_AC *pAc, /* Adapter context struct. */
+unsigned ReceiveFlags, /* New receive flags. */
+unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */
+unsigned *pChecksum2Offset) /* Offset for hardware checksum 2. */
+{
+ /* Save the receive flags. */
+
+ pAc->Csum.ReceiveFlags = ReceiveFlags;
+
+ /* First checksum start offset is the IP header. */
+ *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
+
+ /*
+ * Second checksum start offset is the IP data. Note that this may vary
+ * if there are any IP header options in the actual packet.
+ */
+ *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
+}
+
+#ifndef SkCsCalculateChecksum
+/******************************************************************************
+ *
+ * SkCsCalculateChecksum - calculate checksum for specified data
+ *
+ * Description:
+ * Calculate and return the 16-bit Internet Checksum for the specified
+ * data.
+ *
+ * Arguments:
+ * pData - Pointer to data for which the checksum shall be calculated.
+ * Note: The pointer should be aligned on a 16-bit boundary.
+ *
+ * Length - Length in bytes of data to checksum.
+ *
+ * Returns:
+ * The 16-bit Internet Checksum for the specified data.
+ *
+ * Note: The checksum is calculated in the machine's natural byte order,
+ * i.e. little vs. big endian. Thus, the resulting checksum is different
+ * for the same input data on little and big endian machines.
+ *
+ * However, when written back to the network packet, the byte order is
+ * always in correct network order.
+ */
+unsigned SkCsCalculateChecksum(
+void *pData, /* Data to checksum. */
+unsigned Length) /* Length of data. */
+{
+ SK_U16 *pU16; /* Pointer to the data as 16-bit words. */
+ unsigned long Checksum; /* Checksum; must be at least 32 bits. */
+
+ /* Sum up all 16-bit words. */
+
+ pU16 = (SK_U16 *) pData;
+ for (Checksum = 0; Length > 1; Length -= 2) {
+ Checksum += *pU16++;
+ }
+
+ /* If this is an odd number of bytes, add-in the last byte. */
+
+ if (Length > 0) {
+#ifdef SK_BIG_ENDIAN
+ /* Add the last byte as the high byte. */
+ Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
+#else /* !SK_BIG_ENDIAN */
+ /* Add the last byte as the low byte. */
+ Checksum += *(SK_U8 *) pU16;
+#endif /* !SK_BIG_ENDIAN */
+ }
+
+ /* Add-in any carries. */
+
+ SKCS_OC_ADD(Checksum, Checksum, 0);
+
+ /* Add-in any new carry. */
+
+ SKCS_OC_ADD(Checksum, Checksum, 0);
+
+ /* Note: All bits beyond the 16-bit limit are now zero. */
+
+ return ((unsigned) Checksum);
+}
+#endif /* SkCsCalculateChecksum */
+
+/******************************************************************************
+ *
+ * SkCsEvent - the CSUM event dispatcher
+ *
+ * Description:
+ * This is the event handler for the CSUM module.
+ *
+ * Arguments:
+ * pAc - Pointer to adapter context.
+ *
+ * Ioc - I/O context.
+ *
+ * Event - Event id.
+ *
+ * Param - Event dependent parameter.
+ *
+ * Returns:
+ * The 16-bit Internet Checksum for the specified data.
+ *
+ * Note: The checksum is calculated in the machine's natural byte order,
+ * i.e. little vs. big endian. Thus, the resulting checksum is different
+ * for the same input data on little and big endian machines.
+ *
+ * However, when written back to the network packet, the byte order is
+ * always in correct network order.
+ */
+int SkCsEvent(
+SK_AC *pAc, /* Pointer to adapter context. */
+SK_IOC Ioc, /* I/O context. */
+SK_U32 Event, /* Event id. */
+SK_EVPARA Param) /* Event dependent parameter. */
+{
+ int ProtoIndex;
+
+ switch (Event) {
+ /*
+ * Clear protocol statistics.
+ *
+ * Param - Protocol index, or -1 for all protocols.
+ */
+ case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
+
+ ProtoIndex = (int) Param.Para32[0];
+ if (ProtoIndex < 0) { /* Clear for all protocols. */
+ memset(&pAc->Csum.ProtoStats[0], 0,
+ sizeof(pAc->Csum.ProtoStats));
+ }
+ else { /* Clear for individual protocol. */
+ memset(&pAc->Csum.ProtoStats[ProtoIndex], 0,
+ sizeof(pAc->Csum.ProtoStats[ProtoIndex]));
+ }
+ break;
+ default:
+ break;
+ }
+ return (0); /* Success. */
+}
+
+#endif /* SK_USE_CSUM */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skge.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.25 $
+ * Date: $Date: 1999/10/07 14:47:52 $
+ * Purpose: The main driver source module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * Driver for SysKonnect Gigabit Ethernet Server Adapters:
+ *
+ * SK-9841 (single link 1000Base-LX)
+ * SK-9842 (dual link 1000Base-LX)
+ * SK-9843 (single link 1000Base-SX)
+ * SK-9844 (dual link 1000Base-SX)
+ * SK-9821 (single link 1000Base-T)
+ * SK-9822 (dual link 1000Base-T)
+ *
+ * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
+ * SysKonnects GEnesis Solaris driver
+ * Author: Christoph Goos (cgoos@syskonnect.de)
+ *
+ * Address all question to: linux@syskonnect.de
+ *
+ * The technical manual for the adapters is available from SysKonnect's
+ * web pages: www.syskonnect.com
+ * Goto "Support" and search Knowledge Base for "manual".
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skge.c,v $
+ * Revision 1.25 1999/10/07 14:47:52 cgoos
+ * Changed 984x to 98xx.
+ *
+ * Revision 1.24 1999/09/30 07:21:01 cgoos
+ * Removed SK_RLMT_SLOW_LOOKAHEAD option.
+ * Giving spanning tree packets also to OS now.
+ *
+ * Revision 1.23 1999/09/29 07:36:50 cgoos
+ * Changed assignment for IsBc/IsMc.
+ *
+ * Revision 1.22 1999/09/28 12:57:09 cgoos
+ * Added CheckQueue also to Single-Port-ISR.
+ *
+ * Revision 1.21 1999/09/28 12:42:41 cgoos
+ * Changed parameter strings for RlmtMode.
+ *
+ * Revision 1.20 1999/09/28 12:37:57 cgoos
+ * Added CheckQueue for fast delivery of RLMT frames.
+ *
+ * Revision 1.19 1999/09/16 07:57:25 cgoos
+ * Copperfield changes.
+ *
+ * Revision 1.18 1999/09/03 13:06:30 cgoos
+ * Fixed RlmtMode=CheckSeg bug: wrong DEV_KFREE_SKB in RLMT_SEND caused
+ * double allocated skb's.
+ * FrameStat in ReceiveIrq was accessed via wrong Rxd.
+ * Queue size for async. standby Tx queue was zero.
+ * FillRxLimit of 0 could cause problems with ReQueue, changed to 1.
+ * Removed debug output of checksum statistic.
+ *
+ * Revision 1.17 1999/08/11 13:55:27 cgoos
+ * Transmit descriptor polling was not reenabled after SkGePortInit.
+ *
+ * Revision 1.16 1999/07/27 15:17:29 cgoos
+ * Added some "\n" in output strings (removed while debuging...).
+ *
+ * Revision 1.15 1999/07/23 12:09:30 cgoos
+ * Performance optimization, rx checksumming, large frame support.
+ *
+ * Revision 1.14 1999/07/14 11:26:27 cgoos
+ * Removed Link LED settings (now in RLMT).
+ * Added status output at NET UP.
+ * Fixed SMP problems with Tx and SWITCH running in parallel.
+ * Fixed return code problem at RLMT_SEND event.
+ *
+ * Revision 1.13 1999/04/07 10:11:42 cgoos
+ * Fixed Single Port problems.
+ * Fixed Multi-Adapter problems.
+ * Always display startup string.
+ *
+ * Revision 1.12 1999/03/29 12:26:37 cgoos
+ * Reversed locking to fine granularity.
+ * Fixed skb double alloc problem (caused by incorrect xmit return code).
+ * Enhanced function descriptions.
+ *
+ * Revision 1.11 1999/03/15 13:10:51 cgoos
+ * Changed device identifier in output string to ethX.
+ *
+ * Revision 1.10 1999/03/15 12:12:34 cgoos
+ * Changed copyright notice.
+ *
+ * Revision 1.9 1999/03/15 12:10:17 cgoos
+ * Changed locking to one driver lock.
+ * Added check of SK_AC-size (for consistency with library).
+ *
+ * Revision 1.8 1999/03/08 11:44:02 cgoos
+ * Fixed missing dev->tbusy in SkGeXmit.
+ * Changed large frame (jumbo) buffer number.
+ * Added copying of short frames.
+ *
+ * Revision 1.7 1999/03/04 13:26:57 cgoos
+ * Fixed spinlock calls for SMP.
+ *
+ * Revision 1.6 1999/03/02 09:53:51 cgoos
+ * Added descriptor revertion for big endian machines.
+ *
+ * Revision 1.5 1999/03/01 08:50:59 cgoos
+ * Fixed SkGeChangeMtu.
+ * Fixed pci config space accesses.
+ *
+ * Revision 1.4 1999/02/18 15:48:44 cgoos
+ * Corrected some printk's.
+ *
+ * Revision 1.3 1999/02/18 12:45:55 cgoos
+ * Changed SK_MAX_CARD_PARAM to default 16
+ *
+ * Revision 1.2 1999/02/18 10:55:32 cgoos
+ * Removed SkGeDrvTimeStamp function.
+ * Printing "ethX:" before adapter type at adapter init.
+ *
+ *
+ * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and
+ * SysKonnects GEnesis Solaris driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Possible compiler options (#define xxx / -Dxxx):
+ *
+ * debugging can be enable by changing SK_DEBUG_CHKMOD and
+ * SK_DEBUG_CHKCAT in makefile (described there).
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the main module of the Linux GE driver.
+ *
+ * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
+ * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
+ * Those are used for drivers on multiple OS', so some thing may seem
+ * unnecessary complicated on Linux. Please do not try to 'clean up'
+ * them without VERY good reasons, because this will make it more
+ * difficult to keep the Linux driver in synchronisation with the
+ * other versions.
+ *
+ * Include file hierarchy:
+ *
+ * <linux/module.h>
+ *
+ * "h/skdrv1st.h"
+ * <linux/version.h>
+ * <linux/types.h>
+ * <linux/kernel.h>
+ * <linux/string.h>
+ * <linux/errno.h>
+ * <linux/ioport.h>
+ * <linux/malloc.h>
+ * <linux/interrupt.h>
+ * <linux/pci.h>
+ * <asm/byteorder.h>
+ * <asm/bitops.h>
+ * <asm/io.h>
+ * <linux/netdevice.h>
+ * <linux/etherdevice.h>
+ * <linux/skbuff.h>
+ * those three depending on kernel version used:
+ * <linux/bios32.h>
+ * <linux/init.h>
+ * <asm/uaccess.h>
+ * <net/checksum.h>
+ *
+ * "h/skerror.h"
+ * "h/skdebug.h"
+ * "h/sktypes.h"
+ * "h/lm80.h"
+ * "h/xmac_ii.h"
+ *
+ * "h/skdrv2nd.h"
+ * "h/skqueue.h"
+ * "h/skgehwt.h"
+ * "h/sktimer.h"
+ * "h/ski2c.h"
+ * "h/skgepnmi.h"
+ * "h/skvpd.h"
+ * "h/skgehw.h"
+ * "h/skgeinit.h"
+ * "h/skaddr.h"
+ * "h/skgesirq.h"
+ * "h/skcsum.h"
+ * "h/skrlmt.h"
+ *
+ ******************************************************************************/
+
+static const char SysKonnectFileId[] = "@(#)" __FILE__ " (C) SysKonnect.";
+static const char SysKonnectBuildNumber[] =
+ "@(#)SK-BUILD: 3.02 (19991111) PL: 01";
+
+#include <linux/module.h>
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* defines ******************************************************************/
+
+#define BOOT_STRING "sk98lin: Network Device Driver v3.02\n" \
+ "Copyright (C) 1999 SysKonnect"
+
+#define VER_STRING "3.02"
+
+
+/* for debuging on x86 only */
+/* #define BREAKPOINT() asm(" int $3"); */
+
+/* use of a transmit complete interrupt */
+#define USE_TX_COMPLETE
+
+/* use interrupt moderation (for tx complete only) */
+// #define USE_INT_MOD
+#define INTS_PER_SEC 1000
+
+/*
+ * threshold for copying small receive frames
+ * set to 0 to avoid copying, set to 9001 to copy all frames
+ */
+#define SK_COPY_THRESHOLD 200
+
+/* number of adapters that can be configured via command line params */
+#define SK_MAX_CARD_PARAM 16
+
+/*
+ * use those defines for a compile-in version of the driver instead
+ * of command line parameters
+ */
+// #define AUTO_NEG_A {"Sense", }
+// #define AUTO_NEG_B {"Sense", }
+// #define DUP_CAP_A {"Both", }
+// #define DUP_CAP_B {"Both", }
+// #define FLOW_CTRL_A {"SymOrRem", }
+// #define FLOW_CTRL_B {"SymOrRem", }
+// #define ROLE_A {"Auto", }
+// #define ROLE_B {"Auto", }
+// #define PREF_PORT {"A", }
+// #define RLMT_MODE {"CheckLink", }
+
+
+#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb);
+
+/* function prototypes ******************************************************/
+static void FreeResources(struct net_device *dev);
+int init_module(void);
+void cleanup_module(void);
+static int SkGeBoardInit(struct net_device *dev, SK_AC *pAC);
+static SK_BOOL BoardAllocMem(SK_AC *pAC);
+static void BoardFreeMem(SK_AC *pAC);
+static void BoardInitMem(SK_AC *pAC);
+static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**,
+ int*, SK_BOOL);
+
+static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs);
+static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs);
+static int SkGeOpen(struct net_device *dev);
+static int SkGeClose(struct net_device *dev);
+static int SkGeXmit(struct sk_buff *skb, struct net_device *dev);
+static int SkGeSetMacAddr(struct net_device *dev, void *p);
+static void SkGeSetRxMode(struct net_device *dev);
+static struct net_device_stats *SkGeStats(struct net_device *dev);
+static int SkGeIoctl(struct net_device *dev, struct ifreq *rq, int cmd);
+static void GetConfiguration(SK_AC*);
+static void ProductStr(SK_AC*);
+static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
+static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
+static void FillRxRing(SK_AC*, RX_PORT*);
+static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
+static void ReceiveIrq(SK_AC*, RX_PORT*);
+static void ClearAndStartRx(SK_AC*, int);
+static void ClearTxIrq(SK_AC*, int, int);
+static void ClearRxRing(SK_AC*, RX_PORT*);
+static void ClearTxRing(SK_AC*, TX_PORT*);
+static void SetQueueSizes(SK_AC *pAC);
+static int SkGeChangeMtu(struct net_device *dev, int new_mtu);
+static void PortReInitBmu(SK_AC*, int);
+static int SkGeIocMib(SK_AC*, unsigned int, int);
+#ifdef DEBUG
+static void DumpMsg(struct sk_buff*, char*);
+static void DumpData(char*, int);
+static void DumpLong(char*, int);
+#endif
+
+
+/* global variables *********************************************************/
+static const char *BootString = BOOT_STRING;
+static struct net_device *root_dev = NULL;
+static int probed __initdata = 0;
+
+/* local variables **********************************************************/
+static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
+static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
+
+/*****************************************************************************
+ *
+ * skge_probe - find all SK-98xx adapters
+ *
+ * Description:
+ * This function scans the PCI bus for SK-98xx adapters. Resources for
+ * each adapter are allocated and the adapter is brought into Init 1
+ * state.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+int __init skge_probe (struct net_device *dev)
+{
+int boards_found = 0;
+int version_disp = 0;
+SK_AC *pAC;
+struct pci_dev *pdev = NULL;
+unsigned int base_address;
+
+ if (probed)
+ return -ENODEV;
+ probed++;
+
+ /* display driver info */
+ if (!version_disp)
+ {
+ /* set display flag to TRUE so that */
+ /* we only display this string ONCE */
+ version_disp = 1;
+ printk("%s\n", BootString);
+ }
+
+ if (!pci_present()) /* is PCI support present? */
+ return -ENODEV;
+
+ while((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pdev)))
+ {
+ dev = NULL;
+
+ if (pdev->vendor != PCI_VENDOR_ID_SYSKONNECT ||
+ pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) {
+ continue;
+ }
+ dev = init_etherdev(dev, sizeof(SK_AC));
+
+ if (dev == NULL){
+ printk(KERN_ERR "Unable to allocate etherdev "
+ "structure!\n");
+ break;
+ }
+
+ if (!dev->priv)
+ dev->priv = kmalloc(sizeof(SK_AC), GFP_KERNEL);
+ if (dev->priv == NULL){
+ printk(KERN_ERR "Unable to allocate adapter "
+ "structure!\n");
+ break;
+ }
+
+
+ memset(dev->priv, 0, sizeof(SK_AC));
+
+ pAC = dev->priv;
+ pAC->PciDev = *pdev;
+ pAC->PciDevId = pdev->device;
+ pAC->dev = dev;
+ sprintf(pAC->Name, "SysKonnect SK-98xx");
+ pAC->CheckQueue = SK_FALSE;
+
+ dev->irq = pdev->irq;
+
+ dev->open = &SkGeOpen;
+ dev->stop = &SkGeClose;
+ dev->hard_start_xmit = &SkGeXmit;
+ dev->get_stats = &SkGeStats;
+ dev->set_multicast_list = &SkGeSetRxMode;
+ dev->set_mac_address = &SkGeSetMacAddr;
+ dev->do_ioctl = &SkGeIoctl;
+ dev->change_mtu = &SkGeChangeMtu;
+
+ /*
+ * Dummy value.
+ */
+ dev->base_addr = 42;
+
+ pci_set_master(pdev);
+
+ base_address = pdev->resource[0].start;
+
+#ifdef SK_BIG_ENDIAN
+ /*
+ * On big endian machines, we use the adapter's aibility of
+ * reading the descriptors as big endian.
+ */
+ {
+ SK_U32 our2;
+ SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2);
+ our2 |= PCI_REV_DESC;
+ SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2);
+ }
+#endif /* BIG ENDIAN */
+
+ /*
+ * Remap the regs into kernel space.
+ */
+
+
+ pAC->IoBase = (char*)ioremap(base_address, 0x4000);
+ if (!pAC->IoBase){
+ printk(KERN_ERR "%s: Unable to map I/O register, "
+ "SK 98xx No. %i will be disabled.\n",
+ dev->name, boards_found);
+ break;
+ }
+ pAC->Index = boards_found;
+
+ if (SkGeBoardInit(dev, pAC)) {
+ FreeResources(dev);
+ continue;
+ }
+
+ memcpy((caddr_t) &dev->dev_addr,
+ (caddr_t) &pAC->Addr.CurrentMacAddress, 6);
+
+ boards_found++;
+
+ /*
+ * This is bollocks, but we need to tell the net-init
+ * code that it shall go for the next device.
+ */
+#ifndef MODULE
+ dev->base_addr = 0;
+#endif
+ }
+
+ /*
+ * If we're at this point we're going through skge_probe() for
+ * the first time. Return success (0) if we've initialized 1
+ * or more boards. Otherwise, return failure (-ENODEV).
+ */
+
+#ifdef MODULE
+ return boards_found;
+#else
+ if (boards_found > 0)
+ return 0;
+ else
+ return -ENODEV;
+#endif
+} /* skge_probe */
+
+
+/*****************************************************************************
+ *
+ * FreeResources - release resources allocated for adapter
+ *
+ * Description:
+ * This function releases the IRQ, unmaps the IO and
+ * frees the desriptor ring.
+ *
+ * Returns: N/A
+ *
+ */
+static void FreeResources(struct net_device *dev)
+{
+SK_U32 AllocFlag;
+SK_AC *pAC;
+
+ if (dev->priv) {
+ pAC = (SK_AC*) dev->priv;
+ AllocFlag = pAC->AllocFlag;
+ if (AllocFlag & SK_ALLOC_IRQ) {
+ free_irq(dev->irq, dev);
+ }
+ if (pAC->IoBase) {
+ iounmap(pAC->IoBase);
+ }
+ if (pAC->pDescrMem) {
+ BoardFreeMem(pAC);
+ }
+ }
+
+} /* FreeResources */
+
+
+#ifdef MODULE
+
+MODULE_AUTHOR("Christoph Goos <cgoos@syskonnect.de>");
+MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
+MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+/* not used, just there because every driver should have them: */
+MODULE_PARM(options, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
+MODULE_PARM(debug, "i");
+
+#endif // MODULE
+
+
+#ifdef AUTO_NEG_A
+static char *AutoNeg_A[SK_MAX_CARD_PARAM] = AUTO_NEG_A;
+#else
+static char *AutoNeg_A[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef DUP_CAP_A
+static char *DupCap_A[SK_MAX_CARD_PARAM] = DUP_CAP_A;
+#else
+static char *DupCap_A[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef FLOW_CTRL_A
+static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = FLOW_CTRL_A;
+#else
+static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef ROLE_A
+static char *Role_A[SK_MAX_CARD_PARAM] = ROLE_A;
+#else
+static char *Role_A[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef AUTO_NEG_B
+static char *AutoNeg_B[SK_MAX_CARD_PARAM] = AUTO_NEG_B;
+#else
+static char *AutoNeg_B[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef DUP_CAP_B
+static char *DupCap_B[SK_MAX_CARD_PARAM] = DUP_CAP_B;
+#else
+static char *DupCap_B[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef FLOW_CTRL_B
+static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = FLOW_CTRL_B;
+#else
+static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef ROLE_B
+static char *Role_B[SK_MAX_CARD_PARAM] = ROLE_B;
+#else
+static char *Role_B[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef PREF_PORT
+static char *PrefPort[SK_MAX_CARD_PARAM] = PREF_PORT;
+#else
+static char *PrefPort[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+#ifdef RLMT_MODE
+static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE;
+#else
+static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", };
+#endif
+
+
+#ifdef MODULE
+
+static int debug = 0; /* not used */
+static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */
+
+
+/*****************************************************************************
+ *
+ * init_module - module initialization function
+ *
+ * Description:
+ * Very simple, only call skge_probe and return approriate result.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+int init_module(void)
+{
+int cards;
+
+ root_dev = NULL;
+
+ /* just to avoid warnings ... */
+ debug = 0;
+ options[0] = 0;
+
+ cards = skge_probe(NULL);
+ if (cards == 0) {
+ printk("No adapter found\n");
+ }
+ return cards ? 0 : -ENODEV;
+} /* init_module */
+
+
+/*****************************************************************************
+ *
+ * cleanup_module - module unload function
+ *
+ * Description:
+ * Disable adapter if it is still running, free resources,
+ * free device struct.
+ *
+ * Returns: N/A
+ */
+void cleanup_module(void)
+{
+SK_AC *pAC;
+struct net_device *next;
+unsigned long Flags;
+SK_EVPARA EvPara;
+
+ while (root_dev) {
+ pAC = (SK_AC*)root_dev->priv;
+ next = pAC->Next;
+
+ root_dev->tbusy = 1;
+ SkGeYellowLED(pAC, pAC->IoBase, 0);
+
+ if(pAC->BoardLevel == 2) {
+ /* board is still alive */
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
+ SkEventDispatcher(pAC, pAC->IoBase);
+ /* disable interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+ SkGeDeInit(pAC, pAC->IoBase);
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ pAC->BoardLevel = 0;
+ /* We do NOT check here, if IRQ was pending, of course*/
+ }
+
+ if(pAC->BoardLevel == 1) {
+ /* board is still alive */
+ SkGeDeInit(pAC, pAC->IoBase);
+ pAC->BoardLevel = 0;
+ }
+
+ FreeResources(root_dev);
+
+ root_dev->get_stats = NULL;
+ /*
+ * otherwise unregister_netdev calls get_stats with
+ * invalid IO ... :-(
+ */
+ unregister_netdev(root_dev);
+ kfree(root_dev);
+
+ root_dev = next;
+ }
+}
+#endif /* cleanup_module */
+
+
+/*****************************************************************************
+ *
+ * SkGeBoardInit - do level 0 and 1 initialization
+ *
+ * Description:
+ * This function prepares the board hardware for running. The desriptor
+ * ring is set up, the IRQ is allocated and the configuration settings
+ * are examined.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+static int __init SkGeBoardInit(struct net_device *dev, SK_AC *pAC)
+{
+short i;
+unsigned long Flags;
+char *DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */
+char *VerStr = VER_STRING;
+int Ret; /* return code of request_irq */
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("IoBase: %08lX\n", (unsigned long)pAC->IoBase));
+ for (i=0; i<SK_MAX_MACS; i++) {
+ pAC->TxPort[i][0].HwAddr = pAC->IoBase + TxQueueAddr[i][0];
+ pAC->TxPort[i][0].PortIndex = i;
+ pAC->RxPort[i].HwAddr = pAC->IoBase + RxQueueAddr[i];
+ pAC->RxPort[i].PortIndex = i;
+ }
+
+ /* Initialize the mutexes */
+
+ for (i=0; i<SK_MAX_MACS; i++) {
+ spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
+ spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
+ }
+ spin_lock_init(&pAC->SlowPathLock);
+
+ /* level 0 init common modules here */
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ /* Does a RESET on board ...*/
+ if (SkGeInit(pAC, pAC->IoBase, 0) != 0) {
+ printk("HWInit (0) failed.\n");
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ return(-EAGAIN);
+ }
+ SkI2cInit( pAC, pAC->IoBase, 0);
+ SkEventInit(pAC, pAC->IoBase, 0);
+ SkPnmiInit( pAC, pAC->IoBase, 0);
+ SkAddrInit( pAC, pAC->IoBase, 0);
+ SkRlmtInit( pAC, pAC->IoBase, 0);
+ SkTimerInit(pAC, pAC->IoBase, 0);
+
+ pAC->BoardLevel = 0;
+ pAC->RxBufSize = ETH_BUF_SIZE;
+
+ SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
+ SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
+
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ GetConfiguration(pAC);
+
+ /* level 1 init common modules here (HW init) */
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ if (SkGeInit(pAC, pAC->IoBase, 1) != 0) {
+ printk("HWInit (1) failed.\n");
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ return(-EAGAIN);
+ }
+ SkI2cInit( pAC, pAC->IoBase, 1);
+ SkEventInit(pAC, pAC->IoBase, 1);
+ SkPnmiInit( pAC, pAC->IoBase, 1);
+ SkAddrInit( pAC, pAC->IoBase, 1);
+ SkRlmtInit( pAC, pAC->IoBase, 1);
+ SkTimerInit(pAC, pAC->IoBase, 1);
+
+ pAC->BoardLevel = 1;
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ if (pAC->GIni.GIMacsFound == 2) {
+ Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev);
+ } else if (pAC->GIni.GIMacsFound == 1) {
+ Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ,
+ pAC->Name, dev);
+ } else {
+ printk(KERN_WARNING "%s: illegal number of ports: %d\n",
+ dev->name, pAC->GIni.GIMacsFound);
+ return -EAGAIN;
+ }
+ if (Ret) {
+ printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
+ dev->name, dev->irq);
+ return -EAGAIN;
+ }
+ pAC->AllocFlag |= SK_ALLOC_IRQ;
+
+ /* Alloc memory for this board (Mem for RxD/TxD) : */
+ if(!BoardAllocMem(pAC)) {
+ printk("No memory for descriptor rings\n");
+ return(-EAGAIN);
+ }
+
+ SkCsSetReceiveFlags(pAC,
+ SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
+ &pAC->CsOfs1, &pAC->CsOfs2);
+ pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
+
+ BoardInitMem(pAC);
+
+ SetQueueSizes(pAC);
+
+ /* Print adapter specific string from vpd */
+ ProductStr(pAC);
+ printk("%s: %s\n", dev->name, pAC->DeviceStr);
+
+ SkGeYellowLED(pAC, pAC->IoBase, 1);
+
+ /*
+ * Register the device here
+ */
+ pAC->Next = root_dev;
+ root_dev = dev;
+
+ return (0);
+} /* SkGeBoardInit */
+
+
+/*****************************************************************************
+ *
+ * BoardAllocMem - allocate the memory for the descriptor rings
+ *
+ * Description:
+ * This function allocates the memory for all descriptor rings.
+ * Each ring is aligned for the desriptor alignment and no ring
+ * has a 4 GByte boundary in it (because the upper 32 bit must
+ * be constant for all descriptiors in one rings).
+ *
+ * Returns:
+ * SK_TRUE, if all memory could be allocated
+ * SK_FALSE, if not
+ */
+static SK_BOOL BoardAllocMem(
+SK_AC *pAC)
+{
+caddr_t pDescrMem; /* pointer to descriptor memory area */
+size_t AllocLength; /* length of complete descriptor area */
+int i; /* loop counter */
+unsigned long BusAddr;
+
+
+ /* rings plus one for alignment (do not cross 4 GB boundary) */
+ /* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */
+#if (BITS_PER_LONG == 32)
+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
+#else
+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
+ + RX_RING_SIZE + 8;
+#endif
+ pDescrMem = kmalloc(AllocLength, GFP_KERNEL);
+ if (pDescrMem == NULL) {
+ return (SK_FALSE);
+ }
+ pAC->pDescrMem = pDescrMem;
+ memset(pDescrMem, 0, AllocLength);
+ /* Descriptors need 8 byte alignment */
+ BusAddr = virt_to_bus(pDescrMem);
+ if (BusAddr & (DESCR_ALIGN-1)) {
+ pDescrMem += DESCR_ALIGN - (BusAddr & (DESCR_ALIGN-1));
+ }
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ if ((virt_to_bus(pDescrMem) & ~0xFFFFFFFFULL) !=
+ (virt_to_bus(pDescrMem+TX_RING_SIZE) & ~0xFFFFFFFFULL)) {
+ pDescrMem += TX_RING_SIZE;
+ }
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+ ("TX%d/A: pDescrMem: %lX, PhysDescrMem: %lX\n",
+ i, (unsigned long) pDescrMem,
+ (unsigned long)virt_to_bus(pDescrMem)));
+ pAC->TxPort[i][0].pTxDescrRing = pDescrMem;
+ pAC->TxPort[i][0].VTxDescrRing = virt_to_bus(pDescrMem);
+ pDescrMem += TX_RING_SIZE;
+
+ if ((virt_to_bus(pDescrMem) & ~0xFFFFFFFFULL) !=
+ (virt_to_bus(pDescrMem+RX_RING_SIZE) & ~0xFFFFFFFFULL)) {
+ pDescrMem += RX_RING_SIZE;
+ }
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+ ("RX%d: pDescrMem: %lX, PhysDescrMem: %lX\n",
+ i, (unsigned long) pDescrMem,
+ (unsigned long)(virt_to_bus(pDescrMem))));
+ pAC->RxPort[i].pRxDescrRing = pDescrMem;
+ pAC->RxPort[i].VRxDescrRing = virt_to_bus(pDescrMem);
+ pDescrMem += RX_RING_SIZE;
+ } /* for */
+
+ return (SK_TRUE);
+} /* BoardAllocMem */
+
+
+/****************************************************************************
+ *
+ * BoardFreeMem - reverse of BoardAllocMem
+ *
+ * Description:
+ * Free all memory allocated in BoardAllocMem: adapter context,
+ * descriptor rings, locks.
+ *
+ * Returns: N/A
+ */
+static void BoardFreeMem(
+SK_AC *pAC)
+{
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("BoardFreeMem\n"));
+ kfree(pAC->pDescrMem);
+} /* BoardFreeMem */
+
+
+/*****************************************************************************
+ *
+ * BoardInitMem - initiate the descriptor rings
+ *
+ * Description:
+ * This function sets the descriptor rings up in memory.
+ * The adapter is initialized with the descriptor start addresses.
+ *
+ * Returns: N/A
+ */
+static void BoardInitMem(
+SK_AC *pAC) /* pointer to adapter context */
+{
+int i; /* loop counter */
+int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/
+int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("BoardInitMem\n"));
+
+ RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
+ pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
+ TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
+ pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
+
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ SetupRing(
+ pAC,
+ pAC->TxPort[i][0].pTxDescrRing,
+ pAC->TxPort[i][0].VTxDescrRing,
+ (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
+ (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
+ (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
+ &pAC->TxPort[i][0].TxdRingFree,
+ SK_TRUE);
+ SetupRing(
+ pAC,
+ pAC->RxPort[i].pRxDescrRing,
+ pAC->RxPort[i].VRxDescrRing,
+ &pAC->RxPort[i].pRxdRingHead,
+ &pAC->RxPort[i].pRxdRingTail,
+ &pAC->RxPort[i].pRxdRingPrev,
+ &pAC->RxPort[i].RxdRingFree,
+ SK_FALSE);
+ }
+} /* BoardInitMem */
+
+
+/*****************************************************************************
+ *
+ * SetupRing - create one descriptor ring
+ *
+ * Description:
+ * This function creates one descriptor ring in the given memory area.
+ * The head, tail and number of free descriptors in the ring are set.
+ *
+ * Returns:
+ * none
+ */
+static void SetupRing(
+SK_AC *pAC,
+void *pMemArea, /* a pointer to the memory area for the ring */
+uintptr_t VMemArea, /* the virtual bus address of the memory area */
+RXD **ppRingHead, /* address where the head should be written */
+RXD **ppRingTail, /* address where the tail should be written */
+RXD **ppRingPrev, /* address where the tail should be written */
+int *pRingFree, /* address where the # of free descr. goes */
+SK_BOOL IsTx) /* flag: is this a tx ring */
+{
+int i; /* loop counter */
+int DescrSize; /* the size of a descriptor rounded up to alignment*/
+int DescrNum; /* number of descriptors per ring */
+RXD *pDescr; /* pointer to a descriptor (receive or transmit) */
+RXD *pNextDescr; /* pointer to the next descriptor */
+RXD *pPrevDescr; /* pointer to the previous descriptor */
+uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */
+
+ if (IsTx == SK_TRUE) {
+ DescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) *
+ DESCR_ALIGN;
+ DescrNum = TX_RING_SIZE / DescrSize;
+ }
+ else {
+ DescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) *
+ DESCR_ALIGN;
+ DescrNum = RX_RING_SIZE / DescrSize;
+ }
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+ ("Descriptor size: %d Descriptor Number: %d\n",
+ DescrSize,DescrNum));
+
+ pDescr = (RXD*) pMemArea;
+ pPrevDescr = NULL;
+ pNextDescr = (RXD*) (((char*)pDescr) + DescrSize);
+ VNextDescr = VMemArea + DescrSize;
+ for(i=0; i<DescrNum; i++) {
+ /* set the pointers right */
+ pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
+ pDescr->pNextRxd = pNextDescr;
+ pDescr->TcpSumStarts = pAC->CsOfs;
+ /* advance on step */
+ pPrevDescr = pDescr;
+ pDescr = pNextDescr;
+ pNextDescr = (RXD*) (((char*)pDescr) + DescrSize);
+ VNextDescr += DescrSize;
+ }
+ pPrevDescr->pNextRxd = (RXD*) pMemArea;
+ pPrevDescr->VNextRxd = VMemArea;
+ pDescr = (RXD*) pMemArea;
+ *ppRingHead = (RXD*) pMemArea;
+ *ppRingTail = *ppRingHead;
+ *ppRingPrev = pPrevDescr;
+ *pRingFree = DescrNum;
+} /* SetupRing */
+
+
+/*****************************************************************************
+ *
+ * PortReInitBmu - re-initiate the descriptor rings for one port
+ *
+ * Description:
+ * This function reinitializes the descriptor rings of one port
+ * in memory. The port must be stopped before.
+ * The HW is initialized with the descriptor start addresses.
+ *
+ * Returns:
+ * none
+ */
+static void PortReInitBmu(
+SK_AC *pAC, /* pointer to adapter context */
+int PortIndex) /* index of the port for which to re-init */
+{
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("PortReInitBmu "));
+
+ /* set address of first descriptor of ring in BMU */
+ SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+
+ TX_Q_CUR_DESCR_LOW,
+ (uint32_t)(((caddr_t)
+ (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) -
+ pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing +
+ pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) &
+ 0xFFFFFFFF));
+ SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+
+ TX_Q_DESCR_HIGH,
+ (uint32_t)(((caddr_t)
+ (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) -
+ pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing +
+ pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) >> 32));
+ SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CUR_DESCR_LOW,
+ (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) -
+ pAC->RxPort[PortIndex].pRxDescrRing +
+ pAC->RxPort[PortIndex].VRxDescrRing) & 0xFFFFFFFF));
+ SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_DESCR_HIGH,
+ (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) -
+ pAC->RxPort[PortIndex].pRxDescrRing +
+ pAC->RxPort[PortIndex].VRxDescrRing) >> 32));
+} /* PortReInitBmu */
+
+
+/****************************************************************************
+ *
+ * SkGeIsr - handle adapter interrupts
+ *
+ * Description:
+ * The interrupt routine is called when the network adapter
+ * generates an interrupt. It may also be called if another device
+ * shares this interrupt vector with the driver.
+ *
+ * Returns: N/A
+ *
+ */
+static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs)
+{
+struct net_device *dev = (struct net_device *)dev_id;
+SK_AC *pAC;
+SK_U32 IntSrc; /* interrupts source register contents */
+
+ pAC = (SK_AC*) dev->priv;
+
+ /*
+ * Check and process if its our interrupt
+ */
+ SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
+ if (IntSrc == 0) {
+ return;
+ }
+
+ while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
+#if 0 /* software irq currently not used */
+ if (IntSrc & IRQ_SW) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("Software IRQ\n"));
+ }
+#endif
+ if (IntSrc & IRQ_EOF_RX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF RX1 IRQ\n"));
+ ReceiveIrq(pAC, &pAC->RxPort[0]);
+ SK_PNMI_CNT_RX_INTR(pAC);
+ }
+ if (IntSrc & IRQ_EOF_RX2) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF RX2 IRQ\n"));
+ ReceiveIrq(pAC, &pAC->RxPort[1]);
+ SK_PNMI_CNT_RX_INTR(pAC);
+ }
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ if (IntSrc & IRQ_EOF_AS_TX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF AS TX1 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ }
+ if (IntSrc & IRQ_EOF_AS_TX2) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF AS TX2 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
+ }
+#if 0 /* only if sync. queues used */
+ if (IntSrc & IRQ_EOF_SY_TX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF SY TX1 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
+ }
+ if (IntSrc & IRQ_EOF_SY_TX2) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF SY TX2 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
+ ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
+ }
+#endif /* 0 */
+#endif /* USE_TX_COMPLETE */
+
+ /* do all IO at once */
+ if (IntSrc & IRQ_EOF_RX1)
+ ClearAndStartRx(pAC, 0);
+ if (IntSrc & IRQ_EOF_RX2)
+ ClearAndStartRx(pAC, 1);
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ if (IntSrc & IRQ_EOF_AS_TX1)
+ ClearTxIrq(pAC, 0, TX_PRIO_LOW);
+ if (IntSrc & IRQ_EOF_AS_TX2)
+ ClearTxIrq(pAC, 1, TX_PRIO_LOW);
+#endif
+ SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
+ } /* while (IntSrc & IRQ_MASK != 0) */
+
+ if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+ ("SPECIAL IRQ\n"));
+ pAC->CheckQueue = SK_FALSE;
+ spin_lock(&pAC->SlowPathLock);
+ if (IntSrc & SPECIAL_IRQS)
+ SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
+ SkEventDispatcher(pAC, pAC->IoBase);
+ spin_unlock(&pAC->SlowPathLock);
+ }
+ /*
+ * do it all again is case we cleared an interrupt that
+ * came in after handling the ring (OUTs may be delayed
+ * in hardware buffers, but are through after IN)
+ */
+ ReceiveIrq(pAC, &pAC->RxPort[pAC->ActivePort]);
+// ReceiveIrq(pAC, &pAC->RxPort[1]);
+
+#if 0
+// #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+
+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
+
+#if 0 /* only if sync. queues used */
+ spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+
+ spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
+#endif /* 0 */
+#endif /* USE_TX_COMPLETE */
+
+ /* IRQ is processed - Enable IRQs again*/
+ SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK);
+
+ return;
+} /* SkGeIsr */
+
+
+/****************************************************************************
+ *
+ * SkGeIsrOnePort - handle adapter interrupts for single port adapter
+ *
+ * Description:
+ * The interrupt routine is called when the network adapter
+ * generates an interrupt. It may also be called if another device
+ * shares this interrupt vector with the driver.
+ * This is the same as above, but handles only one port.
+ *
+ * Returns: N/A
+ *
+ */
+static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs)
+{
+struct net_device *dev = (struct net_device *)dev_id;
+SK_AC *pAC;
+SK_U32 IntSrc; /* interrupts source register contents */
+
+ pAC = (SK_AC*) dev->priv;
+
+ /*
+ * Check and process if its our interrupt
+ */
+ SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
+ if (IntSrc == 0) {
+ return;
+ }
+
+ while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
+#if 0 /* software irq currently not used */
+ if (IntSrc & IRQ_SW) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("Software IRQ\n"));
+ }
+#endif
+ if (IntSrc & IRQ_EOF_RX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF RX1 IRQ\n"));
+ ReceiveIrq(pAC, &pAC->RxPort[0]);
+ SK_PNMI_CNT_RX_INTR(pAC);
+ }
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ if (IntSrc & IRQ_EOF_AS_TX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF AS TX1 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ }
+#if 0 /* only if sync. queues used */
+ if (IntSrc & IRQ_EOF_SY_TX1) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_INT_SRC,
+ ("EOF SY TX1 IRQ\n"));
+ SK_PNMI_CNT_TX_INTR(pAC);
+ spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
+ }
+#endif /* 0 */
+#endif /* USE_TX_COMPLETE */
+
+ /* do all IO at once */
+ if (IntSrc & IRQ_EOF_RX1)
+ ClearAndStartRx(pAC, 0);
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ if (IntSrc & IRQ_EOF_AS_TX1)
+ ClearTxIrq(pAC, 0, TX_PRIO_LOW);
+#endif
+ SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
+ } /* while (IntSrc & IRQ_MASK != 0) */
+
+ if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+ ("SPECIAL IRQ\n"));
+ pAC->CheckQueue = SK_FALSE;
+ spin_lock(&pAC->SlowPathLock);
+ if (IntSrc & SPECIAL_IRQS)
+ SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
+ SkEventDispatcher(pAC, pAC->IoBase);
+ spin_unlock(&pAC->SlowPathLock);
+ }
+ /*
+ * do it all again is case we cleared an interrupt that
+ * came in after handling the ring (OUTs may be delayed
+ * in hardware buffers, but are through after IN)
+ */
+ ReceiveIrq(pAC, &pAC->RxPort[0]);
+
+#if 0
+// #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+
+#if 0 /* only if sync. queues used */
+ spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+ FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
+ spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+
+#endif /* 0 */
+#endif /* USE_TX_COMPLETE */
+
+ /* IRQ is processed - Enable IRQs again*/
+ SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK);
+
+ return;
+} /* SkGeIsrOnePort */
+
+
+/****************************************************************************
+ *
+ * SkGeOpen - handle start of initialized adapter
+ *
+ * Description:
+ * This function starts the initialized adapter.
+ * The board level variable is set and the adapter is
+ * brought to full functionality.
+ * The device flags are set for operation.
+ * Do all necessary level 2 initialization, enable interrupts and
+ * give start command to RLMT.
+ *
+ * Returns:
+ * 0 on success
+ * != 0 on error
+ */
+static int SkGeOpen(
+struct net_device *dev)
+{
+SK_AC *pAC; /* pointer to adapter context struct */
+unsigned int Flags; /* for spin lock */
+int i;
+SK_EVPARA EvPara; /* an event parameter union */
+
+ pAC = (SK_AC*) dev->priv;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
+
+ if (pAC->BoardLevel == 0) {
+ /* level 1 init common modules here */
+ if (SkGeInit(pAC, pAC->IoBase, 1) != 0) {
+ printk("%s: HWInit(1) failed\n", pAC->dev->name);
+ return (-1);
+ }
+ SkI2cInit (pAC, pAC->IoBase, 1);
+ SkEventInit (pAC, pAC->IoBase, 1);
+ SkPnmiInit (pAC, pAC->IoBase, 1);
+ SkAddrInit (pAC, pAC->IoBase, 1);
+ SkRlmtInit (pAC, pAC->IoBase, 1);
+ SkTimerInit (pAC, pAC->IoBase, 1);
+ pAC->BoardLevel = 1;
+ }
+
+ /* level 2 init modules here */
+ SkGeInit (pAC, pAC->IoBase, 2);
+ SkI2cInit (pAC, pAC->IoBase, 2);
+ SkEventInit (pAC, pAC->IoBase, 2);
+ SkPnmiInit (pAC, pAC->IoBase, 2);
+ SkAddrInit (pAC, pAC->IoBase, 2);
+ SkRlmtInit (pAC, pAC->IoBase, 2);
+ SkTimerInit (pAC, pAC->IoBase, 2);
+ pAC->BoardLevel = 2;
+
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ // Enable transmit descriptor polling.
+ SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
+ FillRxRing(pAC, &pAC->RxPort[i]);
+ }
+ SkGeYellowLED(pAC, pAC->IoBase, 1);
+
+#ifdef USE_INT_MOD
+// moderate only TX complete interrupts (these are not time critical)
+#define IRQ_MOD_MASK (IRQ_EOF_AS_TX1 | IRQ_EOF_AS_TX2)
+ {
+ unsigned long ModBase;
+ ModBase = 53125000 / INTS_PER_SEC;
+ SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
+ SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK);
+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
+ }
+#endif
+
+ /* enable Interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK);
+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
+ if (pAC->RlmtMode != 0) {
+ EvPara.Para32[0] = pAC->RlmtMode;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
+ EvPara);
+ }
+ SkEventDispatcher(pAC, pAC->IoBase);
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ dev->tbusy = 0;
+ dev->interrupt = 0;
+ dev->start = 1;
+
+ MOD_INC_USE_COUNT;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeOpen suceeded\n"));
+
+ return (0);
+} /* SkGeOpen */
+
+
+/****************************************************************************
+ *
+ * SkGeClose - Stop initialized adapter
+ *
+ * Description:
+ * Close initialized adapter.
+ *
+ * Returns:
+ * 0 - on success
+ * error code - on error
+ */
+static int SkGeClose(
+struct net_device *dev)
+{
+SK_AC *pAC;
+unsigned int Flags; /* for spin lock */
+int i;
+SK_EVPARA EvPara;
+
+ dev->start = 0;
+ set_bit(0, (void*)&dev->tbusy);
+
+ pAC = (SK_AC*) dev->priv;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
+
+ /*
+ * Clear multicast table, promiscuous mode ....
+ */
+ SkAddrMcClear(pAC, pAC->IoBase, pAC->ActivePort, 0);
+ SkAddrPromiscuousChange(pAC, pAC->IoBase, pAC->ActivePort,
+ SK_PROM_MODE_NONE);
+
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ /* disable interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
+ SkEventDispatcher(pAC, pAC->IoBase);
+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+ /* stop the hardware */
+ SkGeDeInit(pAC, pAC->IoBase);
+ pAC->BoardLevel = 0;
+
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ /* clear all descriptor rings */
+ ReceiveIrq(pAC, &pAC->RxPort[i]);
+ ClearRxRing(pAC, &pAC->RxPort[i]);
+ ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
+ }
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeClose: done "));
+
+ MOD_DEC_USE_COUNT;
+
+ return (0);
+} /* SkGeClose */
+
+/*****************************************************************************
+ *
+ * SkGeXmit - Linux frame transmit function
+ *
+ * Description:
+ * The system calls this function to send frames onto the wire.
+ * It puts the frame in the tx descriptor ring. If the ring is
+ * full then, the 'tbusy' flag is set.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ * WARNING: returning 1 in 'tbusy' case caused system crashes (double
+ * allocated skb's) !!!
+ */
+static int SkGeXmit(struct sk_buff *skb, struct net_device *dev)
+{
+SK_AC *pAC;
+int Rc; /* return code of XmitFrame */
+
+ pAC = (SK_AC*) dev->priv;
+
+ Rc = XmitFrame(pAC, &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], skb);
+
+ if (Rc == 0) {
+ /* transmitter out of resources */
+ set_bit(0, (void*) &dev->tbusy);
+ return (0);
+ }
+ dev->trans_start = jiffies;
+ return (0);
+} /* SkGeXmit */
+
+
+/*****************************************************************************
+ *
+ * XmitFrame - fill one socket buffer into the transmit ring
+ *
+ * Description:
+ * This function puts a message into the transmit descriptor ring
+ * if there is a descriptors left.
+ * Linux skb's consist of only one continuous buffer.
+ * The first step locks the ring. It is held locked
+ * all time to avoid problems with SWITCH_../PORT_RESET.
+ * Then the descriptoris allocated.
+ * The second part is linking the buffer to the descriptor.
+ * At the very last, the Control field of the descriptor
+ * is made valid for the BMU and a start TX command is given
+ * if necessary.
+ *
+ * Returns:
+ * > 0 - on succes: the number of bytes in the message
+ * = 0 - on resource shortage: this frame sent or dropped, now
+ * the ring is full ( -> set tbusy)
+ * < 0 - on failure: other problems (not used)
+ */
+static int XmitFrame(
+SK_AC *pAC, /* pointer to adapter context */
+TX_PORT *pTxPort, /* pointer to struct of port to send to */
+struct sk_buff *pMessage) /* pointer to send-message */
+{
+TXD *pTxd; /* the rxd to fill */
+unsigned int Flags;
+SK_U64 PhysAddr;
+int BytesSend;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+ ("X"));
+
+ spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
+
+ if (pTxPort->TxdRingFree == 0) {
+ /* no enough free descriptors in ring at the moment */
+ FreeTxDescriptors(pAC, pTxPort);
+ if (pTxPort->TxdRingFree == 0) {
+ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+ SK_PNMI_CNT_NO_TX_BUF(pAC);
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_TX_PROGRESS,
+ ("XmitFrame failed\n"));
+ /* this message can not be sent now */
+ DEV_KFREE_SKB(pMessage);
+ return (0);
+ }
+ }
+ /* advance head counter behind descriptor needed for this frame */
+ pTxd = pTxPort->pTxdRingHead;
+ pTxPort->pTxdRingHead = pTxd->pNextTxd;
+ pTxPort->TxdRingFree--;
+ /* the needed descriptor is reserved now */
+
+ /*
+ * everything allocated ok, so add buffer to descriptor
+ */
+
+#ifdef SK_DUMP_TX
+ DumpMsg(pMessage, "XmitFrame");
+#endif
+
+ /* set up descriptor and CONTROL dword */
+ PhysAddr = virt_to_bus(pMessage->data);
+ pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
+ pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+ pTxd->pMBuf = pMessage;
+ pTxd->TBControl = TX_CTRL_OWN_BMU | TX_CTRL_STF |
+ TX_CTRL_CHECK_DEFAULT | TX_CTRL_SOFTWARE |
+#ifdef USE_TX_COMPLETE
+ TX_CTRL_EOF | TX_CTRL_EOF_IRQ | pMessage->len;
+#else
+ TX_CTRL_EOF | pMessage->len;
+#endif
+
+ if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) {
+ /* previous descriptor already done, so give tx start cmd */
+ /* StartTx(pAC, pTxPort->HwAddr); */
+ SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START);
+ }
+ pTxPort->pTxdRingPrev = pTxd;
+
+
+ BytesSend = pMessage->len;
+ /* after releasing the lock, the skb may be immidiately freed */
+ if (pTxPort->TxdRingFree != 0) {
+ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+ return (BytesSend);
+ }
+ else {
+ /* ring full: set tbusy on return */
+ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+ return (0);
+ }
+} /* XmitFrame */
+
+
+/*****************************************************************************
+ *
+ * FreeTxDescriptors - release descriptors from the descriptor ring
+ *
+ * Description:
+ * This function releases descriptors from a transmit ring if they
+ * have been sent by the BMU.
+ * If a descriptors is sent, it can be freed and the message can
+ * be freed, too.
+ * The SOFTWARE controllable bit is used to prevent running around a
+ * completely free ring for ever. If this bit is no set in the
+ * frame (by XmitFrame), this frame has never been sent or is
+ * already freed.
+ * The Tx descriptor ring lock must be held while calling this function !!!
+ *
+ * Returns:
+ * none
+ */
+static void FreeTxDescriptors(
+SK_AC *pAC, /* pointer to the adapter context */
+TX_PORT *pTxPort) /* pointer to destination port structure */
+{
+TXD *pTxd; /* pointer to the checked descriptor */
+TXD *pNewTail; /* pointer to 'end' of the ring */
+SK_U32 Control; /* TBControl field of descriptor */
+
+ pNewTail = pTxPort->pTxdRingTail;
+ pTxd = pNewTail;
+
+ /*
+ * loop forever; exits if TX_CTRL_SOFTWARE bit not set in start frame
+ * or TX_CTRL_OWN_BMU bit set in any frame
+ */
+ while (1) {
+ Control = pTxd->TBControl;
+ if ((Control & TX_CTRL_SOFTWARE) == 0) {
+ /*
+ * software controllable bit is set in first
+ * fragment when given to BMU. Not set means that
+ * this fragment was never sent or is already
+ * freed ( -> ring completely free now).
+ */
+ pTxPort->pTxdRingTail = pTxd;
+ pAC->dev->tbusy = 0;
+ return;
+ }
+ if (Control & TX_CTRL_OWN_BMU) {
+ pTxPort->pTxdRingTail = pTxd;
+ if (pTxPort->TxdRingFree > 0) {
+ pAC->dev->tbusy = 0;
+ }
+ return;
+ }
+
+ DEV_KFREE_SKB(pTxd->pMBuf); /* free message */
+ pTxPort->TxdRingFree++;
+ pTxd->TBControl &= ~TX_CTRL_SOFTWARE;
+ pTxd = pTxd->pNextTxd; /* point behind fragment with EOF */
+ } /* while(forever) */
+} /* FreeTxDescriptors */
+
+
+/*****************************************************************************
+ *
+ * FillRxRing - fill the receive ring with valid descriptors
+ *
+ * Description:
+ * This function fills the receive ring descriptors with data
+ * segments and makes them valid for the BMU.
+ * The active ring is filled completely, if possible.
+ * The non-active ring is filled only partial to save memory.
+ *
+ * Description of rx ring structure:
+ * head - points to the descriptor which will be used next by the BMU
+ * tail - points to the next descriptor to give to the BMU
+ *
+ * Returns: N/A
+ */
+static void FillRxRing(
+SK_AC *pAC, /* pointer to the adapter context */
+RX_PORT *pRxPort) /* ptr to port struct for which the ring
+ should be filled */
+{
+unsigned int Flags;
+
+ spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags);
+ while (pRxPort->RxdRingFree > pRxPort->RxFillLimit) {
+ if(!FillRxDescriptor(pAC, pRxPort))
+ break;
+ }
+ spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags);
+} /* FillRxRing */
+
+
+/*****************************************************************************
+ *
+ * FillRxDescriptor - fill one buffer into the receive ring
+ *
+ * Description:
+ * The function allocates a new receive buffer and
+ * puts it into the next descriptor.
+ *
+ * Returns:
+ * SK_TRUE - a buffer was added to the ring
+ * SK_FALSE - a buffer could not be added
+ */
+static SK_BOOL FillRxDescriptor(
+SK_AC *pAC, /* pointer to the adapter context struct */
+RX_PORT *pRxPort) /* ptr to port struct of ring to fill */
+{
+struct sk_buff *pMsgBlock; /* pointer to a new message block */
+RXD *pRxd; /* the rxd to fill */
+SK_U16 Length; /* data fragment length */
+SK_U64 PhysAddr; /* physical address of a rx buffer */
+
+ pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
+ if (pMsgBlock == NULL) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_ENTRY,
+ ("%s: Allocation of rx buffer failed !\n",
+ pAC->dev->name));
+ SK_PNMI_CNT_NO_RX_BUF(pAC);
+ return(SK_FALSE);
+ }
+ skb_reserve(pMsgBlock, 2); /* to align IP frames */
+ /* skb allocated ok, so add buffer */
+ pRxd = pRxPort->pRxdRingTail;
+ pRxPort->pRxdRingTail = pRxd->pNextRxd;
+ pRxPort->RxdRingFree--;
+ Length = pAC->RxBufSize;
+ PhysAddr = virt_to_bus(pMsgBlock->data);
+ pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
+ pRxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+ pRxd->pMBuf = pMsgBlock;
+ pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF |
+ RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length;
+ return (SK_TRUE);
+
+} /* FillRxDescriptor */
+
+
+/*****************************************************************************
+ *
+ * ReQueueRxBuffer - fill one buffer back into the receive ring
+ *
+ * Description:
+ * Fill a given buffer back into the rx ring. The buffer
+ * has been previously allocated and aligned, and its phys.
+ * address calculated, so this is no more necessary.
+ *
+ * Returns: N/A
+ */
+static void ReQueueRxBuffer(
+SK_AC *pAC, /* pointer to the adapter context struct */
+RX_PORT *pRxPort, /* ptr to port struct of ring to fill */
+struct sk_buff *pMsg, /* pointer to the buffer */
+SK_U32 PhysHigh, /* phys address high dword */
+SK_U32 PhysLow) /* phys address low dword */
+{
+RXD *pRxd; /* the rxd to fill */
+SK_U16 Length; /* data fragment length */
+
+ pRxd = pRxPort->pRxdRingTail;
+ pRxPort->pRxdRingTail = pRxd->pNextRxd;
+ pRxPort->RxdRingFree--;
+ Length = pAC->RxBufSize;
+ pRxd->VDataLow = PhysLow;
+ pRxd->VDataHigh = PhysHigh;
+ pRxd->pMBuf = pMsg;
+ pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF |
+ RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length;
+ return;
+} /* ReQueueRxBuffer */
+
+
+/*****************************************************************************
+ *
+ * ReceiveIrq - handle a receive IRQ
+ *
+ * Description:
+ * This function is called when a receive IRQ is set.
+ * It walks the receive descriptor ring and sends up all
+ * frames that are complete.
+ *
+ * Returns: N/A
+ */
+static void ReceiveIrq(
+SK_AC *pAC, /* pointer to adapter context */
+RX_PORT *pRxPort) /* pointer to receive port struct */
+{
+RXD *pRxd; /* pointer to receive descriptors */
+SK_U32 Control; /* control field of descriptor */
+struct sk_buff *pMsg; /* pointer to message holding frame */
+struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
+int FrameLength; /* total length of received frame */
+SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
+SK_EVPARA EvPara; /* an event parameter union */
+int PortIndex = pRxPort->PortIndex;
+unsigned int Offset;
+unsigned int NumBytes;
+unsigned int ForRlmt;
+SK_BOOL IsBc;
+SK_BOOL IsMc;
+SK_U32 FrameStat;
+unsigned short Csum1;
+unsigned short Csum2;
+unsigned short Type;
+int Result;
+
+rx_start:
+ /* do forever; exit if RX_CTRL_OWN_BMU found */
+ while (pRxPort->RxdRingFree < pAC->RxDescrPerRing) {
+ pRxd = pRxPort->pRxdRingHead;
+
+ Control = pRxd->RBControl;
+
+ /* check if this descriptor is ready */
+ if ((Control & RX_CTRL_OWN_BMU) != 0) {
+ /* this descriptor is not yet ready */
+ FillRxRing(pAC, pRxPort);
+ return;
+ }
+
+ /* get length of frame and check it */
+ FrameLength = Control & RX_CTRL_LEN_MASK;
+ if (FrameLength > pAC->RxBufSize)
+ goto rx_failed;
+
+ /* check for STF and EOF */
+ if ((Control & (RX_CTRL_STF | RX_CTRL_EOF)) !=
+ (RX_CTRL_STF | RX_CTRL_EOF))
+ goto rx_failed;
+
+ /* here we have a complete frame in the ring */
+ pMsg = pRxd->pMBuf;
+
+ /*
+ * if short frame then copy data to reduce memory waste
+ */
+ if (FrameLength < SK_COPY_THRESHOLD) {
+ pNewMsg = alloc_skb(FrameLength+2, GFP_ATOMIC);
+ if (pNewMsg == NULL) {
+ /* use original skb */
+ /* set length in message */
+ skb_put(pMsg, FrameLength);
+ }
+ else {
+ /* alloc new skb and copy data */
+ skb_reserve(pNewMsg, 2);
+ skb_put(pNewMsg, FrameLength);
+ eth_copy_and_sum(pNewMsg, pMsg->data,
+ FrameLength, 0);
+ ReQueueRxBuffer(pAC, pRxPort, pMsg,
+ pRxd->VDataHigh, pRxd->VDataLow);
+ pMsg = pNewMsg;
+ }
+ }
+ else {
+ /* set length in message */
+ skb_put(pMsg, FrameLength);
+ /* hardware checksum */
+ Type = ntohs(*((short*)&pMsg->data[12]));
+ if (Type == 0x800) {
+ Csum1= pRxd->TcpSums & 0xffff;
+ Csum2=(pRxd->TcpSums >> 16) & 0xffff;
+ if ((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) {
+ Result = SkCsGetReceiveInfo(pAC,
+ &pMsg->data[14],
+ Csum1, Csum2);
+ if (Result ==
+ SKCS_STATUS_IP_FRAGMENT ||
+ Result ==
+ SKCS_STATUS_IP_CSUM_OK ||
+ Result ==
+ SKCS_STATUS_TCP_CSUM_OK ||
+ Result ==
+ SKCS_STATUS_UDP_CSUM_OK) {
+ pMsg->ip_summed =
+ CHECKSUM_UNNECESSARY;
+ }
+ } /* checksum calculation valid */
+ } /* IP frame */
+ } /* frame > SK_COPY_TRESHOLD */
+
+ FrameStat = pRxd->FrameStat;
+ pRxd = pRxd->pNextRxd;
+ pRxPort->pRxdRingHead = pRxd;
+ pRxPort->RxdRingFree ++;
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+ ("Received frame of length %d on port %d\n",
+ FrameLength, PortIndex));
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+ ("Number of free rx descriptors: %d\n",
+ pRxPort->RxdRingFree));
+
+ if ((Control & RX_CTRL_STAT_VALID) == RX_CTRL_STAT_VALID &&
+ (FrameStat &
+ (XMR_FS_ANY_ERR | XMR_FS_1L_VLAN | XMR_FS_2L_VLAN))
+ == 0) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS,("V"));
+ ForRlmt = SK_RLMT_RX_PROTOCOL;
+ IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
+ SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
+ IsBc, &Offset, &NumBytes);
+ if (NumBytes != 0) {
+ IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
+ SK_RLMT_LOOKAHEAD(pAC, PortIndex,
+ &pMsg->data[Offset],
+ IsBc, IsMc, &ForRlmt);
+ }
+ if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
+ /* send up only frames from active port */
+ if (PortIndex == pAC->ActivePort) {
+ /* frame for upper layer */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS,
+ ("U"));
+#ifdef DUMP_RX
+ DumpMsg(pMsg, "Rx");
+#endif
+ pMsg->dev = pAC->dev;
+ pMsg->protocol = eth_type_trans(pMsg,
+ pAC->dev);
+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
+ FrameLength);
+ netif_rx(pMsg);
+ pAC->dev->last_rx = jiffies;
+ }
+ else {
+ /* drop frame */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS,
+ ("D"));
+ DEV_KFREE_SKB(pMsg);
+ }
+ } /* if not for rlmt */
+ else {
+ /* packet for rlmt */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
+ pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
+ pAC->IoBase, FrameLength);
+ if (pRlmtMbuf != NULL) {
+ pRlmtMbuf->pNext = NULL;
+ pRlmtMbuf->Length = FrameLength;
+ pRlmtMbuf->PortIdx = PortIndex;
+ EvPara.pParaPtr = pRlmtMbuf;
+ memcpy((char*)(pRlmtMbuf->pData),
+ (char*)(pMsg->data),
+ FrameLength);
+ SkEventQueue(pAC, SKGE_RLMT,
+ SK_RLMT_PACKET_RECEIVED,
+ EvPara);
+ pAC->CheckQueue = SK_TRUE;
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS,
+ ("Q"));
+ }
+ if ((pAC->dev->flags &
+ (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
+ (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
+ SK_RLMT_RX_PROTOCOL) {
+ pMsg->dev = pAC->dev;
+ pMsg->protocol = eth_type_trans(pMsg,
+ pAC->dev);
+ netif_rx(pMsg);
+ pAC->dev->last_rx = jiffies;
+ }
+ else {
+ DEV_KFREE_SKB(pMsg);
+ }
+
+ } /* if packet for rlmt */
+ } /* if valid frame */
+ else {
+ /* there is a receive error in this frame */
+ if ((FrameStat & XMR_FS_1L_VLAN) != 0) {
+ printk("%s: Received frame"
+ " with VLAN Level 1 header, check"
+ " switch configuration\n",
+ pAC->dev->name);
+ }
+ if ((FrameStat & XMR_FS_2L_VLAN) != 0) {
+ printk("%s: Received frame"
+ " with VLAN Level 2 header, check"
+ " switch configuration\n",
+ pAC->dev->name);
+ }
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBGCAT_DRV_RX_PROGRESS,
+ ("skge: Error in received frame, dropped!\n"
+ "Control: %x\nRxStat: %x\n",
+ Control, FrameStat));
+ DEV_KFREE_SKB(pMsg);
+ }
+ } /* while */
+ FillRxRing(pAC, pRxPort);
+ /* do not start if called from Close */
+ if (pAC->BoardLevel > 0) {
+ ClearAndStartRx(pAC, PortIndex);
+ }
+ return;
+
+rx_failed:
+ /* remove error frame */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
+ ("Schrottdescriptor, length: 0x%x\n", FrameLength));
+ DEV_KFREE_SKB(pRxd->pMBuf);
+ pRxd->pMBuf = NULL;
+ pRxPort->RxdRingFree++;
+ pRxPort->pRxdRingHead = pRxd->pNextRxd;
+ goto rx_start;
+
+} /* ReceiveIrq */
+
+
+/*****************************************************************************
+ *
+ * ClearAndStartRx - give a start receive command to BMU, clear IRQ
+ *
+ * Description:
+ * This function sends a start command and a clear interrupt
+ * command for one receive queue to the BMU.
+ *
+ * Returns: N/A
+ * none
+ */
+static void ClearAndStartRx(
+SK_AC *pAC, /* pointer to the adapter context */
+int PortIndex) /* index of the receive port (XMAC) */
+{
+ SK_OUT8(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CTRL,
+ RX_Q_CTRL_START | RX_Q_CTRL_CLR_I_EOF);
+} /* ClearAndStartRx */
+
+
+/*****************************************************************************
+ *
+ * ClearTxIrq - give a clear transmit IRQ command to BMU
+ *
+ * Description:
+ * This function sends a clear tx IRQ command for one
+ * transmit queue to the BMU.
+ *
+ * Returns: N/A
+ */
+static void ClearTxIrq(
+SK_AC *pAC, /* pointer to the adapter context */
+int PortIndex, /* index of the transmit port (XMAC) */
+int Prio) /* priority or normal queue */
+{
+ SK_OUT8(pAC->IoBase, TxQueueAddr[PortIndex][Prio]+TX_Q_CTRL,
+ TX_Q_CTRL_CLR_I_EOF);
+} /* ClearTxIrq */
+
+
+/*****************************************************************************
+ *
+ * ClearRxRing - remove all buffers from the receive ring
+ *
+ * Description:
+ * This function removes all receive buffers from the ring.
+ * The receive BMU must be stopped before calling this function.
+ *
+ * Returns: N/A
+ */
+static void ClearRxRing(
+SK_AC *pAC, /* pointer to adapter context */
+RX_PORT *pRxPort) /* pointer to rx port struct */
+{
+RXD *pRxd; /* pointer to the current descriptor */
+unsigned int Flags;
+
+ if (pRxPort->RxdRingFree == pAC->RxDescrPerRing) {
+ return;
+ }
+ spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags);
+ pRxd = pRxPort->pRxdRingHead;
+ do {
+ if (pRxd->pMBuf != NULL) {
+ DEV_KFREE_SKB(pRxd->pMBuf);
+ pRxd->pMBuf = NULL;
+ }
+ pRxd->RBControl &= RX_CTRL_OWN_BMU;
+ pRxd = pRxd->pNextRxd;
+ pRxPort->RxdRingFree++;
+ } while (pRxd != pRxPort->pRxdRingTail);
+ pRxPort->pRxdRingTail = pRxPort->pRxdRingHead;
+ spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags);
+} /* ClearRxRing */
+
+
+/*****************************************************************************
+ *
+ * ClearTxRing - remove all buffers from the transmit ring
+ *
+ * Description:
+ * This function removes all transmit buffers from the ring.
+ * The transmit BMU must be stopped before calling this function
+ * and transmitting at the upper level must be disabled.
+ * The BMU own bit of all descriptors is cleared, the rest is
+ * done by calling FreeTxDescriptors.
+ *
+ * Returns: N/A
+ */
+static void ClearTxRing(
+SK_AC *pAC, /* pointer to adapter context */
+TX_PORT *pTxPort) /* pointer to tx prt struct */
+{
+TXD *pTxd; /* pointer to the current descriptor */
+int i;
+unsigned int Flags;
+
+ spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
+ pTxd = pTxPort->pTxdRingHead;
+ for (i=0; i<pAC->TxDescrPerRing; i++) {
+ pTxd->TBControl &= ~TX_CTRL_OWN_BMU;
+ pTxd = pTxd->pNextTxd;
+ }
+ FreeTxDescriptors(pAC, pTxPort);
+ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+} /* ClearTxRing */
+
+
+/*****************************************************************************
+ *
+ * SetQueueSizes - configure the sizes of rx and tx queues
+ *
+ * Description:
+ * This function assigns the sizes for active and passive port
+ * to the appropriate HWinit structure variables.
+ * The passive port(s) get standard values, all remaining RAM
+ * is given to the active port.
+ * The queue sizes are in kbyte and must be multiple of 8.
+ * The limits for the number of buffers filled into the rx rings
+ * is also set in this routine.
+ *
+ * Returns:
+ * none
+ */
+static void SetQueueSizes(
+SK_AC *pAC) /* pointer to the adapter context */
+{
+int StandbyRam; /* adapter RAM used for a standby port */
+int RemainingRam; /* adapter RAM available for the active port */
+int RxRam; /* RAM used for the active port receive queue */
+int i; /* loop counter */
+
+ StandbyRam = SK_RLMT_STANDBY_QRXSIZE + SK_RLMT_STANDBY_QXASIZE +
+ SK_RLMT_STANDBY_QXSSIZE;
+ RemainingRam = pAC->GIni.GIRamSize -
+ (pAC->GIni.GIMacsFound-1) * StandbyRam;
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ pAC->GIni.GP[i].PRxQSize = SK_RLMT_STANDBY_QRXSIZE;
+ pAC->GIni.GP[i].PXSQSize = SK_RLMT_STANDBY_QXSSIZE;
+ pAC->GIni.GP[i].PXAQSize = SK_RLMT_STANDBY_QXASIZE;
+ }
+ RxRam = (RemainingRam * 8 / 10) & ~7;
+ pAC->GIni.GP[pAC->ActivePort].PRxQSize = RxRam;
+ pAC->GIni.GP[pAC->ActivePort].PXSQSize = 0;
+ pAC->GIni.GP[pAC->ActivePort].PXAQSize =
+ (RemainingRam - RxRam) & ~7;
+ pAC->RxQueueSize = RxRam;
+ pAC->TxSQueueSize = 0;
+ pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7;
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("queue sizes settings - rx:%d txA:%d txS:%d\n",
+ pAC->RxQueueSize,pAC->TxAQueueSize, pAC->TxSQueueSize));
+
+ for (i=0; i<SK_MAX_MACS; i++) {
+ pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing;
+ }
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100;
+ }
+ /*
+ * Do not set the Limit to 0, because this could cause
+ * wrap around with ReQueue'ed buffers (a buffer could
+ * be requeued in the same position, made accessable to
+ * the hardware, and the hardware could change its
+ * contents!
+ */
+ pAC->RxPort[pAC->ActivePort].RxFillLimit = 1;
+
+#ifdef DEBUG
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+ ("i: %d, RxQSize: %d, PXSQsize: %d, PXAQSize: %d\n",
+ i,
+ pAC->GIni.GP[i].PRxQSize,
+ pAC->GIni.GP[i].PXSQSize,
+ pAC->GIni.GP[i].PXAQSize));
+ }
+#endif
+} /* SetQueueSizes */
+
+
+/*****************************************************************************
+ *
+ * SkGeSetMacAddr - Set the hardware MAC address
+ *
+ * Description:
+ * This function sets the MAC address used by the adapter.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+static int SkGeSetMacAddr(struct net_device *dev, void *p)
+{
+SK_AC *pAC = (SK_AC*) dev->priv;
+struct sockaddr *addr = p;
+unsigned int Flags;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeSetMacAddr starts now...\n"));
+ if(dev->start) {
+ return -EBUSY;
+ }
+ memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
+ (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
+
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ return 0;
+} /* SkGeSetMacAddr */
+
+
+/*****************************************************************************
+ *
+ * SkGeSetRxMode - set receive mode
+ *
+ * Description:
+ * This function sets the receive mode of an adapter. The adapter
+ * supports promiscuous mode, allmulticast mode and a number of
+ * multicast addresses. If more multicast addresses the available
+ * are selected, a hash function in the hardware is used.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+static void SkGeSetRxMode(struct net_device *dev)
+{
+SK_AC *pAC;
+struct dev_mc_list *pMcList;
+int i;
+unsigned int Flags;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeSetRxMode starts now... "));
+ pAC = (SK_AC*) dev->priv;
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ if (dev->flags & IFF_PROMISC) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("PROMISCUOUS mode\n"));
+ SkAddrPromiscuousChange(pAC, pAC->IoBase, pAC->ActivePort,
+ SK_PROM_MODE_LLC);
+ } else if (dev->flags & IFF_ALLMULTI) {
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("ALLMULTI mode\n"));
+ SkAddrPromiscuousChange(pAC, pAC->IoBase, pAC->ActivePort,
+ SK_PROM_MODE_ALL_MC);
+ } else {
+ SkAddrPromiscuousChange(pAC, pAC->IoBase, pAC->ActivePort,
+ SK_PROM_MODE_NONE);
+ SkAddrMcClear(pAC, pAC->IoBase, pAC->ActivePort, 0);
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("Number of MC entries: %d ", dev->mc_count));
+
+ pMcList = dev->mc_list;
+ for (i=0; i<dev->mc_count; i++, pMcList = pMcList->next) {
+ SkAddrMcAdd(pAC, pAC->IoBase, pAC->ActivePort,
+ (SK_MAC_ADDR*)pMcList->dmi_addr, 0);
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MCA,
+ ("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ pMcList->dmi_addr[0],
+ pMcList->dmi_addr[1],
+ pMcList->dmi_addr[2],
+ pMcList->dmi_addr[3],
+ pMcList->dmi_addr[4],
+ pMcList->dmi_addr[5]));
+ }
+ SkAddrMcUpdate(pAC, pAC->IoBase, pAC->ActivePort);
+
+ }
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ return;
+} /* SkGeSetRxMode */
+
+
+/*****************************************************************************
+ *
+ * SkGeChangeMtu - set the MTU to another value
+ *
+ * Description:
+ * This function sets is called whenever the MTU size is changed
+ * (ifconfig mtu xxx dev ethX). If the MTU is bigger than standard
+ * ethernet MTU size, long frame support is activated.
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+static int SkGeChangeMtu(struct net_device *dev, int NewMtu)
+{
+SK_AC *pAC;
+unsigned int Flags;
+int i;
+SK_EVPARA EvPara;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeChangeMtu starts now...\n"));
+
+ pAC = (SK_AC*) dev->priv;
+ if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
+ return -EINVAL;
+ }
+
+ pAC->RxBufSize = NewMtu + 32;
+ dev->mtu = NewMtu;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("New MTU: %d\n", NewMtu));
+
+ /* prevent reconfiguration while changing the MTU */
+
+ /* disable interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
+ SkEventDispatcher(pAC, pAC->IoBase);
+
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ spin_lock_irqsave(
+ &pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock, Flags);
+ }
+ pAC->dev->tbusy = 1;
+
+ /*
+ * adjust number of rx buffers allocated
+ */
+ if (NewMtu > 1500) {
+ /* use less rx buffers */
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ if (i == pAC->ActivePort)
+ pAC->RxPort[i].RxFillLimit =
+ pAC->RxDescrPerRing - 100;
+ else
+ pAC->RxPort[i].RxFillLimit =
+ pAC->RxDescrPerRing - 10;
+
+ }
+ }
+ else {
+ /* use normal anoumt of rx buffers */
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ if (i == pAC->ActivePort)
+ pAC->RxPort[i].RxFillLimit = 1;
+ else
+ pAC->RxPort[i].RxFillLimit =
+ pAC->RxDescrPerRing - 100;
+ }
+ }
+
+ SkGeDeInit(pAC, pAC->IoBase);
+
+ /*
+ * enable/disable hardware support for long frames
+ */
+ if (NewMtu > 1500) {
+ pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ pAC->GIni.GP[i].PRxCmd =
+ XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
+ }
+ }
+ else {
+ pAC->GIni.GIPortUsage = SK_RED_LINK;
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ pAC->GIni.GP[i].PRxCmd =
+ XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
+ }
+ }
+
+ SkGeInit( pAC, pAC->IoBase, 1);
+ SkI2cInit( pAC, pAC->IoBase, 1);
+ SkEventInit(pAC, pAC->IoBase, 1);
+ SkPnmiInit( pAC, pAC->IoBase, 1);
+ SkAddrInit( pAC, pAC->IoBase, 1);
+ SkRlmtInit( pAC, pAC->IoBase, 1);
+ SkTimerInit(pAC, pAC->IoBase, 1);
+
+ SkGeInit( pAC, pAC->IoBase, 2);
+ SkI2cInit( pAC, pAC->IoBase, 2);
+ SkEventInit(pAC, pAC->IoBase, 2);
+ SkPnmiInit( pAC, pAC->IoBase, 2);
+ SkAddrInit( pAC, pAC->IoBase, 2);
+ SkRlmtInit( pAC, pAC->IoBase, 2);
+ SkTimerInit(pAC, pAC->IoBase, 2);
+
+ /*
+ * clear and reinit the rx rings here
+ */
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ ReceiveIrq(pAC, &pAC->RxPort[i]);
+ ClearRxRing(pAC, &pAC->RxPort[i]);
+ FillRxRing(pAC, &pAC->RxPort[i]);
+
+ // Enable transmit descriptor polling.
+ SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
+ FillRxRing(pAC, &pAC->RxPort[i]);
+ };
+
+ SkGeYellowLED(pAC, pAC->IoBase, 1);
+
+#ifdef USE_INT_MOD
+ {
+ unsigned long ModBase;
+ ModBase = 53125000 / INTS_PER_SEC;
+ SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
+ SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK);
+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
+ }
+#endif
+
+ pAC->dev->tbusy = 0;
+ for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
+ spin_unlock_irqrestore(
+ &pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock, Flags);
+ }
+
+ /* enable Interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK);
+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
+ SkEventDispatcher(pAC, pAC->IoBase);
+
+
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+ return 0;
+} /* SkGeChangeMtu */
+
+
+/*****************************************************************************
+ *
+ * SkGeStats - return ethernet device statistics
+ *
+ * Description:
+ * This function return statistic data about the ethernet device
+ * to the operating system.
+ *
+ * Returns:
+ * pointer to the statistic structure.
+ */
+static struct net_device_stats *SkGeStats(struct net_device *dev)
+{
+SK_AC *pAC = (SK_AC*) dev->priv;
+SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */
+SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */
+unsigned int Size; /* size of pnmi struct */
+unsigned int Flags; /* for spin lock */
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeStats starts now...\n"));
+ pPnmiStruct = &pAC->PnmiStruct;
+ memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ Size = SK_PNMI_STRUCT_SIZE;
+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size);
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ pPnmiStat = &pPnmiStruct->Stat[0];
+ pPnmiConf = &pPnmiStruct->Conf[0];
+
+ pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
+ pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
+ pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
+ pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
+ pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
+ pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
+ pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
+ pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
+ pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
+ pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
+
+ /* detailed rx_errors: */
+ pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
+ pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
+ pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
+ pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
+ pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
+ pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
+
+ /* detailed tx_errors */
+ pAC->stats.tx_aborted_errors = (SK_U32) 0;
+ pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
+ pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
+ pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
+ pAC->stats.tx_window_errors = (SK_U32) 0;
+
+ return(&pAC->stats);
+} /* SkGeStats */
+
+
+/*****************************************************************************
+ *
+ * SkGeIoctl - IO-control function
+ *
+ * Description:
+ * This function is called if an ioctl is issued on the device.
+ * There are three subfunction for reading, writing and test-writing
+ * the private MIB data structure (usefull for SysKonnect-internal tools).
+ *
+ * Returns:
+ * 0, if everything is ok
+ * !=0, on error
+ */
+static int SkGeIoctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+SK_AC *pAC;
+SK_GE_IOCTL Ioctl;
+unsigned int Err = 0;
+int Size;
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeIoctl starts now...\n"));
+ pAC = (SK_AC*) dev->priv;
+
+ if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
+ return -EFAULT;
+ }
+
+ switch(cmd) {
+ case SK_IOCTL_SETMIB:
+ case SK_IOCTL_PRESETMIB:
+ if (!capable(CAP_NET_ADMIN)) return -EPERM;
+ case SK_IOCTL_GETMIB:
+ if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
+ Ioctl.Len<sizeof(pAC->PnmiStruct)?
+ Ioctl.Len : sizeof(pAC->PnmiStruct))) {
+ return -EFAULT;
+ }
+ Size = SkGeIocMib(pAC, Ioctl.Len, cmd);
+ if(copy_to_user(Ioctl.pData, &pAC->PnmiStruct,
+ Ioctl.Len<Size? Ioctl.Len : Size)) {
+ return -EFAULT;
+ }
+ Ioctl.Len = Size;
+ if(copy_to_user(rq->ifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) {
+ return -EFAULT;
+ }
+ break;
+ default:
+ Err = -EOPNOTSUPP;
+ }
+ return(Err);
+} /* SkGeIoctl */
+
+
+/*****************************************************************************
+ *
+ * SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message
+ *
+ * Description:
+ * This function reads/writes the MIB data using PNMI (Private Network
+ * Management Interface).
+ * The destination for the data must be provided with the
+ * ioctl call and is given to the driver in the form of
+ * a user space address.
+ * Copying from the user-provided data area into kernel messages
+ * and back is done by copy_from_user and copy_to_user calls in
+ * SkGeIoctl.
+ *
+ * Returns:
+ * returned size from PNMI call
+ */
+static int SkGeIocMib(
+SK_AC *pAC, /* pointer to the adapter context */
+unsigned int Size, /* length of ioctl data */
+int mode) /* flag for set/preset */
+{
+unsigned int Flags; /* for spin lock */
+
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("SkGeIocMib starts now...\n"));
+ /* access MIB */
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ switch(mode) {
+ case SK_IOCTL_GETMIB:
+ SkPnmiGetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size);
+ break;
+ case SK_IOCTL_PRESETMIB:
+ SkPnmiPreSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size);
+ break;
+ case SK_IOCTL_SETMIB:
+ SkPnmiSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size);
+ break;
+ default:
+ break;
+ }
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+ ("MIB data access succeeded\n"));
+ return (Size);
+} /* SkGeIocMib */
+
+
+/*****************************************************************************
+ *
+ * GetConfiguration - read configuration information
+ *
+ * Description:
+ * This function reads per-adapter configuration information from
+ * the options provided on the command line.
+ *
+ * Returns:
+ * none
+ */
+static void GetConfiguration(
+SK_AC *pAC) /* pointer to the adapter context structure */
+{
+SK_I32 Port; /* preferred port */
+int AutoNeg; /* auto negotiation off (0) or on (1) */
+int DuplexCap; /* duplex capabilities (0=both, 1=full, 2=half */
+int MSMode; /* master / slave mode selection */
+SK_BOOL AutoSet;
+SK_BOOL DupSet;
+/*
+ * The two parameters AutoNeg. and DuplexCap. map to one configuration
+ * parameter. The mapping is described by this table:
+ * DuplexCap -> | both | full | half |
+ * AutoNeg | | | |
+ * -----------------------------------------------------------------
+ * Off | illegal | Full | Half |
+ * -----------------------------------------------------------------
+ * On | AutoBoth | AutoFull | AutoHalf |
+ * -----------------------------------------------------------------
+ * Sense | AutoSense | AutoSense | AutoSense |
+ */
+int Capabilities[3][3] =
+ { { -1, SK_LMODE_FULL, SK_LMODE_HALF},
+ {SK_LMODE_AUTOBOTH, SK_LMODE_AUTOFULL, SK_LMODE_AUTOHALF},
+ {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
+#define DC_BOTH 0
+#define DC_FULL 1
+#define DC_HALF 2
+#define AN_OFF 0
+#define AN_ON 1
+#define AN_SENS 2
+
+ /* settings for port A */
+ AutoNeg = AN_SENS; /* default: do auto Sense */
+ AutoSet = SK_FALSE;
+ if (AutoNeg_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ AutoNeg_A[pAC->Index] != NULL) {
+ AutoSet = SK_TRUE;
+ if (strcmp(AutoNeg_A[pAC->Index],"")==0) {
+ AutoSet = SK_FALSE;
+ }
+ else if (strcmp(AutoNeg_A[pAC->Index],"On")==0) {
+ AutoNeg = AN_ON;
+ }
+ else if (strcmp(AutoNeg_A[pAC->Index],"Off")==0) {
+ AutoNeg = AN_OFF;
+ }
+ else if (strcmp(AutoNeg_A[pAC->Index],"Sense")==0) {
+ AutoNeg = AN_SENS;
+ }
+ else printk("%s: Illegal value for AutoNeg_A\n",
+ pAC->dev->name);
+ }
+
+ DuplexCap = DC_BOTH;
+ DupSet = SK_FALSE;
+ if (DupCap_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ DupCap_A[pAC->Index] != NULL) {
+ DupSet = SK_TRUE;
+ if (strcmp(DupCap_A[pAC->Index],"")==0) {
+ DupSet = SK_FALSE;
+ }
+ else if (strcmp(DupCap_A[pAC->Index],"Both")==0) {
+ DuplexCap = DC_BOTH;
+ }
+ else if (strcmp(DupCap_A[pAC->Index],"Full")==0) {
+ DuplexCap = DC_FULL;
+ }
+ else if (strcmp(DupCap_A[pAC->Index],"Half")==0) {
+ DuplexCap = DC_HALF;
+ }
+ else printk("%s: Illegal value for DupCap_A\n",
+ pAC->dev->name);
+ }
+
+ /* check for illegal combinations */
+ if (AutoSet && AutoNeg==AN_SENS && DupSet) {
+ printk("%s, Port A: DuplexCapabilities"
+ " ignored using Sense mode\n", pAC->dev->name);
+ }
+ if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){
+ printk("%s, Port A: Illegal combination"
+ " of values AutoNeg. and DuplexCap.\n Using "
+ "Full Duplex\n", pAC->dev->name);
+
+ DuplexCap = DC_FULL;
+ }
+ if (AutoSet && AutoNeg==AN_OFF && !DupSet) {
+ DuplexCap = DC_FULL;
+ }
+
+ if (!AutoSet && DupSet) {
+ printk("%s, Port A: Duplex setting not"
+ " possible in\n default AutoNegotiation mode"
+ " (Sense).\n Using AutoNegotiation On\n",
+ pAC->dev->name);
+ AutoNeg = AN_ON;
+ }
+
+ /* set the desired mode */
+ pAC->GIni.GP[0].PLinkModeConf =
+ Capabilities[AutoNeg][DuplexCap];
+
+ pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
+ if (FlowCtrl_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ FlowCtrl_A[pAC->Index] != NULL) {
+ if (strcmp(FlowCtrl_A[pAC->Index],"") == 0) {
+ }
+ else if (strcmp(FlowCtrl_A[pAC->Index],"SymOrRem") == 0) {
+ pAC->GIni.GP[0].PFlowCtrlMode =
+ SK_FLOW_MODE_SYM_OR_REM;
+ }
+ else if (strcmp(FlowCtrl_A[pAC->Index],"Sym")==0) {
+ pAC->GIni.GP[0].PFlowCtrlMode =
+ SK_FLOW_MODE_SYMMETRIC;
+ }
+ else if (strcmp(FlowCtrl_A[pAC->Index],"LocSend")==0) {
+ pAC->GIni.GP[0].PFlowCtrlMode =
+ SK_FLOW_MODE_LOC_SEND;
+ }
+ else if (strcmp(FlowCtrl_A[pAC->Index],"None")==0) {
+ pAC->GIni.GP[0].PFlowCtrlMode =
+ SK_FLOW_MODE_NONE;
+ }
+ else printk("Illegal value for FlowCtrl_A\n");
+ }
+ if (AutoNeg==AN_OFF && pAC->GIni.GP[0].PFlowCtrlMode!=
+ SK_FLOW_MODE_NONE) {
+ printk("%s, Port A: FlowControl"
+ " impossible without AutoNegotiation,"
+ " disabled\n", pAC->dev->name);
+ pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+ }
+
+ MSMode = SK_MS_MODE_AUTO; /* default: do auto select */
+ if (Role_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ Role_A[pAC->Index] != NULL) {
+ if (strcmp(Role_A[pAC->Index],"")==0) {
+ }
+ else if (strcmp(Role_A[pAC->Index],"Auto")==0) {
+ MSMode = SK_MS_MODE_AUTO;
+ }
+ else if (strcmp(Role_A[pAC->Index],"Master")==0) {
+ MSMode = SK_MS_MODE_MASTER;
+ }
+ else if (strcmp(Role_A[pAC->Index],"Slave")==0) {
+ MSMode = SK_MS_MODE_SLAVE;
+ }
+ else printk("%s: Illegal value for Role_A\n",
+ pAC->dev->name);
+ }
+ pAC->GIni.GP[0].PMSMode = MSMode;
+
+
+ /* settings for port B */
+ AutoNeg = AN_SENS; /* default: do auto Sense */
+ AutoSet = SK_FALSE;
+ if (AutoNeg_B != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ AutoNeg_B[pAC->Index] != NULL) {
+ AutoSet = SK_TRUE;
+ if (strcmp(AutoNeg_B[pAC->Index],"")==0) {
+ AutoSet = SK_FALSE;
+ }
+ else if (strcmp(AutoNeg_B[pAC->Index],"On")==0) {
+ AutoNeg = AN_ON;
+ }
+ else if (strcmp(AutoNeg_B[pAC->Index],"Off")==0) {
+ AutoNeg = AN_OFF;
+ }
+ else if (strcmp(AutoNeg_B[pAC->Index],"Sense")==0) {
+ AutoNeg = AN_SENS;
+ }
+ else printk("Illegal value for AutoNeg_B\n");
+ }
+
+ DuplexCap = DC_BOTH;
+ DupSet = SK_FALSE;
+ if (DupCap_B != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ DupCap_B[pAC->Index] != NULL) {
+ DupSet = SK_TRUE;
+ if (strcmp(DupCap_B[pAC->Index],"")==0) {
+ DupSet = SK_FALSE;
+ }
+ else if (strcmp(DupCap_B[pAC->Index],"Both")==0) {
+ DuplexCap = DC_BOTH;
+ }
+ else if (strcmp(DupCap_B[pAC->Index],"Full")==0) {
+ DuplexCap = DC_FULL;
+ }
+ else if (strcmp(DupCap_B[pAC->Index],"Half")==0) {
+ DuplexCap = DC_HALF;
+ }
+ else printk("Illegal value for DupCap_B\n");
+ }
+
+ /* check for illegal combinations */
+ if (AutoSet && AutoNeg==AN_SENS && DupSet) {
+ printk("%s, Port B: DuplexCapabilities"
+ " ignored using Sense mode\n", pAC->dev->name);
+ }
+ if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){
+ printk("%s, Port B: Illegal combination"
+ " of values AutoNeg. and DuplexCap.\n Using "
+ "Full Duplex\n", pAC->dev->name);
+
+ DuplexCap = DC_FULL;
+ }
+ if (AutoSet && AutoNeg==AN_OFF && !DupSet) {
+ DuplexCap = DC_FULL;
+ }
+
+ if (!AutoSet && DupSet) {
+ printk("%s, Port B: Duplex setting not"
+ " possible in\n default AutoNegotiation mode"
+ " (Sense).\n Using AutoNegotiation On\n",
+ pAC->dev->name);
+ AutoNeg = AN_ON;
+ }
+
+ /* set the desired mode */
+ pAC->GIni.GP[1].PLinkModeConf =
+ Capabilities[AutoNeg][DuplexCap];
+
+ pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
+ if (FlowCtrl_B != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ FlowCtrl_B[pAC->Index] != NULL) {
+ if (strcmp(FlowCtrl_B[pAC->Index],"") == 0) {
+ }
+ else if (strcmp(FlowCtrl_B[pAC->Index],"SymOrRem") == 0) {
+ pAC->GIni.GP[1].PFlowCtrlMode =
+ SK_FLOW_MODE_SYM_OR_REM;
+ }
+ else if (strcmp(FlowCtrl_B[pAC->Index],"Sym")==0) {
+ pAC->GIni.GP[1].PFlowCtrlMode =
+ SK_FLOW_MODE_SYMMETRIC;
+ }
+ else if (strcmp(FlowCtrl_B[pAC->Index],"LocSend")==0) {
+ pAC->GIni.GP[1].PFlowCtrlMode =
+ SK_FLOW_MODE_LOC_SEND;
+ }
+ else if (strcmp(FlowCtrl_B[pAC->Index],"None")==0) {
+ pAC->GIni.GP[1].PFlowCtrlMode =
+ SK_FLOW_MODE_NONE;
+ }
+ else printk("Illegal value for FlowCtrl_B\n");
+ }
+ if (AutoNeg==AN_OFF && pAC->GIni.GP[1].PFlowCtrlMode!=
+ SK_FLOW_MODE_NONE) {
+ printk("%s, Port B: FlowControl"
+ " impossible without AutoNegotiation,"
+ " disabled\n", pAC->dev->name);
+ pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+ }
+
+ MSMode = SK_MS_MODE_AUTO; /* default: do auto select */
+ if (Role_B != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ Role_B[pAC->Index] != NULL) {
+ if (strcmp(Role_B[pAC->Index],"")==0) {
+ }
+ else if (strcmp(Role_B[pAC->Index],"Auto")==0) {
+ MSMode = SK_MS_MODE_AUTO;
+ }
+ else if (strcmp(Role_B[pAC->Index],"Master")==0) {
+ MSMode = SK_MS_MODE_MASTER;
+ }
+ else if (strcmp(Role_B[pAC->Index],"Slave")==0) {
+ MSMode = SK_MS_MODE_SLAVE;
+ }
+ else printk("%s: Illegal value for Role_B\n",
+ pAC->dev->name);
+ }
+ pAC->GIni.GP[1].PMSMode = MSMode;
+
+
+ /* settings for both ports */
+ pAC->ActivePort = 0;
+ if (PrefPort != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ PrefPort[pAC->Index] != NULL) {
+ if (strcmp(PrefPort[pAC->Index],"") == 0) { /* Auto */
+ pAC->ActivePort = 0;
+ pAC->Rlmt.MacPreferred = -1; /* auto */
+ pAC->Rlmt.PrefPort = 0;
+ }
+ else if (strcmp(PrefPort[pAC->Index],"A") == 0) {
+ /*
+ * do not set ActivePort here, thus a port
+ * switch is issued after net up.
+ */
+ Port = 0;
+ pAC->Rlmt.MacPreferred = Port;
+ pAC->Rlmt.PrefPort = Port;
+ }
+ else if (strcmp(PrefPort[pAC->Index],"B") == 0) {
+ /*
+ * do not set ActivePort here, thus a port
+ * switch is issued after net up.
+ */
+ Port = 1;
+ pAC->Rlmt.MacPreferred = Port;
+ pAC->Rlmt.PrefPort = Port;
+ }
+ else printk("%s: Illegal value for PrefPort\n",
+ pAC->dev->name);
+ }
+
+ if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
+ RlmtMode[pAC->Index] != NULL) {
+ if (strcmp(RlmtMode[pAC->Index], "") == 0) {
+ pAC->RlmtMode = 0;
+ }
+ else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
+ }
+ else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
+ pAC->RlmtMode = SK_RLMT_CHECK_LINK |
+ SK_RLMT_CHECK_LOC_LINK;
+ }
+ else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) {
+ pAC->RlmtMode = SK_RLMT_CHECK_LINK |
+ SK_RLMT_CHECK_LOC_LINK |
+ SK_RLMT_CHECK_SEG;
+ }
+ else {
+ printk("%s: Illegal value for"
+ " RlmtMode, using default\n", pAC->dev->name);
+ pAC->RlmtMode = 0;
+ }
+ }
+ else {
+ pAC->RlmtMode = 0;
+ }
+} /* GetConfiguration */
+
+
+/*****************************************************************************
+ *
+ * ProductStr - return a adapter identification string from vpd
+ *
+ * Description:
+ * This function reads the product name string from the vpd area
+ * and puts it the field pAC->DeviceString.
+ *
+ * Returns: N/A
+ */
+static void ProductStr(
+SK_AC *pAC /* pointer to adapter context */
+)
+{
+int StrLen = 80; /* length of the string, defined in SK_AC */
+char Keyword[] = VPD_NAME; /* vpd productname identifier */
+int ReturnCode; /* return code from vpd_read */
+unsigned int Flags;
+
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, pAC->DeviceStr,
+ &StrLen);
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ if (ReturnCode != 0) {
+ /* there was an error reading the vpd data */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
+ ("Error reading VPD data: %d\n", ReturnCode));
+ pAC->DeviceStr[0] = '\0';
+ }
+} /* ProductStr */
+
+
+
+
+/****************************************************************************/
+/* functions for common modules *********************************************/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * SkDrvAllocRlmtMbuf - allocate an RLMT mbuf
+ *
+ * Description:
+ * This routine returns an RLMT mbuf or NULL. The RLMT Mbuf structure
+ * is embedded into a socket buff data area.
+ *
+ * Context:
+ * runtime
+ *
+ * Returns:
+ * NULL or pointer to Mbuf.
+ */
+SK_MBUF *SkDrvAllocRlmtMbuf(
+SK_AC *pAC, /* pointer to adapter context */
+SK_IOC IoC, /* the IO-context */
+unsigned BufferSize) /* size of the requested buffer */
+{
+SK_MBUF *pRlmtMbuf; /* pointer to a new rlmt-mbuf structure */
+struct sk_buff *pMsgBlock; /* pointer to a new message block */
+
+ pMsgBlock = alloc_skb(BufferSize + sizeof(SK_MBUF), GFP_ATOMIC);
+ if (pMsgBlock == NULL) {
+ return (NULL);
+ }
+ pRlmtMbuf = (SK_MBUF*) pMsgBlock->data;
+ skb_reserve(pMsgBlock, sizeof(SK_MBUF));
+ pRlmtMbuf->pNext = NULL;
+ pRlmtMbuf->pOs = pMsgBlock;
+ pRlmtMbuf->pData = pMsgBlock->data; /* Data buffer. */
+ pRlmtMbuf->Size = BufferSize; /* Data buffer size. */
+ pRlmtMbuf->Length = 0; /* Length of packet (<= Size). */
+ return (pRlmtMbuf);
+
+} /* SkDrvAllocRlmtMbuf */
+
+
+/*****************************************************************************
+ *
+ * SkDrvFreeRlmtMbuf - free an RLMT mbuf
+ *
+ * Description:
+ * This routine frees one or more RLMT mbuf(s).
+ *
+ * Context:
+ * runtime
+ *
+ * Returns:
+ * Nothing
+ */
+void SkDrvFreeRlmtMbuf(
+SK_AC *pAC, /* pointer to adapter context */
+SK_IOC IoC, /* the IO-context */
+SK_MBUF *pMbuf) /* size of the requested buffer */
+{
+SK_MBUF *pFreeMbuf;
+SK_MBUF *pNextMbuf;
+
+ pFreeMbuf = pMbuf;
+ do {
+ pNextMbuf = pFreeMbuf->pNext;
+ DEV_KFREE_SKB(pFreeMbuf->pOs);
+ pFreeMbuf = pNextMbuf;
+ } while ( pFreeMbuf != NULL );
+} /* SkDrvFreeRlmtMbuf */
+
+
+/*****************************************************************************
+ *
+ * SkOsGetTime - provide a time value
+ *
+ * Description:
+ * This routine provides a time value. The unit is 1/HZ (defined by Linux).
+ * It is not used for absolute time, but only for time differences.
+ *
+ *
+ * Returns:
+ * Time value
+ */
+SK_U64 SkOsGetTime(SK_AC *pAC)
+{
+ return jiffies;
+} /* SkOsGetTime */
+
+
+/*****************************************************************************
+ *
+ * SkPciReadCfgDWord - read a 32 bit value from pci config space
+ *
+ * Description:
+ * This routine reads a 32 bit value from the pci configuration
+ * space.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciReadCfgDWord(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U32 *pVal) /* pointer to store the read value */
+{
+ pci_read_config_dword(&pAC->PciDev, PciAddr, pVal);
+ return(0);
+} /* SkPciReadCfgDWord */
+
+
+/*****************************************************************************
+ *
+ * SkPciReadCfgWord - read a 16 bit value from pci config space
+ *
+ * Description:
+ * This routine reads a 16 bit value from the pci configuration
+ * space.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciReadCfgWord(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U16 *pVal) /* pointer to store the read value */
+{
+ pci_read_config_word(&pAC->PciDev, PciAddr, pVal);
+ return(0);
+} /* SkPciReadCfgWord */
+
+
+/*****************************************************************************
+ *
+ * SkPciReadCfgByte - read a 8 bit value from pci config space
+ *
+ * Description:
+ * This routine reads a 8 bit value from the pci configuration
+ * space.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciReadCfgByte(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U8 *pVal) /* pointer to store the read value */
+{
+ pci_read_config_byte(&pAC->PciDev, PciAddr, pVal);
+ return(0);
+} /* SkPciReadCfgByte */
+
+
+/*****************************************************************************
+ *
+ * SkPciWriteCfgDWord - write a 32 bit value to pci config space
+ *
+ * Description:
+ * This routine writes a 32 bit value to the pci configuration
+ * space.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciWriteCfgDWord(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U32 Val) /* pointer to store the read value */
+{
+ pci_write_config_dword(&pAC->PciDev, PciAddr, Val);
+ return(0);
+} /* SkPciWriteCfgDWord */
+
+
+/*****************************************************************************
+ *
+ * SkPciWriteCfgWord - write a 16 bit value to pci config space
+ *
+ * Description:
+ * This routine writes a 16 bit value to the pci configuration
+ * space. The flag PciConfigUp indicates whether the config space
+ * is accesible or must be set up first.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciWriteCfgWord(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U16 Val) /* pointer to store the read value */
+{
+ pci_write_config_word(&pAC->PciDev, PciAddr, Val);
+ return(0);
+} /* SkPciWriteCfgWord */
+
+
+/*****************************************************************************
+ *
+ * SkPciWriteCfgWord - write a 8 bit value to pci config space
+ *
+ * Description:
+ * This routine writes a 8 bit value to the pci configuration
+ * space. The flag PciConfigUp indicates whether the config space
+ * is accesible or must be set up first.
+ *
+ * Returns:
+ * 0 - indicate everything worked ok.
+ * != 0 - error indication
+ */
+int SkPciWriteCfgByte(
+SK_AC *pAC, /* Adapter Control structure pointer */
+int PciAddr, /* PCI register address */
+SK_U8 Val) /* pointer to store the read value */
+{
+ pci_write_config_byte(&pAC->PciDev, PciAddr, Val);
+ return(0);
+} /* SkPciWriteCfgByte */
+
+
+/*****************************************************************************
+ *
+ * SkDrvEvent - handle driver events
+ *
+ * Description:
+ * This function handles events from all modules directed to the driver
+ *
+ * Context:
+ * Is called under protection of slow path lock.
+ *
+ * Returns:
+ * 0 if everything ok
+ * < 0 on error
+ *
+ */
+int SkDrvEvent(
+SK_AC *pAC, /* pointer to adapter context */
+SK_IOC IoC, /* io-context */
+SK_U32 Event, /* event-id */
+SK_EVPARA Param) /* event-parameter */
+{
+SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
+struct sk_buff *pMsg; /* pointer to a message block */
+int FromPort; /* the port from which we switch away */
+int ToPort; /* the port we switch to */
+SK_EVPARA NewPara; /* parameter for further events */
+int Stat;
+unsigned int Flags;
+
+ switch (Event) {
+ case SK_DRV_ADAP_FAIL:
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("ADAPTER FAIL EVENT\n"));
+ printk("%s: Adapter failed.\n", pAC->dev->name);
+ /* disable interrupts */
+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+ /* cgoos */
+ break;
+ case SK_DRV_PORT_FAIL:
+ FromPort = Param.Para32[0];
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("PORT FAIL EVENT, Port: %d\n", FromPort));
+ if (FromPort == 0) {
+ printk("%s: Port A failed.\n", pAC->dev->name);
+ } else {
+ printk("%s: Port B failed.\n", pAC->dev->name);
+ }
+ /* cgoos */
+ break;
+ case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */
+ /* action list 4 */
+ FromPort = Param.Para32[0];
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("PORT RESET EVENT, Port: %d ", FromPort));
+ NewPara.Para64 = FromPort;
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
+ spin_lock_irqsave(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+
+ /* clear rx ring from received frames */
+ ReceiveIrq(pAC, &pAC->RxPort[FromPort]);
+
+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
+ spin_lock_irqsave(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ SkGeInitPort(pAC, IoC, FromPort);
+ SkAddrMcUpdate(pAC,IoC, FromPort);
+ PortReInitBmu(pAC, FromPort);
+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
+ ClearAndStartRx(pAC, FromPort);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ break;
+ case SK_DRV_NET_UP: /* SK_U32 PortIdx */
+ /* action list 5 */
+ FromPort = Param.Para32[0];
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("NET UP EVENT, Port: %d ", Param.Para32[0]));
+ printk("%s: network connection up using"
+ " port %c\n", pAC->dev->name, 'A'+Param.Para32[0]);
+ printk(" speed: 1000\n");
+ Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
+ if (Stat == SK_LMODE_STAT_AUTOHALF ||
+ Stat == SK_LMODE_STAT_AUTOFULL) {
+ printk(" autonegotiation: yes\n");
+ }
+ else {
+ printk(" autonegotiation: no\n");
+ }
+ if (Stat == SK_LMODE_STAT_AUTOHALF ||
+ Stat == SK_LMODE_STAT_HALF) {
+ printk(" duplex mode: half\n");
+ }
+ else {
+ printk(" duplex mode: full\n");
+ }
+ Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
+ if (Stat == SK_FLOW_STAT_REM_SEND ) {
+ printk(" flowctrl: remote send\n");
+ }
+ else if (Stat == SK_FLOW_STAT_LOC_SEND ){
+ printk(" flowctrl: local send\n");
+ }
+ else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
+ printk(" flowctrl: symmetric\n");
+ }
+ else {
+ printk(" flowctrl: none\n");
+ }
+ if (pAC->GIni.GP[FromPort].PhyType != SK_PHY_XMAC) {
+ Stat = pAC->GIni.GP[FromPort].PMSStatus;
+ if (Stat == SK_MS_STAT_MASTER ) {
+ printk(" role: master\n");
+ }
+ else if (Stat == SK_MS_STAT_SLAVE ) {
+ printk(" role: slave\n");
+ }
+ else {
+ printk(" role: ???\n");
+ }
+ }
+
+ if (Param.Para32[0] != pAC->ActivePort) {
+ NewPara.Para32[0] = pAC->ActivePort;
+ NewPara.Para32[1] = Param.Para32[0];
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
+ NewPara);
+ }
+ break;
+ case SK_DRV_NET_DOWN: /* SK_U32 Reason */
+ /* action list 7 */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("NET DOWN EVENT "));
+ printk("%s: network connection down\n", pAC->dev->name);
+ break;
+ case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("PORT SWITCH HARD "));
+ case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
+ /* action list 6 */
+ printk("%s: switching to port %c\n", pAC->dev->name,
+ 'A'+Param.Para32[1]);
+ case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
+ FromPort = Param.Para32[0];
+ ToPort = Param.Para32[1];
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ",
+ FromPort, ToPort, pAC->Rlmt.PrefPort));
+ NewPara.Para64 = FromPort;
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
+ NewPara.Para64 = ToPort;
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
+ spin_lock_irqsave(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ spin_lock_irqsave(
+ &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags);
+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
+ SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+
+ ReceiveIrq(pAC, &pAC->RxPort[FromPort]); /* clears rx ring */
+ ReceiveIrq(pAC, &pAC->RxPort[ToPort]); /* clears rx ring */
+
+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
+ ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
+ spin_lock_irqsave(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ spin_lock_irqsave(
+ &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags);
+ pAC->ActivePort = ToPort;
+ SetQueueSizes(pAC);
+ SkGeInitPort(pAC, IoC, FromPort);
+ SkGeInitPort(pAC, IoC, ToPort);
+ if (Event == SK_DRV_SWITCH_SOFT) {
+ SkXmRxTxEnable(pAC, IoC, FromPort);
+ }
+ SkXmRxTxEnable(pAC, IoC, ToPort);
+ SkAddrSwap(pAC, IoC, FromPort, ToPort);
+ SkAddrMcUpdate(pAC, IoC, FromPort);
+ SkAddrMcUpdate(pAC, IoC, ToPort);
+ PortReInitBmu(pAC, FromPort);
+ PortReInitBmu(pAC, ToPort);
+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
+ SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
+ ClearAndStartRx(pAC, FromPort);
+ ClearAndStartRx(pAC, ToPort);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags);
+ spin_unlock_irqrestore(
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ Flags);
+ break;
+ case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("RLS "));
+ pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
+ pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
+ skb_put(pMsg, pRlmtMbuf->Length);
+ XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
+ pMsg);
+ break;
+ default:
+ break;
+ }
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+ ("END EVENT "));
+
+ return (0);
+} /* SkDrvEvent */
+
+
+/*****************************************************************************
+ *
+ * SkErrorLog - log errors
+ *
+ * Description:
+ * This function logs errors to the system buffer and to the console
+ *
+ * Returns:
+ * 0 if everything ok
+ * < 0 on error
+ *
+ */
+void SkErrorLog(
+SK_AC *pAC,
+int ErrClass,
+int ErrNum,
+char *pErrorMsg)
+{
+char ClassStr[80];
+
+ switch (ErrClass) {
+ case SK_ERRCL_OTHER:
+ strcpy(ClassStr, "Other error");
+ break;
+ case SK_ERRCL_CONFIG:
+ strcpy(ClassStr, "Configuration error");
+ break;
+ case SK_ERRCL_INIT:
+ strcpy(ClassStr, "Initialization error");
+ break;
+ case SK_ERRCL_NORES:
+ strcpy(ClassStr, "Out of resources error");
+ break;
+ case SK_ERRCL_SW:
+ strcpy(ClassStr, "internal Software error");
+ break;
+ case SK_ERRCL_HW:
+ strcpy(ClassStr, "Hardware failure");
+ break;
+ case SK_ERRCL_COMM:
+ strcpy(ClassStr, "Communication error");
+ break;
+ }
+ printk(KERN_INFO "%s: -- ERROR --\n Class: %s\n"
+ " Nr: 0x%x\n Msg: %s\n", pAC->dev->name,
+ ClassStr, ErrNum, pErrorMsg);
+
+} /* SkErrorLog */
+
+#ifdef DEBUG /***************************************************************/
+/* "debug only" section *****************************************************/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * DumpMsg - print a frame
+ *
+ * Description:
+ * This function prints frames to the system logfile/to the console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpMsg(struct sk_buff *skb, char *str)
+{
+ int msglen;
+
+ if (skb == NULL) {
+ printk("DumpMsg(): NULL-Message\n");
+ return;
+ }
+
+ if (skb->data == NULL) {
+ printk("DumpMsg(): Message empty\n");
+ return;
+ }
+
+ msglen = skb->len;
+ if (msglen > 64)
+ msglen = 64;
+
+ printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
+
+ DumpData((char *)skb->data, msglen);
+
+ printk("------- End of message ---------\n");
+} /* DumpMsg */
+
+
+
+/*****************************************************************************
+ *
+ * DumpData - print a data area
+ *
+ * Description:
+ * This function prints a area of data to the system logfile/to the
+ * console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpData(char *p, int size)
+{
+register int i;
+int haddr, addr;
+char hex_buffer[180];
+char asc_buffer[180];
+char HEXCHAR[] = "0123456789ABCDEF";
+
+ addr = 0;
+ haddr = 0;
+ hex_buffer[0] = 0;
+ asc_buffer[0] = 0;
+ for (i=0; i < size; ) {
+ if (*p >= '0' && *p <='z')
+ asc_buffer[addr] = *p;
+ else
+ asc_buffer[addr] = '.';
+ addr++;
+ asc_buffer[addr] = 0;
+ hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[*p & 0x0f];
+ haddr++;
+ hex_buffer[haddr] = ' ';
+ haddr++;
+ hex_buffer[haddr] = 0;
+ p++;
+ i++;
+ if (i%16 == 0) {
+ printk("%s %s\n", hex_buffer, asc_buffer);
+ addr = 0;
+ haddr = 0;
+ }
+ }
+} /* DumpData */
+
+
+/*****************************************************************************
+ *
+ * DumpLong - print a data area as long values
+ *
+ * Description:
+ * This function prints a area of data to the system logfile/to the
+ * console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpLong(char *pc, int size)
+{
+register int i;
+int haddr, addr;
+char hex_buffer[180];
+char asc_buffer[180];
+char HEXCHAR[] = "0123456789ABCDEF";
+long *p;
+int l;
+
+ addr = 0;
+ haddr = 0;
+ hex_buffer[0] = 0;
+ asc_buffer[0] = 0;
+ p = (long*) pc;
+ for (i=0; i < size; ) {
+ l = (long) *p;
+ hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 24) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 20) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 16) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 12) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 8) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[(l >> 4) & 0xf];
+ haddr++;
+ hex_buffer[haddr] = HEXCHAR[l & 0x0f];
+ haddr++;
+ hex_buffer[haddr] = ' ';
+ haddr++;
+ hex_buffer[haddr] = 0;
+ p++;
+ i++;
+ if (i%8 == 0) {
+ printk("%4x %s\n", (i-8)*4, hex_buffer);
+ haddr = 0;
+ }
+ }
+ printk("------------------------\n");
+} /* DumpLong */
+
+#endif /* DEBUG */
+
+/*
+ * Local variables:
+ * compile-command: "make"
+ * End:
+ */
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgehwt.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.12 $
+ * Date: $Date: 1998/10/15 15:11:34 $
+ * Purpose: Hardware Timer.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgehwt.c,v $
+ * Revision 1.12 1998/10/15 15:11:34 gklug
+ * fix: ID_sccs to SysKonnectFileId
+ *
+ * Revision 1.11 1998/10/08 15:27:51 gklug
+ * chg: correction factor is host clock dependent
+ *
+ * Revision 1.10 1998/09/15 14:18:31 cgoos
+ * Changed more BOOLEANs to SK_xxx
+ *
+ * Revision 1.9 1998/09/15 14:16:06 cgoos
+ * Changed line 107: FALSE to SK_FALSE
+ *
+ * Revision 1.8 1998/08/24 13:04:44 gklug
+ * fix: typo
+ *
+ * Revision 1.7 1998/08/19 09:50:49 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.6 1998/08/17 09:59:02 gklug
+ * fix: typos
+ *
+ * Revision 1.5 1998/08/14 07:09:10 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.4 1998/08/10 14:14:52 gklug
+ * rmv: unneccessary SK_ADDR macro
+ *
+ * Revision 1.3 1998/08/07 12:53:44 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.2 1998/08/07 09:19:29 gklug
+ * adapt functions to the C coding conventions
+ * rmv unneccessary functions.
+ *
+ * Revision 1.1 1998/08/05 11:28:36 gklug
+ * first version: adapted from SMT/FDDI
+ *
+ *
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ Event queue and dispatcher
+*/
+static const char SysKonnectFileId[] =
+ "$Header: /usr56/projects/ge/schedule/skgehwt.c,v 1.12 1998/10/15 15:11:34 gklug Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+ Hardware Timer function queue management.
+
+ General Description:
+
+ */
+intro()
+{}
+#endif
+
+/*
+ * Prototypes of local functions.
+ */
+#define SK_HWT_MAX (65000)
+
+/* correction factor */
+#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
+
+/*
+ * Initialize hardware timer.
+ *
+ * Must be called during init level 1.
+ */
+void SkHwtInit(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc) /* IoContext */
+{
+ pAC->Hwt.TStart = 0 ;
+ pAC->Hwt.TStop = 0 ;
+ pAC->Hwt.TActive = SK_FALSE ;
+
+ SkHwtStop(pAC,Ioc) ;
+}
+
+/*
+ *
+ * Start hardware timer (clock ticks are 16us).
+ *
+ */
+void SkHwtStart(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc, /* IoContext */
+SK_U32 Time) /* Time in units of 16us to load the timer with. */
+{
+ SK_U32 Cnt ;
+
+ if (Time > SK_HWT_MAX)
+ Time = SK_HWT_MAX ;
+
+ pAC->Hwt.TStart = Time ;
+ pAC->Hwt.TStop = 0L ;
+
+ Cnt = Time ;
+
+ /*
+ * if time < 16 us
+ * time = 16 us
+ */
+ if (!Cnt) {
+ Cnt++ ;
+ }
+
+ SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC) ;
+ SK_OUT16(Ioc, B2_TI_CRTL, TIM_START) ; /* Start timer. */
+
+ pAC->Hwt.TActive = SK_TRUE ;
+}
+
+/*
+ * Stop hardware timer.
+ * and clear the timer IRQ
+ */
+void SkHwtStop(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc) /* IoContext */
+{
+ SK_OUT16(Ioc, B2_TI_CRTL, TIM_STOP) ;
+ SK_OUT16(Ioc, B2_TI_CRTL, TIM_CLR_IRQ) ;
+
+ pAC->Hwt.TActive = SK_FALSE ;
+}
+
+
+/*
+ * Stop hardware timer and read time elapsed since last start.
+ *
+ * returns
+ * The elapsed time since last start in units of 16us.
+ *
+ */
+SK_U32 SkHwtRead(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc) /* IoContext */
+{
+ SK_U32 TRead ;
+ SK_U32 IStatus ;
+
+ if (pAC->Hwt.TActive) {
+ SkHwtStop(pAC,Ioc) ;
+
+ SK_IN32(Ioc, B2_TI_VAL, &TRead);
+ TRead /= SK_HWT_FAC;
+
+ SK_IN32(Ioc, B0_ISRC, &IStatus);
+
+ /* Check if timer expired (or wraparound). */
+ if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
+ SkHwtStop(pAC,Ioc) ;
+ pAC->Hwt.TStop = pAC->Hwt.TStart ;
+ } else {
+ pAC->Hwt.TStop = pAC->Hwt.TStart - TRead ;
+ }
+ }
+ return (pAC->Hwt.TStop) ;
+}
+
+/*
+ * interrupt source= timer
+ */
+void SkHwtIsr(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc) /* IoContext */
+{
+ SkHwtStop(pAC,Ioc);
+ pAC->Hwt.TStop = pAC->Hwt.TStart;
+ SkTimerDone(pAC,Ioc) ;
+}
+
+/* End of file */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgeinit.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.54 $
+ * Date: $Date: 1999/10/26 07:32:54 $
+ * Purpose: Contains functions to initialize the GE HW
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgeinit.c,v $
+ * Revision 1.54 1999/10/26 07:32:54 malthoff
+ * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
+ *
+ * Revision 1.53 1999/08/12 19:13:50 malthoff
+ * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
+ * disabling receiver and transmitter. Other bits
+ * may be lost.
+ *
+ * Revision 1.52 1999/07/01 09:29:54 gklug
+ * fix: DoInitRamQueue needs pAC
+ *
+ * Revision 1.51 1999/07/01 08:42:21 gklug
+ * chg: use Store & forward for RAM buffer when Jumbos are used
+ *
+ * Revision 1.50 1999/05/27 13:19:38 cgoos
+ * Added Tx PCI watermark initialization.
+ * Removed Tx RAM queue Store & Forward setting.
+ *
+ * Revision 1.49 1999/05/20 14:32:45 malthoff
+ * SkGeLinkLED() is completly removed now.
+ *
+ * Revision 1.48 1999/05/19 07:28:24 cgoos
+ * SkGeLinkLED no more available for drivers.
+ * Changes for 1000Base-T.
+ *
+ * Revision 1.47 1999/04/08 13:57:45 gklug
+ * add: Init of new port struct fiels PLinkResCt
+ * chg: StopPort Timer check
+ *
+ * Revision 1.46 1999/03/25 07:42:15 malthoff
+ * SkGeStopPort(): Add workaround for cache incoherency.
+ * Create error log entry, disable port, and
+ * exit loop if it does not terminate.
+ * Add XM_RX_LENERR_OK to the default value for the
+ * XMAC receive command register.
+ *
+ * Revision 1.45 1999/03/12 16:24:47 malthoff
+ * Remove PPollRxD and PPollTxD.
+ * Add check for GIPollTimerVal.
+ *
+ * Revision 1.44 1999/03/12 13:40:23 malthoff
+ * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
+ * Add: Jumbo frame support.
+ * Chg: Resolution of parameter IntTime in SkGeCfgSync().
+ *
+ * Revision 1.43 1999/02/09 10:29:46 malthoff
+ * Bugfix: The previous modification again also for the second location.
+ *
+ * Revision 1.42 1999/02/09 09:35:16 malthoff
+ * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
+ * clearing the error bits in the PCI status register.
+ *
+ * Revision 1.41 1999/01/18 13:07:02 malthoff
+ * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
+ * they may not be available after Boottime.
+ *
+ * Revision 1.40 1999/01/11 12:40:49 malthoff
+ * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
+ *
+ * Revision 1.39 1998/12/11 15:17:33 gklug
+ * chg: Init LipaAutoNeg with Unknown
+ *
+ * Revision 1.38 1998/12/10 11:02:57 malthoff
+ * Disable Error Log Message when calling SkGeInit(level 2)
+ * more than once.
+ *
+ * Revision 1.37 1998/12/07 12:18:25 gklug
+ * add: refinement of autosense mode: take into account the autoneg cap of LiPa
+ *
+ * Revision 1.36 1998/12/07 07:10:39 gklug
+ * fix: init values of LinkBroken/ Capabilities for management
+ *
+ * Revision 1.35 1998/12/02 10:56:20 gklug
+ * fix: do NOT init LoinkSync Counter.
+ *
+ * Revision 1.34 1998/12/01 10:53:21 gklug
+ * add: init of additional Counters for workaround
+ *
+ * Revision 1.33 1998/12/01 10:00:49 gklug
+ * add: init PIsave var in Port struct
+ *
+ * Revision 1.32 1998/11/26 14:50:40 gklug
+ * chg: Default is autosensing with AUTOFULL mode
+ *
+ * Revision 1.31 1998/11/25 15:36:16 gklug
+ * fix: do NOT stop LED Timer when port should be stoped
+ *
+ * Revision 1.30 1998/11/24 13:15:28 gklug
+ * add: Init PCkeckPar struct member
+ *
+ * Revision 1.29 1998/11/18 13:19:27 malthoff
+ * Disable packet arbiter timeouts on receive side.
+ * Use maximum timeout value for packet arbiter
+ * transmit timeouts.
+ * Add TestStopBit() function to handle stop RX/TX
+ * problem with active descriptor poll timers.
+ * Bug Fix: Descriptor Poll Timer not started, beacuse
+ * GIPollTimerVal was initilaized with 0.
+ *
+ * Revision 1.28 1998/11/13 14:24:26 malthoff
+ * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
+ * is pending or occurs while waiting for TX_STOP and RX_STOP.
+ * The PA timeout is cleared now while waiting for TX- or RX_STOP.
+ *
+ * Revision 1.27 1998/11/02 11:04:36 malthoff
+ * fix the last fix
+ *
+ * Revision 1.26 1998/11/02 10:37:03 malthoff
+ * Fix: SkGePollTxD() enables always the synchronounous poll timer.
+ *
+ * Revision 1.25 1998/10/28 07:12:43 cgoos
+ * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
+ * Removed: Reset of RAM Interface in SkGeStopPort.
+ *
+ * Revision 1.24 1998/10/27 08:13:12 malthoff
+ * Remove temporary code.
+ *
+ * Revision 1.23 1998/10/26 07:45:03 malthoff
+ * Add Address Calculation Workaround: If the EPROM byte
+ * Id is 3, the address offset is 512 kB.
+ * Initialize default values for PLinkMode and PFlowCtrlMode.
+ *
+ * Revision 1.22 1998/10/22 09:46:47 gklug
+ * fix SysKonnectFileId typo
+ *
+ * Revision 1.21 1998/10/20 12:11:56 malthoff
+ * Don't dendy the Queue config if the size of the unused
+ * rx qeueu is zero.
+ *
+ * Revision 1.20 1998/10/19 07:27:58 malthoff
+ * SkGeInitRamIface() is public to be called by diagnostics.
+ *
+ * Revision 1.19 1998/10/16 13:33:45 malthoff
+ * Fix: enabling descriptor polling is not allowed until
+ * the descriptor addresses are set. Descriptor polling
+ * must be handled by the driver.
+ *
+ * Revision 1.18 1998/10/16 10:58:27 malthoff
+ * Remove temp. code for Diag prototype.
+ * Remove lint warning for dummy reads.
+ * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
+ *
+ * Revision 1.17 1998/10/14 09:16:06 malthoff
+ * Change parameter LimCount and programming of
+ * the limit counter in SkGeCfgSync().
+ *
+ * Revision 1.16 1998/10/13 09:21:16 malthoff
+ * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
+ * like a Loopback Mode in half duplex.
+ *
+ * Revision 1.15 1998/10/09 06:47:40 malthoff
+ * SkGeInitMacArb(): set recovery counters init value
+ * to zero although this counters are not uesd.
+ * Bug fix in Rx Upper/Lower Pause Threshold calculation.
+ * Add XM_RX_SELF_RX to RxCmd.
+ *
+ * Revision 1.14 1998/10/06 15:15:53 malthoff
+ * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
+ *
+ * Revision 1.13 1998/10/06 14:09:36 malthoff
+ * Add SkGeLoadLnkSyncCnt(). Modify
+ * the 'port stopped' condition according
+ * to the current problem report.
+ *
+ * Revision 1.12 1998/10/05 08:17:21 malthoff
+ * Add functions: SkGePollRxD(), SkGePollTxD(),
+ * DoCalcAddr(), SkGeCheckQSize(),
+ * DoInitRamQueue(), and SkGeCfgSync().
+ * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
+ * SkGeInitMacFifo(), SkGeInitRamBufs(),
+ * SkGeInitRamIface(), and SkGeInitBmu().
+ *
+ * Revision 1.11 1998/09/29 08:26:29 malthoff
+ * bug fix: SkGeInit0() 'i' should be increment.
+ *
+ * Revision 1.10 1998/09/28 13:19:01 malthoff
+ * Coding time: Save the done work.
+ * Modify SkGeLinkLED(), add SkGeXmitLED(),
+ * define SkGeCheckQSize(), SkGeInitMacArb(),
+ * SkGeInitPktArb(), SkGeInitMacFifo(),
+ * SkGeInitRamBufs(), SkGeInitRamIface(),
+ * and SkGeInitBmu(). Do coding for SkGeStopPort(),
+ * SkGeInit1(), SkGeInit2(), and SkGeInit3().
+ * Do coding for SkGeDinit() and SkGeInitPort().
+ *
+ * Revision 1.9 1998/09/16 14:29:05 malthoff
+ * Some minor changes.
+ *
+ * Revision 1.8 1998/09/11 05:29:14 gklug
+ * add: init state of a port
+ *
+ * Revision 1.7 1998/09/04 09:26:25 malthoff
+ * Short temporary modification.
+ *
+ * Revision 1.6 1998/09/04 08:27:59 malthoff
+ * Remark the do-while in StopPort() because it never ends
+ * without a GE adapter.
+ *
+ * Revision 1.5 1998/09/03 14:05:45 malthoff
+ * Change comment for SkGeInitPort(). Do not
+ * repair the queue sizes if invalid.
+ *
+ * Revision 1.4 1998/09/03 10:03:19 malthoff
+ * Implement the new interface according to the
+ * reviewed interface specification.
+ *
+ * Revision 1.3 1998/08/19 09:11:25 gklug
+ * fix: struct are removed from c-source (see CCC)
+ *
+ * Revision 1.2 1998/07/28 12:33:58 malthoff
+ * Add 'IoC' parameter in function declaration and SK IO macros.
+ *
+ * Revision 1.1 1998/07/23 09:48:57 malthoff
+ * Creation. First dummy 'C' file.
+ * SkGeInit(Level 0) is card_start for ML.
+ * SkGeDeInit() is card_stop for ML.
+ *
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/xmac_ii.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+/* defines for SkGeXmitLed() */
+#define XMIT_LED_INI 0
+#define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI)
+#define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI)
+#define XMIT_LED_TST (RX_LED_TST - RX_LED_INI)
+
+/* Queue Size units */
+#define QZ_UNITS 0x7
+
+/* Types of RAM Buffer Queues */
+#define SK_RX_SRAM_Q 1 /* small receive queue */
+#define SK_RX_BRAM_Q 2 /* big receive queue */
+#define SK_TX_RAM_Q 3 /* small or big transmit queue */
+
+/* typedefs *******************************************************************/
+/* global variables ***********************************************************/
+
+/* local variables ************************************************************/
+
+static const char SysKonnectFileId[] =
+ "@(#)$Id: skgeinit.c,v 1.54 1999/10/26 07:32:54 malthoff Exp $ (C) SK ";
+
+struct s_QOffTab {
+ int RxQOff; /* Receive Queue Address Offset */
+ int XsQOff; /* Sync Tx Queue Address Offset */
+ int XaQOff; /* Async Tx Queue Address Offset */
+};
+static struct s_QOffTab QOffTab[] = {
+ { Q_R1, Q_XS1, Q_XA1 }, { Q_R2, Q_XS2, Q_XA2 }
+};
+
+
+/******************************************************************************
+ *
+ * SkGePollRxD() - Enable/Disable Descriptor Polling of RxD Ring
+ *
+ * Description:
+ * Enable or disable the descriptor polling the receive descriptor
+ * ring (RxD) of port 'port'.
+ * The new configuration is *not* saved over any SkGeStopPort() and
+ * SkGeInitPort() calls.
+ *
+ * Returns:
+ * nothing
+ */
+void SkGePollRxD(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (PollRxD) {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_CSR), CSR_ENA_POL);
+ }
+ else {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_CSR), CSR_DIS_POL);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGePollTxD() - Enable/Disable Descriptor Polling of TxD Rings
+ *
+ * Description:
+ * Enable or disable the descriptor polling the transmit descriptor
+ * ring(s) (RxD) of port 'port'.
+ * The new configuration is *not* saved over any SkGeStopPort() and
+ * SkGeInitPort() calls.
+ *
+ * Returns:
+ * nothing
+ */
+void SkGePollTxD(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
+{
+ SK_GEPORT *pPrt;
+ SK_U32 DWord;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (PollTxD) {
+ DWord = CSR_ENA_POL;
+ }
+ else {
+ DWord = CSR_DIS_POL;
+ }
+
+ if (pPrt->PXSQSize != 0) {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff,Q_CSR), DWord);
+ }
+ if (pPrt->PXAQSize != 0) {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff,Q_CSR), DWord);
+ }
+}
+
+
+/******************************************************************************
+ *
+ * SkGeYellowLED() - Switch the yellow LED on or off.
+ *
+ * Description:
+ * Switch the yellow LED on or off.
+ *
+ * Note:
+ * This function may be called any time after SkGeInit(Level 1).
+ *
+ * Returns:
+ * nothing
+ */
+void SkGeYellowLED(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int State) /* yellow LED state, 0 = OFF, 0 != ON */
+{
+ if (State == 0) {
+ /* Switch yellow LED OFF */
+ SK_OUT8(IoC, B0_LED, LED_STAT_OFF) ;
+ }
+ else {
+ /* Switch yellow LED ON */
+ SK_OUT8(IoC, B0_LED, LED_STAT_ON) ;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
+ *
+ * Description:
+ * The Rx or Tx LED which is specified by 'Led' will be
+ * enabled, disabled or switched on in test mode.
+ *
+ * Note:
+ * 'Led' must contain the address offset of the LEDs INI register.
+ *
+ * Usage:
+ * SkGeXmitLED(pAC, IoC, MR_ADDR(Port,TX_LED_INI), SK_LED_ENA);
+ *
+ * Returns:
+ * nothing
+ */
+void SkGeXmitLED(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Led, /* offset to the LED Init Value register */
+int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
+{
+ SK_U32 LedIni;
+
+ switch (Mode) {
+ case SK_LED_ENA:
+ LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
+ SK_OUT32(IoC, Led+XMIT_LED_INI, LedIni);
+ SK_OUT8(IoC, Led+XMIT_LED_CTRL, LED_START);
+ break ;
+ case SK_LED_TST:
+ SK_OUT8(IoC, Led+XMIT_LED_TST, LED_T_ON);
+ SK_OUT32(IoC, Led+XMIT_LED_CNT, 100);
+ SK_OUT8(IoC, Led+XMIT_LED_CTRL, LED_START);
+ break ;
+ case SK_LED_DIS:
+ default:
+ /*
+ * Do NOT stop the LED Timer here. The LED might be
+ * in on state. But it needs to go off.
+ */
+ SK_OUT32(IoC, Led+XMIT_LED_CNT, 0);
+ SK_OUT8(IoC, Led+XMIT_LED_TST, LED_T_OFF);
+ break ;
+ }
+
+ /*
+ * 1000BT: The Transmit LED is driven by the PHY.
+ * But the default LED configuration is used for
+ * Level One and Broadcom PHYs.
+ * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
+ * (In this case it has to be added here. But we will see. XXX)
+ */
+}
+
+/******************************************************************************
+ *
+ * DoCalcAddr() - Calculates the start and the end address of a queue.
+ *
+ * Description:
+ * This function calculates the start- end the end address
+ * of a queue. Afterwards the 'StartVal' is incremented to the
+ * next start position.
+ * If the port is already initialized the calculated values
+ * will be checked against the configured values and an
+ * error will be returned, if they are not equal.
+ * If the port is not initialized the values will be written to
+ * *StartAdr and *EndAddr.
+ *
+ * Returns:
+ * 0: success
+ * 1: configuration error
+ */
+static int DoCalcAddr(
+SK_AC *pAC, /* adapter context */
+SK_GEPORT *pPrt, /* port index */
+int QuSize, /* size of the queue to configure in kB */
+SK_U32 *StartVal, /* start value for address calculation */
+SK_U32 *QuStartAddr, /* start addr to calculate */
+SK_U32 *QuEndAddr) /* end address to calculate */
+{
+ SK_U32 EndVal;
+ SK_U32 NextStart;
+ int Rtv;
+
+ Rtv = 0;
+ if (QuSize == 0) {
+ EndVal = *StartVal;
+ NextStart = EndVal;
+ }
+ else {
+ EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
+ NextStart = EndVal + 1;
+ }
+
+ if (pPrt->PState >= SK_PRT_INIT) {
+ if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
+ Rtv = 1;
+ }
+ }
+ else {
+ *QuStartAddr = *StartVal;
+ *QuEndAddr = EndVal;
+ }
+
+ *StartVal = NextStart;
+ return (Rtv);
+}
+
+
+/******************************************************************************
+ *
+ * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
+ *
+ * Description:
+ * This function verifies the Queue Size Configuration specified
+ * in the variabels PRxQSize, PXSQSize, and PXAQSize of all
+ * used ports.
+ * This requirements must be fullfilled to have a valid configuration:
+ * - The size of all queues must not exceed GIRamSize.
+ * - The queue sizes must be specified in units of 8 kB.
+ * - The size of rx queues of available ports must not be
+ * smaller than 16kB.
+ * - The RAM start and end addresses must not be changed
+ * for ports which are already initialized.
+ * Furthermore SkGeCheckQSize() defines the Start and End
+ * Addresses of all ports and stores them into the HWAC port
+ * structure.
+ *
+ * Returns:
+ * 0: Queue Size Configuration valid
+ * 1: Queue Size Configuration invalid
+ */
+static int SkGeCheckQSize(
+SK_AC *pAC, /* adapter context */
+int Port) /* port index */
+{
+ SK_GEPORT *pPrt;
+ int UsedMem;
+ int i;
+ int Rtv;
+ int Rtv2;
+ SK_U32 StartAddr;
+
+ UsedMem = 0;
+ Rtv = 0;
+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+ pPrt = &pAC->GIni.GP[i];
+
+ if (( pPrt->PRxQSize & QZ_UNITS) ||
+ (pPrt->PXSQSize & QZ_UNITS) ||
+ (pPrt->PXAQSize & QZ_UNITS)) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SKERR_HWI_E012,
+ SKERR_HWI_E012MSG);
+ Rtv = 1;
+ goto CheckQSizeEnd;
+ }
+
+ UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
+
+ if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SKERR_HWI_E011,
+ SKERR_HWI_E011MSG);
+ Rtv = 1;
+ goto CheckQSizeEnd;
+ }
+ }
+ if (UsedMem > pAC->GIni.GIRamSize) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
+ Rtv = 1;
+ goto CheckQSizeEnd;
+ }
+
+ /* Now start address calculation */
+ StartAddr = pAC->GIni.GIRamOffs;
+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+ pPrt = &pAC->GIni.GP[i];
+
+ /* Calculate/Check values for the receive queue */
+ Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
+ &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
+ Rtv |= Rtv2;
+
+ /* Calculate/Check values for the synchronous tx queue */
+ Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
+ &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
+ Rtv |= Rtv2;
+
+ /* Calculate/Check values for the asynchronous tx queue */
+ Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
+ &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
+ Rtv |= Rtv2;
+
+ if (Rtv) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SKERR_HWI_E013,
+ SKERR_HWI_E013MSG);
+ break;
+ }
+ }
+
+
+CheckQSizeEnd:
+ return (Rtv);
+}
+
+/******************************************************************************
+ *
+ * SkGeInitMacArb() - Initialize the MAC Arbiter
+ *
+ * Description:
+ * This function initializes the MAC Arbiter.
+ * It must not be called if there is still an
+ * initilaized or active port.
+ *
+ * Returns:
+ * nothing:
+ */
+static void SkGeInitMacArb(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ /* release local reset */
+ SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
+
+ /* configure timeout values */
+ SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
+ SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
+ SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
+ SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
+
+ SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
+ SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
+ SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
+ SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
+
+ /* recovery values are needed for XMAC II Rev. B2 only */
+ /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
+
+ /*
+ * There is not start or enable buttom to push, therefore
+ * the MAC arbiter is configured and enabled now.
+ */
+}
+
+/******************************************************************************
+ *
+ * SkGeInitPktArb() - Initialize the Packet Arbiter
+ *
+ * Description:
+ * This function initializes the Packet Arbiter.
+ * It must not be called if there is still an
+ * initilaized or active port.
+ *
+ * Returns:
+ * nothing:
+ */
+static void SkGeInitPktArb(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ /* release local reset */
+ SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
+
+ /* configure timeout values */
+ SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
+ SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
+ SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
+ SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
+
+ /* enable timeout timers if jumbo frames not used */
+ if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
+ if (pAC->GIni.GIMacsFound == 1) {
+ SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
+ }
+ else {
+ SK_OUT16(IoC, B3_PA_CTRL,(PA_ENA_TO_TX1|PA_ENA_TO_TX2));
+ }
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeInitMacFifo() - Initialize the MAC FIFOs
+ *
+ * Description:
+ * Initialize all MAC FIFOs of the specified port
+ *
+ * Returns:
+ * nothing
+ */
+static void SkGeInitMacFifo(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ /*
+ * For each FIFO:
+ * - release local reset
+ * - use default value for MAC FIFO size
+ * - setup defaults for the control register
+ * - enable the FIFO
+ */
+ /* Configure RX MAC FIFO */
+ SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
+ SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
+ SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
+
+ /* Configure TX MAC FIFO */
+ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
+ SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
+ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
+
+ /* Enable frame flushing if jumbo frames used */
+ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
+ SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
+ *
+ * Description:
+ * This function starts the Link Sync Counter of the specified
+ * port and enables the generation of an Link Sync IRQ.
+ * The Link Sync Counter may be used to detect an active link,
+ * if autonegotiation is not used.
+ *
+ * Note:
+ * o To ensure receiving the Link Sync Event the LinkSyncCounter
+ * should be initialized BEFORE clearing the XMACs reset!
+ * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
+ * function.
+ *
+ * Retruns:
+ * nothing
+ */
+void SkGeLoadLnkSyncCnt(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U32 CntVal) /* Counter value */
+{
+ SK_U32 OrgIMsk;
+ SK_U32 NewIMsk;
+ SK_U32 ISrc;
+ SK_BOOL IrqPend;
+
+ /* stop counter */
+ SK_OUT8(IoC, MR_ADDR(Port,LNK_SYNC_CTRL), LED_STOP);
+
+ /*
+ * ASIC problem:
+ * Each time starting the Link Sync Counter an IRQ is generated
+ * by the adapter. See problem report entry from 21.07.98
+ *
+ * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
+ * if no IRQ is already pending.
+ */
+ IrqPend = SK_FALSE;
+ SK_IN32(IoC, B0_ISRC, &ISrc);
+ SK_IN32(IoC, B0_IMSK, &OrgIMsk);
+ if (Port == MAC_1) {
+ NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
+ if (ISrc & IS_LNK_SYNC_M1) {
+ IrqPend = SK_TRUE;
+ }
+ }
+ else {
+ NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
+ if (ISrc & IS_LNK_SYNC_M2) {
+ IrqPend = SK_TRUE;
+ }
+ }
+ if (!IrqPend) {
+ SK_OUT32(IoC, B0_IMSK, NewIMsk);
+ }
+
+ /* load counter */
+ SK_OUT32(IoC, MR_ADDR(Port,LNK_SYNC_INI), CntVal);
+
+ /* start counter */
+ SK_OUT8(IoC, MR_ADDR(Port,LNK_SYNC_CTRL), LED_START);
+
+ if (!IrqPend) {
+ /* clear the unexpected IRQ, and restore the interrupt mask */
+ SK_OUT8(IoC, MR_ADDR(Port,LNK_SYNC_CTRL), LED_CLR_IRQ);
+ SK_OUT32(IoC, B0_IMSK, OrgIMsk);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeCfgSync() - Configure synchronous bandwidth for this port.
+ *
+ * Description:
+ * This function may be used to configure synchronous bandwidth
+ * to the specified port. This may be done any time after
+ * initializing the port. The configuration values are NOT saved
+ * in the HWAC port structure and will be overwritten any
+ * time when stopping and starting the port.
+ * Any values for the synchronous configuration will be ignored
+ * if the size of the synchronous queue is zero!
+ *
+ * The default configuration for the synchronous service is
+ * TXA_ENA_FSYNC. This means if the size of
+ * the synchronous queue is unequal zero but no specific
+ * synchronous bandwidth is configured, the synchronous queue
+ * will always have the 'unlimitted' transmit priority!
+ *
+ * This mode will be restored if the synchronous bandwidth is
+ * deallocated ('IntTime' = 0 and 'LimCount' = 0).
+ *
+ * Returns:
+ * 0: success
+ * 1: paramter configuration error
+ * 2: try to configure quality of service although no
+ * synchronous queue is configured
+ */
+int SkGeCfgSync(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
+SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
+int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
+{
+ int Rtv;
+
+ Rtv = 0;
+
+ /* check the parameters */
+ if (LimCount > IntTime ||
+ (LimCount == 0 && IntTime != 0) ||
+ (LimCount !=0 && IntTime == 0)) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
+ Rtv = 1;
+ goto CfgSyncEnd;
+ }
+ if (pAC->GIni.GP[Port].PXSQSize != 0) {
+ /* calculate register values */
+ IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
+ LimCount = LimCount / 8;
+ if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010,
+ SKERR_HWI_E010MSG);
+ Rtv = 1;
+ goto CfgSyncEnd;
+ }
+
+ /*
+ * - Enable 'Force Sync' to ensure the synchronous queue
+ * has the priority while configuring the new values.
+ * - Also 'disable alloc' to ensure the settings complies
+ * to the SyncMode parameter.
+ * - Disable 'Rate Control' to configure the new values.
+ * - write IntTime and Limcount
+ * - start 'Rate Control' and disable 'Force Sync'
+ * if Interval Timer or Limit Counter not zero.
+ */
+ SK_OUT8(IoC, MR_ADDR(Port,TXA_CTRL),
+ TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
+ SK_OUT32(IoC, MR_ADDR(Port,TXA_ITI_INI), IntTime);
+ SK_OUT32(IoC, MR_ADDR(Port,TXA_LIM_INI), LimCount);
+ SK_OUT8(IoC, MR_ADDR(Port,TXA_CTRL),
+ (SyncMode & (TXA_ENA_ALLOC|TXA_DIS_ALLOC)));
+ if (IntTime != 0 || LimCount != 0) {
+ SK_OUT8(IoC, MR_ADDR(Port,TXA_CTRL),
+ TXA_DIS_FSYNC|TXA_START_RC);
+ }
+ }
+ else {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
+ Rtv = 2;
+ }
+
+CfgSyncEnd:
+ return (Rtv);
+}
+
+/******************************************************************************
+ *
+ * DoInitRamQueue() - Initilaize the RAM Buffer Address of a single Queue
+ *
+ * Desccription:
+ * If the queue is used, enable and initilaize it.
+ * Make sure the queue is still reset, if it is not used.
+ *
+ * Returns:
+ * nothing
+ */
+static void DoInitRamQueue(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int QuIoOffs, /* Queue IO Address Offset */
+SK_U32 QuStartAddr, /* Queue Start Address */
+SK_U32 QuEndAddr, /* Queue End Address */
+int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
+{
+ SK_U32 RxUpThresVal;
+ SK_U32 RxLoThresVal;
+
+ if (QuStartAddr != QuEndAddr) {
+ /* calculate thresholds, assume we have a big Rx queue */
+ RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
+ RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
+
+ /* build HW address format */
+ QuStartAddr = QuStartAddr / 8;
+ QuEndAddr = QuEndAddr / 8;
+
+ /* release local reset */
+ SK_OUT8(IoC, RB_ADDR(QuIoOffs,RB_CTRL), RB_RST_CLR);
+
+ /* configure addresses */
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_START), QuStartAddr);
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_END), QuEndAddr);
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_WP), QuStartAddr);
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_RP), QuStartAddr);
+
+ switch (QuType) {
+ case SK_RX_SRAM_Q:
+ /* configure threshold for small Rx Queue */
+ RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
+
+ /* continue with SK_RX_BRAM_Q */
+ case SK_RX_BRAM_Q:
+ /* write threshold for Rx Queue */
+
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_RX_UTPP),
+ RxUpThresVal);
+ SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_RX_LTPP),
+ RxLoThresVal);
+ /* the high priority threshold not used */
+ break;
+ case SK_TX_RAM_Q:
+ /*
+ * Do NOT use Store and forward under normal
+ * operation due to performance optimization.
+ * But if Jumbo frames are configured we NEED
+ * the store and forward of the RAM buffer.
+ */
+ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
+ /*
+ * enable Store & Forward Mode for the
+ * Tx Side
+ */
+ SK_OUT8(IoC, RB_ADDR(QuIoOffs,RB_CTRL),
+ RB_ENA_STFWD);
+ }
+ break;
+ }
+
+ /* set queue operational */
+ SK_OUT8(IoC, RB_ADDR(QuIoOffs,RB_CTRL), RB_ENA_OP_MD);
+ }
+ else {
+ /* ensure the queue is still disabled */
+ SK_OUT8(IoC, RB_ADDR(QuIoOffs,RB_CTRL), RB_RST_SET);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
+ *
+ * Description:
+ * Initialize all RAM Buffer Queues of the specified port
+ *
+ * Returns:
+ * nothing
+ */
+static void SkGeInitRamBufs(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ int RxQType;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
+ RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
+ }
+ else {
+ RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
+ }
+
+ DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
+ pPrt->PRxQRamEnd, RxQType);
+ DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
+ pPrt->PXsQRamEnd, SK_TX_RAM_Q);
+ DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
+ pPrt->PXaQRamEnd, SK_TX_RAM_Q);
+}
+
+/******************************************************************************
+ *
+ * SkGeInitRamIface() - Initialize the RAM Interface
+ *
+ * Description:
+ * This function initializes the Adapbers RAM Interface.
+ *
+ * Note:
+ * This function is used in the diagnostics.
+ *
+ * Returns:
+ * nothing
+ */
+void SkGeInitRamIface(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ /* release local reset */
+ SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
+
+ /* configure timeout values */
+ SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
+ SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
+}
+
+/******************************************************************************
+ *
+ * SkGeInitBmu() - Initialize the BMU state machines
+ *
+ * Description:
+ * Initialize all BMU state machines of the specified port
+ *
+ * Returns:
+ * nothing
+ */
+static void SkGeInitBmu(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Rx Queue: Release all local resets and set the watermark */
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_CSR), CSR_CLR_RESET);
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_F), SK_BMU_RX_WM);
+
+ /*
+ * Tx Queue: Release all local resets if the queue is used!
+ * set watermark
+ */
+ if (pPrt->PXSQSize != 0) {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff,Q_CSR), CSR_CLR_RESET);
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff,Q_F), SK_BMU_TX_WM);
+ }
+ if (pPrt->PXAQSize != 0) {
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff,Q_CSR), CSR_CLR_RESET);
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff,Q_F), SK_BMU_TX_WM);
+ }
+ /*
+ * Do NOT enable the descriptor poll timers here, because
+ * the descriptor addresses are not specified yet.
+ */
+}
+
+/******************************************************************************
+ *
+ * TestStopBit() - Test the stop bit of the queue
+ *
+ * Description:
+ * Stopping a queue is not as simple as it seems to be.
+ * If descriptor polling is enabled, it may happen
+ * that RX/TX stop is done and SV idle is NOT set.
+ * In this case we have to issue another stop command.
+ *
+ * Retruns:
+ * The queues control status register
+ */
+static SK_U32 TestStopBit(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC, /* IO Context */
+int QuIoOffs) /* Queue IO Address Offset */
+{
+ SK_U32 QuCsr; /* CSR contents */
+
+ SK_IN32(IoC, Q_ADDR(QuIoOffs,Q_CSR), &QuCsr);
+ if ((QuCsr & (CSR_STOP|CSR_SV_IDLE)) == 0) {
+ SK_OUT32(IoC, Q_ADDR(QuIoOffs,Q_CSR), CSR_STOP);
+ SK_IN32(IoC, Q_ADDR(QuIoOffs,Q_CSR), &QuCsr);
+ }
+ return (QuCsr);
+}
+
+/******************************************************************************
+ *
+ * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
+ *
+ * Description:
+ * After calling this function the descriptor rings and rx and tx
+ * queues of this port may be reconfigured.
+ *
+ * It is possible to stop the receive and transmit path seperate or
+ * both together.
+ *
+ * Dir = SK_STOP_TX Stops the transmit path only and resets
+ * the XMAC. The receive queue is still and
+ * the pending rx frames may still transfered
+ * into the RxD.
+ * SK_STOP_RX Stop the receive path. The tansmit path
+ * has to be stoped once before.
+ * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
+ *
+ * RstMode=SK_SOFT_RST Resets the XMAC. The PHY is still alive.
+ * SK_HARD_RST Resets the XMAC and the PHY.
+ *
+ * Example:
+ * 1) A Link Down event was signaled for a port. Therefore the activity
+ * of this port should be stoped and a hardware reset should be issued
+ * to enable the workaround of XMAC errata #2. But the received frames
+ * should not be discarded.
+ * ...
+ * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
+ * (transfer all pending rx frames)
+ * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
+ * ...
+ *
+ * 2) An event was issued which request the driver to switch
+ * the 'virtual active' link to an other already active port
+ * as soon as possible. The frames in the receive queue of this
+ * port may be lost. But the PHY must not be reset during this
+ * event.
+ * ...
+ * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
+ * ...
+ *
+ * Extended Description:
+ * If SK_STOP_TX is set,
+ * o disable the XMACs receive and transmiter to prevent
+ * from sending incomplete frames
+ * o stop the port's transmit queues before terminating the
+ * BMUs to prevent from performing incomplete PCI cycles
+ * on the PCI bus
+ * - The network rx and tx activity and PCI tx transfer is
+ * disabled now.
+ * o reset the XMAC depending on the RstMode
+ * o Stop Interval Timer and Limit Counter of Tx Arbiter,
+ * also disable Force Sync bit and Enable Alloc bit.
+ * o perform a local reset of the port's tx path
+ * - reset the PCI FIFO of the async tx queue
+ * - reset the PCI FIFO of the sync tx queue
+ * - reset the RAM Buffer async tx queue
+ * - reset the RAM Butter sync tx queue
+ * - reset the MAC Tx FIFO
+ * o switch Link and Tx LED off, stop the LED counters
+ *
+ * If SK_STOP_RX is set,
+ * o stop the port's receive queue
+ * - The path data transfer activity is fully stopped now.
+ * o perform a local reset of the port's rx path
+ * - reset the PCI FIFO of the rx queue
+ * - reset the RAM Buffer receive queue
+ * - reset the MAC Rx FIFO
+ * o switch Rx LED off, stop the LED counter
+ *
+ * If all ports are stopped,
+ * o reset the RAM Interface.
+ *
+ * Notes:
+ * o This function may be called during the driver states RESET_PORT and
+ * SWITCH_PORT.
+ */
+void SkGeStopPort(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* port to stop (MAC_1 + n) */
+int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
+int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
+{
+#ifndef SK_DIAG
+ SK_EVPARA Para;
+#endif /* !SK_DIAG */
+ SK_GEPORT *pPrt;
+ SK_U32 DWord;
+ SK_U16 Word;
+ SK_U32 XsCsr;
+ SK_U32 XaCsr;
+ int i;
+ SK_BOOL AllPortsDis;
+ SK_U64 ToutStart;
+ int ToutCnt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (Dir & SK_STOP_TX) {
+ /* disable the XMACs receiver and transmitter */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+ XM_OUT16(IoC, Port, XM_MMU_CMD,
+ Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
+
+ /* dummy read to ensure writing */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+
+ /* stop both transmit queues */
+ /*
+ * If the BMU is in the reset state CSR_STOP will terminate
+ * immediately.
+ */
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff,Q_CSR), CSR_STOP);
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff,Q_CSR), CSR_STOP);
+
+ ToutStart = SkOsGetTime(pAC);
+ ToutCnt = 0;
+ do {
+ /*
+ * Clear packet arbiter timeout to make sure
+ * this loop will terminate
+ */
+ if (Port == MAC_1) {
+ Word = PA_CLR_TO_TX1;
+ }
+ else {
+ Word = PA_CLR_TO_TX2;
+ }
+ SK_OUT16(IoC, B3_PA_CTRL, Word);
+
+ /*
+ * If the transfer stucks at the XMAC the STOP command
+ * will not terminate if we don't flush the XMACs
+ * transmit FIFO !
+ */
+ XM_IN32(IoC, Port, XM_MODE, &DWord);
+ DWord |= XM_MD_FTF ;
+ XM_OUT32(IoC, Port, XM_MODE, DWord);
+
+ XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
+ XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
+
+ if (ToutStart + (SK_TICKS_PER_SEC / 18) <
+ SkOsGetTime(pAC)) {
+
+ /*
+ * Timeout of 1/18 second reached.
+ */
+ ToutCnt++;
+ switch (ToutCnt) {
+ case 1:
+ /*
+ * Cache Incoherency workaround:
+ * Assume a start command has been
+ * lost while sending the frame.
+ */
+ ToutStart = SkOsGetTime(pAC);
+ if (XsCsr & CSR_STOP) {
+ SK_OUT32(IoC,
+ Q_ADDR(pPrt->PXsQOff,
+ Q_CSR), CSR_START);
+ }
+ if (XaCsr & CSR_STOP) {
+ SK_OUT32(IoC,
+ Q_ADDR(pPrt->PXaQOff,
+ Q_CSR), CSR_START);
+ }
+ break;
+ case 2:
+ default: /* Fatal Error, Loop aborted */
+ /* Create an Error Log Entry */
+ SK_ERR_LOG(pAC, SK_ERRCL_HW,
+ SKERR_HWI_E018,
+ SKERR_HWI_E018MSG);
+#ifndef SK_DIAG
+ Para.Para64 = Port;
+ SkEventQueue(pAC, SKGE_DRV,
+ SK_DRV_PORT_FAIL, Para);
+#endif /* !SK_DIAG */
+ return;
+ }
+ }
+
+ /*
+ * because of the ASIC problem report entry from 21.08.98
+ * it is required to wait until CSR_STOP is reset and
+ * CSR_SV_IDLE is set.
+ */
+ } while ((XsCsr & (CSR_STOP|CSR_SV_IDLE)) != CSR_SV_IDLE ||
+ (XaCsr & (CSR_STOP|CSR_SV_IDLE)) != CSR_SV_IDLE);
+
+ /* reset the XMAC depending on the RstMode */
+ if (RstMode == SK_SOFT_RST) {
+ SkXmSoftRst(pAC, IoC, Port);
+ }
+ else {
+ SkXmHardRst(pAC, IoC, Port);
+ }
+
+ /*
+ * Stop Interval Timer and Limit Counter of Tx Arbiter,
+ * also disable Force Sync bit and Enable Alloc bit.
+ */
+ SK_OUT8(IoC, MR_ADDR(Port,TXA_CTRL),
+ TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
+ SK_OUT32(IoC, MR_ADDR(Port,TXA_ITI_INI), 0x00000000L);
+ SK_OUT32(IoC, MR_ADDR(Port,TXA_LIM_INI), 0x00000000L);
+
+ /*
+ * perform a local reset of the port's tx path
+ * - reset the PCI FIFO of the async tx queue
+ * - reset the PCI FIFO of the sync tx queue
+ * - reset the RAM Buffer async tx queue
+ * - reset the RAM Butter sync tx queue
+ * - reset the MAC Tx FIFO
+ */
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff,Q_CSR), CSR_SET_RESET);
+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff,Q_CSR), CSR_SET_RESET);
+ SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff,RB_CTRL), RB_RST_SET);
+ SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff,RB_CTRL), RB_RST_SET);
+ /* Note: MFF_RST_SET does NOT reset the XMAC! */
+ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
+
+ /* switch Link and Tx LED off, stop the LED counters */
+ /* Link LED is switched off by the RLMT and the Diag itself */
+ SkGeXmitLED(pAC, IoC, MR_ADDR(Port,TX_LED_INI), SK_LED_DIS);
+ }
+
+ if (Dir & SK_STOP_RX) {
+ /*
+ * The RX Stop Command will not terminate if no buffers
+ * are queued in the RxD ring. But it will always reach
+ * the Idle state. Therefore we can use this feature to
+ * stop the transfer of received packets.
+ */
+ /* stop the port's receive queue */
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_CSR), CSR_STOP);
+ i = 100;
+ do {
+ /*
+ * Clear packet arbiter timeout to make sure
+ * this loop will terminate
+ */
+ if (Port == MAC_1) {
+ Word = PA_CLR_TO_RX1;
+ }
+ else {
+ Word = PA_CLR_TO_RX2;
+ }
+ SK_OUT16(IoC, B3_PA_CTRL, Word);
+
+ DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
+ if (i != 0) {
+ i--;
+ }
+
+ /* finish if CSR_STOP is done or CSR_SV_IDLE is true and i==0 */
+ /*
+ * because of the ASIC problem report entry from 21.08.98
+ * it is required to wait until CSR_STOP is reset and
+ * CSR_SV_IDLE is set.
+ */
+ } while ((DWord & (CSR_STOP|CSR_SV_IDLE)) != CSR_SV_IDLE &&
+ ((DWord & CSR_SV_IDLE) == 0 || i != 0));
+
+ /* The path data transfer activity is fully stopped now. */
+
+ /*
+ * perform a local reset of the port's rx path
+ * - reset the PCI FIFO of the rx queue
+ * - reset the RAM Buffer receive queue
+ * - reset the MAC Rx FIFO
+ */
+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff,Q_CSR), CSR_SET_RESET);
+ SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff,RB_CTRL), RB_RST_SET);
+ SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
+
+ /* switch Rx LED off, stop the LED counter */
+ SkGeXmitLED(pAC, IoC, MR_ADDR(Port,RX_LED_INI), SK_LED_DIS);
+
+ }
+
+ /*
+ * If all ports are stopped reset the RAM Interface.
+ */
+ for (i = 0, AllPortsDis = SK_TRUE; i < pAC->GIni.GIMacsFound; i++) {
+ if (pAC->GIni.GP[i].PState != SK_PRT_RESET &&
+ pAC->GIni.GP[i].PState != SK_PRT_STOP) {
+
+ AllPortsDis = SK_FALSE;
+ break;
+ }
+ }
+ if (AllPortsDis) {
+ pAC->GIni.GIAnyPortAct = SK_FALSE;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeInit0() - Level 0 Initialization
+ *
+ * Description:
+ * - Initialize the BMU address offsets
+ *
+ * Returns:
+ * nothing
+ */
+static void SkGeInit0(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ int i;
+ SK_GEPORT *pPrt;
+
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ pPrt = &pAC->GIni.GP[i];
+ pPrt->PState = SK_PRT_RESET;
+ pPrt->PRxQOff = QOffTab[i].RxQOff;
+ pPrt->PXsQOff = QOffTab[i].XsQOff;
+ pPrt->PXaQOff = QOffTab[i].XaQOff;
+ pPrt->PCheckPar = SK_FALSE;
+ pPrt->PRxCmd = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
+ pPrt->PIsave = 0;
+ pPrt->PPrevShorts = 0;
+ pPrt->PLinkResCt = 0;
+ pPrt->PPrevRx = 0;
+ pPrt->PPrevFcs = 0;
+ pPrt->PRxLim = SK_DEF_RX_WA_LIM;
+ pPrt->PLinkMode = SK_LMODE_AUTOFULL;
+ pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE;
+ pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
+ pPrt->PLinkBroken = SK_TRUE; /* See WA code */
+ pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
+ SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
+ pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM;
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+ pPrt->PMSCap = (SK_MS_CAP_AUTO | SK_MS_CAP_MASTER |
+ SK_MS_CAP_SLAVE);
+ pPrt->PMSMode = SK_MS_MODE_AUTO;
+ pPrt->PMSStatus = SK_MS_STAT_UNSET;
+ pPrt->PAutoNegFail = SK_FALSE;
+ pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
+ pPrt->PHWLinkUp = SK_FALSE;
+ }
+
+ pAC->GIni.GIPortUsage = SK_RED_LINK;
+ pAC->GIni.GIAnyPortAct = SK_FALSE;
+}
+
+/******************************************************************************
+ *
+ * SkGeInit1() - Level 1 Initialization
+ *
+ * Description:
+ * o Do a software reset.
+ * o Clear all reset bits.
+ * o Verify that the detected hardware is present.
+ * Return an error if not.
+ * o Get the hardware configuration
+ * + Read the number of MACs/Ports.
+ * + Read the RAM size.
+ * + Read the PCI Revision ID.
+ * + Find out the adapters host clock speed
+ * + Read and check the PHY type
+ *
+ * Returns:
+ * 0: success
+ * 5: Unexpected PHY type detected
+ */
+static int SkGeInit1(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ SK_U8 Byte;
+ SK_U16 Word;
+ int RetVal;
+ int i;
+
+ RetVal = 0;
+
+ /* Do the reset */
+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
+
+ /* Release the reset */
+ SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
+
+ /* Reset all error bits in the PCI STATUS register */
+ /*
+ * Note: Cfg cycles cannot be used, because they are not
+ * available on some platforms after 'boot time'.
+ */
+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+ SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
+ SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+
+ /* Release Master_Reset */
+ SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
+
+ /* Read number of MACs */
+ SK_IN8(IoC, B2_MAC_CFG, &Byte);
+ if (Byte & CFG_SNG_MAC) {
+ pAC->GIni.GIMacsFound = 1;
+ }
+ else {
+ pAC->GIni.GIMacsFound = 2;
+ }
+ SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
+ pAC->GIni.GIPciHwRev = (int) Byte;
+
+ /* Read the adapters RAM size */
+ SK_IN8(IoC, B2_E_0, &Byte);
+ if (Byte == 3) {
+ pAC->GIni.GIRamSize = (int)(Byte-1) * 512;
+ pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
+ }
+ else {
+ pAC->GIni.GIRamSize = (int)Byte * 512;
+ pAC->GIni.GIRamOffs = 0;
+ }
+
+ /* All known GE Adapters works with 53.125 MHz host clock */
+ pAC->GIni.GIHstClkFact = SK_FACT_53;
+ pAC->GIni.GIPollTimerVal =
+ SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
+
+ /* Read the PHY type */
+ SK_IN8(IoC, B2_E_1, &Byte);
+ Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ pAC->GIni.GP[i].PhyType = Byte;
+ switch (Byte) {
+ case SK_PHY_XMAC:
+ pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
+ break;
+ case SK_PHY_BCOM:
+ pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
+ break;
+ case SK_PHY_LONE:
+ pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
+ break;
+ case SK_PHY_NAT:
+ pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
+ break;
+ default:
+ /* ERROR: unexpected PHY typ detected */
+ RetVal = 5;
+ break;
+ }
+ }
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_INIT,
+ ("PHY type: %d PHY addr: %x\n", pAC->GIni.GP[i].PhyType,
+ pAC->GIni.GP[i].PhyAddr)) ;
+
+ return (RetVal);
+}
+
+/******************************************************************************
+ *
+ * SkGeInit2() - Level 2 Initialization
+ *
+ * Description:
+ * - start the Blink Source Counter
+ * - start the Descriptor Poll Timer
+ * - configure the MAC-Arbiter
+ * - configure the Packet-Arbiter
+ * - enable the Tx Arbiters
+ * - enable the RAM Interface Arbiter
+ *
+ * Returns:
+ * nothing
+ */
+static void SkGeInit2(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ SK_GEPORT *pPrt;
+ SK_U32 DWord;
+ int i;
+
+ /* start the Blink Source Counter */
+ DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
+ SK_OUT32(IoC, B2_BSC_INI, DWord);
+ SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
+
+ /* start the Descriptor Poll Timer */
+ if (pAC->GIni.GIPollTimerVal != 0) {
+ if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
+ pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
+
+ /* Create an Error Log Entry */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017,
+ SKERR_HWI_E017MSG);
+ }
+ SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
+ SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
+ }
+
+ /*
+ * Configure
+ * - the MAC-Arbiter and
+ * - the Paket Arbiter
+ *
+ * The MAC and the packet arbiter will be started once
+ * and never be stopped.
+ */
+ SkGeInitMacArb(pAC, IoC);
+ SkGeInitPktArb(pAC, IoC);
+
+ /* enable the Tx Arbiters */
+ SK_OUT8(IoC, MR_ADDR(MAC_1,TXA_CTRL), TXA_ENA_ARB);
+ if (pAC->GIni.GIMacsFound > 1) {
+ SK_OUT8(IoC, MR_ADDR(MAC_2,TXA_CTRL), TXA_ENA_ARB);
+ }
+
+ /* enable the RAM Interface Arbiter */
+ SkGeInitRamIface(pAC, IoC);
+
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ pPrt = &pAC->GIni.GP[i];
+ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
+ pPrt->PRxCmd |= XM_RX_BIG_PK_OK;
+ }
+ }
+}
+
+/******************************************************************************
+ *
+ * SkGeInit() - Initialize the GE Adapter with the specified level.
+ *
+ * Description:
+ * Level 0: Initialize the Module structures.
+ * Level 1: Generic Hardware Initialization. The
+ * IOP/MemBase pointer has to be set before
+ * calling this level.
+ *
+ * o Do a software reset.
+ * o Clear all reset bits.
+ * o Verify that the detected hardware is present.
+ * Return an error if not.
+ * o Get the hardware configuration
+ * + Set GIMacsFound with the number of MACs.
+ * + Store the RAM size in GIRamSize.
+ * + Save the PCI Revision ID in GIPciHwRev.
+ * o return an error
+ * if Number of MACs > SK_MAX_MACS
+ *
+ * After returning from Level 0 the adapter
+ * may be accessed with IO operations.
+ *
+ * Level 2: start the Blink Source Counter
+ *
+ * Returns:
+ * 0: success
+ * 1: Number of MACs exceeds SK_MAX_MACS ( after level 1)
+ * 2: Adapter not present or not accessable
+ * 3: Illegal initialization level
+ * 4: Initialization Level 1 Call missing
+ * 5: Unexpected PHY type detected
+ */
+int SkGeInit(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Level) /* initialization level */
+{
+ int RetVal; /* return value */
+ SK_U32 DWord;
+
+ RetVal = 0;
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_INIT,
+ ("SkGeInit(Level %d)\n",Level)) ;
+
+ switch (Level) {
+ case SK_INIT_DATA:
+ /* Initialization Level 0 */
+ SkGeInit0(pAC,IoC) ;
+ pAC->GIni.GILevel = SK_INIT_DATA;
+ break;
+ case SK_INIT_IO:
+ /* Initialization Level 1 */
+ RetVal = SkGeInit1(pAC,IoC) ;
+
+ /* Check if the adapter seems to be accessable */
+ SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
+ SK_IN32(IoC, B2_IRQM_INI, &DWord);
+ SK_OUT32(IoC, B2_IRQM_INI, 0x00000000L);
+ if (DWord != 0x11335577L) {
+ RetVal = 2;
+ break;
+ }
+
+ /* Check if the number of GIMacsFound matches SK_MAX_MACS */
+ if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
+ RetVal = 1;
+ break;
+ }
+
+ /* Level 1 successfully passed */
+ pAC->GIni.GILevel = SK_INIT_IO;
+ break;
+ case SK_INIT_RUN:
+ /* Initialization Level 2 */
+ if (pAC->GIni.GILevel != SK_INIT_IO) {
+#ifndef SK_DIAG
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002,
+ SKERR_HWI_E002MSG);
+#endif
+ RetVal = 4;
+ break;
+ }
+ SkGeInit2(pAC,IoC) ;
+
+ /* Level 2 successfully passed */
+ pAC->GIni.GILevel = SK_INIT_RUN;
+ break;
+ default:
+ /* Create an Error Log Entry */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
+ RetVal = 3 ;
+ break;
+ }
+
+ return (RetVal);
+}
+
+/******************************************************************************
+ *
+ * SkGeDeInit() - Deinitialize the adapter.
+ *
+ * Description:
+ * All ports of the adapter will be stopped if not already done.
+ * Do a software reset and switch off all LEDs.
+ *
+ * Returns:
+ * nothing
+ */
+void SkGeDeInit(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* IO context */
+{
+ int i;
+ SK_U16 Word;
+
+ /* Stop all current transfer activity */
+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+ if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
+ pAC->GIni.GP[i].PState != SK_PRT_RESET) {
+
+ SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
+ }
+ }
+
+ /* Reset all bits in the PCI STATUS register */
+ /*
+ * Note: Cfg cycles cannot be used, because they are not
+ * available on some platforms after 'boot time'.
+ */
+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+ SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
+ SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+
+ /* Do the reset, all LEDs are switched off now */
+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
+}
+
+/******************************************************************************
+ *
+ * SkGeInitPort() Initialize the specified prot.
+ *
+ * Description:
+ * PRxQSize, PXSQSize, and PXAQSize has to be
+ * configured for the specified port before calling this
+ * function. The descriptor rings has to be initialized, too.
+ *
+ * o (Re)configure queues of the specified port.
+ * o configure the XMAC of the specified port.
+ * o put ASIC and XMAC(s) in operational mode.
+ * o initialize Rx/Tx and Sync LED
+ * o initialize RAM Buffers and MAC FIFOs
+ *
+ * The port is ready to connect when returning.
+ *
+ * Note:
+ * The XMACs Rx and Tx state machine is still disabled when
+ * returning.
+ *
+ * Returns:
+ * 0: success
+ * 1: Queue size initialization error. The configured values
+ * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
+ * or more queues. The specified port was NOT initialized.
+ * An error log entry was generated.
+ * 2: The port has to be stopped before it can be initilaized again.
+ */
+int SkGeInitPort(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port to configure */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (SkGeCheckQSize(pAC,Port) != 0) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
+ return (1);
+ }
+ if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
+ return (2);
+ }
+
+ /* Configuration ok, initialize the Port now */
+
+ /* Initialize Rx, Tx and Link LED */
+ /*
+ * If 1000BT Phy needs LED initialization than swap
+ * LED and XMAC initialization order
+ */
+ SkGeXmitLED(pAC, IoC, MR_ADDR(Port,TX_LED_INI), SK_LED_ENA);
+ SkGeXmitLED(pAC, IoC, MR_ADDR(Port,RX_LED_INI), SK_LED_ENA);
+ /* The Link LED is initialized by RLMT or Diagnostics itself */
+
+ /* Do NOT initialize the Link Sync Counter */
+
+ /*
+ * Configure
+ * - XMAC
+ * - MAC FIFOs
+ * - RAM Buffers
+ * - enable Force Sync bit if synchronous queue available
+ * - BMUs
+ */
+ SkXmInitMac(pAC, IoC, Port);
+ SkGeInitMacFifo(pAC, IoC, Port);
+ SkGeInitRamBufs(pAC, IoC, Port);
+ if (pPrt->PXSQSize != 0) {
+ SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
+ }
+ SkGeInitBmu(pAC, IoC, Port);
+
+ /* Mark port as initialized. */
+ pPrt->PState = SK_PRT_INIT;
+ pAC->GIni.GIAnyPortAct = SK_TRUE;
+
+ return (0);
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Name: skgepnmi.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.69 $
+ * Date: $Date: 1999/10/18 11:42:15 $
+ * Purpose: Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgepnmi.c,v $
+ * Revision 1.69 1999/10/18 11:42:15 rwahl
+ * Added typecasts for checking event dependent param (debug only).
+ *
+ * Revision 1.68 1999/10/06 09:35:59 cgoos
+ * Added state check to PHY_READ call (hanged if called during startup).
+ *
+ * Revision 1.67 1999/09/22 09:53:20 rwahl
+ * - Read Broadcom register for updating fcs error counter (1000Base-T).
+ *
+ * Revision 1.66 1999/08/26 13:47:56 rwahl
+ * Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap.
+ *
+ * Revision 1.65 1999/07/26 07:49:35 cgoos
+ * Added two typecasts to avoid compiler warnings.
+ *
+ * Revision 1.64 1999/05/20 09:24:12 cgoos
+ * Changes for 1000Base-T (sensors, Master/Slave).
+ *
+ * Revision 1.63 1999/04/13 15:11:58 mhaveman
+ * Moved include of rlmt.h to header skgepnmi.h because some macros
+ * are needed there.
+ *
+ * Revision 1.62 1999/04/13 15:08:07 mhaveman
+ * Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK
+ * to grant unified interface by only using the PNMI header file.
+ * SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK.
+ *
+ * Revision 1.61 1999/04/13 15:02:48 mhaveman
+ * Changes caused by review:
+ * -Changed some comments
+ * -Removed redundant check for OID_SKGE_PHYS_FAC_ADDR
+ * -Optimized PRESET check.
+ * -Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same
+ * address will now not cause this error. Removed corresponding check.
+ *
+ * Revision 1.60 1999/03/23 10:41:23 mhaveman
+ * Added comments.
+ *
+ * Revision 1.59 1999/02/19 08:01:28 mhaveman
+ * Fixed bug 10372 that after counter reset all ports were displayed
+ * as inactive.
+ *
+ * Revision 1.58 1999/02/16 18:04:47 mhaveman
+ * Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME.
+ *
+ * Revision 1.56 1999/01/27 12:29:11 mhaveman
+ * SkTimerStart was called with time value in milli seconds but needs
+ * micro seconds.
+ *
+ * Revision 1.55 1999/01/25 15:00:38 mhaveman
+ * Added support to allow multiple ports to be active. If this feature in
+ * future will be used, the Management Data Base variables PORT_ACTIVE
+ * and PORT_PREFERED should be moved to the port specific part of RLMT.
+ * Currently they return the values of the first active physical port
+ * found. A set to the virtual port will actually change all active
+ * physical ports. A get returns the melted values of all active physical
+ * ports. If the port values differ a return value INDETERMINATED will
+ * be returned. This effects especially the CONF group.
+ *
+ * Revision 1.54 1999/01/19 10:10:22 mhaveman
+ * -Fixed bug 10354: Counter values of virtual port were wrong after port
+ * switches
+ * -Added check if a switch to the same port is notified.
+ *
+ * Revision 1.53 1999/01/07 09:25:21 mhaveman
+ * Forgot to initialize a variable.
+ *
+ * Revision 1.52 1999/01/05 10:34:33 mhaveman
+ * Fixed little error in RlmtChangeEstimate calculation.
+ *
+ * Revision 1.51 1999/01/05 09:59:07 mhaveman
+ * -Moved timer start to init level 2
+ * -Redesigned port switch average calculation to avoid 64bit
+ * arithmetic.
+ *
+ * Revision 1.50 1998/12/10 15:13:59 mhaveman
+ * -Fixed: PHYS_CUR_ADDR returned wrong addresses
+ * -Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned
+ * always BAD_VALUE.
+ * -Fixed: TRAP buffer seemed to sometimes suddenly empty
+ *
+ * Revision 1.49 1998/12/09 16:17:07 mhaveman
+ * Fixed: Couldnot delete VPD keys on UNIX.
+ *
+ * Revision 1.48 1998/12/09 14:11:10 mhaveman
+ * -Add: Debugmessage for XMAC_RESET supressed to minimize output.
+ * -Fixed: RlmtChangeThreshold will now be initialized.
+ * -Fixed: VPD_ENTRIES_LIST extended value with unnecessary space char.
+ * -Fixed: On VPD key creation an invalid key name could be created
+ * (e.g. A5)
+ * -Some minor changes in comments and code.
+ *
+ * Revision 1.47 1998/12/08 16:00:31 mhaveman
+ * -Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port
+ * is active.
+ * -Fixed: For the RLMT statistics group only the last value was
+ * returned and the rest of the buffer was filled with 0xff
+ * -Fixed: Mysteriously the preset on RLMT_MODE still returned
+ * BAD_VALUE.
+ * Revision 1.46 1998/12/08 10:04:56 mhaveman
+ * -Fixed: Preset on RLMT_MODE returned always BAD_VALUE error.
+ * -Fixed: Alignment error in GetStruct
+ * -Fixed: If for Get/Preset/SetStruct the buffer size is equal or
+ * larger than SK_PNMI_MIN_STRUCT_SIZE the return value is stored
+ * to the buffer. In this case the caller should always return
+ * ok to its upper routines. Only if the buffer size is less
+ * than SK_PNMI_MIN_STRUCT_SIZE and the return value is unequal
+ * to 0, an error should be returned by the caller.
+ * -Fixed: Wrong number of instances with RLMT statistic.
+ * -Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0.
+ *
+ * Revision 1.45 1998/12/03 17:17:24 mhaveman
+ * -Removed for VPD create action the buffer size limitation to 4 bytes.
+ * -Pass now physical/active physical port to ADDR for CUR_ADDR set
+ *
+ * Revision 1.44 1998/12/03 15:14:35 mhaveman
+ * Another change to Vpd instance evaluation.
+ *
+ * Revision 1.43 1998/12/03 14:18:10 mhaveman
+ * -Fixed problem in PnmiSetStruct. It was impossible to set any value.
+ * -Removed VPD key evaluation for VPD_FREE_BYTES and VPD_ACTION.
+ *
+ * Revision 1.42 1998/12/03 11:31:47 mhaveman
+ * Inserted cast to satisfy lint.
+ *
+ * Revision 1.41 1998/12/03 11:28:16 mhaveman
+ * Removed SK_PNMI_CHECKPTR
+ *
+ * Revision 1.40 1998/12/03 11:19:07 mhaveman
+ * Fixed problems
+ * -A set to virtual port will now be ignored. A set with broadcast
+ * address to any port will be ignored.
+ * -GetStruct function made VPD instance calculation wrong.
+ * -Prefered port returned -1 instead of 0.
+ *
+ * Revision 1.39 1998/11/26 15:30:29 mhaveman
+ * Added sense mode to link mode.
+ *
+ * Revision 1.38 1998/11/23 15:34:00 mhaveman
+ * -Fixed bug for RX counters. On an RX overflow interrupt the high
+ * words of all RX counters were incremented.
+ * -SET operations on FLOWCTRL_MODE and LINK_MODE accept now the
+ * value 0, which has no effect. It is usefull for multiple instance
+ * SETs.
+ *
+ * Revision 1.37 1998/11/20 08:02:04 mhaveman
+ * -Fixed: Ports were compared with MAX_SENSORS
+ * -Fixed: Crash in GetTrapEntry with MEMSET macro
+ * -Fixed: Conversions between physical, logical port index and instance
+ *
+ * Revision 1.36 1998/11/16 07:48:53 mhaveman
+ * Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings
+ * on Solaris.
+ *
+ * Revision 1.35 1998/11/16 07:45:34 mhaveman
+ * SkAddrOverride now returns value and will be checked.
+ *
+ * Revision 1.34 1998/11/10 13:40:37 mhaveman
+ * Needed to change interface, because NT driver needs a return value
+ * of needed buffer space on TOO_SHORT errors. Therefore all
+ * SkPnmiGet/Preset/Set functions now have a pointer to the length
+ * parameter, where the needed space on error is returned.
+ *
+ * Revision 1.33 1998/11/03 13:52:46 mhaveman
+ * Made file lint conform.
+ *
+ * Revision 1.32 1998/11/03 13:19:07 mhaveman
+ * The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in
+ * Para32[0] the physical MAC index and in Para32[1] the new mode.
+ *
+ * Revision 1.31 1998/11/03 12:30:40 gklug
+ * fix: compiler warning memset
+ *
+ * Revision 1.30 1998/11/03 12:04:46 mhaveman
+ * Fixed problem in SENSOR_VALUE, which wrote beyond the buffer end
+ * Fixed alignment problem with CHIPSET.
+ *
+ * Revision 1.29 1998/11/02 11:23:54 mhaveman
+ * Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry.
+ *
+ * Revision 1.28 1998/11/02 10:47:16 mhaveman
+ * Added syslog messages for internal errors.
+ *
+ * Revision 1.27 1998/10/30 15:48:06 mhaveman
+ * Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and
+ * RlmtChangeThreshold calculation.
+ *
+ * Revision 1.26 1998/10/29 15:36:55 mhaveman
+ * -Fixed bug in trap buffer handling.
+ * -OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR,
+ * OID_SKGE_HW_VERSION, OID_SKGE_VPD_ENTRIES_LIST, OID_SKGE_VPD_KEY,
+ * OID_SKGE_VPD_VALUE, and OID_SKGE_SENSOR_DESCR return values with
+ * a leading octet before each string storing the string length.
+ * -Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize
+ * RlmtUpdate calls in GetStatVal.
+ * -Inserted SK_PNMI_CHECKFLAGS macro increase readability.
+ *
+ * Revision 1.25 1998/10/29 08:50:36 mhaveman
+ * Fixed problems after second event simulation.
+ *
+ * Revision 1.24 1998/10/28 08:44:37 mhaveman
+ * -Fixed alignment problem
+ * -Fixed problems during event simulation
+ * -Fixed sequence of error return code (INSTANCE -> ACCESS -> SHORT)
+ * -Changed type of parameter Instance back to SK_U32 because of VPD
+ * -Updated new VPD function calls
+ *
+ * Revision 1.23 1998/10/23 10:16:37 mhaveman
+ * Fixed bugs after buffer test simulation.
+ *
+ * Revision 1.22 1998/10/21 13:23:52 mhaveman
+ * -Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc).
+ * -Changed calculation of hundrets of seconds.
+ *
+ * Revision 1.20 1998/10/20 07:30:45 mhaveman
+ * Made type changes to unsigned integer where possible.
+ *
+ * Revision 1.19 1998/10/19 10:51:30 mhaveman
+ * -Made Bug fixes after simulation run
+ * -Renamed RlmtMAC... to RlmtPort...
+ * -Marked workarounds with Errata comments
+ *
+ * Revision 1.18 1998/10/14 07:50:08 mhaveman
+ * -For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT
+ * to HWACCESS.
+ * -Provided all MEMCPY/MEMSET macros with (char *) pointers, because
+ * Solaris throwed warnings when mapping to bcopy/bset.
+ *
+ * Revision 1.17 1998/10/13 07:42:01 mhaveman
+ * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA
+ * -Removed old cvs history entries
+ * -Renamed MacNumber to PortNumber
+ *
+ * Revision 1.16 1998/10/07 10:52:49 mhaveman
+ * -Inserted handling of some OID_GEN_ Ids for windows
+ * -Fixed problem with 803.2 statistic.
+ *
+ * Revision 1.15 1998/10/01 09:16:29 mhaveman
+ * Added Debug messages for function call and UpdateFlag tracing.
+ *
+ * Revision 1.14 1998/09/30 13:39:09 mhaveman
+ * -Reduced namings of 'MAC' by replacing them with 'PORT'.
+ * -Completed counting of OID_SKGE_RX_HW_ERROR_CTS,
+ * OID_SKGE_TX_HW_ERROR_CTS,
+ * OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS.
+ * -SET check for RlmtMode
+ *
+ * Revision 1.13 1998/09/28 13:13:08 mhaveman
+ * Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN,
+ * and SK_STRNCPY. (Same reasons as for mem.. and MEM..)
+ *
+ * Revision 1.12 1998/09/16 08:18:36 cgoos
+ * Fix: XM_INxx and XM_OUTxx called with different parameter order:
+ * sometimes IoC,Mac,... sometimes Mac,IoC,... Now always first variant.
+ * Fix: inserted "Pnmi." into some pAC->pDriverDescription / Version.
+ * Change: memset, memcpy to makros SK_MEMSET, SK_MEMCPY
+ *
+ * Revision 1.11 1998/09/04 17:01:45 mhaveman
+ * Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to
+ * OID_SKGE_RX_NO_BUF_CTS.
+ *
+ * Revision 1.10 1998/09/04 14:35:35 mhaveman
+ * Added macro counters, that are counted by driver.
+ *
+ ****************************************************************************/
+
+
+static const char SysKonnectFileId[] =
+ "@(#) $Id: skgepnmi.c,v 1.69 1999/10/18 11:42:15 rwahl Exp $ (C) SysKonnect.";
+
+#include "h/skdrv1st.h"
+#include "h/sktypes.h"
+#include "h/xmac_ii.h"
+
+#include "h/skdebug.h"
+#include "h/skqueue.h"
+#include "h/skgepnmi.h"
+#include "h/skgesirq.h"
+#include "h/skcsum.h"
+#include "h/skvpd.h"
+#include "h/skgehw.h"
+#include "h/skgeinit.h"
+#include "h/skdrv2nd.h"
+#include "h/skgepnm2.h"
+
+
+/*
+ * Public Function prototypes
+ */
+int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);
+int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
+ unsigned int *pLen, SK_U32 Instance);
+int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
+ unsigned int *pLen, SK_U32 Instance);
+int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
+ unsigned int *pLen, SK_U32 Instance);
+int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, unsigned int *pLen);
+int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, unsigned int *pLen);
+int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, unsigned int *pLen);
+int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
+
+
+/*
+ * Private Function prototypes
+ */
+static int Addr(SK_AC *pAC, SK_IOC IoC, int action,
+ SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
+ PhysPortIndex);
+static SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
+ PhysPortIndex);
+static void CopyMac(char *pDst, SK_MAC_ADDR *pMac);
+static void CopyTrapQueue(SK_AC *pAC, char *pDstBuf);
+static int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC,
+ unsigned int PhysPortIndex, unsigned int StatIndex);
+static SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex,
+ unsigned int StatIndex);
+static char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size);
+static void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen,
+ unsigned int *pEntries);
+static int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr,
+ unsigned int KeyArrLen, unsigned int *pKeyNo);
+static int LookupId(SK_U32 Id);
+static int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac,
+ unsigned int LastMac);
+static int Monitor(SK_AC *pAC, SK_IOC IoC, int action,
+ SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int* pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf,
+ unsigned int *pLen);
+static int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance);
+static void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac);
+static void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId,
+ unsigned int PortIndex);
+static void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId,
+ unsigned int SensorIndex);
+static void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId);
+static void ResetCounter(SK_AC *pAC, SK_IOC IoC);
+static int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int RlmtUpdate(SK_AC *pAC, SK_IOC IoC);
+static int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+static int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
+static void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
+static int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
+ unsigned int TableIndex);
+
+
+/******************************************************************************
+ *
+ * Global variables
+ */
+
+/*
+ * Table to correlate OID with handler function and index to
+ * hardware register stored in StatAddress if applicable.
+ */
+static const SK_PNMI_TAB_ENTRY IdTable[] = {
+ {OID_GEN_XMIT_OK,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX},
+ {OID_GEN_RCV_OK,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX},
+ {OID_GEN_XMIT_ERROR,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, General, 0},
+ {OID_GEN_RCV_ERROR,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, General, 0},
+ {OID_GEN_RCV_NO_BUFFER,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, General, 0},
+ {OID_GEN_DIRECTED_FRAMES_XMIT,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST},
+ {OID_GEN_MULTICAST_FRAMES_XMIT,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST},
+ {OID_GEN_BROADCAST_FRAMES_XMIT,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST},
+ {OID_GEN_DIRECTED_FRAMES_RCV,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST},
+ {OID_GEN_MULTICAST_FRAMES_RCV,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST},
+ {OID_GEN_BROADCAST_FRAMES_RCV,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST},
+ {OID_GEN_RCV_CRC_ERROR,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS},
+ {OID_GEN_TRANSMIT_QUEUE_LENGTH,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, General, 0},
+ {OID_802_3_PERMANENT_ADDRESS,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, 0},
+ {OID_802_3_CURRENT_ADDRESS,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, 0},
+ {OID_802_3_RCV_ERROR_ALIGNMENT,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING},
+ {OID_802_3_XMIT_ONE_COLLISION,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL},
+ {OID_802_3_XMIT_MORE_COLLISIONS,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL},
+ {OID_802_3_XMIT_DEFERRED,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL},
+ {OID_802_3_XMIT_MAX_COLLISIONS,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL},
+ {OID_802_3_RCV_OVERRUN,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW},
+ {OID_802_3_XMIT_UNDERRUN,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN},
+ {OID_802_3_XMIT_TIMES_CRS_LOST,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER},
+ {OID_802_3_XMIT_LATE_COLLISIONS,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL},
+ {OID_SKGE_MDB_VERSION,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(MgmtDBVersion),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_SUPPORTED_LIST,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_ALL_DATA,
+ 0,
+ 0,
+ 0,
+ SK_PNMI_RW, OidStruct, 0},
+ {OID_SKGE_VPD_FREE_BYTES,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(VpdFreeBytes),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_ENTRIES_LIST,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(VpdEntriesList),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_ENTRIES_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(VpdEntriesNumber),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_KEY,
+ SK_PNMI_VPD_ENTRIES,
+ sizeof(SK_PNMI_VPD),
+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_VALUE,
+ SK_PNMI_VPD_ENTRIES,
+ sizeof(SK_PNMI_VPD),
+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_ACCESS,
+ SK_PNMI_VPD_ENTRIES,
+ sizeof(SK_PNMI_VPD),
+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess),
+ SK_PNMI_RO, Vpd, 0},
+ {OID_SKGE_VPD_ACTION,
+ SK_PNMI_VPD_ENTRIES,
+ sizeof(SK_PNMI_VPD),
+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction),
+ SK_PNMI_RW, Vpd, 0},
+ {OID_SKGE_PORT_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(PortNumber),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_DEVICE_TYPE,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(DeviceType),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_DRIVER_DESCR,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(DriverDescr),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_DRIVER_VERSION,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(DriverVersion),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_HW_DESCR,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(HwDescr),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_HW_VERSION,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(HwVersion),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_CHIPSET,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(Chipset),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_ACTION,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(Action),
+ SK_PNMI_RW, Perform, 0},
+ {OID_SKGE_RESULT,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TestResult),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_BUS_TYPE,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(BusType),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_BUS_SPEED,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(BusSpeed),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_BUS_WIDTH,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(BusWidth),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_SW_QUEUE_LEN,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxSwQueueLen),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_SW_QUEUE_MAX,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxSwQueueMax),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_RETRY,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxRetryCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RX_INTR_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RxIntrCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_INTR_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxIntrCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RX_NO_BUF_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RxNoBufCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_NO_BUF_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxNoBufCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_USED_DESCR_NO,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxUsedDescrNo),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RX_DELIVERED_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RxDeliveredCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RX_OCTETS_DELIV_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RxOctetsDeliveredCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RX_HW_ERROR_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RxHwErrorsCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TX_HW_ERROR_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TxHwErrorsCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_IN_ERRORS_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(InErrorsCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_OUT_ERROR_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(OutErrorsCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_ERR_RECOVERY_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(ErrRecoveryCts),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_SYSUPTIME,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(SysUpTime),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_SENSOR_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(SensorNumber),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_SENSOR_INDEX,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_DESCR,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_TYPE,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_VALUE,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_WAR_THRES_LOW,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_WAR_THRES_UPP,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_ERR_THRES_LOW,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_ERR_THRES_UPP,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_STATUS,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_WAR_CTS,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_ERR_CTS,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_WAR_TIME,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_SENSOR_ERR_TIME,
+ SK_PNMI_SENSOR_ENTRIES,
+ sizeof(SK_PNMI_SENSOR),
+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp),
+ SK_PNMI_RO, SensorStat, 0},
+ {OID_SKGE_CHKSM_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(ChecksumNumber),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_CHKSM_RX_OK_CTS,
+ SKCS_NUM_PROTOCOLS,
+ sizeof(SK_PNMI_CHECKSUM),
+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts),
+ SK_PNMI_RO, CsumStat, 0},
+ {OID_SKGE_CHKSM_RX_UNABLE_CTS,
+ SKCS_NUM_PROTOCOLS,
+ sizeof(SK_PNMI_CHECKSUM),
+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts),
+ SK_PNMI_RO, CsumStat, 0},
+ {OID_SKGE_CHKSM_RX_ERR_CTS,
+ SKCS_NUM_PROTOCOLS,
+ sizeof(SK_PNMI_CHECKSUM),
+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts),
+ SK_PNMI_RO, CsumStat, 0},
+ {OID_SKGE_CHKSM_TX_OK_CTS,
+ SKCS_NUM_PROTOCOLS,
+ sizeof(SK_PNMI_CHECKSUM),
+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts),
+ SK_PNMI_RO, CsumStat, 0},
+ {OID_SKGE_CHKSM_TX_UNABLE_CTS,
+ SKCS_NUM_PROTOCOLS,
+ sizeof(SK_PNMI_CHECKSUM),
+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts),
+ SK_PNMI_RO, CsumStat, 0},
+ {OID_SKGE_STAT_TX,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX},
+ {OID_SKGE_STAT_TX_OCTETS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET},
+ {OID_SKGE_STAT_TX_BROADCAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST},
+ {OID_SKGE_STAT_TX_MULTICAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST},
+ {OID_SKGE_STAT_TX_UNICAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST},
+ {OID_SKGE_STAT_TX_LONGFRAMES,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES},
+ {OID_SKGE_STAT_TX_BURST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST},
+ {OID_SKGE_STAT_TX_PFLOWC,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC},
+ {OID_SKGE_STAT_TX_FLOWC,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC},
+ {OID_SKGE_STAT_TX_SINGLE_COL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL},
+ {OID_SKGE_STAT_TX_MULTI_COL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL},
+ {OID_SKGE_STAT_TX_EXCESS_COL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL},
+ {OID_SKGE_STAT_TX_LATE_COL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL},
+ {OID_SKGE_STAT_TX_DEFFERAL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL},
+ {OID_SKGE_STAT_TX_EXCESS_DEF,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF},
+ {OID_SKGE_STAT_TX_UNDERRUN,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN},
+ {OID_SKGE_STAT_TX_CARRIER,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER},
+/* {OID_SKGE_STAT_TX_UTIL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization),
+ SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
+ {OID_SKGE_STAT_TX_64,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64},
+ {OID_SKGE_STAT_TX_127,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127},
+ {OID_SKGE_STAT_TX_255,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255},
+ {OID_SKGE_STAT_TX_511,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511},
+ {OID_SKGE_STAT_TX_1023,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023},
+ {OID_SKGE_STAT_TX_MAX,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX},
+ {OID_SKGE_STAT_TX_SYNC,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC},
+ {OID_SKGE_STAT_TX_SYNC_OCTETS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET},
+ {OID_SKGE_STAT_RX,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX},
+ {OID_SKGE_STAT_RX_OCTETS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET},
+ {OID_SKGE_STAT_RX_BROADCAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST},
+ {OID_SKGE_STAT_RX_MULTICAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST},
+ {OID_SKGE_STAT_RX_UNICAST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST},
+ {OID_SKGE_STAT_RX_PFLOWC,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC},
+ {OID_SKGE_STAT_RX_FLOWC,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC},
+ {OID_SKGE_STAT_RX_PFLOWC_ERR,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR},
+ {OID_SKGE_STAT_RX_FLOWC_UNKWN,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN},
+ {OID_SKGE_STAT_RX_BURST,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST},
+ {OID_SKGE_STAT_RX_MISSED,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED},
+ {OID_SKGE_STAT_RX_FRAMING,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING},
+ {OID_SKGE_STAT_RX_OVERFLOW,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW},
+ {OID_SKGE_STAT_RX_JABBER,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER},
+ {OID_SKGE_STAT_RX_CARRIER,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER},
+ {OID_SKGE_STAT_RX_IR_LENGTH,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH},
+ {OID_SKGE_STAT_RX_SYMBOL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL},
+ {OID_SKGE_STAT_RX_SHORTS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS},
+ {OID_SKGE_STAT_RX_RUNT,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT},
+ {OID_SKGE_STAT_RX_CEXT,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT},
+ {OID_SKGE_STAT_RX_TOO_LONG,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG},
+ {OID_SKGE_STAT_RX_FCS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS},
+/* {OID_SKGE_STAT_RX_UTIL,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization),
+ SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
+ {OID_SKGE_STAT_RX_64,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64},
+ {OID_SKGE_STAT_RX_127,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127},
+ {OID_SKGE_STAT_RX_255,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255},
+ {OID_SKGE_STAT_RX_511,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511},
+ {OID_SKGE_STAT_RX_1023,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023},
+ {OID_SKGE_STAT_RX_MAX,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_STAT),
+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts),
+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX},
+ {OID_SKGE_PHYS_CUR_ADDR,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr),
+ SK_PNMI_RW, Addr, 0},
+ {OID_SKGE_PHYS_FAC_ADDR,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr),
+ SK_PNMI_RO, Addr, 0},
+ {OID_SKGE_PMD,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_CONNECTOR,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_LINK_CAP,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_LINK_MODE,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode),
+ SK_PNMI_RW, MacPrivateConf, 0},
+ {OID_SKGE_LINK_MODE_STATUS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_LINK_STATUS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_FLOWCTRL_CAP,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_FLOWCTRL_MODE,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode),
+ SK_PNMI_RW, MacPrivateConf, 0},
+ {OID_SKGE_FLOWCTRL_STATUS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_PHY_OPERATION_CAP,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_PHY_OPERATION_MODE,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode),
+ SK_PNMI_RW, MacPrivateConf, 0},
+ {OID_SKGE_PHY_OPERATION_STATUS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_CONF),
+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus),
+ SK_PNMI_RO, MacPrivateConf, 0},
+ {OID_SKGE_TRAP,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(Trap),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_TRAP_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(TrapNumber),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RLMT_MODE,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtMode),
+ SK_PNMI_RW, Rlmt, 0},
+ {OID_SKGE_RLMT_PORT_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtPortNumber),
+ SK_PNMI_RO, Rlmt, 0},
+ {OID_SKGE_RLMT_PORT_ACTIVE,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtPortActive),
+ SK_PNMI_RO, Rlmt, 0},
+ {OID_SKGE_RLMT_PORT_PREFERED,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtPortPreferred),
+ SK_PNMI_RW, Rlmt, 0},
+ {OID_SKGE_RLMT_CHANGE_CTS,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtChangeCts),
+ SK_PNMI_RO, Rlmt, 0},
+ {OID_SKGE_RLMT_CHANGE_TIME,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtChangeTime),
+ SK_PNMI_RO, Rlmt, 0},
+ {OID_SKGE_RLMT_CHANGE_ESTIM,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtChangeEstimate),
+ SK_PNMI_RO, Rlmt, 0},
+ {OID_SKGE_RLMT_CHANGE_THRES,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtChangeThreshold),
+ SK_PNMI_RW, Rlmt, 0},
+ {OID_SKGE_RLMT_PORT_INDEX,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_STATUS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_TX_HELLO_CTS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_RX_HELLO_CTS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_TX_SP_REQ_CTS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_RX_SP_CTS,
+ SK_PNMI_MAC_ENTRIES,
+ sizeof(SK_PNMI_RLMT),
+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts),
+ SK_PNMI_RO, RlmtStat, 0},
+ {OID_SKGE_RLMT_MONITOR_NUMBER,
+ 1,
+ 0,
+ SK_PNMI_MAI_OFF(RlmtMonitorNumber),
+ SK_PNMI_RO, General, 0},
+ {OID_SKGE_RLMT_MONITOR_INDEX,
+ SK_PNMI_MONITOR_ENTRIES,
+ sizeof(SK_PNMI_RLMT_MONITOR),
+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex),
+ SK_PNMI_RO, Monitor, 0},
+ {OID_SKGE_RLMT_MONITOR_ADDR,
+ SK_PNMI_MONITOR_ENTRIES,
+ sizeof(SK_PNMI_RLMT_MONITOR),
+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr),
+ SK_PNMI_RO, Monitor, 0},
+ {OID_SKGE_RLMT_MONITOR_ERRS,
+ SK_PNMI_MONITOR_ENTRIES,
+ sizeof(SK_PNMI_RLMT_MONITOR),
+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts),
+ SK_PNMI_RO, Monitor, 0},
+ {OID_SKGE_RLMT_MONITOR_TIMESTAMP,
+ SK_PNMI_MONITOR_ENTRIES,
+ sizeof(SK_PNMI_RLMT_MONITOR),
+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp),
+ SK_PNMI_RO, Monitor, 0},
+ {OID_SKGE_RLMT_MONITOR_ADMIN,
+ SK_PNMI_MONITOR_ENTRIES,
+ sizeof(SK_PNMI_RLMT_MONITOR),
+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin),
+ SK_PNMI_RW, Monitor, 0},
+};
+
+/*
+ * Table for hardware register saving on resets and port switches
+*/
+static const SK_PNMI_STATADDR StatAddress[SK_PNMI_MAX_IDX] = {
+ /* 0 */ {TRUE, XM_TXF_OK},
+ /* 1 */ {TRUE, 0},
+ /* 2 */ {FALSE, 0},
+ /* 3 */ {TRUE, XM_TXF_BC_OK},
+ /* 4 */ {TRUE, XM_TXF_MC_OK},
+ /* 5 */ {TRUE, XM_TXF_UC_OK},
+ /* 6 */ {TRUE, XM_TXF_LONG},
+ /* 7 */ {TRUE, XM_TXE_BURST},
+ /* 8 */ {TRUE, XM_TXF_MPAUSE},
+ /* 9 */ {TRUE, XM_TXF_MCTRL},
+ /* 10 */ {TRUE, XM_TXF_SNG_COL},
+ /* 11 */ {TRUE, XM_TXF_MUL_COL},
+ /* 12 */ {TRUE, XM_TXF_ABO_COL},
+ /* 13 */ {TRUE, XM_TXF_LAT_COL},
+ /* 14 */ {TRUE, XM_TXF_DEF},
+ /* 15 */ {TRUE, XM_TXF_EX_DEF},
+ /* 16 */ {TRUE, XM_TXE_FIFO_UR},
+ /* 17 */ {TRUE, XM_TXE_CS_ERR},
+ /* 18 */ {FALSE, 0},
+ /* 19 */ {FALSE, 0},
+ /* 20 */ {TRUE, XM_TXF_64B},
+ /* 21 */ {TRUE, XM_TXF_127B},
+ /* 22 */ {TRUE, XM_TXF_255B},
+ /* 23 */ {TRUE, XM_TXF_511B},
+ /* 24 */ {TRUE, XM_TXF_1023B},
+ /* 25 */ {TRUE, XM_TXF_MAX_SZ},
+ /* 26 */ {FALSE, 0},
+ /* 27 */ {FALSE, 0},
+ /* 28 */ {FALSE, 0},
+ /* 29 */ {FALSE, 0},
+ /* 30 */ {FALSE, 0},
+ /* 31 */ {FALSE, 0},
+ /* 32 */ {TRUE, XM_RXF_OK},
+ /* 33 */ {TRUE, 0},
+ /* 34 */ {FALSE, 0},
+ /* 35 */ {TRUE, XM_RXF_BC_OK},
+ /* 36 */ {TRUE, XM_RXF_MC_OK},
+ /* 37 */ {TRUE, XM_RXF_UC_OK},
+ /* 38 */ {TRUE, XM_RXF_MPAUSE},
+ /* 39 */ {TRUE, XM_RXF_MCTRL},
+ /* 40 */ {TRUE, XM_RXF_INV_MP},
+ /* 41 */ {TRUE, XM_RXF_INV_MOC},
+ /* 42 */ {TRUE, XM_RXE_BURST},
+ /* 43 */ {TRUE, XM_RXE_FMISS},
+ /* 44 */ {TRUE, XM_RXF_FRA_ERR},
+ /* 45 */ {TRUE, XM_RXE_FIFO_OV},
+ /* 46 */ {TRUE, XM_RXF_JAB_PKT},
+ /* 47 */ {TRUE, XM_RXE_CAR_ERR},
+ /* 48 */ {TRUE, XM_RXF_LEN_ERR},
+ /* 49 */ {TRUE, XM_RXE_SYM_ERR},
+ /* 50 */ {TRUE, XM_RXE_SHT_ERR},
+ /* 51 */ {TRUE, XM_RXE_RUNT},
+ /* 52 */ {TRUE, XM_RXF_LNG_ERR},
+ /* 53 */ {TRUE, XM_RXF_FCS_ERR},
+ /* 54 */ {FALSE, 0},
+ /* 55 */ {TRUE, XM_RXF_CEX_ERR},
+ /* 56 */ {FALSE, 0},
+ /* 57 */ {FALSE, 0},
+ /* 58 */ {TRUE, XM_RXF_64B},
+ /* 59 */ {TRUE, XM_RXF_127B},
+ /* 60 */ {TRUE, XM_RXF_255B},
+ /* 61 */ {TRUE, XM_RXF_511B},
+ /* 62 */ {TRUE, XM_RXF_1023B},
+ /* 63 */ {TRUE, XM_RXF_MAX_SZ},
+ /* 64 */ {FALSE, 0},
+ /* 65 */ {FALSE, 0}
+};
+
+
+/*****************************************************************************
+ *
+ * Public functions
+ *
+ */
+
+/*****************************************************************************
+ *
+ * SkPnmiInit - Init function of PNMI
+ *
+ * Description:
+ * SK_INIT_DATA: Initialises the data structures
+ * SK_INIT_IO: Resets the XMAC statistics, determines the device and
+ * connector type.
+ * SK_INIT_RUN: Starts a timer event for port switch per hour
+ * calculation.
+ *
+ * Returns:
+ * Always 0
+ */
+
+int SkPnmiInit(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Level) /* Initialization level */
+{
+ unsigned int PortMax; /* Number of ports */
+ unsigned int PortIndex; /* Current port index in loop */
+ SK_U16 Val16; /* Multiple purpose 16 bit variable */
+ SK_U8 Val8; /* Mulitple purpose 8 bit variable */
+ SK_EVPARA EventParam; /* Event struct for timer event */
+
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiInit: Called, level=%d\n", Level));
+
+ switch (Level) {
+
+ case SK_INIT_DATA:
+ SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
+ pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
+ pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+ pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
+ for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
+
+ pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
+ }
+ break;
+
+ case SK_INIT_IO:
+ /*
+ * Reset MAC counters
+ */
+ PortMax = pAC->GIni.GIMacsFound;
+
+ for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
+
+ Val16 = XM_SC_CLR_RXC | XM_SC_CLR_TXC;
+ XM_OUT16(IoC, PortIndex, XM_STAT_CMD, Val16);
+ /* Clear two times according to Errata #3 */
+ XM_OUT16(IoC, PortIndex, XM_STAT_CMD, Val16);
+ }
+
+ /*
+ * Get pci bus speed
+ */
+ SK_IN16(IoC, B0_CTST, &Val16);
+ if ((Val16 & CS_BUS_CLOCK) == 0) {
+
+ pAC->Pnmi.PciBusSpeed = 33;
+ }
+ else {
+ pAC->Pnmi.PciBusSpeed = 66;
+ }
+
+ /*
+ * Get pci bus width
+ */
+ SK_IN16(IoC, B0_CTST, &Val16);
+ if ((Val16 & CS_BUS_SLOT_SZ) == 0) {
+
+ pAC->Pnmi.PciBusWidth = 32;
+ }
+ else {
+ pAC->Pnmi.PciBusWidth = 64;
+ }
+
+ /*
+ * Get PMD and DeviceType
+ */
+ SK_IN8(IoC, B2_PMD_TYP, &Val8);
+ switch (Val8) {
+ case 'S':
+ pAC->Pnmi.PMD = 3;
+ if (pAC->GIni.GIMacsFound > 1) {
+
+ pAC->Pnmi.DeviceType = 0x00020002;
+ }
+ else {
+ pAC->Pnmi.DeviceType = 0x00020001;
+ }
+ break;
+
+ case 'L':
+ pAC->Pnmi.PMD = 2;
+ if (pAC->GIni.GIMacsFound > 1) {
+
+ pAC->Pnmi.DeviceType = 0x00020004;
+ }
+ else {
+ pAC->Pnmi.DeviceType = 0x00020003;
+ }
+ break;
+
+ case 'C':
+ pAC->Pnmi.PMD = 4;
+ if (pAC->GIni.GIMacsFound > 1) {
+
+ pAC->Pnmi.DeviceType = 0x00020006;
+ }
+ else {
+ pAC->Pnmi.DeviceType = 0x00020005;
+ }
+ break;
+
+ case 'T':
+ pAC->Pnmi.PMD = 5;
+ if (pAC->GIni.GIMacsFound > 1) {
+
+ pAC->Pnmi.DeviceType = 0x00020008;
+ }
+ else {
+ pAC->Pnmi.DeviceType = 0x00020007;
+ }
+ break;
+
+ default :
+ pAC->Pnmi.PMD = 1;
+ pAC->Pnmi.DeviceType = 0;
+ break;
+ }
+
+ /*
+ * Get connector
+ */
+ SK_IN8(IoC, B2_CONN_TYP, &Val8);
+ switch (Val8) {
+ case 'C':
+ pAC->Pnmi.Connector = 2;
+ break;
+
+ case 'D':
+ pAC->Pnmi.Connector = 3;
+ break;
+
+ case 'F':
+ pAC->Pnmi.Connector = 4;
+ break;
+
+ case 'J':
+ pAC->Pnmi.Connector = 5;
+ break;
+
+ default:
+ pAC->Pnmi.Connector = 1;
+ break;
+ }
+ break;
+
+ case SK_INIT_RUN:
+ /*
+ * Start timer for RLMT change counter
+ */
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
+ 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
+ EventParam);
+ break;
+
+ default:
+ break; /* Nothing todo */
+ }
+
+ return (0);
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiGetVar - Retrieves the value of a single OID
+ *
+ * Description:
+ * Calls a general sub-function for all this stuff. If the instance
+ * -1 is passed, the values of all instances are returned in an
+ * array of values.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
+ * the data.
+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+int SkPnmiGetVar(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+SK_U32 Id, /* Object ID that is to be processed */
+void *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance) /* Instance (1..n) that is to be queried or -1 */
+{
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d\n", Id,
+ *pLen));
+
+ return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen,
+ Instance));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiPreSetVar - Presets the value of a single OID
+ *
+ * Description:
+ * Calls a general sub-function for all this stuff. The preset does
+ * the same as a set, but returns just before finally setting the
+ * new value. This is usefull to check if a set might be successfull.
+ * If as instance a -1 is passed, an array of values is supposed and
+ * all instance of the OID will be set.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+int SkPnmiPreSetVar(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+SK_U32 Id, /* Object ID that is to be processed */
+void *pBuf, /* Buffer which stores the mgmt data to be set */
+unsigned int *pLen, /* Total length of mgmt data */
+SK_U32 Instance) /* Instance (1..n) that is to be set or -1 */
+{
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d\n",
+ Id, *pLen));
+
+ return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
+ Instance));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiSetVar - Sets the value of a single OID
+ *
+ * Description:
+ * Calls a general sub-function for all this stuff. The preset does
+ * the same as a set, but returns just before finally setting the
+ * new value. This is usefull to check if a set might be successfull.
+ * If as instance a -1 is passed, an array of values is supposed and
+ * all instance of the OID will be set.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+int SkPnmiSetVar(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+SK_U32 Id, /* Object ID that is to be processed */
+void *pBuf, /* Buffer which stores the mgmt data to be set */
+unsigned int *pLen, /* Total length of mgmt data */
+SK_U32 Instance) /* Instance (1..n) that is to be set or -1 */
+{
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d\n", Id,
+ *pLen));
+
+ return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen,
+ Instance));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ * Runs through the IdTable, queries the single OIDs and stores the
+ * returned data into the management database structure
+ * SK_PNMI_STRUCT_DATA. The offset of the OID in the structure
+ * is stored in the IdTable. The return value of the function will also
+ * be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
+ * minimum size of SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
+ * the data.
+ */
+
+int SkPnmiGetStruct(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+void *pBuf, /* Buffer which will store the retrieved data */
+unsigned int *pLen) /* Length of buffer */
+{
+ int Ret;
+ unsigned int TableIndex;
+ unsigned int DstOffset;
+ unsigned int InstanceNo;
+ unsigned int InstanceCnt;
+ SK_U32 Instance;
+ unsigned int TmpLen;
+ char KeyArr[SK_PNMI_VPD_ARR_SIZE][SK_PNMI_VPD_STR_SIZE];
+
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiGetStruct: Called, BufLen=%d\n", *pLen));
+
+ if (*pLen < SK_PNMI_STRUCT_SIZE) {
+
+ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
+
+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
+ (SK_U32)(-1));
+ }
+
+ *pLen = SK_PNMI_STRUCT_SIZE;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /* Update statistic */
+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
+
+ if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
+ SK_PNMI_ERR_OK) {
+
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+
+ if ((Ret = RlmtUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+
+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+
+ /*
+ * Increment semaphores to indicate that an update was
+ * already done
+ */
+ pAC->Pnmi.MacUpdatedFlag ++;
+ pAC->Pnmi.RlmtUpdatedFlag ++;
+ pAC->Pnmi.SirqUpdatedFlag ++;
+
+ /* Get vpd keys for instance calculation */
+ Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /* Retrieve values */
+ SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
+ for (TableIndex = 0; TableIndex < sizeof(IdTable)/sizeof(IdTable[0]);
+ TableIndex ++) {
+
+ InstanceNo = IdTable[TableIndex].InstanceNo;
+
+ for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
+ InstanceCnt ++) {
+
+ DstOffset = IdTable[TableIndex].Offset +
+ (InstanceCnt - 1) *
+ IdTable[TableIndex].StructSize;
+
+ /*
+ * For the VPD the instance is not an index number
+ * but the key itself. Determin with the instance
+ * counter the VPD key to be used.
+ */
+ if (IdTable[TableIndex].Id == OID_SKGE_VPD_KEY ||
+ IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE ||
+ IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS ||
+ IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) {
+
+ SK_PNMI_READ_U32(KeyArr[InstanceCnt - 1],
+ Instance);
+ }
+ else {
+ Instance = (SK_U32)InstanceCnt;
+ }
+
+ TmpLen = *pLen - DstOffset;
+ Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET,
+ IdTable[TableIndex].Id, (char *)pBuf +
+ DstOffset, &TmpLen, Instance, TableIndex);
+
+ /*
+ * An unknown instance error means that we reached
+ * the last instance of that variable. Proceed with
+ * the next OID in the table and ignore the return
+ * code.
+ */
+ if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
+
+ break;
+ }
+
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+ SK_PNMI_SET_STAT(pBuf, Ret, DstOffset);
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+ }
+ }
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ *pLen = SK_PNMI_STRUCT_SIZE;
+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ * Calls a general sub-function for all this set stuff. The preset does
+ * the same as a set, but returns just before finally setting the
+ * new value. This is usefull to check if a set might be successfull.
+ * The sub-function runs through the IdTable, checks which OIDs are able
+ * to set, and calls the handler function of the OID to perform the
+ * preset. The return value of the function will also be stored in
+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ * SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ */
+
+int SkPnmiPreSetStruct(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+void *pBuf, /* Buffer which contains the data to be set */
+unsigned int *pLen) /* Length of buffer */
+{
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d\n", *pLen));
+
+ return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf, pLen));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ * Calls a general sub-function for all this set stuff. The return value
+ * of the function will also be stored in SK_PNMI_STRUCT_DATA if the
+ * passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE.
+ * The sub-function runs through the IdTable, checks which OIDs are able
+ * to set, and calls the handler function of the OID to perform the
+ * set. The return value of the function will also be stored in
+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ * SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ */
+
+int SkPnmiSetStruct(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+void *pBuf, /* Buffer which contains the data to be set */
+unsigned int *pLen) /* Length of buffer */
+{
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiSetStruct: Called, BufLen=%d\n", *pLen));
+
+ return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf, pLen));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiEvent - Event handler
+ *
+ * Description:
+ * Handles the following events:
+ * SK_PNMI_EVT_SIRQ_OVERFLOW When a hardware counter overflows an
+ * interrupt will be generated which is
+ * first handled by SIRQ which generates a
+ * this event. The event increments the
+ * upper 32 bit of the 64 bit counter.
+ * SK_PNMI_EVT_SEN_XXX The event is generated by the I2C module
+ * when a sensor reports a warning or
+ * error. The event will store a trap
+ * message in the trap buffer.
+ * SK_PNMI_EVT_CHG_EST_TIMER The timer event was initiated by this
+ * module and is used to calculate the
+ * port switches per hour.
+ * SK_PNMI_EVT_CLEAR_COUNTER The event clears all counters and
+ * timestamps.
+ * SK_PNMI_EVT_XMAC_RESET The event is generated by the driver
+ * before a hard reset of the XMAC is
+ * performed. All counters will be saved
+ * and added to the hardware counter
+ * values after reset to grant continuous
+ * counter values.
+ * SK_PNMI_EVT_RLMT_PORT_UP Generated by RLMT to notify that a port
+ * went logically up. A trap message will
+ * be stored to the trap buffer.
+ * SK_PNMI_EVT_RLMT_PORT_DOWN Generated by RLMT to notify that a port
+ * went logically down. A trap message will
+ * be stored to the trap buffer.
+ * SK_PNMI_EVT_RLMT_PORT_SWITCH Generated by RLMT to notify that the
+ * active port switched. PNMI will split
+ * this into two message ACTIVE_DOWN and
+ * ACTIVE_UP to be future compatible with
+ * load balancing and card fail over.
+ * SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two
+ * spanning tree root bridges were
+ * detected. A trap message will be stored
+ * to the trap buffer.
+ * SK_PNMI_EVT_RLMT_ACTIVE_DOWN Notifies PNMI that an active port went
+ * down. PNMI will not further add the
+ * statistic values to the virtual port.
+ * SK_PNMI_EVT_RLMT_ACTIVE_UP Notifies PNMI that a port went up and
+ * is now an active port. PNMI will now
+ * add the statistic data of this port to
+ * the virtual port.
+ *
+ * Returns:
+ * Always 0
+ */
+
+int SkPnmiEvent(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+SK_U32 Event, /* Event-Id */
+SK_EVPARA Param) /* Event dependent parameter */
+{
+ unsigned int PhysPortIndex;
+ int CounterIndex;
+ int Ret;
+ SK_U16 MacStatus;
+ SK_U64 OverflowStatus;
+ SK_U64 Mask;
+ SK_U32 MacCntEvent;
+ SK_U64 Value;
+ SK_U16 Register;
+ SK_EVPARA EventParam;
+ SK_U64 NewestValue;
+ SK_U64 OldestValue;
+ SK_U64 Delta;
+ SK_PNMI_ESTIMATE *pEst;
+
+
+#ifdef DEBUG
+ if (Event != SK_PNMI_EVT_XMAC_RESET) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n",
+ (unsigned long)Event, (unsigned long)Param.Para64));
+ }
+#endif
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call");
+
+ switch (Event) {
+
+ case SK_PNMI_EVT_SIRQ_OVERFLOW:
+ PhysPortIndex = (int)Param.Para32[0];
+ MacStatus = (SK_U16)Param.Para32[1];
+#ifdef DEBUG
+ if (PhysPortIndex >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter wrong, PhysPortIndex=0x%x\n",
+ PhysPortIndex));
+ return (0);
+ }
+#endif
+ OverflowStatus = 0;
+
+ /*
+ * Check which source caused an overflow interrupt. The
+ * interrupt source is a self-clearing register. We only
+ * need to check the interrupt source once. Another check
+ * will be done by the SIRQ module to be sure that no
+ * interrupt get lost during process time.
+ */
+ if ((MacStatus & XM_IS_RXC_OV) == XM_IS_RXC_OV) {
+
+ XM_IN32(IoC, PhysPortIndex, XM_RX_CNT_EV,
+ &MacCntEvent);
+ OverflowStatus |= (SK_U64)MacCntEvent << 32;
+ }
+ if ((MacStatus & XM_IS_TXC_OV) == XM_IS_TXC_OV) {
+
+ XM_IN32(IoC, PhysPortIndex, XM_TX_CNT_EV,
+ &MacCntEvent);
+ OverflowStatus |= (SK_U64)MacCntEvent;
+ }
+ if (OverflowStatus == 0) {
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+ }
+
+ /*
+ * Check the overflow status register and increment
+ * the upper dword of corresponding counter.
+ */
+ for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8;
+ CounterIndex ++) {
+
+ Mask = (SK_U64)1 << CounterIndex;
+ if ((OverflowStatus & Mask) == 0) {
+
+ continue;
+ }
+
+ switch (CounterIndex) {
+
+ case SK_PNMI_HTX_UTILUNDER:
+ case SK_PNMI_HTX_UTILOVER:
+ XM_IN16(IoC, PhysPortIndex, XM_TX_CMD,
+ &Register);
+ Register |= XM_TX_SAM_LINE;
+ XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD,
+ Register);
+ break;
+
+ case SK_PNMI_HRX_UTILUNDER:
+ case SK_PNMI_HRX_UTILOVER:
+ XM_IN16(IoC, PhysPortIndex, XM_RX_CMD,
+ &Register);
+ Register |= XM_RX_SAM_LINE;
+ XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD,
+ Register);
+ break;
+
+ case SK_PNMI_HTX_OCTETHIGH:
+ case SK_PNMI_HTX_OCTETLOW:
+ case SK_PNMI_HTX_RESERVED26:
+ case SK_PNMI_HTX_RESERVED27:
+ case SK_PNMI_HTX_RESERVED28:
+ case SK_PNMI_HTX_RESERVED29:
+ case SK_PNMI_HTX_RESERVED30:
+ case SK_PNMI_HTX_RESERVED31:
+ case SK_PNMI_HRX_OCTETHIGH:
+ case SK_PNMI_HRX_OCTETLOW:
+ case SK_PNMI_HRX_IRLENGTH:
+ case SK_PNMI_HRX_RESERVED22:
+ case SK_PNMI_HTX_SYNC:
+ case SK_PNMI_HTX_SYNC_OCTET:
+ break;
+
+ default:
+ pAC->Pnmi.Port[PhysPortIndex].
+ CounterHigh[CounterIndex] ++;
+ }
+ }
+ break;
+
+ case SK_PNMI_EVT_SEN_WAR_LOW:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n",
+ (unsigned int)Param.Para64));
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW,
+ (unsigned int)Param.Para64);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_SEN_WAR_UPP:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR:SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n",
+ (unsigned int)Param.Para64));
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP,
+ (unsigned int)Param.Para64);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_SEN_ERR_LOW:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n",
+ (unsigned int)Param.Para64));
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW,
+ (unsigned int)Param.Para64);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_SEN_ERR_UPP:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
+ (unsigned int)Param.Para64));
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP,
+ (unsigned int)Param.Para64);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_CHG_EST_TIMER:
+ /*
+ * Calculate port switch average on a per hour basis
+ * Time interval for check : 28125 ms
+ * Number of values for average : 8
+ *
+ * Be careful in changing these values, on change check
+ * - typedef of SK_PNMI_ESTIMATE (Size of EstValue
+ * array one less than value number)
+ * - Timer initilization SkTimerStart() in SkPnmiInit
+ * - Delta value below must be multiplicated with
+ * power of 2
+ *
+ */
+ pEst = &pAC->Pnmi.RlmtChangeEstimate;
+ CounterIndex = pEst->EstValueIndex + 1;
+ if (CounterIndex == 7) {
+
+ CounterIndex = 0;
+ }
+ pEst->EstValueIndex = CounterIndex;
+
+ NewestValue = pAC->Pnmi.RlmtChangeCts;
+ OldestValue = pEst->EstValue[CounterIndex];
+ pEst->EstValue[CounterIndex] = NewestValue;
+
+ /*
+ * Calculate average. Delta stores the number of
+ * port switches per 28125 * 8 = 225000 ms
+ */
+ if (NewestValue >= OldestValue) {
+
+ Delta = NewestValue - OldestValue;
+ }
+ else {
+ /* Overflow situation */
+ Delta = (SK_U64)(0 - OldestValue) + NewestValue;
+ }
+
+ /*
+ * Extrapolate delta to port switches per hour.
+ * Estimate = Delta * (3600000 / 225000)
+ * = Delta * 16
+ * = Delta << 4
+ */
+ pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4;
+
+ /*
+ * Check if threshold is exceeded. If the threshold is
+ * permanently exceeded every 28125 ms an event will be
+ * generated to remind the user of this condition.
+ */
+ if ((pAC->Pnmi.RlmtChangeThreshold != 0) &&
+ (pAC->Pnmi.RlmtChangeEstimate.Estimate >=
+ pAC->Pnmi.RlmtChangeThreshold)) {
+
+ QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ }
+
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
+ 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
+ EventParam);
+ break;
+
+ case SK_PNMI_EVT_CLEAR_COUNTER:
+ /*
+ * Set all counters and timestamps to zero
+ */
+ ResetCounter(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_XMAC_RESET:
+ /*
+ * To grant continuous counter values store the current
+ * XMAC statistic values to the entries 1..n of the
+ * CounterOffset array. XMAC Errata #2
+ */
+#ifdef DEBUG
+ if ((unsigned int)Param.Para64 >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n",
+ (unsigned int)Param.Para64));
+ return (0);
+ }
+#endif
+ PhysPortIndex = (unsigned int)Param.Para64;
+
+ /*
+ * Update XMAC statistic to get fresh values
+ */
+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+ }
+ /*
+ * Increment semaphore to indicate that an update was
+ * already done
+ */
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+ CounterIndex ++) {
+
+ if (!StatAddress[CounterIndex].GetOffset) {
+
+ continue;
+ }
+
+ pAC->Pnmi.Port[PhysPortIndex].
+ CounterOffset[CounterIndex] = GetPhysStatVal(
+ pAC, IoC, PhysPortIndex, CounterIndex);
+ pAC->Pnmi.Port[PhysPortIndex].
+ CounterHigh[CounterIndex] = 0;
+ }
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ break;
+
+ case SK_PNMI_EVT_RLMT_PORT_UP:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para32[0] >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter wrong, PhysPortIndex=%d\n",
+ (unsigned int)Param.Para32[0]));
+
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP,
+ (unsigned int)Param.Para32[0]);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_RLMT_PORT_DOWN:
+#ifdef DEBUG
+ if ((unsigned int)Param.Para32[0] >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter wrong, PhysPortIndex=%d\n",
+ (unsigned int)Param.Para32[0]));
+
+ return (0);
+ }
+#endif
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN,
+ (unsigned int)Param.Para32[0]);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ case SK_PNMI_EVT_RLMT_ACTIVE_DOWN:
+ PhysPortIndex = (unsigned int)Param.Para32[0];
+#ifdef DEBUG
+ if (PhysPortIndex >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n",
+ PhysPortIndex));
+ }
+#endif
+ /*
+ * Nothing to do if port is already inactive
+ */
+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ return (0);
+ }
+
+ /*
+ * Update statistic counters to calculate new offset
+ * for the virtual port and increment semaphore to
+ * indicate that an update was already done.
+ */
+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+ SK_PNMI_ERR_OK) {
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ /*
+ * Calculate new counter offset for virtual port to
+ * grant continous counting on port switches. The virtual
+ * port consists of all currently active ports. The port
+ * down event indicates that a port is removed fromt the
+ * virtual port. Therefore add the counter value of the
+ * removed port to the CounterOffset for the virtual port
+ * to grant the same counter value.
+ */
+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+ CounterIndex ++) {
+
+ if (!StatAddress[CounterIndex].GetOffset) {
+
+ continue;
+ }
+
+ Value = GetPhysStatVal(pAC, IoC, PhysPortIndex,
+ CounterIndex);
+
+ pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
+ }
+
+ /*
+ * Set port to inactive
+ */
+ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ break;
+
+ case SK_PNMI_EVT_RLMT_ACTIVE_UP:
+ PhysPortIndex = (unsigned int)Param.Para32[0];
+#ifdef DEBUG
+ if (PhysPortIndex >= SK_MAX_MACS) {
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n",
+ PhysPortIndex));
+ }
+#endif
+ /*
+ * Nothing to do if port is already active
+ */
+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ return (0);
+ }
+
+ /*
+ * Statistic maintanence
+ */
+ pAC->Pnmi.RlmtChangeCts ++;
+ pAC->Pnmi.RlmtChangeTime =
+ SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueRlmtNewMacTrap(pAC, PhysPortIndex);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+
+ /*
+ * Update statistic counters to calculate new offset
+ * for the virtual port and increment semaphore to indicate
+ * that an update was already done.
+ */
+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+ SK_PNMI_ERR_OK) {
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ /*
+ * Calculate new counter offset for virtual port to
+ * grant continous counting on port switches. A new port
+ * is added to the virtual port. Therefore substract the
+ * counter value of the new port from the CounterOffset
+ * for the virtual port to grant the same value.
+ */
+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+ CounterIndex ++) {
+
+ if (!StatAddress[CounterIndex].GetOffset) {
+
+ continue;
+ }
+
+ Value = GetPhysStatVal(pAC, IoC, PhysPortIndex,
+ CounterIndex);
+
+ pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
+ }
+
+ /*
+ * Set port to active
+ */
+ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ break;
+
+ case SK_PNMI_EVT_RLMT_PORT_SWITCH:
+ /*
+ * This event becomes obsolete if RLMT generates directly
+ * the events SK_PNMI_EVT_RLMT_ACTIVE_DOWN and
+ * SK_PNMI_EVT_RLMT_ACTIVE_UP. The events are here emulated.
+ * PNMI handles that multiple ports may become active.
+ * Increment semaphore to indicate that an update was
+ * already done.
+ */
+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+ SK_PNMI_ERR_OK) {
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Param);
+ Param.Para32[0] = Param.Para32[1];
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_RLMT_ACTIVE_UP, Param);
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ break;
+
+ case SK_PNMI_EVT_RLMT_SEGMENTATION:
+ /*
+ * Store a trap message in the trap buffer and generate
+ * an event for user space applications with the
+ * SK_DRIVER_SENDEVENT macro.
+ */
+ QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION);
+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);
+ break;
+
+ default:
+ break;
+ }
+
+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+ return (0);
+}
+
+
+/******************************************************************************
+ *
+ * Private functions
+ *
+ */
+
+/*****************************************************************************
+ *
+ * PnmiVar - Gets, presets, and sets single OIDs
+ *
+ * Description:
+ * Looks up the requested OID, calls the corresponding handler
+ * function, and passes the parameters with the get, preset, or
+ * set command. The function is called by SkGePnmiGetVar,
+ * SkGePnmiPreSetVar, or SkGePnmiSetVar.
+ *
+ * Returns:
+ * SK_PNMI_ERR_XXX. For details have a look to the description of the
+ * calling functions.
+ */
+
+static int PnmiVar(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer which stores the mgmt data to be set */
+unsigned int *pLen, /* Total length of mgmt data */
+SK_U32 Instance) /* Instance (1..n) that is to be set or -1 */
+{
+ unsigned int TableIndex;
+ int Ret;
+
+
+ if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_OID);
+ }
+
+ SK_PNMI_CHECKFLAGS("PnmiVar: On call");
+
+ Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen,
+ Instance, TableIndex);
+
+ SK_PNMI_CHECKFLAGS("PnmiVar: On return");
+
+ return (Ret);
+}
+
+/*****************************************************************************
+ *
+ * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ * The return value of the function will also be stored in
+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ * SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable,
+ * checks which OIDs are able to set, and calls the handler function of
+ * the OID to perform the set. The return value of the function will
+ * also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
+ * minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called
+ * by SkGePnmiPreSetStruct and SkGePnmiSetStruct.
+ *
+ * Returns:
+ * SK_PNMI_ERR_XXX. The codes are described in the calling functions.
+ */
+
+static int PnmiStruct(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Set action to be performed */
+char *pBuf, /* Buffer which contains the data to be set */
+unsigned int *pLen) /* Length of buffer */
+{
+ int Ret;
+ unsigned int TableIndex;
+ unsigned int DstOffset;
+ unsigned int Len;
+ unsigned int InstanceNo;
+ unsigned int InstanceCnt;
+ SK_U32 Instance;
+ SK_U32 Id;
+
+
+ /* Check if the passed buffer has the right size */
+ if (*pLen < SK_PNMI_STRUCT_SIZE) {
+
+ /* Check if we can return the error within the buffer */
+ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
+
+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
+ (SK_U32)(-1));
+ }
+
+ *pLen = SK_PNMI_STRUCT_SIZE;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ SK_PNMI_CHECKFLAGS("PnmiStruct: On call");
+
+ /*
+ * Update the values of RLMT and SIRQ and increment semaphores to
+ * indicate that an update was already done.
+ */
+ if ((Ret = RlmtUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+
+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (Ret);
+ }
+
+ pAC->Pnmi.RlmtUpdatedFlag ++;
+ pAC->Pnmi.SirqUpdatedFlag ++;
+
+ /* Preset/Set values */
+ for (TableIndex = 0; TableIndex < sizeof(IdTable)/sizeof(IdTable[0]);
+ TableIndex ++) {
+
+ if (IdTable[TableIndex].Access != SK_PNMI_RW) {
+
+ continue;
+ }
+
+ InstanceNo = IdTable[TableIndex].InstanceNo;
+ Id = IdTable[TableIndex].Id;
+
+ for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
+ InstanceCnt ++) {
+
+ DstOffset = IdTable[TableIndex].Offset +
+ (InstanceCnt - 1) *
+ IdTable[TableIndex].StructSize;
+
+ /*
+ * Because VPD multiple instance variables are
+ * not setable we do not need to evaluate VPD
+ * instances. Have a look to VPD instance
+ * calculation in SkPnmiGetStruct().
+ */
+ Instance = (SK_U32)InstanceCnt;
+
+ /*
+ * Evaluate needed buffer length
+ */
+ Len = 0;
+ Ret = IdTable[TableIndex].Func(pAC, IoC,
+ SK_PNMI_GET, IdTable[TableIndex].Id,
+ NULL, &Len, Instance, TableIndex);
+
+ if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
+
+ break;
+ }
+ if (Ret != SK_PNMI_ERR_TOO_SHORT) {
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+ SK_PNMI_SET_STAT(pBuf,
+ SK_PNMI_ERR_GENERAL, DstOffset);
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ if (Id == OID_SKGE_VPD_ACTION) {
+
+ switch (*(pBuf + DstOffset)) {
+
+ case SK_PNMI_VPD_CREATE:
+ Len = 3 + *(pBuf + DstOffset + 3);
+ break;
+
+ case SK_PNMI_VPD_DELETE:
+ Len = 3;
+ break;
+
+ default:
+ Len = 1;
+ break;
+ }
+ }
+
+ /* Call the OID handler function */
+ Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
+ IdTable[TableIndex].Id, pBuf + DstOffset,
+ &Len, Instance, TableIndex);
+
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE,
+ DstOffset);
+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ }
+ }
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * LookupId - Lookup an OID in the IdTable
+ *
+ * Description:
+ * Scans the IdTable to find the table entry of an OID.
+ *
+ * Returns:
+ * The table index or -1 if not found.
+ */
+
+static int LookupId(
+SK_U32 Id) /* Object identifier to be searched */
+{
+ int i;
+ int Len = sizeof(IdTable)/sizeof(IdTable[0]);
+
+ for (i=0; i<Len; i++) {
+
+ if (IdTable[i].Id == Id) {
+
+ return i;
+ }
+ }
+
+ return (-1);
+}
+
+/*****************************************************************************
+ *
+ * OidStruct - Handler of OID_SKGE_ALL_DATA
+ *
+ * Description:
+ * This OID performs a Get/Preset/SetStruct call and returns all data
+ * in a SK_PNMI_STRUCT_DATA structure.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int OidStruct(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ if (Id != OID_SKGE_ALL_DATA) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003,
+ SK_PNMI_ERR003MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Check instance. We only handle single instance variables
+ */
+ if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ switch (Action) {
+
+ case SK_PNMI_GET:
+ return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen));
+
+ case SK_PNMI_PRESET:
+ return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen));
+
+ case SK_PNMI_SET:
+ return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen));
+ }
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+}
+
+/*****************************************************************************
+ *
+ * Perform - OID handler of OID_SKGE_ACTION
+ *
+ * Description:
+ * None.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Perform(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ int Ret;
+ SK_U32 ActionOp;
+
+
+ /*
+ * Check instance. We only handle single instance variables
+ */
+ if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ if (*pLen < sizeof(SK_U32)) {
+
+ *pLen = sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /* Check if a get should be performed */
+ if (Action == SK_PNMI_GET) {
+
+ /* A get is easy. We always return the same value */
+ ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
+ SK_PNMI_STORE_U32(pBuf, ActionOp);
+ *pLen = sizeof(SK_U32);
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Continue with PRESET/SET action */
+ if (*pLen > sizeof(SK_U32)) {
+
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ /* Check if the command is a known one */
+ SK_PNMI_READ_U32(pBuf, ActionOp);
+ if (*pLen > sizeof(SK_U32) ||
+ (ActionOp != SK_PNMI_ACT_IDLE &&
+ ActionOp != SK_PNMI_ACT_RESET &&
+ ActionOp != SK_PNMI_ACT_SELFTEST &&
+ ActionOp != SK_PNMI_ACT_RESETCNT)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ /* A preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ switch (ActionOp) {
+
+ case SK_PNMI_ACT_IDLE:
+ /* Nothing to do */
+ break;
+
+ case SK_PNMI_ACT_RESET:
+ /*
+ * Perform a driver reset or something that comes near
+ * to this.
+ */
+ Ret = SK_DRIVER_RESET(pAC, IoC);
+ if (Ret != 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005,
+ SK_PNMI_ERR005MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ break;
+
+ case SK_PNMI_ACT_SELFTEST:
+ /*
+ * Perform a driver selftest or something similar to this.
+ * Currently this feature is not used and will probably
+ * implemented in another way.
+ */
+ Ret = SK_DRIVER_SELFTEST(pAC, IoC);
+ pAC->Pnmi.TestResult = Ret;
+ break;
+
+ case SK_PNMI_ACT_RESETCNT:
+ /* Set all counters and timestamps to zero */
+ ResetCounter(pAC, IoC);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006,
+ SK_PNMI_ERR006MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX
+ *
+ * Description:
+ * Retrieves the statistic values of the virtual port (logical
+ * index 0). Only special OIDs of NDIS are handled which consist
+ * of a 32 bit instead of a 64 bit value. The OIDs are public
+ * because perhaps some other platform can use them too.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Mac8023Stat(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ int Ret;
+ SK_U32 StatVal;
+
+
+ /*
+ * Only the active Mac is returned
+ */
+ if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ /*
+ * Check action type
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check length
+ */
+ switch (Id) {
+
+ case OID_802_3_PERMANENT_ADDRESS:
+ case OID_802_3_CURRENT_ADDRESS:
+ if (*pLen < sizeof(SK_MAC_ADDR)) {
+
+ *pLen = sizeof(SK_MAC_ADDR);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ if (*pLen < 4) {
+
+ *pLen = 4;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+ }
+
+ /*
+ * Update all statistics, because we retrieve virtual MAC, which
+ * consists of multiple physical statistics and increment semaphore
+ * to indicate that an update was already done.
+ */
+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+ if ( Ret != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ /*
+ * Get value (MAC Index 0 identifies the virtual MAC)
+ */
+ switch (Id) {
+
+ case OID_802_3_PERMANENT_ADDRESS:
+ CopyMac(pBuf, &pAC->Addr.PermanentMacAddress);
+ *pLen = sizeof(SK_MAC_ADDR);
+ break;
+
+ case OID_802_3_CURRENT_ADDRESS:
+ CopyMac(pBuf, &pAC->Addr.CurrentMacAddress);
+ *pLen = sizeof(SK_MAC_ADDR);
+ break;
+
+ default:
+ StatVal = (SK_U32)GetStatVal(pAC, IoC, 0,
+ IdTable[TableIndex].Param);
+ SK_PNMI_STORE_U32(pBuf, StatVal);
+ *pLen = sizeof(SK_U32);
+ break;
+ }
+
+ pAC->Pnmi.MacUpdatedFlag --;
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX
+ *
+ * Description:
+ * Retrieves the XMAC statistic data.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int MacPrivateStat(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int LogPortMax;
+ unsigned int LogPortIndex;
+ unsigned int PhysPortMax;
+ unsigned int Limit;
+ unsigned int Offset;
+ int Ret;
+ SK_U64 StatVal;
+
+
+ /*
+ * Calculate instance if wished. MAC index 0 is the virtual
+ * MAC.
+ */
+ PhysPortMax = pAC->GIni.GIMacsFound;
+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > LogPortMax)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+ Limit = LogPortIndex + 1;
+ }
+ else {
+ LogPortIndex = 0;
+ Limit = LogPortMax;
+ }
+
+ /*
+ * Check action
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check length
+ */
+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
+
+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * Update XMAC statistic and increment semaphore to indicate that
+ * an update was already done.
+ */
+ Ret = MacUpdate(pAC, IoC, 0, PhysPortMax - 1);
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ /*
+ * Get value
+ */
+ Offset = 0;
+ for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+ switch (Id) {
+
+/* XXX not yet implemented due to XMAC problems
+ case OID_SKGE_STAT_TX_UTIL:
+ return (SK_PNMI_ERR_GENERAL);
+*/
+/* XXX not yet implemented due to XMAC problems
+ case OID_SKGE_STAT_RX_UTIL:
+ return (SK_PNMI_ERR_GENERAL);
+*/
+ default:
+ StatVal = GetStatVal(pAC, IoC, LogPortIndex,
+ IdTable[TableIndex].Param);
+ SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
+ break;
+ }
+
+ Offset += sizeof(SK_U64);
+ }
+ *pLen = Offset;
+
+ pAC->Pnmi.MacUpdatedFlag --;
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR
+ *
+ * Description:
+ * Get/Presets/Sets the current and factory MAC address. The MAC
+ * address of the virtual port, which is reported to the OS, may
+ * not be changed, but the physical ones. A set to the virtual port
+ * will be ignored. No error should be reported because otherwise
+ * a multiple instance set (-1) would always fail.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Addr(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ int Ret;
+ unsigned int LogPortMax;
+ unsigned int PhysPortMax;
+ unsigned int LogPortIndex;
+ unsigned int PhysPortIndex;
+ unsigned int Limit;
+ unsigned int Offset = 0;
+
+
+ /*
+ * Calculate instance if wished
+ */
+ PhysPortMax = pAC->GIni.GIMacsFound;
+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+ Limit = LogPortIndex + 1;
+ }
+ else {
+ LogPortIndex = 0;
+ Limit = LogPortMax;
+ }
+
+ /*
+ * Perform Action
+ */
+ if (Action == SK_PNMI_GET) {
+
+ /*
+ * Check length
+ */
+ if (*pLen < (Limit - LogPortIndex) * 6) {
+
+ *pLen = (Limit - LogPortIndex) * 6;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * Get value
+ */
+ for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_PHYS_CUR_ADDR:
+ if (LogPortIndex == 0) {
+
+ CopyMac(pBuf + Offset, &pAC->Addr.
+ CurrentMacAddress);
+ }
+ else {
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ CopyMac(pBuf + Offset, &pAC->Addr.
+ Port[PhysPortIndex].
+ CurrentMacAddress);
+ }
+ Offset += 6;
+ break;
+
+ case OID_SKGE_PHYS_FAC_ADDR:
+ if (LogPortIndex == 0) {
+
+ CopyMac(pBuf + Offset, &pAC->Addr.
+ PermanentMacAddress);
+ }
+ else {
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ CopyMac(pBuf + Offset, &pAC->Addr.
+ Port[PhysPortIndex].
+ PermanentMacAddress);
+ }
+ Offset += 6;
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008,
+ SK_PNMI_ERR008MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+
+ *pLen = Offset;
+ }
+ else {
+ /*
+ * The logical MAC address may not be changed only
+ * the physical ones
+ */
+ if (Id == OID_SKGE_PHYS_FAC_ADDR) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Only the current address may be changed
+ */
+ if (Id != OID_SKGE_PHYS_CUR_ADDR) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009,
+ SK_PNMI_ERR009MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Check length
+ */
+ if (*pLen < (Limit - LogPortIndex) * 6) {
+
+ *pLen = (Limit - LogPortIndex) * 6;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ if (*pLen > (Limit - LogPortIndex) * 6) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ /*
+ * Check Action
+ */
+ if (Action == SK_PNMI_PRESET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /*
+ * Set OID_SKGE_MAC_CUR_ADDR
+ */
+ for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
+
+ /*
+ * A set to virtual port and set of broadcast
+ * address will be ignored
+ */
+ if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
+ "\xff\xff\xff\xff\xff\xff", 6) == 0) {
+
+ continue;
+ }
+
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC,
+ LogPortIndex);
+
+ Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
+ (SK_MAC_ADDR *)(pBuf + Offset),
+ (LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS :
+ SK_ADDR_PHYSICAL_ADDRESS));
+ if (Ret != SK_ADDR_OVERRIDE_SUCCESS) {
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ *pLen = Offset;
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX
+ *
+ * Description:
+ * Retrieves the statistic values of the CSUM module. The CSUM data
+ * structure must be available in the SK_AC even if the CSUM module
+ * is not included, because PNMI reads the statistic data from the
+ * CSUM part of SK_AC directly.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int CsumStat(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int Index;
+ unsigned int Limit;
+ unsigned int Offset = 0;
+ SK_U64 StatVal;
+
+
+ /*
+ * Calculate instance if wished
+ */
+ if (Instance != (SK_U32)(-1)) {
+
+ if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ Index = (unsigned int)Instance - 1;
+ Limit = (unsigned int)Instance;
+ }
+ else {
+ Index = 0;
+ Limit = SKCS_NUM_PROTOCOLS;
+ }
+
+ /*
+ * Check action
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check length
+ */
+ if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
+
+ *pLen = (Limit - Index) * sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * Get value
+ */
+ for (; Index < Limit; Index ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_CHKSM_RX_OK_CTS:
+ StatVal = pAC->Csum.ProtoStats[Index].RxOkCts;
+ break;
+
+ case OID_SKGE_CHKSM_RX_UNABLE_CTS:
+ StatVal = pAC->Csum.ProtoStats[Index].RxUnableCts;
+ break;
+
+ case OID_SKGE_CHKSM_RX_ERR_CTS:
+ StatVal = pAC->Csum.ProtoStats[Index].RxErrCts;
+ break;
+
+ case OID_SKGE_CHKSM_TX_OK_CTS:
+ StatVal = pAC->Csum.ProtoStats[Index].TxOkCts;
+ break;
+
+ case OID_SKGE_CHKSM_TX_UNABLE_CTS:
+ StatVal = pAC->Csum.ProtoStats[Index].TxUnableCts;
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010,
+ SK_PNMI_ERR010MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
+ Offset += sizeof(SK_U64);
+ }
+
+ /*
+ * Store used buffer space
+ */
+ *pLen = Offset;
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX
+ *
+ * Description:
+ * Retrieves the statistic values of the I2C module, which handles
+ * the temperature and voltage sensors.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int SensorStat(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int i;
+ unsigned int Index;
+ unsigned int Limit;
+ unsigned int Offset;
+ unsigned int Len;
+ SK_U32 Val32;
+ SK_U64 Val64;
+
+
+ /*
+ * Calculate instance if wished
+ */
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ Index = (unsigned int)Instance -1;
+ Limit = (unsigned int)Instance;
+ }
+ else {
+ Index = 0;
+ Limit = (unsigned int) pAC->I2c.MaxSens;
+ }
+
+ /*
+ * Check action
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check length
+ */
+ switch (Id) {
+
+ case OID_SKGE_SENSOR_VALUE:
+ case OID_SKGE_SENSOR_WAR_THRES_LOW:
+ case OID_SKGE_SENSOR_WAR_THRES_UPP:
+ case OID_SKGE_SENSOR_ERR_THRES_LOW:
+ case OID_SKGE_SENSOR_ERR_THRES_UPP:
+ if (*pLen < (Limit - Index) * sizeof(SK_U32)) {
+
+ *pLen = (Limit - Index) * sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_SENSOR_DESCR:
+ for (Offset = 0, i = Index; i < Limit; i ++) {
+
+ Len = (unsigned int)
+ SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1;
+ if (Len >= SK_PNMI_STRINGLEN2) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011,
+ SK_PNMI_ERR011MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ Offset += Len;
+ }
+ if (*pLen < Offset) {
+
+ *pLen = Offset;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_SENSOR_INDEX:
+ case OID_SKGE_SENSOR_TYPE:
+ case OID_SKGE_SENSOR_STATUS:
+ if (*pLen < Limit - Index) {
+
+ *pLen = Limit - Index;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_SENSOR_WAR_CTS:
+ case OID_SKGE_SENSOR_WAR_TIME:
+ case OID_SKGE_SENSOR_ERR_CTS:
+ case OID_SKGE_SENSOR_ERR_TIME:
+ if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
+
+ *pLen = (Limit - Index) * sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012,
+ SK_PNMI_ERR012MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+
+ }
+
+ /*
+ * Get value
+ */
+ for (Offset = 0; Index < Limit; Index ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_SENSOR_INDEX:
+ *(pBuf + Offset) = (char)Index;
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_SENSOR_DESCR:
+ Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
+ SK_MEMCPY(pBuf + Offset + 1,
+ pAC->I2c.SenTable[Index].SenDesc, Len);
+ *(pBuf + Offset) = (char)Len;
+ Offset += Len + 1;
+ break;
+
+ case OID_SKGE_SENSOR_TYPE:
+ *(pBuf + Offset) =
+ (char)pAC->I2c.SenTable[Index].SenType;
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_SENSOR_VALUE:
+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_WAR_THRES_LOW:
+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+ SenThreWarnLow;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_WAR_THRES_UPP:
+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+ SenThreWarnHigh;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_ERR_THRES_LOW:
+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+ SenThreErrLow;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_ERR_THRES_UPP:
+ Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_STATUS:
+ *(pBuf + Offset) =
+ (char)pAC->I2c.SenTable[Index].SenErrFlag;
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_SENSOR_WAR_CTS:
+ Val64 = pAC->I2c.SenTable[Index].SenWarnCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_SENSOR_ERR_CTS:
+ Val64 = pAC->I2c.SenTable[Index].SenErrCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_SENSOR_WAR_TIME:
+ Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
+ SenBegWarnTS);
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_SENSOR_ERR_TIME:
+ Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
+ SenBegErrTS);
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR013,
+ SK_PNMI_ERR013MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+
+ /*
+ * Store used buffer space
+ */
+ *pLen = Offset;
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Vpd - OID handler function of OID_SKGE_VPD_XXX
+ *
+ * Description:
+ * Get/preset/set of VPD data. As instance the name of a VPD key
+ * can be passed. The Instance parameter is a SK_U32 and can be
+ * used as a string buffer for the VPD key, because their maximum
+ * length is 4 byte.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Vpd(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ SK_VPD_STATUS *pVpdStatus;
+ unsigned int BufLen;
+ char Buf[256];
+ char KeyArr[SK_PNMI_VPD_ARR_SIZE][SK_PNMI_VPD_STR_SIZE];
+ char KeyStr[SK_PNMI_VPD_STR_SIZE];
+ unsigned int KeyNo;
+ unsigned int Offset;
+ unsigned int Index;
+ unsigned int FirstIndex;
+ unsigned int LastIndex;
+ unsigned int Len;
+ int Ret;
+ SK_U32 Val32;
+
+ /*
+ * Get array of all currently stored VPD keys
+ */
+ Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr),
+ &KeyNo);
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+
+ /*
+ * If instance is not -1, try to find the requested VPD key for
+ * the multiple instance variables. The other OIDs as for example
+ * OID VPD_ACTION are single instance variables and must be
+ * handled separatly.
+ */
+ FirstIndex = 0;
+ LastIndex = KeyNo;
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE ||
+ Id == OID_SKGE_VPD_ACCESS) {
+
+ SK_STRNCPY(KeyStr, (char *)&Instance, 4);
+ KeyStr[4] = 0;
+
+ for (Index = 0; Index < KeyNo; Index ++) {
+
+ if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
+
+ FirstIndex = Index;
+ LastIndex = Index+1;
+ break;
+ }
+ }
+ if (Index == KeyNo) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+ }
+ else if (Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+ }
+
+ /*
+ * Get value, if a query should be performed
+ */
+ if (Action == SK_PNMI_GET) {
+
+ switch (Id) {
+
+ case OID_SKGE_VPD_FREE_BYTES:
+ /* Check length of buffer */
+ if (*pLen < sizeof(SK_U32)) {
+
+ *pLen = sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ /* Get number of free bytes */
+ pVpdStatus = VpdStat(pAC, IoC);
+ if (pVpdStatus == NULL) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017,
+ SK_PNMI_ERR017MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018,
+ SK_PNMI_ERR018MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ Val32 = (SK_U32)pVpdStatus->vpd_free_rw;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_VPD_ENTRIES_LIST:
+ /* Check length */
+ for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
+
+ Len += SK_STRLEN(KeyArr[Index]) + 1;
+ }
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /* Get value */
+ *(pBuf) = (char)Len - 1;
+ for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
+
+ Len = SK_STRLEN(KeyArr[Index]);
+ SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len);
+
+ Offset += Len;
+
+ if (Index < KeyNo - 1) {
+
+ *(pBuf + Offset) = ' ';
+ Offset ++;
+ }
+ }
+ *pLen = Offset;
+ break;
+
+ case OID_SKGE_VPD_ENTRIES_NUMBER:
+ /* Check length */
+ if (*pLen < sizeof(SK_U32)) {
+
+ *pLen = sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ Val32 = (SK_U32)KeyNo;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_VPD_KEY:
+ /* Check buffer length, if it is large enough */
+ for (Len = 0, Index = FirstIndex;
+ Index < LastIndex; Index ++) {
+
+ Len += SK_STRLEN(KeyArr[Index]) + 1;
+ }
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * Get the key to an intermediate buffer, because
+ * we have to prepend a length byte.
+ */
+ for (Offset = 0, Index = FirstIndex;
+ Index < LastIndex; Index ++) {
+
+ Len = SK_STRLEN(KeyArr[Index]);
+
+ *(pBuf + Offset) = (char)Len;
+ SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index],
+ Len);
+ Offset += Len + 1;
+ }
+ *pLen = Offset;
+ break;
+
+ case OID_SKGE_VPD_VALUE:
+ /* Check the buffer length if it is large enough */
+ for (Offset = 0, Index = FirstIndex;
+ Index < LastIndex; Index ++) {
+
+ BufLen = 256;
+ if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
+ (int *)&BufLen) > 0 ||
+ BufLen >= SK_PNMI_VPD_DATALEN) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR021,
+ SK_PNMI_ERR021MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ Offset += BufLen + 1;
+ }
+ if (*pLen < Offset) {
+
+ *pLen = Offset;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * Get the value to an intermediate buffer, because
+ * we have to prepend a length byte.
+ */
+ for (Offset = 0, Index = FirstIndex;
+ Index < LastIndex; Index ++) {
+
+ BufLen = 256;
+ if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
+ (int *)&BufLen) > 0 ||
+ BufLen >= SK_PNMI_VPD_DATALEN) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR022,
+ SK_PNMI_ERR022MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ *(pBuf + Offset) = (char)BufLen;
+ SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen);
+ Offset += BufLen + 1;
+ }
+ *pLen = Offset;
+ break;
+
+ case OID_SKGE_VPD_ACCESS:
+ if (*pLen < LastIndex - FirstIndex) {
+
+ *pLen = LastIndex - FirstIndex;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ for (Offset = 0, Index = FirstIndex;
+ Index < LastIndex; Index ++) {
+
+ if (VpdMayWrite(KeyArr[Index])) {
+
+ *(pBuf + Offset) = SK_PNMI_VPD_RW;
+ }
+ else {
+ *(pBuf + Offset) = SK_PNMI_VPD_RO;
+ }
+ Offset ++;
+ }
+ *pLen = Offset;
+ break;
+
+ case OID_SKGE_VPD_ACTION:
+ Offset = LastIndex - FirstIndex;
+ if (*pLen < Offset) {
+
+ *pLen = Offset;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ SK_MEMSET(pBuf, 0, Offset);
+ *pLen = Offset;
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023,
+ SK_PNMI_ERR023MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ else {
+ /* The only OID which can be set is VPD_ACTION */
+ if (Id != OID_SKGE_VPD_ACTION) {
+
+ if (Id == OID_SKGE_VPD_FREE_BYTES ||
+ Id == OID_SKGE_VPD_ENTRIES_LIST ||
+ Id == OID_SKGE_VPD_ENTRIES_NUMBER ||
+ Id == OID_SKGE_VPD_KEY ||
+ Id == OID_SKGE_VPD_VALUE ||
+ Id == OID_SKGE_VPD_ACCESS) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024,
+ SK_PNMI_ERR024MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * From this point we handle VPD_ACTION. Check the buffer
+ * length. It should at least have the size of one byte.
+ */
+ if (*pLen < 1) {
+
+ *pLen = 1;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+
+ /*
+ * The first byte contains the VPD action type we should
+ * perform.
+ */
+ switch (*pBuf) {
+
+ case SK_PNMI_VPD_IGNORE:
+ /* Nothing to do */
+ break;
+
+ case SK_PNMI_VPD_CREATE:
+ /*
+ * We have to create a new VPD entry or we modify
+ * an existing one. Check first the buffer length.
+ */
+ if (*pLen < 4) {
+
+ *pLen = 4;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ KeyStr[0] = pBuf[1];
+ KeyStr[1] = pBuf[2];
+ KeyStr[2] = 0;
+
+ /*
+ * Is the entry writable or does it belong to the
+ * read-only area?
+ */
+ if (!VpdMayWrite(KeyStr)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ Offset = (int)pBuf[3] & 0xFF;
+
+ SK_MEMCPY(Buf, pBuf + 4, Offset);
+ Buf[Offset] = 0;
+
+ /* A preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Write the new entry or modify an existing one */
+ Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
+ if (Ret == SK_PNMI_VPD_NOWRITE ) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ else if (Ret != SK_PNMI_VPD_OK) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025,
+ SK_PNMI_ERR025MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Perform an update of the VPD data. This is
+ * not mandantory, but just to be sure.
+ */
+ Ret = VpdUpdate(pAC, IoC);
+ if (Ret != SK_PNMI_VPD_OK) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026,
+ SK_PNMI_ERR026MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ break;
+
+ case SK_PNMI_VPD_DELETE:
+ /* Check if the buffer size is plausible */
+ if (*pLen < 3) {
+
+ *pLen = 3;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ if (*pLen > 3) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ KeyStr[0] = pBuf[1];
+ KeyStr[1] = pBuf[2];
+ KeyStr[2] = 0;
+
+ /* Find the passed key in the array */
+ for (Index = 0; Index < KeyNo; Index ++) {
+
+ if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
+
+ break;
+ }
+ }
+ /*
+ * If we cannot find the key it is wrong, so we
+ * return an appropriate error value.
+ */
+ if (Index == KeyNo) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ if (Action == SK_PNMI_PRESET) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Ok, you wanted it and you will get it */
+ Ret = VpdDelete(pAC, IoC, KeyStr);
+ if (Ret != SK_PNMI_VPD_OK) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027,
+ SK_PNMI_ERR027MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Perform an update of the VPD data. This is
+ * not mandantory, but just to be sure.
+ */
+ Ret = VpdUpdate(pAC, IoC);
+ if (Ret != SK_PNMI_VPD_OK) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028,
+ SK_PNMI_ERR028MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ break;
+
+ default:
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * General - OID handler function of various single instance OIDs
+ *
+ * Description:
+ * The code is simple. No description necessary.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int General(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ int Ret;
+ unsigned int Index;
+ unsigned int Len;
+ unsigned int Offset;
+ unsigned int Val;
+ SK_U8 Val8;
+ SK_U16 Val16;
+ SK_U32 Val32;
+ SK_U64 Val64;
+ SK_U64 Val64RxHwErrs = 0;
+ SK_U64 Val64TxHwErrs = 0;
+ char Buf[256];
+
+
+ /*
+ * Check instance. We only handle single instance variables
+ */
+ if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ /*
+ * Check action. We only allow get requests.
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check length for the various supported OIDs
+ */
+ switch (Id) {
+
+ case OID_SKGE_PORT_NUMBER:
+ case OID_SKGE_DEVICE_TYPE:
+ case OID_SKGE_RESULT:
+ case OID_SKGE_RLMT_MONITOR_NUMBER:
+ case OID_GEN_XMIT_ERROR:
+ case OID_GEN_RCV_ERROR:
+ case OID_GEN_RCV_NO_BUFFER:
+ case OID_GEN_TRANSMIT_QUEUE_LENGTH:
+ case OID_SKGE_TRAP_NUMBER:
+ case OID_SKGE_MDB_VERSION:
+ if (*pLen < sizeof(SK_U32)) {
+
+ *pLen = sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_CHIPSET:
+ if (*pLen < sizeof(SK_U16)) {
+
+ *pLen = sizeof(SK_U16);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_BUS_TYPE:
+ case OID_SKGE_BUS_SPEED:
+ case OID_SKGE_BUS_WIDTH:
+ case OID_SKGE_SENSOR_NUMBER:
+ case OID_SKGE_CHKSM_NUMBER:
+ if (*pLen < sizeof(SK_U8)) {
+
+ *pLen = sizeof(SK_U8);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_TX_SW_QUEUE_LEN:
+ case OID_SKGE_TX_SW_QUEUE_MAX:
+ case OID_SKGE_TX_RETRY:
+ case OID_SKGE_RX_INTR_CTS:
+ case OID_SKGE_TX_INTR_CTS:
+ case OID_SKGE_RX_NO_BUF_CTS:
+ case OID_SKGE_TX_NO_BUF_CTS:
+ case OID_SKGE_TX_USED_DESCR_NO:
+ case OID_SKGE_RX_DELIVERED_CTS:
+ case OID_SKGE_RX_OCTETS_DELIV_CTS:
+ case OID_SKGE_RX_HW_ERROR_CTS:
+ case OID_SKGE_TX_HW_ERROR_CTS:
+ case OID_SKGE_IN_ERRORS_CTS:
+ case OID_SKGE_OUT_ERROR_CTS:
+ case OID_SKGE_ERR_RECOVERY_CTS:
+ case OID_SKGE_SYSUPTIME:
+ if (*pLen < sizeof(SK_U64)) {
+
+ *pLen = sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ /* Checked later */
+ break;
+ }
+
+ /* Update statistic */
+ if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
+ Id == OID_SKGE_TX_HW_ERROR_CTS ||
+ Id == OID_SKGE_IN_ERRORS_CTS ||
+ Id == OID_SKGE_OUT_ERROR_CTS ||
+ Id == OID_GEN_XMIT_ERROR ||
+ Id == OID_GEN_RCV_ERROR) {
+
+ /* Force the XMAC to update its statistic counters and
+ * Increment semaphore to indicate that an update was
+ * already done.
+ */
+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+ if (Ret != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.MacUpdatedFlag ++;
+
+ /*
+ * Some OIDs consist of multiple hardware counters. Those
+ * values which are contained in all of them will be added
+ * now.
+ */
+ switch (Id) {
+
+ case OID_SKGE_RX_HW_ERROR_CTS:
+ case OID_SKGE_IN_ERRORS_CTS:
+ case OID_GEN_RCV_ERROR:
+ Val64RxHwErrs =
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW)+
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH)+
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG)+
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT);
+ break;
+
+ case OID_SKGE_TX_HW_ERROR_CTS:
+ case OID_SKGE_OUT_ERROR_CTS:
+ case OID_GEN_XMIT_ERROR:
+ Val64TxHwErrs =
+ GetStatVal(pAC, IoC, 0,
+ SK_PNMI_HTX_EXCESS_COL) +
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL)+
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN)+
+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER)+
+ GetStatVal(pAC, IoC, 0,
+ SK_PNMI_HTX_EXCESS_COL);
+ break;
+ }
+ }
+
+ /*
+ * Retrieve value
+ */
+ switch (Id) {
+
+ case OID_SKGE_SUPPORTED_LIST:
+ Len = sizeof(IdTable)/sizeof(IdTable[0]) * sizeof(SK_U32);
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ for (Offset = 0, Index = 0; Offset < Len;
+ Offset += sizeof(SK_U32), Index ++) {
+
+ Val32 = (SK_U32)IdTable[Index].Id;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ }
+ *pLen = Len;
+ break;
+
+ case OID_SKGE_PORT_NUMBER:
+ Val32 = (SK_U32)pAC->GIni.GIMacsFound;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_DEVICE_TYPE:
+ Val32 = (SK_U32)pAC->Pnmi.DeviceType;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_DRIVER_DESCR:
+ if (pAC->Pnmi.pDriverDescription == NULL) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007,
+ SK_PNMI_ERR007MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
+ if (Len > SK_PNMI_STRINGLEN1) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029,
+ SK_PNMI_ERR029MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ *pBuf = (char)(Len - 1);
+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1);
+ *pLen = Len;
+ break;
+
+ case OID_SKGE_DRIVER_VERSION:
+ if (pAC->Pnmi.pDriverVersion == NULL) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
+ SK_PNMI_ERR030MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
+ if (Len > SK_PNMI_STRINGLEN1) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
+ SK_PNMI_ERR031MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ *pBuf = (char)(Len - 1);
+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1);
+ *pLen = Len;
+ break;
+
+ case OID_SKGE_HW_DESCR:
+ /*
+ * The hardware description is located in the VPD. This
+ * query may move to the initialisation routine. But
+ * the VPD data is cached and therefore a call here
+ * will not make much difference.
+ */
+ Len = 256;
+ if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032,
+ SK_PNMI_ERR032MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ Len ++;
+ if (Len > SK_PNMI_STRINGLEN1) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033,
+ SK_PNMI_ERR033MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ *pBuf = (char)(Len - 1);
+ SK_MEMCPY(pBuf + 1, Buf, Len - 1);
+ *pLen = Len;
+ break;
+
+ case OID_SKGE_HW_VERSION:
+ /* Oh, I love to do some string manipulation */
+ if (*pLen < 5) {
+
+ *pLen = 5;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
+ pBuf[0] = 4;
+ pBuf[1] = 'v';
+ pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F));
+ pBuf[3] = '.';
+ pBuf[4] = (char)(0x30 | (Val8 & 0x0F));
+ *pLen = 5;
+ break;
+
+ case OID_SKGE_CHIPSET:
+ Val16 = SK_PNMI_CHIPSET;
+ SK_PNMI_STORE_U16(pBuf, Val16);
+ *pLen = sizeof(SK_U16);
+ break;
+
+ case OID_SKGE_BUS_TYPE:
+ *pBuf = (char)SK_PNMI_BUS_PCI;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_BUS_SPEED:
+ *pBuf = pAC->Pnmi.PciBusSpeed;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_BUS_WIDTH:
+ *pBuf = pAC->Pnmi.PciBusWidth;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_RESULT:
+ Val32 = pAC->Pnmi.TestResult;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_SENSOR_NUMBER:
+ *pBuf = (char)pAC->I2c.MaxSens;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_CHKSM_NUMBER:
+ *pBuf = SKCS_NUM_PROTOCOLS;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_TRAP_NUMBER:
+ GetTrapQueueLen(pAC, &Len, &Val);
+ Val32 = (SK_U32)Val;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_TRAP:
+ GetTrapQueueLen(pAC, &Len, &Val);
+ if (*pLen < Len) {
+
+ *pLen = Len;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ CopyTrapQueue(pAC, pBuf);
+ *pLen = Len;
+ break;
+
+ case OID_SKGE_RLMT_MONITOR_NUMBER:
+/* XXX Not yet implemented by RLMT therefore we return zero elements */
+ Val32 = 0;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_TX_SW_QUEUE_LEN:
+ Val64 = pAC->Pnmi.TxSwQueueLen;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_SW_QUEUE_MAX:
+ Val64 = pAC->Pnmi.TxSwQueueMax;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_RETRY:
+ Val64 = pAC->Pnmi.TxRetryCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RX_INTR_CTS:
+ Val64 = pAC->Pnmi.RxIntrCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_INTR_CTS:
+ Val64 = pAC->Pnmi.TxIntrCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RX_NO_BUF_CTS:
+ Val64 = pAC->Pnmi.RxNoBufCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_NO_BUF_CTS:
+ Val64 = pAC->Pnmi.TxNoBufCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_USED_DESCR_NO:
+ Val64 = pAC->Pnmi.TxUsedDescrNo;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RX_DELIVERED_CTS:
+ Val64 = pAC->Pnmi.RxDeliveredCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RX_OCTETS_DELIV_CTS:
+ Val64 = pAC->Pnmi.RxOctetsDeliveredCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RX_HW_ERROR_CTS:
+ SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_TX_HW_ERROR_CTS:
+ SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_IN_ERRORS_CTS:
+ Val64 = Val64RxHwErrs + pAC->Pnmi.RxNoBufCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_OUT_ERROR_CTS:
+ Val64 = Val64TxHwErrs + pAC->Pnmi.TxNoBufCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_ERR_RECOVERY_CTS:
+ Val64 = pAC->Pnmi.ErrRecoveryCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_SYSUPTIME:
+ Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+ Val64 -= pAC->Pnmi.StartUpTime;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_MDB_VERSION:
+ Val32 = SK_PNMI_MDB_VERSION;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_GEN_RCV_ERROR:
+ Val32 = (SK_U32)(Val64RxHwErrs + pAC->Pnmi.RxNoBufCts);
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_GEN_XMIT_ERROR:
+ Val32 = (SK_U32)(Val64TxHwErrs + pAC->Pnmi.TxNoBufCts);
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_GEN_RCV_NO_BUFFER:
+ Val32 = (SK_U32)pAC->Pnmi.RxNoBufCts;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_GEN_TRANSMIT_QUEUE_LENGTH:
+ Val32 = (SK_U32)pAC->Pnmi.TxSwQueueLen;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034,
+ SK_PNMI_ERR034MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
+ Id == OID_SKGE_TX_HW_ERROR_CTS ||
+ Id == OID_SKGE_IN_ERRORS_CTS ||
+ Id == OID_SKGE_OUT_ERROR_CTS ||
+ Id == OID_GEN_XMIT_ERROR ||
+ Id == OID_GEN_RCV_ERROR) {
+
+ pAC->Pnmi.MacUpdatedFlag --;
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance.
+ *
+ * Description:
+ * Get/Presets/Sets the RLMT OIDs.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Rlmt(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ int Ret;
+ unsigned int PhysPortIndex;
+ unsigned int PhysPortMax;
+ SK_EVPARA EventParam;
+ SK_U32 Val32;
+ SK_U64 Val64;
+
+
+ /*
+ * Check instance. Only single instance OIDs are allowed here.
+ */
+ if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ /*
+ * Perform the requested action
+ */
+ if (Action == SK_PNMI_GET) {
+
+ /*
+ * Check if the buffer length is large enough.
+ */
+
+ switch (Id) {
+
+ case OID_SKGE_RLMT_MODE:
+ case OID_SKGE_RLMT_PORT_ACTIVE:
+ case OID_SKGE_RLMT_PORT_PREFERED:
+ if (*pLen < sizeof(SK_U8)) {
+
+ *pLen = sizeof(SK_U8);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_RLMT_PORT_NUMBER:
+ if (*pLen < sizeof(SK_U32)) {
+
+ *pLen = sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_CTS:
+ case OID_SKGE_RLMT_CHANGE_TIME:
+ case OID_SKGE_RLMT_CHANGE_ESTIM:
+ case OID_SKGE_RLMT_CHANGE_THRES:
+ if (*pLen < sizeof(SK_U64)) {
+
+ *pLen = sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035,
+ SK_PNMI_ERR035MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Update RLMT statistic and increment semaphores to indicate
+ * that an update was already done. Maybe RLMT will hold its
+ * statistic always up to date some time. Then we can
+ * remove this type of call.
+ */
+ if ((Ret = RlmtUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.RlmtUpdatedFlag ++;
+
+ /*
+ * Retrieve Value
+ */
+ switch (Id) {
+
+ case OID_SKGE_RLMT_MODE:
+ *pBuf = (char)pAC->Rlmt.RlmtMode;
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_RLMT_PORT_NUMBER:
+ Val32 = (SK_U32)pAC->GIni.GIMacsFound;
+ SK_PNMI_STORE_U32(pBuf, Val32);
+ *pLen = sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_RLMT_PORT_ACTIVE:
+ *pBuf = 0;
+ /*
+ * If multiple ports may become active this OID
+ * doesn't make sense any more. A new variable in
+ * the port structure should be created. However,
+ * for this variable the first active port is
+ * returned.
+ */
+ PhysPortMax = pAC->GIni.GIMacsFound;
+
+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+ PhysPortIndex ++) {
+
+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(
+ PhysPortIndex);
+ break;
+ }
+ }
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_RLMT_PORT_PREFERED:
+ *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(
+ pAC->Rlmt.MacPreferred);
+ *pLen = sizeof(char);
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_CTS:
+ Val64 = pAC->Pnmi.RlmtChangeCts;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_TIME:
+ Val64 = pAC->Pnmi.RlmtChangeTime;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_ESTIM:
+ Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_THRES:
+ Val64 = pAC->Pnmi.RlmtChangeThreshold;
+ SK_PNMI_STORE_U64(pBuf, Val64);
+ *pLen = sizeof(SK_U64);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR036,
+ SK_PNMI_ERR036MSG);
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ }
+ else {
+ /* Perform a preset or set */
+ switch (Id) {
+
+ case OID_SKGE_RLMT_MODE:
+ /* Check if the buffer length is plausible */
+ if (*pLen < sizeof(char)) {
+
+ *pLen = sizeof(char);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ /* Check if the value range is correct */
+ if (*pLen != sizeof(char) ||
+ (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
+ *(SK_U8 *)pBuf > 15) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ /* The preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_OK);
+ }
+ /* Send an event to RLMT to change the mode */
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ EventParam.Para32[0] |= (SK_U32)(*pBuf);
+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
+ EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037,
+ SK_PNMI_ERR037MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ break;
+
+ case OID_SKGE_RLMT_PORT_PREFERED:
+ /* Check if the buffer length is plausible */
+ if (*pLen < sizeof(char)) {
+
+ *pLen = sizeof(char);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ /* Check if the value range is correct */
+ if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
+ (SK_U8)pAC->GIni.GIMacsFound) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ /* The preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /*
+ * Send an event to RLMT change the preferred port.
+ * A param of -1 means automatic mode. RLMT will
+ * make the decision which is the preferred port.
+ */
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
+ EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038,
+ SK_PNMI_ERR038MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ break;
+
+ case OID_SKGE_RLMT_CHANGE_THRES:
+ /* Check if the buffer length is plausible */
+ if (*pLen < sizeof(SK_U64)) {
+
+ *pLen = sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ /*
+ * There are not many restrictions to the
+ * value range.
+ */
+ if (*pLen != sizeof(SK_U64)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ /* A preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_OK);
+ }
+ /*
+ * Store the new threshold, which will be taken
+ * on the next timer event.
+ */
+ SK_PNMI_READ_U64(pBuf, Val64);
+ pAC->Pnmi.RlmtChangeThreshold = Val64;
+ break;
+
+ default:
+ /* The other OIDs are not be able for set */
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance.
+ *
+ * Description:
+ * Performs get requests on multiple instance variables.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int RlmtStat(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int PhysPortMax;
+ unsigned int PhysPortIndex;
+ unsigned int Limit;
+ unsigned int Offset;
+ int Ret;
+ SK_U32 Val32;
+ SK_U64 Val64;
+
+
+ /*
+ * Calculate the port indexes from the instance
+ */
+ PhysPortMax = pAC->GIni.GIMacsFound;
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > PhysPortMax)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ PhysPortIndex = Instance - 1;
+ Limit = PhysPortIndex + 1;
+ }
+ else {
+ PhysPortIndex = 0;
+ Limit = PhysPortMax;
+ }
+
+ /*
+ * Currently only get requests are allowed.
+ */
+ if (Action != SK_PNMI_GET) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Check if the buffer length is large enough.
+ */
+ switch (Id) {
+
+ case OID_SKGE_RLMT_PORT_INDEX:
+ case OID_SKGE_RLMT_STATUS:
+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
+
+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ case OID_SKGE_RLMT_TX_HELLO_CTS:
+ case OID_SKGE_RLMT_RX_HELLO_CTS:
+ case OID_SKGE_RLMT_TX_SP_REQ_CTS:
+ case OID_SKGE_RLMT_RX_SP_CTS:
+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) {
+
+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U64);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039,
+ SK_PNMI_ERR039MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+
+ }
+
+ /*
+ * Update statistic and increment semaphores to indicate that
+ * an update was already done.
+ */
+ if ((Ret = RlmtUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.RlmtUpdatedFlag ++;
+
+ /*
+ * Get value
+ */
+ Offset = 0;
+ for (; PhysPortIndex < Limit; PhysPortIndex ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_RLMT_PORT_INDEX:
+ Val32 = PhysPortIndex;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_RLMT_STATUS:
+ if (pAC->Rlmt.Port[PhysPortIndex].PortState ==
+ SK_RLMT_PS_INIT ||
+ pAC->Rlmt.Port[PhysPortIndex].PortState ==
+ SK_RLMT_PS_DOWN) {
+
+ Val32 = SK_PNMI_RLMT_STATUS_ERROR;
+ }
+ else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ Val32 = SK_PNMI_RLMT_STATUS_ACTIVE;
+ }
+ else {
+ Val32 = SK_PNMI_RLMT_STATUS_STANDBY;
+ }
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ Offset += sizeof(SK_U32);
+ break;
+
+ case OID_SKGE_RLMT_TX_HELLO_CTS:
+ Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_RX_HELLO_CTS:
+ Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_TX_SP_REQ_CTS:
+ Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ case OID_SKGE_RLMT_RX_SP_CTS:
+ Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts;
+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+ Offset += sizeof(SK_U64);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040,
+ SK_PNMI_ERR040MSG);
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ *pLen = Offset;
+
+ pAC->Pnmi.RlmtUpdatedFlag --;
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * MacPrivateConf - OID handler function of OIDs concerning the configuration
+ *
+ * Description:
+ * Get/Presets/Sets the OIDs concerning the configuration.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int MacPrivateConf(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int PhysPortMax;
+ unsigned int PhysPortIndex;
+ unsigned int LogPortMax;
+ unsigned int LogPortIndex;
+ unsigned int Limit;
+ unsigned int Offset;
+ char Val8;
+ int Ret;
+ SK_EVPARA EventParam;
+
+
+ /*
+ * Calculate instance if wished. MAC index 0 is the virtual
+ * MAC.
+ */
+ PhysPortMax = pAC->GIni.GIMacsFound;
+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > LogPortMax)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+ Limit = LogPortIndex + 1;
+ }
+ else {
+ LogPortIndex = 0;
+ Limit = LogPortMax;
+ }
+
+ /*
+ * Perform action
+ */
+ if (Action == SK_PNMI_GET) {
+
+ /*
+ * Check length
+ */
+ switch (Id) {
+
+ case OID_SKGE_PMD:
+ case OID_SKGE_CONNECTOR:
+ case OID_SKGE_LINK_CAP:
+ case OID_SKGE_LINK_MODE:
+ case OID_SKGE_LINK_MODE_STATUS:
+ case OID_SKGE_LINK_STATUS:
+ case OID_SKGE_FLOWCTRL_CAP:
+ case OID_SKGE_FLOWCTRL_MODE:
+ case OID_SKGE_FLOWCTRL_STATUS:
+ case OID_SKGE_PHY_OPERATION_CAP:
+ case OID_SKGE_PHY_OPERATION_MODE:
+ case OID_SKGE_PHY_OPERATION_STATUS:
+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
+
+ *pLen = (Limit - LogPortIndex) *
+ sizeof(SK_U8);
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041,
+ SK_PNMI_ERR041MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ /*
+ * Update statistic and increment semaphore to indicate
+ * that an update was already done.
+ */
+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+ *pLen = 0;
+ return (Ret);
+ }
+ pAC->Pnmi.SirqUpdatedFlag ++;
+
+ /*
+ * Get value
+ */
+ Offset = 0;
+ for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_PMD:
+ *(pBuf + Offset) = pAC->Pnmi.PMD;
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_CONNECTOR:
+ *(pBuf + Offset) = pAC->Pnmi.Connector;
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_LINK_CAP:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical ports */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PLinkCap;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_LINK_MODE:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical ports */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PLinkModeConf;
+ }
+
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_LINK_MODE_STATUS:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) =
+ CalculateLinkModeStatus(pAC,
+ IoC, PhysPortIndex);
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_LINK_STATUS:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical ports */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) =
+ CalculateLinkStatus(pAC,
+ IoC, PhysPortIndex);
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_FLOWCTRL_CAP:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical ports */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PFlowCtrlCap;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_FLOWCTRL_MODE:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PFlowCtrlMode;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_FLOWCTRL_STATUS:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PFlowCtrlStatus;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_PHY_OPERATION_CAP:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical ports */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PMSCap;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_PHY_OPERATION_MODE:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PMSMode;
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_PHY_OPERATION_STATUS:
+ if (LogPortIndex == 0) {
+
+ /* Get value for virtual port */
+ VirtualConf(pAC, IoC, Id, pBuf +
+ Offset);
+ }
+ else {
+ /* Get value for physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+
+ *(pBuf + Offset) = pAC->GIni.GP[
+ PhysPortIndex].PMSStatus;
+ }
+ Offset += sizeof(char);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042,
+ SK_PNMI_ERR042MSG);
+
+ pAC->Pnmi.SirqUpdatedFlag --;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ *pLen = Offset;
+ pAC->Pnmi.SirqUpdatedFlag --;
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /*
+ * From here SET or PRESET action. Check if the passed
+ * buffer length is plausible.
+ */
+ switch (Id) {
+
+ case OID_SKGE_LINK_MODE:
+ case OID_SKGE_FLOWCTRL_MODE:
+ if (*pLen < Limit - LogPortIndex) {
+
+ *pLen = Limit - LogPortIndex;
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ if (*pLen != Limit - LogPortIndex) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+ break;
+
+ default:
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /*
+ * Perform preset or set
+ */
+ Offset = 0;
+ for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_LINK_MODE:
+ /* Check the value range */
+ Val8 = *(pBuf + Offset);
+ if (Val8 == 0) {
+
+ Offset += sizeof(char);
+ break;
+ }
+ if (Val8 < SK_LMODE_HALF ||
+ Val8 > SK_LMODE_AUTOSENSE) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ /* The preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ if (LogPortIndex == 0) {
+
+ /*
+ * The virtual port consists of all currently
+ * active ports. Find them and send an event
+ * with the new link mode to SIRQ.
+ */
+ for (PhysPortIndex = 0;
+ PhysPortIndex < PhysPortMax;
+ PhysPortIndex ++) {
+
+ if (!pAC->Pnmi.Port[PhysPortIndex].
+ ActiveFlag) {
+
+ continue;
+ }
+
+ EventParam.Para32[0] = PhysPortIndex;
+ EventParam.Para32[1] = (SK_U32)Val8;
+ if (SkGeSirqEvent(pAC, IoC,
+ SK_HWEV_SET_LMODE,
+ EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR043,
+ SK_PNMI_ERR043MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ }
+ else {
+ /*
+ * Send an event with the new link mode to
+ * the SIRQ module.
+ */
+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+ EventParam.Para32[1] = (SK_U32)Val8;
+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
+ EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR043,
+ SK_PNMI_ERR043MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ Offset += sizeof(char);
+ break;
+
+ case OID_SKGE_FLOWCTRL_MODE:
+ /* Check the value range */
+ Val8 = *(pBuf + Offset);
+ if (Val8 == 0) {
+
+ Offset += sizeof(char);
+ break;
+ }
+ if (Val8 < SK_FLOW_MODE_NONE ||
+ Val8 > SK_FLOW_MODE_SYM_OR_REM) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ /* The preset ends here */
+ if (Action == SK_PNMI_PRESET) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ if (LogPortIndex == 0) {
+
+ /*
+ * The virtual port consists of all currently
+ * active ports. Find them and send an event
+ * with the new flow control mode to SIRQ.
+ */
+ for (PhysPortIndex = 0;
+ PhysPortIndex < PhysPortMax;
+ PhysPortIndex ++) {
+
+ if (!pAC->Pnmi.Port[PhysPortIndex].
+ ActiveFlag) {
+
+ continue;
+ }
+
+ EventParam.Para32[0] = PhysPortIndex;
+ EventParam.Para32[1] = (SK_U32)Val8;
+ if (SkGeSirqEvent(pAC, IoC,
+ SK_HWEV_SET_FLOWMODE,
+ EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR044,
+ SK_PNMI_ERR044MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ }
+ else {
+ /*
+ * Send an event with the new flow control
+ * mode to the SIRQ module.
+ */
+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+ pAC, LogPortIndex);
+ EventParam.Para32[1] = (SK_U32)Val8;
+ if (SkGeSirqEvent(pAC, IoC,
+ SK_HWEV_SET_FLOWMODE, EventParam)
+ > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
+ SK_PNMI_ERR044,
+ SK_PNMI_ERR044MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ Offset += sizeof(char);
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR045,
+ SK_PNMI_ERR045MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Monitor - OID handler function for RLMT_MONITOR_XXX
+ *
+ * Description:
+ * Because RLMT currently does not support the monitoring of
+ * remote adapter cards, we return always an empty table.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK The request was successfully performed.
+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
+ * the correct data (e.g. a 32bit value is
+ * needed, but a 16 bit value was passed).
+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
+ * value range.
+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ * exist (e.g. port instance 3 on a two port
+ * adapter.
+ */
+
+static int Monitor(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+int Action, /* Get/PreSet/Set action */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf, /* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen, /* On call: buffer length. On return: used buffer */
+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex) /* Index to the Id table */
+{
+ unsigned int Index;
+ unsigned int Limit;
+ unsigned int Offset;
+ unsigned int Entries;
+
+
+ /*
+ * Calculate instance if wished.
+ */
+/* XXX Not yet implemented. Return always an empty table. */
+ Entries = 0;
+
+ if ((Instance != (SK_U32)(-1))) {
+
+ if ((Instance < 1) || (Instance > Entries)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_UNKNOWN_INST);
+ }
+
+ Index = (unsigned int)Instance - 1;
+ Limit = (unsigned int)Instance;
+ }
+ else {
+ Index = 0;
+ Limit = Entries;
+ }
+
+ /*
+ * Get/Set value
+ */
+ if (Action == SK_PNMI_GET) {
+
+ for (Offset=0; Index < Limit; Index ++) {
+
+ switch (Id) {
+
+ case OID_SKGE_RLMT_MONITOR_INDEX:
+ case OID_SKGE_RLMT_MONITOR_ADDR:
+ case OID_SKGE_RLMT_MONITOR_ERRS:
+ case OID_SKGE_RLMT_MONITOR_TIMESTAMP:
+ case OID_SKGE_RLMT_MONITOR_ADMIN:
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046,
+ SK_PNMI_ERR046MSG);
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+ *pLen = Offset;
+ }
+ else {
+ /* Only MONITOR_ADMIN can be set */
+ if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_READ_ONLY);
+ }
+
+ /* Check if the length is plausible */
+ if (*pLen < (Limit - Index)) {
+
+ return (SK_PNMI_ERR_TOO_SHORT);
+ }
+ /* Okay, we have a wide value range */
+ if (*pLen != (Limit - Index)) {
+
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+/*
+ for (Offset=0; Index < Limit; Index ++) {
+ }
+*/
+/*
+ * XXX Not yet implemented. Return always BAD_VALUE, because the table
+ * is empty.
+ */
+ *pLen = 0;
+ return (SK_PNMI_ERR_BAD_VALUE);
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * VirtualConf - Calculates the values of configuration OIDs for virtual port
+ *
+ * Description:
+ * We handle here the get of the configuration group OIDs, which are
+ * a little bit complicated. The virtual port consists of all currently
+ * active physical ports. If multiple ports are active and configured
+ * differently we get in some trouble to return a single value. So we
+ * get the value of the first active port and compare it with that of
+ * the other active ports. If they are not the same, we return a value
+ * that indicates that the state is indeterminated.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void VirtualConf(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+SK_U32 Id, /* Object ID that is to be processed */
+char *pBuf) /* Buffer to which to mgmt data will be retrieved */
+{
+ unsigned int PhysPortMax;
+ unsigned int PhysPortIndex;
+ SK_U8 Val8;
+ SK_BOOL PortActiveFlag;
+
+
+ *pBuf = 0;
+ PortActiveFlag = SK_FALSE;
+ PhysPortMax = pAC->GIni.GIMacsFound;
+
+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+ PhysPortIndex ++) {
+
+ /* Check if the physical port is active */
+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ continue;
+ }
+
+ PortActiveFlag = SK_TRUE;
+
+ switch (Id) {
+
+ case OID_SKGE_LINK_CAP:
+
+ /*
+ * Different capabilities should not happen, but
+ * in the case of the cases OR them all together.
+ * From a curious point of view the virtual port
+ * is capable of all found capabilities.
+ */
+ *pBuf |= pAC->GIni.GP[PhysPortIndex].PLinkCap;
+ break;
+
+ case OID_SKGE_LINK_MODE:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PLinkModeConf;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different link
+ * mode than the first one we return a value that
+ * indicates that the link mode is indeterminated.
+ */
+ if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkModeConf
+ ) {
+
+ *pBuf = SK_LMODE_INDETERMINATED;
+ }
+ break;
+
+ case OID_SKGE_LINK_MODE_STATUS:
+ /* Get the link mode of the physical port */
+ Val8 = CalculateLinkModeStatus(pAC, IoC,
+ PhysPortIndex);
+
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = Val8;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different link
+ * mode status than the first one we return a value
+ * that indicates that the link mode status is
+ * indeterminated.
+ */
+ if (*pBuf != Val8) {
+
+ *pBuf = SK_LMODE_STAT_INDETERMINATED;
+ }
+ break;
+
+ case OID_SKGE_LINK_STATUS:
+ /* Get the link status of the physical port */
+ Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
+
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = Val8;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different link
+ * status than the first one, we return a value
+ * that indicates that the link status is
+ * indeterminated.
+ */
+ if (*pBuf != Val8) {
+
+ *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
+ }
+ break;
+
+ case OID_SKGE_FLOWCTRL_CAP:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PFlowCtrlCap;
+ continue;
+ }
+
+ /*
+ * From a curious point of view the virtual port
+ * is capable of all found capabilities.
+ */
+ *pBuf |= pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
+ break;
+
+ case OID_SKGE_FLOWCTRL_MODE:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PFlowCtrlMode;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different flow
+ * control mode than the first one, we return a value
+ * that indicates that the mode is indeterminated.
+ */
+ if (*pBuf != pAC->GIni.GP[PhysPortIndex].
+ PFlowCtrlMode) {
+
+ *pBuf = SK_FLOW_MODE_INDETERMINATED;
+ }
+ break;
+
+ case OID_SKGE_FLOWCTRL_STATUS:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PFlowCtrlStatus;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different flow
+ * control status than the first one, we return a
+ * value that indicates that the status is
+ * indeterminated.
+ */
+ if (*pBuf != pAC->GIni.GP[PhysPortIndex].
+ PFlowCtrlStatus) {
+
+ *pBuf = SK_FLOW_STAT_INDETERMINATED;
+ }
+ break;
+ case OID_SKGE_PHY_OPERATION_CAP:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PMSCap;
+ continue;
+ }
+
+ /*
+ * From a curious point of view the virtual port
+ * is capable of all found capabilities.
+ */
+ *pBuf |= pAC->GIni.GP[PhysPortIndex].PMSCap;
+ break;
+
+ case OID_SKGE_PHY_OPERATION_MODE:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PMSMode;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different master/
+ * slave mode than the first one, we return a value
+ * that indicates that the mode is indeterminated.
+ */
+ if (*pBuf != pAC->GIni.GP[PhysPortIndex].
+ PMSMode) {
+
+ *pBuf = SK_MS_MODE_INDETERMINATED;
+ }
+ break;
+
+ case OID_SKGE_PHY_OPERATION_STATUS:
+ /* Check if it is the first active port */
+ if (*pBuf == 0) {
+
+ *pBuf = pAC->GIni.GP[PhysPortIndex].
+ PMSStatus;
+ continue;
+ }
+
+ /*
+ * If we find an active port with a different master/
+ * slave status than the first one, we return a
+ * value that indicates that the status is
+ * indeterminated.
+ */
+ if (*pBuf != pAC->GIni.GP[PhysPortIndex].
+ PMSStatus) {
+
+ *pBuf = SK_MS_STAT_INDETERMINATED;
+ }
+ break;
+ }
+ }
+
+ /*
+ * If no port is active return an indeterminated answer
+ */
+ if (!PortActiveFlag) {
+
+ switch (Id) {
+
+ case OID_SKGE_LINK_CAP:
+ *pBuf = SK_LMODE_CAP_INDETERMINATED;
+ break;
+
+ case OID_SKGE_LINK_MODE:
+ *pBuf = SK_LMODE_INDETERMINATED;
+ break;
+
+ case OID_SKGE_LINK_MODE_STATUS:
+ *pBuf = SK_LMODE_STAT_INDETERMINATED;
+ break;
+
+ case OID_SKGE_LINK_STATUS:
+ *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
+ break;
+
+ case OID_SKGE_FLOWCTRL_CAP:
+ case OID_SKGE_FLOWCTRL_MODE:
+ *pBuf = SK_FLOW_MODE_INDETERMINATED;
+ break;
+
+ case OID_SKGE_FLOWCTRL_STATUS:
+ *pBuf = SK_FLOW_STAT_INDETERMINATED;
+ break;
+
+ case OID_SKGE_PHY_OPERATION_CAP:
+ *pBuf = SK_MS_CAP_INDETERMINATED;
+ break;
+
+ case OID_SKGE_PHY_OPERATION_MODE:
+ *pBuf = SK_MS_MODE_INDETERMINATED;
+ break;
+
+ case OID_SKGE_PHY_OPERATION_STATUS:
+ *pBuf = SK_MS_STAT_INDETERMINATED;
+ break;
+ }
+ }
+}
+
+/*****************************************************************************
+ *
+ * CalculateLinkStatus - Determins the link status of a physical port
+ *
+ * Description:
+ * Determins the link status the following way:
+ * LSTAT_PHY_DOWN: Link is down
+ * LSTAT_AUTONEG: Auto-negotiation failed
+ * LSTAT_LOG_DOWN: Link is up but RLMT did not yet put the port
+ * logically up.
+ * LSTAT_LOG_UP: RLMT marked the port as up
+ *
+ * Returns:
+ * Link status of physical port
+ */
+
+static SK_U8 CalculateLinkStatus(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+unsigned int PhysPortIndex) /* Physical port index */
+{
+ SK_U8 Result;
+
+
+ if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) {
+
+ Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN;
+ }
+ else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) {
+
+ Result = SK_PNMI_RLMT_LSTAT_AUTONEG;
+ }
+ else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) {
+
+ Result = SK_PNMI_RLMT_LSTAT_LOG_UP;
+ }
+ else {
+ Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN;
+ }
+
+ return (Result);
+}
+
+/*****************************************************************************
+ *
+ * CalculateLinkModeStatus - Determins the link mode status of a phys. port
+ *
+ * Description:
+ * The COMMON module only tells us if the mode is half or full duplex.
+ * But in the decade of auto sensing it is usefull for the user to
+ * know if the mode was negotiated or forced. Therefore we have a
+ * look to the mode, which was last used by the negotiation process.
+ *
+ * Returns:
+ * The link mode status
+ */
+
+static SK_U8 CalculateLinkModeStatus(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+unsigned int PhysPortIndex) /* Physical port index */
+{
+ SK_U8 Result;
+
+
+ /* Get the current mode, which can be full or half duplex */
+ Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
+
+ /* Check if no valid mode could be found (link is down) */
+ if (Result < SK_LMODE_STAT_HALF) {
+
+ Result = SK_LMODE_STAT_UNKNOWN;
+ }
+ else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
+
+ /*
+ * Auto-negotiation was used to bring up the link. Change
+ * the already found duplex status that it indicates
+ * auto-negotiation was involved.
+ */
+ if (Result == SK_LMODE_STAT_HALF) {
+
+ Result = SK_LMODE_STAT_AUTOHALF;
+ }
+ else if (Result == SK_LMODE_STAT_FULL) {
+
+ Result = SK_LMODE_STAT_AUTOFULL;
+ }
+ }
+
+ return (Result);
+}
+
+/*****************************************************************************
+ *
+ * GetVpdKeyArr - Obtain an array of VPD keys
+ *
+ * Description:
+ * Read the VPD keys and build an array of VPD keys, which are
+ * easy to access.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK Task successfully performed.
+ * SK_PNMI_ERR_GENERAL Something went wrong.
+ */
+
+static int GetVpdKeyArr(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+char *pKeyArr, /* Ptr KeyArray */
+unsigned int KeyArrLen, /* Length of array in bytes */
+unsigned int *pKeyNo) /* Number of keys */
+{
+ unsigned int BufKeysLen = 128;
+ char BufKeys[128];
+ unsigned int StartOffset;
+ unsigned int Offset;
+ int Index;
+ int Ret;
+
+
+ SK_MEMSET(pKeyArr, 0, KeyArrLen);
+
+ /*
+ * Get VPD key list
+ */
+ Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen,
+ (int *)pKeyNo);
+ if (Ret > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014,
+ SK_PNMI_ERR014MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ /* If no keys are available return now */
+ if (*pKeyNo == 0 || BufKeysLen == 0) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+ /*
+ * If the key list is too long for us trunc it and give a
+ * errorlog notification. This case should not happen because
+ * the maximum number of keys is limited due to RAM limitations
+ */
+ if (*pKeyNo > SK_PNMI_VPD_ARR_SIZE) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015,
+ SK_PNMI_ERR015MSG);
+
+ *pKeyNo = SK_PNMI_VPD_ARR_SIZE;
+ }
+
+ /*
+ * Now build an array of fixed string length size and copy
+ * the keys together.
+ */
+ for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen;
+ Offset ++) {
+
+ if (BufKeys[Offset] != 0) {
+
+ continue;
+ }
+
+ if (Offset - StartOffset > SK_PNMI_VPD_STR_SIZE) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016,
+ SK_PNMI_ERR016MSG);
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_STR_SIZE,
+ &BufKeys[StartOffset], SK_PNMI_VPD_STR_SIZE);
+
+ Index ++;
+ StartOffset = Offset + 1;
+ }
+
+ /* Last key not zero terminated? Get it anyway */
+ if (StartOffset < Offset) {
+
+ SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_STR_SIZE,
+ &BufKeys[StartOffset], SK_PNMI_VPD_STR_SIZE);
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SirqUpdate - Let the SIRQ update its internal values
+ *
+ * Description:
+ * Just to be sure that the SIRQ module holds its internal data
+ * structures up to date, we send an update event before we make
+ * any access.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK Task successfully performed.
+ * SK_PNMI_ERR_GENERAL Something went wrong.
+ */
+
+static int SirqUpdate(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC) /* IO context handle */
+{
+ SK_EVPARA EventParam;
+
+
+ /* Was the module already updated during the current PNMI call? */
+ if (pAC->Pnmi.SirqUpdatedFlag > 0) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Send an synchronuous update event to the module */
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047,
+ SK_PNMI_ERR047MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * RlmtUpdate - Let the RLMT update its internal values
+ *
+ * Description:
+ * Just to be sure that the RLMT module holds its internal data
+ * structures up to date, we send an update event before we make
+ * any access.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK Task successfully performed.
+ * SK_PNMI_ERR_GENERAL Something went wrong.
+ */
+
+static int RlmtUpdate(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC) /* IO context handle */
+{
+ SK_EVPARA EventParam;
+
+
+ /* Was the module already updated during the current PNMI call? */
+ if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Send an synchronuous update event to the module */
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048,
+ SK_PNMI_ERR048MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * MacUpdate - Force the XMAC to output the current statistic
+ *
+ * Description:
+ * The XMAC holds its statistic internally. To obtain the current
+ * values we must send a command so that the statistic data will
+ * be written to a predefined memory area on the adapter.
+ *
+ * Returns:
+ * SK_PNMI_ERR_OK Task successfully performed.
+ * SK_PNMI_ERR_GENERAL Something went wrong.
+ */
+
+static int MacUpdate(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+unsigned int FirstMac, /* Index of the first Mac to be updated */
+unsigned int LastMac) /* Index of the last Mac to be updated */
+{
+ unsigned int MacIndex;
+ SK_U16 StatReg;
+ unsigned int WaitIndex;
+
+
+ /*
+ * Were the statistics already updated during the
+ * current PNMI call?
+ */
+ if (pAC->Pnmi.MacUpdatedFlag > 0) {
+
+ return (SK_PNMI_ERR_OK);
+ }
+
+ /* Send an update command to all XMACs specified */
+ for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
+
+ StatReg = XM_SC_SNP_TXC | XM_SC_SNP_RXC;
+ XM_OUT16(IoC, MacIndex, XM_STAT_CMD, StatReg);
+
+ /*
+ * It is an auto-clearing register. If the command bits
+ * went to zero again, the statistics are transfered.
+ * Normally the command should be executed immediately.
+ * But just to be sure we execute a loop.
+ */
+ for (WaitIndex = 0; WaitIndex < 10; WaitIndex ++) {
+
+ XM_IN16(IoC, MacIndex, XM_STAT_CMD, &StatReg);
+ if ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) ==
+ 0) {
+
+ break;
+ }
+ }
+ if (WaitIndex == 10 ) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SK_PNMI_ERR050,
+ SK_PNMI_ERR050MSG);
+
+ return (SK_PNMI_ERR_GENERAL);
+ }
+ }
+
+ return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * GetStatVal - Retrieve an XMAC statistic counter
+ *
+ * Description:
+ * Retrieves the statistic counter of a virtual or physical port. The
+ * virtual port is identified by the index 0. It consists of all
+ * currently active ports. To obtain the counter value for this port
+ * we must add the statistic counter of all active ports. To grant
+ * continuous counter values for the virtual port even when port
+ * switches occur we must additionally add a delta value, which was
+ * calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event.
+ *
+ * Returns:
+ * Requested statistic value
+ */
+
+static SK_U64 GetStatVal(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+unsigned int LogPortIndex, /* Index of the logical Port to be processed */
+unsigned int StatIndex) /* Index to statistic value */
+{
+ unsigned int PhysPortIndex;
+ unsigned int PhysPortMax;
+ SK_U64 Val = 0;
+
+
+ if (LogPortIndex == 0) {
+
+ PhysPortMax = pAC->GIni.GIMacsFound;
+
+ /* Add counter of all active ports */
+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+ PhysPortIndex ++) {
+
+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+ Val += GetPhysStatVal(pAC, IoC, PhysPortIndex,
+ StatIndex);
+ }
+ }
+
+ /* Correct value because of port switches */
+ Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
+ }
+ else {
+ /* Get counter value of physical port */
+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+ Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
+ }
+
+ return (Val);
+}
+
+/*****************************************************************************
+ *
+ * GetPhysStatVal - Get counter value for physical port
+ *
+ * Description:
+ * Builds a 64bit counter value. Except for the octet counters
+ * the lower 32bit are counted in hardware and the upper 32bit
+ * in software by monitoring counter overflow interrupts in the
+ * event handler. To grant continous counter values during XMAC
+ * resets (caused by a workaround) we must add a delta value.
+ * The delta was calculated in the event handler when a
+ * SK_PNMI_EVT_XMAC_RESET was received.
+ *
+ * Returns:
+ * Counter value
+ */
+
+static SK_U64 GetPhysStatVal(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC, /* IO context handle */
+unsigned int PhysPortIndex, /* Index of the logical Port to be processed */
+unsigned int StatIndex) /* Index to statistic value */
+{
+ SK_U64 Val = 0;
+ SK_U32 LowVal;
+ SK_U32 HighVal;
+
+
+ switch (StatIndex) {
+
+ case SK_PNMI_HTX_OCTET:
+ XM_IN32(IoC, PhysPortIndex, XM_TXO_OK_LO, &LowVal);
+ XM_IN32(IoC, PhysPortIndex, XM_TXO_OK_HI, &HighVal);
+ break;
+
+ case SK_PNMI_HRX_OCTET:
+ XM_IN32(IoC, PhysPortIndex, XM_RXO_OK_LO, &LowVal);
+ XM_IN32(IoC, PhysPortIndex, XM_RXO_OK_HI, &HighVal);
+ break;
+
+ case SK_PNMI_HTX_OCTETLOW:
+ case SK_PNMI_HRX_OCTETLOW:
+ return (Val);
+
+ case SK_PNMI_HTX_SYNC:
+ LowVal = (SK_U32)pAC->Pnmi.Port[PhysPortIndex].StatSyncCts;
+ HighVal = (SK_U32)
+ (pAC->Pnmi.Port[PhysPortIndex].StatSyncCts >> 32);
+ break;
+
+ case SK_PNMI_HTX_SYNC_OCTET:
+ LowVal = (SK_U32)pAC->Pnmi.Port[PhysPortIndex].
+ StatSyncOctetsCts;
+ HighVal = (SK_U32)
+ (pAC->Pnmi.Port[PhysPortIndex].StatSyncOctetsCts >>
+ 32);
+ break;
+
+ case SK_PNMI_HRX_FCS:
+ /*
+ * Broadcom filters fcs errors and counts it in
+ * Receive Error Counter register
+ */
+ if (pAC->GIni.GP[PhysPortIndex].PhyType == SK_PHY_BCOM) {
+ /* do not read while not initialized (PHY_READ hangs!)*/
+ if (pAC->GIni.GP[PhysPortIndex].PState) {
+ PHY_READ(IoC, &pAC->GIni.GP[PhysPortIndex],
+ PhysPortIndex, PHY_BCOM_RE_CTR,
+ &LowVal);
+ }
+ else {
+ LowVal = 0;
+ }
+ HighVal = pAC->Pnmi.Port[PhysPortIndex].CounterHigh[StatIndex];
+ }
+ else {
+ XM_IN32(IoC, PhysPortIndex,
+ StatAddress[StatIndex].Param, &LowVal);
+ HighVal = pAC->Pnmi.Port[PhysPortIndex].CounterHigh[StatIndex];
+ }
+ default:
+ XM_IN32(IoC, PhysPortIndex, StatAddress[StatIndex].Param,
+ &LowVal);
+ HighVal = pAC->Pnmi.Port[PhysPortIndex].CounterHigh[StatIndex];
+ break;
+ }
+
+ Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
+
+ /* Correct value because of possible XMAC reset. XMAC Errata #2 */
+ Val += pAC->Pnmi.Port[PhysPortIndex].CounterOffset[StatIndex];
+
+ return (Val);
+}
+
+/*****************************************************************************
+ *
+ * ResetCounter - Set all counters and timestamps to zero
+ *
+ * Description:
+ * Notifies other common modules which store statistic data to
+ * reset their counters and finally reset our own counters.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void ResetCounter(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_IOC IoC) /* IO context handle */
+{
+ unsigned int PhysPortIndex;
+ SK_EVPARA EventParam;
+
+
+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+ /* Notify sensor module */
+ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
+
+ /* Notify RLMT module */
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
+
+ /* Notify SIRQ module */
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
+
+ /* Notify CSUM module */
+#ifdef SK_USE_CSUM
+ EventParam.Para64 = (SK_U64)(-1);
+ SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS,
+ EventParam);
+#endif
+
+ /* Clear XMAC statistic */
+ for (PhysPortIndex = 0; PhysPortIndex <
+ (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
+
+ XM_OUT16(IoC, PhysPortIndex, XM_STAT_CMD,
+ XM_SC_CLR_RXC | XM_SC_CLR_TXC);
+ /* Clear two times according to Errata #3 */
+ XM_OUT16(IoC, PhysPortIndex, XM_STAT_CMD,
+ XM_SC_CLR_RXC | XM_SC_CLR_TXC);
+
+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh,
+ 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh));
+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
+ CounterOffset, 0, sizeof(pAC->Pnmi.Port[
+ PhysPortIndex].CounterOffset));
+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts,
+ 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts));
+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
+ StatSyncOctetsCts, 0, sizeof(pAC->Pnmi.Port[
+ PhysPortIndex].StatSyncOctetsCts));
+ }
+
+ /*
+ * Clear local statistics
+ */
+ pAC->Pnmi.RlmtChangeCts = 0;
+ pAC->Pnmi.RlmtChangeTime = 0;
+ SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
+ sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
+ pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
+ pAC->Pnmi.RlmtChangeEstimate.Estimate = 0;
+ pAC->Pnmi.TxSwQueueMax = 0;
+ pAC->Pnmi.TxRetryCts = 0;
+ pAC->Pnmi.RxIntrCts = 0;
+ pAC->Pnmi.TxIntrCts = 0;
+ pAC->Pnmi.RxNoBufCts = 0;
+ pAC->Pnmi.TxNoBufCts = 0;
+ pAC->Pnmi.TxUsedDescrNo = 0;
+ pAC->Pnmi.RxDeliveredCts = 0;
+ pAC->Pnmi.RxOctetsDeliveredCts = 0;
+ pAC->Pnmi.ErrRecoveryCts = 0;
+}
+
+/*****************************************************************************
+ *
+ * GetTrapEntry - Get an entry in the trap buffer
+ *
+ * Description:
+ * The trap buffer stores various events. A user application somehow
+ * gets notified that an event occured and retrieves the trap buffer
+ * contens (or simply polls the buffer). The buffer is organized as
+ * a ring which stores the newest traps at the beginning. The oldest
+ * traps are overwritten by the newest ones. Each trap entry has a
+ * unique number, so that applications may detect new trap entries.
+ *
+ * Returns:
+ * A pointer to the trap entry
+ */
+
+static char* GetTrapEntry(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_U32 TrapId, /* SNMP ID of the trap */
+unsigned int Size) /* Space needed for trap entry */
+{
+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;
+ unsigned int BufFree = pAC->Pnmi.TrapBufFree;
+ unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
+ unsigned int End = pAC->Pnmi.TrapQueueEnd;
+ char *pBuf = &pAC->Pnmi.TrapBuf[0];
+ int Wrap;
+ unsigned int NeededSpace;
+ unsigned int EntrySize;
+ SK_U32 Val32;
+ SK_U64 Val64;
+
+
+ /* Last byte of entry will get a copy of the entry length */
+ Size ++;
+
+ /*
+ * Calculate needed buffer space */
+ if (Beg >= Size) {
+
+ NeededSpace = Size;
+ Wrap = FALSE;
+ }
+ else {
+ NeededSpace = Beg + Size;
+ Wrap = TRUE;
+ }
+
+ /*
+ * Check if enough buffer space is provided. Otherwise
+ * free some entries. Leave one byte space between begin
+ * and end of buffer to make it possible to detect whether
+ * the buffer is full or empty
+ */
+ while (BufFree < NeededSpace + 1) {
+
+ if (End == 0) {
+
+ End = SK_PNMI_TRAP_QUEUE_LEN;
+ }
+
+ EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1);
+ BufFree += EntrySize;
+ End -= EntrySize;
+#ifdef DEBUG
+ SK_MEMSET(pBuf + End, (char)(-1), EntrySize);
+#endif
+ if (End == BufPad) {
+#ifdef DEBUG
+ SK_MEMSET(pBuf, (char)(-1), End);
+#endif
+ BufFree += End;
+ End = 0;
+ BufPad = 0;
+ }
+ }
+
+ /*
+ * Insert new entry as first entry. Newest entries are
+ * stored at the beginning of the queue.
+ */
+ if (Wrap) {
+
+ BufPad = Beg;
+ Beg = SK_PNMI_TRAP_QUEUE_LEN - Size;
+ }
+ else {
+ Beg = Beg - Size;
+ }
+ BufFree -= NeededSpace;
+
+ /* Save the current offsets */
+ pAC->Pnmi.TrapQueueBeg = Beg;
+ pAC->Pnmi.TrapQueueEnd = End;
+ pAC->Pnmi.TrapBufPad = BufPad;
+ pAC->Pnmi.TrapBufFree = BufFree;
+
+ /* Initialize the trap entry */
+ *(pBuf + Beg + Size - 1) = (char)Size;
+ *(pBuf + Beg) = (char)Size;
+ Val32 = (pAC->Pnmi.TrapUnique) ++;
+ SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32);
+ SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId);
+ Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+ SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64);
+
+ return (pBuf + Beg);
+}
+
+/*****************************************************************************
+ *
+ * CopyTrapQueue - Copies the trap buffer for the TRAP OID
+ *
+ * Description:
+ * On a query of the TRAP OID the trap buffer contents will be
+ * copied continuously to the request buffer, which must be large
+ * enough. No length check is performed.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void CopyTrapQueue(
+SK_AC *pAC, /* Pointer to adapter context */
+char *pDstBuf) /* Buffer to which the queued traps will be copied */
+{
+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;
+ unsigned int Trap = pAC->Pnmi.TrapQueueBeg;
+ unsigned int End = pAC->Pnmi.TrapQueueEnd;
+ char *pBuf = &pAC->Pnmi.TrapBuf[0];
+ unsigned int Len;
+ unsigned int DstOff = 0;
+
+
+ while (Trap != End) {
+
+ Len = (unsigned int)*(pBuf + Trap);
+
+ /*
+ * Last byte containing a copy of the length will
+ * not be copied.
+ */
+ *(pDstBuf + DstOff) = (char)(Len - 1);
+ SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2);
+ DstOff += Len - 1;
+
+ Trap += Len;
+ if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
+
+ Trap = BufPad;
+ }
+ }
+}
+
+/*****************************************************************************
+ *
+ * GetTrapQueueLen - Get the length of the trap buffer
+ *
+ * Description:
+ * Evaluates the number of currently stored traps and the needed
+ * buffer size to retrieve them.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void GetTrapQueueLen(
+SK_AC *pAC, /* Pointer to adapter context */
+unsigned int *pLen, /* Length in Bytes of all queued traps */
+unsigned int *pEntries) /* Returns number of trapes stored in queue */
+{
+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;
+ unsigned int Trap = pAC->Pnmi.TrapQueueBeg;
+ unsigned int End = pAC->Pnmi.TrapQueueEnd;
+ char *pBuf = &pAC->Pnmi.TrapBuf[0];
+ unsigned int Len;
+ unsigned int Entries = 0;
+ unsigned int TotalLen = 0;
+
+
+ while (Trap != End) {
+
+ Len = (unsigned int)*(pBuf + Trap);
+ TotalLen += Len - 1;
+ Entries ++;
+
+ Trap += Len;
+ if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
+
+ Trap = BufPad;
+ }
+ }
+
+ *pEntries = Entries;
+ *pLen = TotalLen;
+}
+
+/*****************************************************************************
+ *
+ * QueueSimpleTrap - Store a simple trap to the trap buffer
+ *
+ * Description:
+ * A simple trap is a trap with now additional data. It consists
+ * simply of a trap code.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void QueueSimpleTrap(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_U32 TrapId) /* Type of sensor trap */
+{
+ GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN);
+}
+
+/*****************************************************************************
+ *
+ * QueueSensorTrap - Stores a sensor trap in the trap buffer
+ *
+ * Description:
+ * Gets an entry in the trap buffer and fills it with sensor related
+ * data.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void QueueSensorTrap(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_U32 TrapId, /* Type of sensor trap */
+unsigned int SensorIndex) /* Index of sensor which caused the trap */
+{
+ char *pBuf;
+ unsigned int Offset;
+ unsigned int DescrLen;
+ SK_U32 Val32;
+
+
+ /* Get trap buffer entry */
+ DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
+ pBuf = GetTrapEntry(pAC, TrapId,
+ SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
+ Offset = SK_PNMI_TRAP_SIMPLE_LEN;
+
+ /* Store additionally sensor trap related data */
+ Val32 = OID_SKGE_SENSOR_INDEX;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ *(pBuf + Offset + 4) = 4;
+ Val32 = (SK_U32)SensorIndex;
+ SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
+ Offset += 9;
+
+ Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ *(pBuf + Offset + 4) = (char)DescrLen;
+ SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc,
+ DescrLen);
+ Offset += DescrLen + 5;
+
+ Val32 = OID_SKGE_SENSOR_TYPE;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ *(pBuf + Offset + 4) = 1;
+ *(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType;
+ Offset += 6;
+
+ Val32 = OID_SKGE_SENSOR_VALUE;
+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+ *(pBuf + Offset + 4) = 4;
+ Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue;
+ SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
+}
+
+/*****************************************************************************
+ *
+ * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer
+ *
+ * Description:
+ * Nothing further to explain.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void QueueRlmtNewMacTrap(
+SK_AC *pAC, /* Pointer to adapter context */
+unsigned int ActiveMac) /* Index (0..n) of the currently active port */
+{
+ char *pBuf;
+ SK_U32 Val32;
+
+
+ pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
+ SK_PNMI_TRAP_RLMT_CHANGE_LEN);
+
+ Val32 = OID_SKGE_RLMT_PORT_ACTIVE;
+ SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac;
+}
+
+/*****************************************************************************
+ *
+ * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer
+ *
+ * Description:
+ * Nothing further to explain.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void QueueRlmtPortTrap(
+SK_AC *pAC, /* Pointer to adapter context */
+SK_U32 TrapId, /* Type of RLMT port trap */
+unsigned int PortIndex) /* Index of the port, which changed its state */
+{
+ char *pBuf;
+ SK_U32 Val32;
+
+
+ pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
+
+ Val32 = OID_SKGE_RLMT_PORT_INDEX;
+ SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex;
+}
+
+/*****************************************************************************
+ *
+ * CopyMac - Copies a MAC address
+ *
+ * Description:
+ * Nothing further to explain.
+ *
+ * Returns:
+ * Nothing
+ */
+
+static void CopyMac(
+char *pDst, /* Pointer to destination buffer */
+SK_MAC_ADDR *pMac) /* Pointer of Source */
+{
+ int i;
+
+
+ for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
+
+ *(pDst + i) = pMac->a[i];
+ }
+}
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skgesirq.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.46 $
+ * Date: $Date: 1999/09/16 10:30:07 $
+ * Purpose: Special IRQ module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skgesirq.c,v $
+ * Revision 1.46 1999/09/16 10:30:07 cgoos
+ * Removed debugging output statement from Linux.
+ *
+ * Revision 1.45 1999/09/16 07:32:55 cgoos
+ * Fixed dual-port copperfield bug (PHY_READ from resetted port).
+ * Removed some unused variables.
+ *
+ * Revision 1.44 1999/08/03 15:25:04 cgoos
+ * Removed workaround for disabled interrupts in half duplex mode.
+ *
+ * Revision 1.43 1999/08/03 14:27:58 cgoos
+ * Removed SENSE mode code from SkGePortCheckUpBcom.
+ *
+ * Revision 1.42 1999/07/26 09:16:54 cgoos
+ * Added some typecasts to avoid compiler warnings.
+ *
+ * Revision 1.41 1999/05/19 07:28:59 cgoos
+ * Changes for 1000Base-T.
+ *
+ * Revision 1.40 1999/04/08 13:59:39 gklug
+ * fix: problem with 3Com switches endless RESTARTs
+ *
+ * Revision 1.39 1999/03/08 10:10:52 gklug
+ * fix: AutoSensing did switch to next mode even if LiPa indicated offline
+ *
+ * Revision 1.38 1999/03/08 09:49:03 gklug
+ * fix: Bug using pAC instead of IoC, causing AIX problems
+ * fix: change compare for Linux compiler bug workaround
+ *
+ * Revision 1.37 1999/01/28 14:51:33 gklug
+ * fix: monitor for autosensing and extra RESETS the RX on wire counters
+ *
+ * Revision 1.36 1999/01/22 09:19:55 gklug
+ * fix: Init DupMode and InitPauseMd are now called in RxTxEnable
+ *
+ * Revision 1.35 1998/12/11 15:22:59 gklug
+ * chg: autosensing: check for receive if manual mode was guessed
+ * chg: simplified workaround for XMAC errata
+ * chg: wait additional 100 ms before link goes up.
+ * chg: autoneg timeout to 600 ms
+ * chg: restart autoneg even if configured to autonegotiation
+ *
+ * Revision 1.34 1998/12/10 10:33:14 gklug
+ * add: more debug messages
+ * fix: do a new InitPhy if link went down (AutoSensing problem)
+ * chg: Check for zero shorts if link is NOT up
+ * chg: reset Port if link goes down
+ * chg: wait additional 100 ms when link comes up to check shorts
+ * fix: dummy read extended autoneg status to prevent link going down immediately
+ *
+ * Revision 1.33 1998/12/07 12:18:29 gklug
+ * add: refinement of autosense mode: take into account the autoneg cap of LiPa
+ *
+ * Revision 1.32 1998/12/07 07:11:21 gklug
+ * fix: compiler warning
+ *
+ * Revision 1.31 1998/12/02 09:29:05 gklug
+ * fix: WA XMAC Errata: FCSCt check was not correct.
+ * fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks.
+ * fix: Clear Stat : now clears the Prev counters of all known Ports
+ *
+ * Revision 1.30 1998/12/01 10:54:15 gklug
+ * dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too.
+ *
+ * Revision 1.29 1998/12/01 10:01:53 gklug
+ * fix: if MAC IRQ occurs during port down, this will be handled correctly
+ *
+ * Revision 1.28 1998/11/26 16:22:11 gklug
+ * fix: bug in autosense if manual modes are used
+ *
+ * Revision 1.27 1998/11/26 15:50:06 gklug
+ * fix: PNMI needs to set PLinkModeConf
+ *
+ * Revision 1.26 1998/11/26 14:51:58 gklug
+ * add: AutoSensing functionalty
+ *
+ * Revision 1.25 1998/11/26 07:34:37 gklug
+ * fix: Init PrevShorts when restarting port due to Link connection
+ *
+ * Revision 1.24 1998/11/25 10:57:32 gklug
+ * fix: remove unreferenced local vars
+ *
+ * Revision 1.23 1998/11/25 08:26:40 gklug
+ * fix: don't do a RESET on a starting or stopping port
+ *
+ * Revision 1.22 1998/11/24 13:29:44 gklug
+ * add: Workaround for MAC parity errata
+ *
+ * Revision 1.21 1998/11/18 15:31:06 gklug
+ * fix: lint bugs
+ *
+ * Revision 1.20 1998/11/18 12:58:54 gklug
+ * fix: use PNMI query instead of hardware access
+ *
+ * Revision 1.19 1998/11/18 12:54:55 gklug
+ * chg: add new workaround for XMAC Errata
+ * add: short event counter monitoring on active link too
+ *
+ * Revision 1.18 1998/11/13 14:27:41 malthoff
+ * Bug Fix: Packet Arbiter Timeout was not cleared correctly
+ * for timeout on TX1 and TX2.
+ *
+ * Revision 1.17 1998/11/04 07:01:59 cgoos
+ * Moved HW link poll sequence.
+ * Added call to SkXmRxTxEnable.
+ *
+ * Revision 1.16 1998/11/03 13:46:03 gklug
+ * add: functionality of SET_LMODE and SET_FLOW_MODE
+ * fix: send RLMT LinkDown event when Port stop is given with LinkUp
+ *
+ * Revision 1.15 1998/11/03 12:56:47 gklug
+ * fix: Needs more events
+ *
+ * Revision 1.14 1998/10/30 07:36:35 gklug
+ * rmv: unnecessary code
+ *
+ * Revision 1.13 1998/10/29 15:21:57 gklug
+ * add: Poll link feature for activating HW link
+ * fix: Deactivate HWLink when Port STOP is given
+ *
+ * Revision 1.12 1998/10/28 07:38:57 cgoos
+ * Checking link status at begin of SkHWLinkUp.
+ *
+ * Revision 1.11 1998/10/22 09:46:50 gklug
+ * fix SysKonnectFileId typo
+ *
+ * Revision 1.10 1998/10/14 13:57:47 gklug
+ * add: Port start/stop event
+ *
+ * Revision 1.9 1998/10/14 05:48:29 cgoos
+ * Added definition for Para.
+ *
+ * Revision 1.8 1998/10/14 05:40:09 gklug
+ * add: Hardware Linkup signal used
+ *
+ * Revision 1.7 1998/10/09 06:50:20 malthoff
+ * Remove ID_sccs by SysKonnectFileId.
+ *
+ * Revision 1.6 1998/10/08 09:11:49 gklug
+ * add: clear IRQ commands
+ *
+ * Revision 1.5 1998/10/02 14:27:35 cgoos
+ * Fixed some typos and wrong event names.
+ *
+ * Revision 1.4 1998/10/02 06:24:17 gklug
+ * add: HW error function
+ * fix: OUT macros
+ *
+ * Revision 1.3 1998/10/01 07:03:00 gklug
+ * add: ISR for the usual interrupt source register
+ *
+ * Revision 1.2 1998/09/03 13:50:33 gklug
+ * add: function prototypes
+ *
+ * Revision 1.1 1998/08/27 11:50:21 gklug
+ * initial revision
+ *
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ Special Interrupt handler
+
+ The following abstract should show how this module is included
+ in the driver path:
+
+ In the ISR of the driver the bits for frame transmission complete and
+ for receive complete are checked and handled by the driver itself.
+ The bits of the slow path mask are checked after this and then the
+ entry into the so-called "slow path" is prepared. It is an implemetors
+ decision whether this is executed directly or just scheduled by
+ disabling the mask. In the interrupt service routine events may be
+ generated, so it would be a good idea to call the EventDispatcher
+ right after this ISR.
+
+ The Interrupt service register of the adapter is NOT read by this
+ module. SO if the drivers implemetor needs a while loop around the
+ slow data paths Interrupt bits, he needs to call the SkGeIsr() for
+ each loop entered.
+
+ However, the XMAC Interrupt status registers are read in a while loop.
+
+*/
+static const char SysKonnectFileId[] =
+ "$Id: skgesirq.c,v 1.46 1999/09/16 10:30:07 cgoos Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/skgepnmi.h" /* PNMI Definitions */
+#include "h/skrlmt.h" /* RLMT Definitions */
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+
+/* local function prototypes */
+static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int);
+static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int);
+static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int);
+static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int);
+static void SkPhyIsrBcom(SK_AC*, SK_IOC, int, SK_U16);
+static void SkPhyIsrLone(SK_AC*, SK_IOC, int, SK_U16);
+
+
+#ifdef __C2MAN__
+/*
+ Special IRQ function
+
+ General Description:
+
+ */
+intro()
+{}
+#endif
+
+/*
+ * Define return codes of SkGePortCheckUp and CheckShort
+ */
+#define SK_HW_PS_NONE 0 /* No action needed */
+#define SK_HW_PS_RESTART 1 /* Restart needed */
+#define SK_HW_PS_LINK 2 /* Link Up actions needed */
+
+/******************************************************************************
+ *
+ * SkHWInitDefSense() - Default Autosensing mode initialization
+ *
+ * Description:
+ * This function handles the Hardware link down signal
+ *
+ * Note:
+ *
+ */
+void SkHWInitDefSense(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port] ;
+
+ pPrt->PAutoNegTimeOut = 0;
+
+ if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
+ pPrt->PLinkMode = pPrt->PLinkModeConf;
+ return;
+ }
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("AutoSensing: First mode %d on Port %d\n",
+ (int) SK_LMODE_AUTOFULL,
+ Port));
+
+ pPrt->PLinkMode = SK_LMODE_AUTOFULL;
+
+ return;
+}
+
+/******************************************************************************
+ *
+ * SkHWSenseGetNext() - GetNextAutosensing Mode
+ *
+ * Description:
+ * This function handles the AutoSensing
+ *
+ * Note:
+ *
+ */
+SK_U8 SkHWSenseGetNext(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port] ;
+
+ pPrt->PAutoNegTimeOut = 0;
+
+ if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
+ /* Leave all as configured */
+ return(pPrt->PLinkModeConf);
+ }
+
+ if (pPrt->PLinkMode == SK_LMODE_AUTOFULL) {
+ /* Return next mode AUTOBOTH */
+ return(SK_LMODE_AUTOBOTH);
+ }
+
+ /* Return default autofull */
+ return(SK_LMODE_AUTOFULL);
+}
+
+/******************************************************************************
+ *
+ * SkHWSenseSetNext() - Autosensing Set next mode
+ *
+ * Description:
+ * This function sets the appropriate next mode.
+ *
+ * Note:
+ *
+ */
+void SkHWSenseSetNext(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U8 NewMode) /* New Mode to be written in sense mode */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port] ;
+
+ pPrt->PAutoNegTimeOut = 0;
+
+ if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
+ return;
+ }
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("AutoSensing: next mode %d on Port %d\n", (int) NewMode,
+ Port));
+ pPrt->PLinkMode = NewMode;
+
+ return;
+}
+
+/******************************************************************************
+ *
+ * SkHWLinkDown() - Link Down handling
+ *
+ * Description:
+ * This function handles the Hardware link down signal
+ *
+ * Note:
+ *
+ */
+void SkHWLinkDown(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Word;
+
+ pPrt = &pAC->GIni.GP[Port] ;
+
+ /* Disable all XMAC interrupts */
+ XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
+
+ /* Disable Receive and Transmitter */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX|XM_MMU_ENA_TX));
+
+ /* disable all PHY interrupts */
+ switch (pAC->GIni.GP[Port].PhyType) {
+ case SK_PHY_BCOM:
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_INT_MASK,
+ 0xffff);
+ break;
+ case SK_PHY_LONE:
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_INT_ENAB,
+ 0x0);
+ break;
+ case SK_PHY_NAT:
+ /* todo: National
+ PHY_WRITE(IoC, pPrt, Port, PHY_NAT_INT_MASK,
+ 0xffff); */
+ break;
+ }
+
+ /* Init default sense mode */
+ SkHWInitDefSense(pAC, IoC, Port);
+
+ if (!pPrt->PHWLinkUp) {
+ return;
+ }
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Link down Port %d\n", Port));
+
+ /* Set Link to DOWN */
+ pPrt->PHWLinkUp = SK_FALSE;
+
+ /* Reset Port stati */
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE ;
+
+ /*
+ * Reinit Phy especially when the AutoSense default is set now
+ */
+ SkXmInitPhy(pAC, IoC, Port, SK_FALSE);
+
+ /*
+ * GP0: used for workaround of Rev. C
+ * Errata 2
+ */
+
+ /* Do NOT signal to RLMT */
+
+ /* Do NOT start the timer here */
+}
+
+/******************************************************************************
+ *
+ * SkHWLinkUp() - Link Up handling
+ *
+ * Description:
+ * This function handles the Hardware link up signal
+ *
+ * Note:
+ *
+ */
+void SkHWLinkUp(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port] ;
+
+ if (pPrt->PHWLinkUp) {
+ /* We do NOT need to proceed on active link */
+ return;
+ }
+
+ pPrt->PHWLinkUp = SK_TRUE ;
+ pPrt->PAutoNegFail = SK_FALSE ;
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
+
+ if (pPrt->PLinkMode != SK_LMODE_AUTOHALF &&
+ pPrt->PLinkMode != SK_LMODE_AUTOFULL &&
+ pPrt->PLinkMode != SK_LMODE_AUTOBOTH) {
+ /* Link is up and no Autonegotiation should be done */
+
+ /* Configure Port */
+
+ /* Set Link Mode */
+ if (pPrt->PLinkMode == SK_LMODE_FULL) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_FULL;
+ } else {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_HALF;
+ }
+
+ /* No flow control without autonegotiation */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE ;
+
+ /* RX/TX enable */
+ SkXmRxTxEnable(pAC, IoC, Port);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkMacParity - does everything to handle MAC parity errors correctly
+ *
+ */
+static void SkMacParity(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index of the port failed */
+{
+ SK_EVPARA Para;
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+ SK_U64 TxMax; /* TxMax Counter */
+ unsigned int Len;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Clear IRQ */
+ SK_OUT16(IoC, MR_ADDR(Port,TX_MFF_CTRL1), MFF_CLR_PERR) ;
+
+ if (pPrt->PCheckPar) {
+ if (Port == MAC_1) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E016,
+ SKERR_SIRQ_E016MSG) ;
+ } else {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E017,
+ SKERR_SIRQ_E017MSG) ;
+ }
+ Para.Para64 = Port;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = Port;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+ return;
+ }
+
+
+ /* Check whether frames with a size of 1k were sent */
+ Len = sizeof(SK_U64);
+ SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_MAX, (char *) &TxMax,
+ &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(Port));
+
+ if (TxMax > 0) {
+ /* From now on check the parity */
+ pPrt->PCheckPar = SK_TRUE;
+ }
+}
+
+/******************************************************************************
+ *
+ * Hardware Error service routine
+ *
+ * Description:
+ *
+ * Notes:
+ */
+static void SkGeHwErr(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+SK_U32 HwStatus) /* Interrupt status word */
+{
+ SK_EVPARA Para;
+
+ if (HwStatus & IS_IRQ_STAT) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E013,
+ SKERR_SIRQ_E013MSG) ;
+ Para.Para64 = 0;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+ }
+
+ if (HwStatus & IS_IRQ_MST_ERR) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E012,
+ SKERR_SIRQ_E012MSG) ;
+ Para.Para64 = 0;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+ }
+
+ if (HwStatus & IS_NO_STAT_M1) {
+ /* Ignore it */
+ /* This situation is also indicated in the descriptor */
+ SK_OUT16(IoC, MR_ADDR(MAC_1,RX_MFF_CTRL1), MFF_CLR_INSTAT) ;
+ }
+
+ if (HwStatus & IS_NO_STAT_M2) {
+ /* Ignore it */
+ /* This situation is also indicated in the descriptor */
+ SK_OUT16(IoC, MR_ADDR(MAC_2,RX_MFF_CTRL1), MFF_CLR_INSTAT) ;
+ }
+
+ if (HwStatus & IS_NO_TIST_M1) {
+ /* Ignore it */
+ /* This situation is also indicated in the descriptor */
+ SK_OUT16(IoC, MR_ADDR(MAC_1,RX_MFF_CTRL1), MFF_CLR_INTIST) ;
+ }
+
+ if (HwStatus & IS_NO_TIST_M2) {
+ /* Ignore it */
+ /* This situation is also indicated in the descriptor */
+ SK_OUT16(IoC, MR_ADDR(MAC_2,RX_MFF_CTRL1), MFF_CLR_INTIST) ;
+ }
+
+ if (HwStatus & IS_RAM_RD_PAR) {
+ SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E014,
+ SKERR_SIRQ_E014MSG) ;
+ Para.Para64 = 0;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+ }
+
+ if (HwStatus & IS_RAM_WR_PAR) {
+ SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E015,
+ SKERR_SIRQ_E015MSG) ;
+ Para.Para64 = 0;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+ }
+
+ if (HwStatus & IS_M1_PAR_ERR) {
+ SkMacParity(pAC, IoC, MAC_1) ;
+ }
+
+ if (HwStatus & IS_M2_PAR_ERR) {
+ SkMacParity(pAC, IoC, MAC_2) ;
+ }
+
+ if (HwStatus & IS_R1_PAR_ERR) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_P) ;
+
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E018,
+ SKERR_SIRQ_E018MSG) ;
+ Para.Para64 = MAC_1;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_1;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (HwStatus & IS_R2_PAR_ERR) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P) ;
+
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E019,
+ SKERR_SIRQ_E019MSG) ;
+ Para.Para64 = MAC_2;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_2;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+}
+
+/******************************************************************************
+ *
+ * Interrupt service routine
+ *
+ * Description:
+ *
+ * Notes:
+ */
+void SkGeSirqIsr(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+SK_U32 Istatus) /* Interrupt status word */
+{
+ SK_U32 RegVal32; /* Read register Value */
+ SK_EVPARA Para;
+ SK_U16 XmIsr;
+
+ if (Istatus & IS_HW_ERR) {
+ SK_IN32(IoC, B0_HWE_ISRC, &RegVal32) ;
+ SkGeHwErr(pAC, IoC, RegVal32) ;
+ }
+
+ /*
+ * Packet Timeout interrupts
+ */
+ /* Check whether XMACs are correctly initialized */
+ if ((Istatus & (IS_PA_TO_RX1 | IS_PA_TO_TX1)) &&
+ !pAC->GIni.GP[MAC_1].PState) {
+ /* XMAC was not initialized but Packet timeout occured */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E004,
+ SKERR_SIRQ_E004MSG) ;
+ }
+
+ if ((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) &&
+ !pAC->GIni.GP[MAC_2].PState) {
+ /* XMAC was not initialized but Packet timeout occured */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
+ SKERR_SIRQ_E005MSG) ;
+ }
+
+ if (Istatus & IS_PA_TO_RX1) {
+ /* Means network is filling us up */
+ SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E002,
+ SKERR_SIRQ_E002MSG) ;
+ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX1) ;
+ }
+
+ if (Istatus & IS_PA_TO_RX2) {
+ /* Means network is filling us up */
+ SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E003,
+ SKERR_SIRQ_E003MSG) ;
+ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX2) ;
+ }
+
+ if (Istatus & IS_PA_TO_TX1) {
+ /* May be a normal situation in a server with a slow network */
+ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1) ;
+ }
+
+ if (Istatus & IS_PA_TO_TX2) {
+ /* May be a normal situation in a server with a slow network */
+ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2) ;
+ }
+
+ /*
+ * Check interrupts of the particular queues.
+ */
+ if (Istatus & IS_R1_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
+ SKERR_SIRQ_E006MSG) ;
+ Para.Para64 = MAC_1;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_1;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (Istatus & IS_R2_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
+ SKERR_SIRQ_E007MSG) ;
+ Para.Para64 = MAC_2;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_2;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (Istatus & IS_XS1_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
+ SKERR_SIRQ_E008MSG) ;
+ Para.Para64 = MAC_1;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_1;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (Istatus & IS_XA1_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
+ SKERR_SIRQ_E009MSG) ;
+ Para.Para64 = MAC_1;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_1;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (Istatus & IS_XS2_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
+ SKERR_SIRQ_E010MSG) ;
+ Para.Para64 = MAC_2;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_2;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ if (Istatus & IS_XA2_C) {
+ /* Clear IRQ */
+ SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C) ;
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
+ SKERR_SIRQ_E011MSG) ;
+ Para.Para64 = MAC_2;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+ Para.Para32[0] = MAC_2;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ /*
+ * I2C Ready interrupt
+ */
+ if (Istatus & IS_I2C_READY) {
+ SK_U16 PhyInt;
+ SK_U16 PhyIMsk;
+ SK_BOOL IsPhyInt = SK_FALSE;
+ int i;
+ /* test IRQs from PHY */
+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+ switch (pAC->GIni.GP[i].PhyType) {
+ case SK_PHY_XMAC:
+ break;
+ case SK_PHY_BCOM:
+ if(pAC->GIni.GP[i].PState) {
+ PHY_READ(IoC, &pAC->GIni.GP[i], i,
+ PHY_BCOM_INT_STAT, &PhyInt);
+ PHY_READ(IoC, &pAC->GIni.GP[i], i,
+ PHY_BCOM_INT_MASK, &PhyIMsk);
+
+ if (PhyInt & (~PhyIMsk)) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("Port %d Bcom Int: %x "
+ " Mask: %x\n",
+ i, PhyInt, PhyIMsk));
+ SkPhyIsrBcom(pAC, IoC, i,
+ (SK_U16)
+ (PhyInt & (~PhyIMsk)));
+ IsPhyInt = SK_TRUE;
+ }
+ }
+ else {
+ }
+ break;
+ case SK_PHY_LONE:
+ PHY_READ(IoC, &pAC->GIni.GP[i], i,
+ PHY_LONE_INT_STAT, &PhyInt);
+ PHY_READ(IoC, &pAC->GIni.GP[i], i,
+ PHY_LONE_INT_ENAB, &PhyIMsk);
+
+ if (PhyInt & PhyIMsk) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("Port %d Lone Int: %x "
+ " Mask: %x\n",
+ i, PhyInt, PhyIMsk));
+ SkPhyIsrLone(pAC, IoC, i,
+ (SK_U16) (PhyInt & PhyIMsk));
+ IsPhyInt = SK_TRUE;
+ }
+ break;
+ case SK_PHY_NAT:
+ /* todo: National */
+ break;
+ }
+ }
+ if (!IsPhyInt) {
+ SkI2cIsr(pAC, IoC);
+ }
+ }
+
+ if (Istatus & IS_LNK_SYNC_M1) {
+ /*
+ * We do NOT need the Link Sync interrupt, because it shows
+ * us only a link going down.
+ */
+ /* clear interrupt */
+ SK_OUT8(IoC, MR_ADDR(MAC_1,LNK_SYNC_CTRL), LED_CLR_IRQ);
+ }
+
+ /* Check MAC after link sync counter */
+ if (Istatus & IS_MAC1) {
+ XM_IN16(IoC, MAC_1, XM_ISRC, &XmIsr) ;
+ SkXmIrq(pAC, IoC, MAC_1, XmIsr);
+ }
+
+ if (Istatus & IS_LNK_SYNC_M2) {
+ /*
+ * We do NOT need the Link Sync interrupt, because it shows
+ * us only a link going down.
+ */
+ /* clear interrupt */
+ SK_OUT8(IoC, MR_ADDR(MAC_2,LNK_SYNC_CTRL), LED_CLR_IRQ);
+ }
+
+ /* Check MAC after link sync counter */
+ if (Istatus & IS_MAC2) {
+ XM_IN16(IoC, MAC_2, XM_ISRC, &XmIsr) ;
+ SkXmIrq(pAC, IoC, MAC_2, XmIsr);
+ }
+
+ /*
+ * Timer interrupt
+ * To be served last
+ */
+ if (Istatus & IS_TIMINT) {
+ SkHwtIsr(pAC, IoC);
+ }
+}
+
+/*
+ * Define an array of RX counter which are checked
+ * in AutoSense mode to check whether a link is not able to autonegotiate.
+ */
+static const SK_U32 SkGeRxOids[]= {
+ OID_SKGE_STAT_RX_64,
+ OID_SKGE_STAT_RX_127,
+ OID_SKGE_STAT_RX_255,
+ OID_SKGE_STAT_RX_511,
+ OID_SKGE_STAT_RX_1023,
+ OID_SKGE_STAT_RX_MAX,
+} ;
+/******************************************************************************
+ *
+ * SkGePortCheckShorts - Implementing of the Workaround Errata # 2
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ */
+int SkGePortCheckShorts(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ SK_U64 Shorts; /* Short Event Counter */
+ SK_U64 CheckShorts; /* Check value for Short Event Counter */
+ SK_U64 RxCts; /* RX Counter (packets on network) */
+ SK_U64 RxTmp; /* RX temp. Counter */
+ SK_U64 FcsErrCts; /* FCS Error Counter */
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+ unsigned int Len;
+ int Rtv; /* Return value */
+ int i;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Default: no action */
+ Rtv = SK_HW_PS_NONE;
+
+ /*
+ * Extra precaution: check for short Event counter
+ */
+ Len = sizeof(SK_U64);
+ SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_RX_SHORTS, (char *) &Shorts,
+ &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(Port));
+
+ /*
+ * Read RX counter (packets seen on the network and not neccesarily
+ * really received.
+ */
+ Len = sizeof(SK_U64);
+ RxCts = 0;
+
+ for (i = 0; i < sizeof(SkGeRxOids)/sizeof(SK_U32) ; i++) {
+ SkPnmiGetVar(pAC, IoC, SkGeRxOids[i], (char *) &RxTmp,
+ &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(Port));
+ RxCts += RxTmp;
+ }
+
+ /* On default: check shorts against zero */
+ CheckShorts = 0;
+
+ /*
+ * Extra extra precaution on active links:
+ */
+ if (pPrt->PHWLinkUp) {
+ /*
+ * Reset Link Restart counter
+ */
+ pPrt->PLinkResCt = 0;
+
+ /* If link is up check for 2 */
+ CheckShorts = 2;
+
+ Len = sizeof(SK_U64);
+ SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_RX_FCS,
+ (char *) &FcsErrCts, &Len,
+ (SK_U32) SK_PNMI_PORT_PHYS2INST(Port));
+
+ if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
+ pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
+ (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL)) {
+ /*
+ * This is autosensing and we are in the fallback
+ * manual full/half duplex mode.
+ */
+ if (RxCts == pPrt->PPrevRx) {
+ /*
+ * Nothing received
+ * restart link
+ */
+ pPrt->PPrevFcs = FcsErrCts;
+ pPrt->PPrevShorts = Shorts;
+ return(SK_HW_PS_RESTART);
+ } else {
+ pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
+ }
+ }
+
+ if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
+ (!(FcsErrCts - pPrt->PPrevFcs))) {
+ /*
+ * Note: The compare with zero above has to be done
+ * the way shown, otherwise the Linux driver will
+ * have a problem.
+ */
+ /*
+ * we received a bunch of frames or no
+ * CRC error occured on the network ->
+ * ok.
+ */
+ pPrt->PPrevRx = RxCts;
+ pPrt->PPrevFcs = FcsErrCts;
+ pPrt->PPrevShorts = Shorts;
+
+ return(SK_HW_PS_NONE) ;
+ }
+
+ pPrt->PPrevFcs = FcsErrCts;
+ }
+
+
+ if ((Shorts - pPrt->PPrevShorts) > CheckShorts) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Short Event Count Restart Port %d \n", Port));
+ Rtv = SK_HW_PS_RESTART;
+ }
+
+ pPrt->PPrevShorts = Shorts;
+ pPrt->PPrevRx = RxCts;
+
+ return(Rtv);
+}
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUp - Implementing of the Workaround Errata # 2
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ * 2 Link came up
+ */
+int SkGePortCheckUp(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ switch (pPrt->PhyType) {
+ case SK_PHY_XMAC:
+ return (SkGePortCheckUpXmac(pAC, IoC, Port));
+ case SK_PHY_BCOM:
+ return (SkGePortCheckUpBcom(pAC, IoC, Port));
+ case SK_PHY_LONE:
+ return (SkGePortCheckUpLone(pAC, IoC, Port));
+ case SK_PHY_NAT:
+ return (SkGePortCheckUpNat(pAC, IoC, Port));
+ }
+
+ return(SK_HW_PS_NONE) ;
+}
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUpXmac - Implementing of the Workaround Errata # 2
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ * 2 Link came up
+ */
+static int SkGePortCheckUpXmac(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+ SK_BOOL AutoNeg; /* Is Autonegotiation used ? */
+ SK_U16 Isrc; /* Interrupt source register */
+ SK_U32 GpReg; /* General Purpose register value */
+ SK_U16 IsrcSum; /* Interrupt source register sum */
+ SK_U16 LpAb; /* Link Partner Ability */
+ SK_U16 ResAb; /* Resolved Ability */
+ SK_U64 Shorts; /* Short Event Counter */
+ unsigned int Len;
+ SK_U8 NextMode; /* Next AutoSensing Mode */
+ SK_U16 ExtStat; /* Extended Status Register */
+ int Done;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PHWLinkUp) {
+ if (pPrt->PhyType != SK_PHY_XMAC) {
+ return(SK_HW_PS_NONE) ;
+ }
+ else {
+ return(SkGePortCheckShorts(pAC, IoC, Port)) ;
+ }
+ }
+
+ IsrcSum = pPrt->PIsave;
+ pPrt->PIsave = 0;
+
+ /* Now wait for each ports link */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ AutoNeg = SK_FALSE;
+ } else {
+ AutoNeg = SK_TRUE;
+ }
+
+ if (pPrt->PLinkBroken) {
+ /* Link was broken */
+ XM_IN32(IoC,Port,XM_GP_PORT, &GpReg) ;
+
+ if ((GpReg & XM_GP_INP_ASS) == 0) {
+ /* The Link is in sync */
+ XM_IN16(IoC,Port,XM_ISRC, &Isrc) ;
+ IsrcSum |= Isrc;
+ SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
+ if ((Isrc & XM_IS_INP_ASS) == 0) {
+ /* It has been in sync since last Time */
+ /* Restart the PORT */
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Link in sync Restart Port %d\n",
+ Port));
+
+ /*
+ * We now need to reinitialize the PrevSHorts
+ * counter.
+ */
+ Len = sizeof(SK_U64);
+ SkPnmiGetVar(pAC, IoC,
+ OID_SKGE_STAT_RX_SHORTS,
+ (char *) &Shorts,
+ &Len,
+ (SK_U32) SK_PNMI_PORT_PHYS2INST(Port));
+ pPrt->PPrevShorts = Shorts;
+
+ pAC->GIni.GP[Port].PLinkBroken = SK_FALSE ;
+
+ /*
+ * Link Restart Workaround:
+ * it may be possible that the other Link side
+ * restarts its link as well an we detect
+ * another LinkBroken. To prevent this
+ * happening we check for a maximum number
+ * of consecutive restart. If those happens,
+ * we do NOT restart the active link and
+ * check whether the lionk is now o.k.
+ */
+ pAC->GIni.GP[Port].PLinkResCt ++;
+ pPrt->PAutoNegTimeOut = 0;
+
+ if (pAC->GIni.GP[Port].PLinkResCt <
+ SK_MAX_LRESTART) {
+ return(SK_HW_PS_RESTART) ;
+ }
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("Do NOT restart on Port %d %x %x\n",
+ Port, Isrc, IsrcSum));
+ pAC->GIni.GP[Port].PLinkResCt = 0;
+ } else {
+ pPrt->PIsave = (SK_U16) (IsrcSum & (XM_IS_AND));
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("Save Sync/nosync Port %d %x %x\n",
+ Port, Isrc, IsrcSum));
+ /* Do nothing more if link is broken */
+ return(SK_HW_PS_NONE) ;
+ }
+ } else {
+ /* Do nothing more if link is broken */
+ return(SK_HW_PS_NONE) ;
+ }
+
+ } else {
+ /* Link was not broken, check if it is */
+ XM_IN16(IoC,Port,XM_ISRC, &Isrc) ;
+ IsrcSum |= Isrc;
+ if ((Isrc & XM_IS_INP_ASS) == XM_IS_INP_ASS) {
+ XM_IN16(IoC,Port,XM_ISRC, &Isrc) ;
+ IsrcSum |= Isrc;
+ if ((Isrc & XM_IS_INP_ASS) == XM_IS_INP_ASS) {
+ XM_IN16(IoC,Port,XM_ISRC, &Isrc) ;
+ IsrcSum |= Isrc;
+ if ((Isrc & XM_IS_INP_ASS) == XM_IS_INP_ASS) {
+ pPrt->PLinkBroken = SK_TRUE ;
+ /*
+ * Re-Init Link partner Autoneg flag
+ */
+ pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("Link broken Port %d\n",
+ Port));
+
+ /* cable removed-> reinit Sensemode */
+ /* Init default sense mode */
+ SkHWInitDefSense(pAC, IoC, Port);
+
+ return(SK_HW_PS_RESTART) ;
+ }
+ }
+ } else {
+ SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
+ if (SkGePortCheckShorts(pAC, IoC, Port) ==
+ SK_HW_PS_RESTART) {
+ return(SK_HW_PS_RESTART) ;
+ }
+ }
+ }
+
+ /*
+ * here we usually can check whether the link is in sync and
+ * autonegotiation is done.
+ */
+ XM_IN32(IoC,Port,XM_GP_PORT, &GpReg) ;
+ XM_IN16(IoC,Port,XM_ISRC, &Isrc) ;
+ IsrcSum |= Isrc;
+
+ SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
+ if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
+ if ((GpReg & XM_GP_INP_ASS) == 0) {
+ /*
+ * Save Autonegotiation Done interrupt only if link
+ * is in sync
+ */
+ pPrt->PIsave = (SK_U16) (IsrcSum & (XM_IS_AND));
+ }
+#ifdef DEBUG
+ if (pPrt->PIsave & (XM_IS_AND)) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg done rescheduled Port %d\n", Port));
+ }
+#endif
+ return(SK_HW_PS_NONE) ;
+ }
+
+ if (AutoNeg) {
+ if (IsrcSum & XM_IS_AND) {
+ SkHWLinkUp(pAC, IoC, Port) ;
+ Done = SkXmAutoNegDone(pAC,IoC,Port);
+ if (Done != SK_AND_OK) {
+ /* Get PHY parameters, for debuging only */
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_AUNE_LP,
+ &LpAb);
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_RES_ABI,
+ &ResAb);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
+ Port, LpAb, ResAb));
+
+ /* Try next possible mode */
+ NextMode = SkHWSenseGetNext(pAC, IoC, Port);
+ SkHWLinkDown(pAC, IoC, Port) ;
+ if (Done == SK_AND_DUP_CAP) {
+ /* GoTo next mode */
+ SkHWSenseSetNext(pAC, IoC, Port,
+ NextMode);
+ }
+
+ return(SK_HW_PS_RESTART) ;
+
+ } else {
+ /*
+ * Dummy Read extended status to prevent
+ * extra link down/ups
+ * (clear Page Received bit if set)
+ */
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg done Port %d\n", Port));
+ return(SK_HW_PS_LINK) ;
+ }
+ }
+
+ /*
+ * AutoNeg not done, but HW link is up. Check for timeouts
+ */
+ pPrt->PAutoNegTimeOut ++;
+ if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
+ /*
+ * Timeout occured.
+ * What do we need now?
+ */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("AutoNeg timeout Port %d\n",
+ Port));
+ if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
+ pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
+ /*
+ * Timeout occured
+ * Set Link manually up.
+ */
+ SkHWSenseSetNext(pAC, IoC, Port,
+ SK_LMODE_FULL);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("Set manual full duplex Port %d\n",
+ Port));
+ }
+
+ /*
+ * Do the restart
+ */
+ return(SK_HW_PS_RESTART) ;
+ }
+ } else {
+ /*
+ * Link is up and we don't need more.
+ */
+#ifdef DEBUG
+ if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("ERROR: Lipa auto detected on port %d\n",
+ Port));
+ }
+#endif
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Link sync(GP), Port %d\n", Port));
+ SkHWLinkUp(pAC, IoC, Port) ;
+ return(SK_HW_PS_LINK) ;
+ }
+
+ return(SK_HW_PS_NONE) ;
+}
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUpBcom - Check, if the link is up
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ * 2 Link came up
+ */
+static int SkGePortCheckUpBcom(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+ SK_BOOL AutoNeg; /* Is Autonegotiation used ? */
+ SK_U16 Isrc; /* Interrupt source register */
+ SK_U16 LpAb; /* Link Partner Ability */
+ SK_U16 ExtStat; /* Extended Status Register */
+ SK_U16 PhyStat; /* Phy Status Register */
+ int Done;
+ SK_U16 ResAb;
+
+ pPrt = &pAC->GIni.GP[Port];
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_STAT, &PhyStat);
+
+ if (pPrt->PHWLinkUp) {
+ return(SK_HW_PS_NONE) ;
+ }
+
+ pPrt->PIsave = 0;
+
+ /* Now wait for each ports link */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ AutoNeg = SK_FALSE;
+ } else {
+ AutoNeg = SK_TRUE;
+ }
+
+ /*
+ * here we usually can check whether the link is in sync and
+ * autonegotiation is done.
+ */
+ XM_IN16(IoC, Port, XM_ISRC, &Isrc) ;
+
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_STAT, &PhyStat);
+
+ SkXmAutoNegLipaBcom(pAC, IoC, Port, PhyStat);
+ if ((PhyStat & PHY_ST_LSYNC) == 0){
+ return(SK_HW_PS_NONE) ;
+ }
+
+ if (AutoNeg) {
+ if (PhyStat & PHY_ST_AN_OVER) {
+ SkHWLinkUp(pAC, IoC, Port) ;
+ Done = SkXmAutoNegDone(pAC,IoC,Port);
+ if (Done != SK_AND_OK) {
+ /* Get PHY parameters, for debuging only */
+ PHY_READ(IoC, pPrt, Port,
+ PHY_BCOM_AUNE_LP,
+ &LpAb);
+ PHY_READ(IoC, pPrt, Port,
+ PHY_BCOM_1000T_STAT,
+ &ExtStat);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg FAIL Port %d (LpAb %x, "
+ "1000TStat %x)\n",
+ Port, LpAb, ExtStat));
+ return(SK_HW_PS_RESTART) ;
+
+ } else {
+ /*
+ * Dummy Read interrupt status to prevent
+ * extra link down/ups
+ */
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_INT_STAT,
+ &ExtStat);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg done Port %d\n", Port));
+ return(SK_HW_PS_LINK) ;
+ }
+ }
+ } else {
+ /*
+ * Link is up and we don't need more.
+ */
+#ifdef DEBUG
+ if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("ERROR: Lipa auto detected on port %d\n",
+ Port));
+ }
+#endif
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_1000T_STAT, &ResAb);
+ if (ResAb & (PHY_B_1000S_MSF)) {
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("Master/Slave Fault port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE;
+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
+ return (SK_AND_OTHER);
+ } else if (ResAb & PHY_B_1000S_MSR) {
+ pPrt->PMSStatus = SK_MS_STAT_MASTER ;
+ } else {
+ pPrt->PMSStatus = SK_MS_STAT_SLAVE ;
+ }
+
+
+ /*
+ * Dummy Read interrupt status to prevent
+ * extra link down/ups
+ */
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_INT_STAT, &ExtStat);
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Link sync(GP), Port %d\n", Port));
+ SkHWLinkUp(pAC, IoC, Port) ;
+ return(SK_HW_PS_LINK) ;
+ }
+
+ return(SK_HW_PS_NONE) ;
+}
+
+/******************************************************************************
+ *
+ * SkGePortCheckUpLone - Check if the link is up
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ * 2 Link came up
+ */
+static int SkGePortCheckUpLone(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
+ SK_BOOL AutoNeg; /* Is Autonegotiation used ? */
+ SK_U16 Isrc; /* Interrupt source register */
+ SK_U16 LpAb; /* Link Partner Ability */
+ SK_U8 NextMode; /* Next AutoSensing Mode */
+ SK_U16 ExtStat; /* Extended Status Register */
+ SK_U16 PhyStat; /* Phy Status Register */
+ SK_U16 StatSum;
+ int Done;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PHWLinkUp) {
+ return(SK_HW_PS_NONE) ;
+ }
+
+ StatSum = pPrt->PIsave;
+ pPrt->PIsave = 0;
+
+ /* Now wait for each ports link */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ AutoNeg = SK_FALSE;
+ } else {
+ AutoNeg = SK_TRUE;
+ }
+
+ /*
+ * here we usually can check whether the link is in sync and
+ * autonegotiation is done.
+ */
+ XM_IN16(IoC, Port, XM_ISRC, &Isrc) ;
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_STAT, &PhyStat);
+ StatSum |= PhyStat;
+
+ SkXmAutoNegLipaLone(pAC, IoC, Port, PhyStat);
+ if ((PhyStat & PHY_ST_LSYNC) == 0){
+ /*
+ * Save Autonegotiation Done bit
+ */
+ pPrt->PIsave = (SK_U16) (StatSum & PHY_ST_AN_OVER);
+#ifdef DEBUG
+ if (pPrt->PIsave & PHY_ST_AN_OVER) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg done rescheduled Port %d\n", Port));
+ }
+#endif
+ return(SK_HW_PS_NONE) ;
+ }
+
+ if (AutoNeg) {
+ if (StatSum & PHY_ST_AN_OVER) {
+ SkHWLinkUp(pAC, IoC, Port) ;
+ Done = SkXmAutoNegDone(pAC,IoC,Port);
+ if (Done != SK_AND_OK) {
+ /* Get PHY parameters, for debuging only */
+ PHY_READ(IoC, pPrt, Port,
+ PHY_LONE_AUNE_LP,
+ &LpAb);
+ PHY_READ(IoC, pPrt, Port,
+ PHY_LONE_1000T_STAT,
+ &ExtStat);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
+ Port, LpAb, ExtStat));
+
+ /* Try next possible mode */
+ NextMode = SkHWSenseGetNext(pAC, IoC, Port);
+ SkHWLinkDown(pAC, IoC, Port) ;
+ if (Done == SK_AND_DUP_CAP) {
+ /* GoTo next mode */
+ SkHWSenseSetNext(pAC, IoC, Port,
+ NextMode);
+ }
+
+ return(SK_HW_PS_RESTART) ;
+
+ } else {
+ /*
+ * Dummy Read interrupt status to prevent
+ * extra link down/ups
+ */
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_INT_STAT,
+ &ExtStat);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg done Port %d\n", Port));
+ return(SK_HW_PS_LINK) ;
+ }
+ }
+
+ /*
+ * AutoNeg not done, but HW link is up. Check for timeouts
+ */
+ pPrt->PAutoNegTimeOut ++;
+ if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
+ /*
+ * Timeout occured.
+ * What do we need now?
+ */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("AutoNeg timeout Port %d\n",
+ Port));
+ if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
+ pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
+ /*
+ * Timeout occured
+ * Set Link manually up.
+ */
+ SkHWSenseSetNext(pAC, IoC, Port,
+ SK_LMODE_FULL);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,
+ SK_DBGCAT_IRQ,
+ ("Set manual full duplex Port %d\n",
+ Port));
+ }
+
+ /*
+ * Do the restart
+ */
+ return(SK_HW_PS_RESTART) ;
+ }
+ } else {
+ /*
+ * Link is up and we don't need more.
+ */
+#ifdef DEBUG
+ if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("ERROR: Lipa auto detected on port %d\n",
+ Port));
+ }
+#endif
+
+ /*
+ * Dummy Read interrupt status to prevent
+ * extra link down/ups
+ */
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_INT_STAT, &ExtStat);
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("Link sync(GP), Port %d\n", Port));
+ SkHWLinkUp(pAC, IoC, Port) ;
+ return(SK_HW_PS_LINK) ;
+ }
+
+ return(SK_HW_PS_NONE) ;
+}
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUpNat - Check if the link is up
+ *
+ * return:
+ * 0 o.k. nothing needed
+ * 1 Restart needed on this port
+ * 2 Link came up
+ */
+static int SkGePortCheckUpNat(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int Port) /* Which port should be checked */
+{
+ /* todo: National */
+ return(SK_HW_PS_NONE) ;
+}
+
+
+/******************************************************************************
+ *
+ * Event service routine
+ *
+ * Description:
+ *
+ * Notes:
+ */
+int SkGeSirqEvent(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* Io Context */
+SK_U32 Event, /* Module specific Event */
+SK_EVPARA Para) /* Event specific Parameter */
+{
+ SK_U32 Port;
+ SK_U32 Time;
+ SK_U8 Val8 ;
+ int PortStat;
+
+ Port = Para.Para32[0];
+
+ switch (Event) {
+ case SK_HWEV_WATIM:
+ /* Check whether port came up */
+ PortStat = SkGePortCheckUp(pAC, IoC, Port);
+
+ switch (PortStat) {
+ case SK_HW_PS_RESTART:
+ if (pAC->GIni.GP[Port].PHWLinkUp) {
+ /*
+ * Set Link to down.
+ */
+ SkHWLinkDown(pAC, IoC, Port);
+
+ /*
+ * Signal directly to RLMT to ensure correct
+ * sequence of SWITCH and RESET event.
+ */
+ Para.Para32[0] = (SK_U32) Port;
+ SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC,
+ &pAC->GIni.GP[Port].PWaTimer,
+ SK_WA_INA_TIME,
+ SKGE_HWAC,
+ SK_HWEV_WATIM,
+ Para);
+ }
+
+ /* Restart needed */
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
+ break;
+
+ case SK_HW_PS_LINK:
+ /* Signal to RLMT */
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
+ break;
+
+ }
+
+ /* Start again the check Timer */
+ if (pAC->GIni.GP[Port].PHWLinkUp) {
+ Time = SK_WA_ACT_TIME;
+ } else {
+ Time = SK_WA_INA_TIME;
+ }
+
+ /* todo: still needed for non-Xmac-PHYs ??? */
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer, Time,
+ SKGE_HWAC, SK_HWEV_WATIM, Para);
+
+ break;
+
+ case SK_HWEV_PORT_START:
+ if (pAC->GIni.GP[Port].PHWLinkUp) {
+ /*
+ * Signal directly to RLMT to ensure correct
+ * sequence of SWITCH and RESET event.
+ */
+ Para.Para32[0] = (SK_U32) Port;
+ SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+ }
+
+ SkHWLinkDown(pAC, IoC, Port) ;
+
+ /* Schedule Port RESET */
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
+
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer,
+ SK_WA_INA_TIME,SKGE_HWAC,SK_HWEV_WATIM,Para);
+ break;
+
+ case SK_HWEV_PORT_STOP:
+ if (pAC->GIni.GP[Port].PHWLinkUp) {
+ /*
+ * Signal directly to RLMT to ensure correct
+ * sequence of SWITCH and RESET event.
+ */
+ Para.Para32[0] = (SK_U32) Port;
+ SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+ }
+ /* Stop Workaround Timer */
+ SkTimerStop(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer) ;
+
+ SkHWLinkDown(pAC, IoC, Port) ;
+ break;
+
+ case SK_HWEV_UPDATE_STAT:
+ /* We do NOT need to update any statistics */
+ break;
+
+ case SK_HWEV_CLEAR_STAT:
+ /* We do NOT need to clear any statistics */
+ for (Port = 0; Port < (SK_U32) pAC->GIni.GIMacsFound; Port++) {
+ pAC->GIni.GP[Port].PPrevRx = 0;
+ pAC->GIni.GP[Port].PPrevFcs = 0;
+ pAC->GIni.GP[Port].PPrevShorts = 0;
+ }
+ break;
+
+ case SK_HWEV_SET_LMODE:
+ Val8 = (SK_U8) Para.Para32[1];
+ if (pAC->GIni.GP[Port].PLinkModeConf != Val8) {
+ /* Set New link mode */
+ pAC->GIni.GP[Port].PLinkModeConf = Val8;
+
+ /* Restart Port */
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+ }
+ break;
+
+ case SK_HWEV_SET_FLOWMODE:
+ Val8 = (SK_U8) Para.Para32[1];
+ if (pAC->GIni.GP[Port].PFlowCtrlMode != Val8) {
+ /* Set New Flow Control mode */
+ pAC->GIni.GP[Port].PFlowCtrlMode = Val8;
+
+ /* Restart Port */
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+ }
+ break;
+
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001,
+ SKERR_SIRQ_E001MSG);
+ break;
+ }
+
+ return(0) ;
+}
+
+
+/******************************************************************************
+ *
+ * SkPhyIsrBcom - PHY interrupt service routine
+ *
+ * Description: handle all interrupts from BCOM PHY
+ *
+ * Returns: N/A
+ */
+static void SkPhyIsrBcom(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* Io Context */
+int Port, /* Port Num = PHY Num */
+SK_U16 IStatus) /* Interrupts masked with PHY-Mask */
+{
+ SK_EVPARA Para;
+
+ if (IStatus & PHY_B_IS_PSE) {
+ /* incorrectable pair swap error */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
+ SKERR_SIRQ_E022MSG) ;
+ }
+
+ if (IStatus & PHY_B_IS_MDXI_SC) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_HCT) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_LCT) {
+ /* not used */
+ }
+
+ if (IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
+ SkHWLinkDown(pAC, IoC, Port);
+
+ /* Signal to RLMT */
+ Para.Para32[0] = (SK_U32) Port;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer,
+ SK_WA_INA_TIME,SKGE_HWAC,SK_HWEV_WATIM,Para);
+ }
+
+ if (IStatus & PHY_B_IS_NO_HDCL) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_NO_HDC) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_NEG_USHDC) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_SCR_S_ER) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_RRS_CHANGE) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_LRS_CHANGE) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_DUP_CHANGE) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_LSP_CHANGE) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_B_IS_CRC_ER) {
+ /* not used */
+ }
+
+}
+
+
+/******************************************************************************
+ *
+ * SkPhyIsrLone - PHY interrupt service routine
+ *
+ * Description: handle all interrupts from LONE PHY
+ *
+ * Returns: N/A
+ */
+static void SkPhyIsrLone(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* Io Context */
+int Port, /* Port Num = PHY Num */
+SK_U16 IStatus) /* Interrupts masked with PHY-Mask */
+{
+ SK_EVPARA Para;
+
+ if (IStatus & PHY_L_IS_CROSS) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_POL) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_SS) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_CFULL) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_AN_C) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_SPEED) {
+ /* not used */
+ }
+
+ if (IStatus & PHY_L_IS_CFULL) {
+ /* not used */
+ }
+
+ if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
+ SkHWLinkDown(pAC, IoC, Port);
+
+ /* Signal to RLMT */
+ Para.Para32[0] = (SK_U32) Port;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer,
+ SK_WA_INA_TIME,SKGE_HWAC,SK_HWEV_WATIM,Para);
+ }
+
+ if (IStatus & PHY_L_IS_MDINT) {
+ /* not used */
+ }
+
+}
+
+
+/* End of File */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: ski2c.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.41 $
+ * Date: $Date: 1999/09/14 14:11:30 $
+ * Purpose: Funktions to access Voltage and Temperature Sensor
+ * (taken from Monalisa (taken from Concentrator))
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: ski2c.c,v $
+ * Revision 1.41 1999/09/14 14:11:30 malthoff
+ * The 1000BT Dual Link adapter has got only one Fan.
+ * The second Fan has been removed.
+ *
+ * Revision 1.40 1999/05/27 13:37:27 malthoff
+ * Set divisor of 1 for fan count calculation.
+ *
+ * Revision 1.39 1999/05/20 14:54:43 malthoff
+ * I2c.DummyReads is not used in Diagnostics.
+ *
+ * Revision 1.38 1999/05/20 09:20:56 cgoos
+ * Changes for 1000Base-T (up to 9 sensors and fans).
+ *
+ * Revision 1.37 1999/03/25 15:11:36 gklug
+ * fix: reset error flag if sensor reads correct value
+ *
+ * Revision 1.36 1999/01/07 14:11:16 gklug
+ * fix: break added
+ *
+ * Revision 1.35 1999/01/05 15:31:49 gklug
+ * fix: CLEAR STAT command is now added correctly
+ *
+ * Revision 1.34 1998/12/01 13:45:16 gklug
+ * fix: introduced Init level, because we don't need reinits
+ *
+ * Revision 1.33 1998/11/09 14:54:25 malthoff
+ * Modify I2C Transfer Timeout handling for Diagnostics.
+ *
+ * Revision 1.32 1998/11/03 06:54:35 gklug
+ * fix: Need dummy reads at the beginning to init sensors
+ *
+ * Revision 1.31 1998/11/03 06:42:42 gklug
+ * fix: select correctVIO range only if between warning levels
+ *
+ * Revision 1.30 1998/11/02 07:36:53 gklug
+ * fix: Error should not include WARNING message
+ *
+ * Revision 1.29 1998/10/30 15:07:43 malthoff
+ * Disable 'I2C does not compelete' error log for diagnostics.
+ *
+ * Revision 1.28 1998/10/22 09:48:11 gklug
+ * fix: SysKonnectFileId typo
+ *
+ * Revision 1.27 1998/10/20 09:59:46 gklug
+ * add: parameter to SkOsGetTime
+ *
+ * Revision 1.26 1998/10/09 06:10:59 malthoff
+ * Remove ID_sccs by SysKonnectFileId.
+ *
+ * Revision 1.25 1998/09/08 12:40:26 gklug
+ * fix: syntax error in if clause
+ *
+ * Revision 1.24 1998/09/08 12:19:42 gklug
+ * chg: INIT Level checking
+ *
+ * Revision 1.23 1998/09/08 07:37:20 gklug
+ * fix: log error if PCI_IO voltage sensor could not be initialized
+ *
+ * Revision 1.22 1998/09/04 08:30:03 malthoff
+ * Bugfixes during SK_DIAG testing:
+ * - correct NS2BCLK() macro
+ * - correct SkI2cSndDev()
+ * - correct SkI2cWait() loop waiting for an event
+ *
+ * Revision 1.21 1998/08/27 14:46:01 gklug
+ * chg: if-then-else replaced by switch
+ *
+ * Revision 1.20 1998/08/27 14:40:07 gklug
+ * test: integral types
+ *
+ * Revision 1.19 1998/08/25 07:51:54 gklug
+ * fix: typos for compiling
+ *
+ * Revision 1.18 1998/08/25 06:12:24 gklug
+ * add: count errors and warnings
+ * fix: check not the sensor state but the ErrFlag!
+ *
+ * Revision 1.17 1998/08/25 05:56:48 gklug
+ * add: CheckSensor function
+ *
+ * Revision 1.16 1998/08/20 11:41:10 gklug
+ * chg: omit STRCPY macro by using char * as Sensor Description
+ *
+ * Revision 1.15 1998/08/20 11:37:35 gklug
+ * chg: change Ioc to IoC
+ *
+ * Revision 1.14 1998/08/20 11:32:52 gklug
+ * fix: Para compile error
+ *
+ * Revision 1.13 1998/08/20 11:27:41 gklug
+ * fix: Compile bugs with new awrning constants
+ *
+ * Revision 1.12 1998/08/20 08:53:05 gklug
+ * fix: compiler errors
+ * add: Threshold values
+ *
+ * Revision 1.11 1998/08/19 12:39:22 malthoff
+ * Compiler Fix: Some names have changed.
+ *
+ * Revision 1.10 1998/08/19 12:20:56 gklug
+ * fix: remove struct from C files (see CCC)
+ *
+ * Revision 1.9 1998/08/19 06:28:46 malthoff
+ * SkOsGetTime returns SK_U64 now.
+ *
+ * Revision 1.8 1998/08/17 13:53:33 gklug
+ * fix: Parameter of event function and its result
+ *
+ * Revision 1.7 1998/08/17 07:02:15 malthoff
+ * Modify the functions for accessing the I2C SW Registers.
+ * Modify SkI2cWait().
+ * Put Lm80RcvReg into sklm80.c
+ * Remove Compiler Errors.
+ *
+ * Revision 1.6 1998/08/14 07:13:20 malthoff
+ * remove pAc with pAC
+ * remove smc with pAC
+ * change names to new convention
+ *
+ * Revision 1.5 1998/08/14 06:24:49 gklug
+ * add: init level 1 and 2
+ *
+ * Revision 1.4 1998/08/12 14:31:12 gklug
+ * add: error log for unknown event
+ *
+ * Revision 1.3 1998/08/12 13:37:04 gklug
+ * add: Init 0 function
+ *
+ * Revision 1.2 1998/08/11 07:27:15 gklug
+ * add: functions of the interface
+ * adapt rest of source to C coding Conventions
+ * rmv: unneccessary code taken from Mona Lisa
+ *
+ * Revision 1.1 1998/06/19 14:28:43 malthoff
+ * Created. Sources taken from ML Projekt.
+ * Sources have to be reworked for GE.
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ i2C Protocol
+*/
+static const char SysKonnectFileId[] =
+ "$Id: ski2c.c,v 1.41 1999/09/14 14:11:30 malthoff Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/lm80.h"
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+ I2C protocol implemetation.
+
+ General Description:
+
+ The I2C protocol is used for the temperature sensors and for
+ the serial EEPROM which hold the configuration.
+
+ This file covers functions that allow to read write and do
+ some bulk requests a specified I2C address.
+
+ The Genesis has 2 I2C busses. One for the EEPROM which holds
+ the VPD Data and one for temperature and voltage sensor.
+ The following picture shows the I2C busses, I2C devices and
+ there control registers.
+
+ Note: The VPD functions are in skvpd.c
+.
+. PCI Config I2C Bus for VPD Data:
+.
+. +------------+
+. | VPD EEPROM |
+. +------------+
+. |
+. | <-- I2C
+. |
+. +-----------+-----------+
+. | |
+. +-----------------+ +-----------------+
+. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
+. +-----------------+ +-----------------+
+.
+.
+. I2C Bus for LM80 sensor:
+.
+. +-----------------+
+. | Temperature and |
+. | Voltage Sensor |
+. | LM80 |
+. +-----------------+
+. |
+. |
+. I2C --> |
+. |
+. +----+
+. +-------------->| OR |<--+
+. | +----+ |
+. +------+------+ |
+. | | |
+. +--------+ +--------+ +----------+
+. | B2_I2C | | B2_I2C | | B2_I2C |
+. | _CTRL | | _DATA | | _SW |
+. +--------+ +--------+ +----------+
+.
+ The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
+ and B2_I2C_DATA registers.
+ For driver software it is recommended to use the I2C control and
+ data register, because I2C bus timing is done by the ASIC and
+ an interrupt may be received when the I2C request is completed.
+
+ Clock Rate Timing: MIN MAX generated by
+ VPD EEPROM: 50 kHz 100 kHz HW
+ LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW
+ LM80 over B2_I2C_SW register 0 400 kHz SW
+
+ Note: The clock generated by the hardware is dependend on the
+ PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
+ clock is 50 kHz.
+ */
+intro()
+{}
+#endif
+
+#ifdef SK_DIAG
+/*
+ * I2C Fast Mode timing values used by the LM80.
+ * If new devices are added to the I2C bus the timing values have to be checked.
+ */
+#ifndef I2C_SLOW_TIMING
+#define T_CLK_LOW 1300L /* clock low time in ns */
+#define T_CLK_HIGH 600L /* clock high time in ns */
+#define T_DATA_IN_SETUP 100L /* data in Set-UP Time */
+#define T_START_HOLD 600L /* start condition hold time */
+#define T_START_SETUP 600L /* start condition Set-up time */
+#define T_STOP_SETUP 600L /* stop condition Set-up time */
+#define T_BUS_IDLE 1300L /* time the bus must free after tx */
+#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
+#else /* I2C_SLOW_TIMING */
+/* I2C Standard Mode Timing */
+#define T_CLK_LOW 4700L /* clock low time in ns */
+#define T_CLK_HIGH 4000L /* clock high time in ns */
+#define T_DATA_IN_SETUP 250L /* data in Set-UP Time */
+#define T_START_HOLD 4000L /* start condition hold time */
+#define T_START_SETUP 4700L /* start condition Set_up time */
+#define T_STOP_SETUP 4000L /* stop condition Set-up time */
+#define T_BUS_IDLE 4700L /* time the bus must free after tx */
+#endif /* !I2C_SLOW_TIMING */
+
+#define NS2BCLK(x) (((x)*125)/10000)
+
+/*
+ * I2C Wire Operations
+ *
+ * About I2C_CLK_LOW():
+ *
+ * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
+ * clock to low, to prevent the ASIC and the I2C data client from driving the
+ * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client
+ * send an 'ACK'). See also Concentrator Bugreport No. 10192.
+ */
+#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC,I2C_DATA)
+#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC,I2C_DATA)
+#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC,I2C_DATA_DIR)
+#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC,I2C_DATA_DIR|I2C_DATA)
+#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC,I2C_CLK)
+#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC,I2C_CLK|I2C_DATA_DIR)
+#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC,I2C_CLK)
+
+#define NS2CLKT(x) ((x*125L)/10000)
+
+/*--------------- I2C Interface Register Functions --------------- */
+
+/*
+ * sending one bit
+ */
+void SkI2cSndBit(
+SK_IOC IoC, /* IoContext */
+SK_U8 Bit) /* Bit to send */
+{
+ I2C_DATA_OUT(IoC) ;
+ if (Bit) {
+ I2C_DATA_HIGH(IoC);
+ } else {
+ I2C_DATA_LOW(IoC);
+ }
+ SkDgWaitTime(IoC,NS2BCLK(T_DATA_IN_SETUP));
+ I2C_CLK_HIGH(IoC);
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_HIGH));
+ I2C_CLK_LOW(IoC);
+}
+
+
+
+/*
+ * Signal a start to the i2C Bus.
+ *
+ * A start is signaled when data goes to low in a high clock cycle.
+ *
+ * Ends with Clock Low.
+ *
+ * Status: not tested
+ */
+void SkI2cStart(SK_IOC IoC) /* I/O Context */
+{
+ /* Init data and Clock to output lines */
+ /* Set Data high */
+ I2C_DATA_OUT(IoC) ;
+ I2C_DATA_HIGH(IoC) ;
+ /* Set Clock high */
+ I2C_CLK_HIGH(IoC) ;
+
+ SkDgWaitTime(IoC,NS2BCLK(T_START_SETUP)) ;
+
+ /* Set Data Low */
+ I2C_DATA_LOW(IoC) ;
+
+ SkDgWaitTime(IoC,NS2BCLK(T_START_HOLD)) ;
+
+ /* Clock low without Data to Input */
+ I2C_START_COND(IoC) ;
+
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_LOW)) ;
+}
+
+
+void SkI2cStop(SK_IOC IoC) /* I/O Context */
+{
+ /* Init data and Clock to output lines */
+ /* Set Data low */
+ I2C_DATA_OUT(IoC) ;
+ I2C_DATA_LOW(IoC) ;
+
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_2_DATA_OUT)) ;
+
+ /* Set Clock high */
+ I2C_CLK_HIGH(IoC) ;
+
+ SkDgWaitTime(IoC,NS2BCLK(T_STOP_SETUP)) ;
+
+ /*
+ * Set Data High: Do it by setting the Data Line to Input.
+ * Because of a pull up resistor the Data Line
+ * floods to high.
+ */
+ I2C_DATA_IN(IoC) ;
+
+ /*
+ * When I2C activity is stopped
+ * o DATA should be set to input and
+ * o CLOCK should be set to high!
+ */
+ SkDgWaitTime(IoC,NS2BCLK(T_BUS_IDLE)) ;
+}
+
+/*
+ * Receive just one bit via the i2C bus.
+ *
+ * Note: Clock must be set to LOW before calling this function.
+ *
+ * Returns The received bit.
+ */
+int SkI2cRcvBit(SK_IOC IoC) /* I/O Context */
+{
+ int Bit;
+ SK_U8 I2cSwCtrl;
+
+ /* Init data as input line */
+ I2C_DATA_IN(IoC);
+
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_2_DATA_OUT)) ;
+
+ I2C_CLK_HIGH(IoC);
+
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_HIGH)) ;
+
+ SK_I2C_GET_SW(IoC,&I2cSwCtrl) ;
+ if (I2cSwCtrl & I2C_DATA) {
+ Bit = 1;
+ } else {
+ Bit = 0;
+ }
+
+ I2C_CLK_LOW(IoC);
+ SkDgWaitTime(IoC,NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT)) ;
+
+ return(Bit);
+}
+
+/*
+ * Receive an ACK.
+ *
+ * returns 0 If acknoledged
+ * 1 in case of an error
+ */
+int SkI2cRcvAck(SK_IOC IoC) /* I/O Context */
+{
+ /*
+ * Received bit must be zero.
+ */
+ return (SkI2cRcvBit(IoC) != 0) ;
+}
+
+/*
+ * Send an NACK.
+ */
+void SkI2cSndNAck(SK_IOC IoC) /* I/O Context */
+{
+ /*
+ * Received bit must be zero.
+ */
+ SkI2cSndBit(IoC,1) ;
+}
+
+/*
+ * Send an ACK.
+ */
+void SkI2cSndAck(SK_IOC IoC) /* I/O Context */
+{
+ /*
+ * Received bit must be zero.
+ *
+ */
+ SkI2cSndBit(IoC,0) ;
+}
+
+/*
+ * Send one byte to the i2C device and wait for ACK.
+ *
+ * Return acknoleged status.
+ */
+int SkI2cSndByte(
+SK_IOC IoC, /* I/O Context */
+int Byte) /* byte to send */
+{
+ int i;
+
+ for (i=0; i<8; i++) {
+ if (Byte & (1<<(7-i))) {
+ SkI2cSndBit(IoC,1) ;
+ } else {
+ SkI2cSndBit(IoC,0) ;
+ }
+ }
+
+ return(SkI2cRcvAck(IoC)) ;
+}
+
+
+/*
+ * Receive one byte and ack it.
+ *
+ * Return byte.
+ */
+int SkI2cRcvByte(
+SK_IOC IoC, /* I/O Context */
+int Last) /* Last Byte Flag */
+{
+ int i;
+ int Byte = 0;
+
+ for (i=0; i<8; i++) {
+ Byte <<= 1 ;
+ Byte |= SkI2cRcvBit(IoC) ;
+ }
+
+ if (Last) {
+ SkI2cSndNAck(IoC) ;
+ } else {
+ SkI2cSndAck(IoC) ;
+ }
+
+ return(Byte) ;
+}
+
+
+/*
+ * Start dialog and send device address
+ *
+ * Return 0 if acknoleged, 1 in case of an error
+ */
+int SkI2cSndDev(
+SK_IOC IoC, /* I/O Context */
+int Addr, /* Device Address */
+int Rw) /* Read / Write Flag */
+{
+ SkI2cStart(IoC) ;
+ Rw = ~Rw ;
+ Rw &= I2C_WRITE ;
+ return(SkI2cSndByte(IoC, (Addr<<1) | Rw)) ;
+}
+
+#endif /* SK_DIAG */
+
+/*----------------- I2C CTRL Register Functions ----------*/
+
+/*
+ * waits for a completetion of a I2C transfer
+ *
+ * returns 0: success, transfer completes
+ * 1: error, transfer does not complete, I2C transfer
+ * killed, wait loop terminated.
+ */
+int SkI2cWait(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC, /* IoContext */
+int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
+{
+ SK_U64 StartTime ;
+ SK_U32 I2cCtrl ;
+
+ StartTime = SkOsGetTime(pAC) ;
+ do {
+ if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC/16) {
+ SK_I2C_STOP(IoC) ;
+#ifndef SK_DIAG
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002,
+ SKERR_I2C_E002MSG) ;
+#endif /* !SK_DIAG */
+ return(1) ;
+ }
+ SK_I2C_GET_CTL(IoC,&I2cCtrl) ;
+ } while((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31) ;
+
+ return(0) ;
+}
+
+#ifdef SK_DIAG
+/*
+ * writes a single byte or 4 bytes into the I2C device
+ *
+ * returns 0: success
+ * 1: error
+ */
+int SkI2cWrite(
+SK_AC *pAC, /* Adapter Context */
+SK_U32 I2cData, /* I2C Data to write */
+int I2cDev, /* I2C Device Address */
+int I2cReg, /* I2C Device Register Address */
+int I2cBurst) /* I2C Burst Flag ( 0 || I2C_BURST ) */
+{
+ SK_OUT32(pAC,B2_I2C_DATA,I2cData) ;
+ SK_I2C_CTL(pAC,I2C_WRITE,I2cDev,I2cReg,I2cBurst);
+ return(SkI2cWait(pAC,pAC,I2C_WRITE)) ;
+}
+
+/*
+ * reads a single byte or 4 bytes from the I2C device
+ *
+ * returns the word read
+ */
+SK_U32 SkI2cRead(
+SK_AC *pAC, /* Adapter Context */
+int I2cDev, /* I2C Device Address */
+int I2cReg, /* I2C Device Register Address */
+int I2cBurst) /* I2C Burst Flag ( 0 || I2C_BURST ) */
+{
+ SK_U32 Data ;
+
+ SK_OUT32(pAC,B2_I2C_DATA,0) ;
+ SK_I2C_CTL(pAC,I2C_READ,I2cDev,I2cReg,I2cBurst);
+ if (SkI2cWait(pAC,pAC,I2C_READ)) {
+ w_print("I2c Transfer Timeout!\n");
+ }
+ SK_IN32(pAC,B2_I2C_DATA,&Data) ;
+ return(Data) ;
+}
+#endif /* SK_DIAG */
+
+/*
+ * read a sensors value
+ *
+ * This function read a sensors value from the I2c sensor chip. The sensor
+ * is defined by its index into the sensors database in the struct pAC points
+ * to.
+ * Returns 1 if the read is completed
+ * 0 if the read must be continued (I2c Bus still allocated)
+ */
+int SkI2cReadSensor(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC, /* IoContext */
+SK_SENSOR *pSen) /* Sensor to be read */
+{
+ return((*pSen->SenRead)(pAC,IoC,pSen)) ;
+}
+
+/*
+ * Do the Init state 0 initialization
+ */
+static int SkI2cInit0(
+SK_AC *pAC) /* Adapter Context */
+{
+ int i;
+
+ /* Begin with first sensor */
+ pAC->I2c.CurrSens = 0;
+
+ /* Set to mimimum sensor number */
+ pAC->I2c.MaxSens = SK_MIN_SENSORS;
+
+#ifndef SK_DIAG
+ /* Initialize Number of Dummy Reads */
+ pAC->I2c.DummyReads = SK_MAX_SENSORS;
+#endif
+
+ for (i=0; i < SK_MAX_SENSORS; i ++) {
+ switch (i) {
+ case 0:
+ pAC->I2c.SenTable[i].SenDesc = "Temperature" ;
+ pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH0;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW0;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH0;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW0;
+ pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 1:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage PCI";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH1;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW1;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH1;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW1;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 2:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH2;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW2;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH2;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW2;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_FALSE;
+ break;
+ case 3:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH3;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW3;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH3;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW3;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 4:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage PMA";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH4;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW4;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH4;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW4;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 5:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH5;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW5;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH5;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW5;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 6:
+ pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH6;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW6;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH6;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW6;
+ pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ case 7:
+ pAC->I2c.SenTable[i].SenDesc = "Speed Fan";
+ pAC->I2c.SenTable[i].SenType = SK_SEN_FAN;
+ pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_ERRHIGH;
+ pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_ERRLOW;
+ pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_WARNHIGH;
+ pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_WARNLOW;
+ pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
+ pAC->I2c.SenTable[i].SenInit = SK_TRUE;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
+ SKERR_I2C_E001, SKERR_I2C_E001MSG);
+ break;
+ }
+
+ pAC->I2c.SenTable[i].SenValue = 0;
+ pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
+ pAC->I2c.SenTable[i].SenErrCts = 0;
+ pAC->I2c.SenTable[i].SenBegErrTS = 0;
+ pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
+ pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor;
+ pAC->I2c.SenTable[i].SenDev = LM80_ADDR;
+ }
+
+ /* Now we are INIT dataed */
+ pAC->I2c.InitLevel = SK_INIT_DATA;
+ return(0);
+}
+
+/*
+ * Do the init state 1 initialization
+ *
+ * initialize the following register of the LM80:
+ * Configuration register:
+ * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
+ *
+ * Interrupt Mask Register 1:
+ * - all interrupts are Disabled (0xff)
+ *
+ * Interrupt Mask Register 2:
+ * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
+ *
+ * Fan Divisor/RST_OUT register:
+ * - Divisors set to 1 (bits 00), all others 0s.
+ *
+ * OS# Configuration/Temperature resolution Register:
+ * - all 0s
+ *
+ */
+static int SkI2cInit1(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC) /* IoContext needed in level 1 */
+{
+ if (pAC->I2c.InitLevel != SK_INIT_DATA) {
+ /* ReInit not needed in I2C module */
+ return(0);
+ }
+
+ SK_OUT32(IoC, B2_I2C_DATA, 0);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_CFG, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ SK_OUT32(IoC, B2_I2C_DATA, 0xff);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_IMSK_1, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ SK_OUT32(IoC, B2_I2C_DATA, 0xff);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_IMSK_2, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ SK_OUT32(IoC, B2_I2C_DATA, 0x0);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_FAN_CTRL, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ SK_OUT32(IoC, B2_I2C_DATA, 0);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_TEMP_CTRL, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ SK_OUT32(IoC, B2_I2C_DATA, LM80_CFG_START);
+ SK_I2C_CTL(IoC, I2C_WRITE, LM80_ADDR, LM80_CFG, 0);
+ (void)SkI2cWait(pAC, IoC, I2C_WRITE) ;
+
+ /*
+ * MaxSens has to be initialized here, because PhyType is not
+ * set when performing Init Level 1
+ */
+ switch (pAC->GIni.GP[0].PhyType) {
+ case SK_PHY_XMAC:
+ pAC->I2c.MaxSens = 5;
+ break;
+ case SK_PHY_BCOM:
+ pAC->I2c.SenTable[4].SenDesc = "Voltage PHY A PLL";
+ if (pAC->GIni.GIMacsFound == 1) {
+ pAC->I2c.MaxSens = 6;
+ }
+ else {
+ pAC->I2c.MaxSens = 8;
+ }
+ break;
+ case SK_PHY_LONE:
+ pAC->I2c.MaxSens = 5;
+ break;
+ }
+
+#ifndef SK_DIAG
+ pAC->I2c.DummyReads = pAC->I2c.MaxSens;
+#endif /* !SK_DIAG */
+
+ /* Now we are IO initialized */
+ pAC->I2c.InitLevel = SK_INIT_IO;
+ return(0);
+}
+
+/*
+ * Init level 2: Start first sensors read
+ */
+static int SkI2cInit2(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC) /* IoContext needed in level 1 */
+{
+ int ReadComplete;
+ SK_SENSOR *pSen;
+
+ if (pAC->I2c.InitLevel != SK_INIT_IO) {
+ /* ReInit not needed in I2C module */
+ /* Init0 and Init2 not permitted */
+ return(0);
+ }
+
+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+ ReadComplete = SkI2cReadSensor(pAC,IoC,pSen);
+
+ if (ReadComplete) {
+ SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008,
+ SKERR_I2C_E008MSG);
+ }
+
+ /* Now we are correctly initialized */
+ pAC->I2c.InitLevel = SK_INIT_RUN;
+
+ return(0);
+}
+
+/*
+ * Initialize I2C devices
+ *
+ * Get the first voltage value and discard it.
+ * Go into temperature read mode. A default pointer is not set.
+ *
+ * The things to be done depend on the init level in the parameter list:
+ * Level 0:
+ * Initialize only the data structures. Do NOT access hardware.
+ * Level 1:
+ * Initialize hardware through SK_IN?OUT commands. Do NOT use interrupts.
+ * Level 2:
+ * Everything is possible. Interrupts may be used from now on.
+ *
+ * return: 0 = success
+ * other = error.
+ */
+int SkI2cInit(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC, /* IoContext needed in level 1 */
+int Level) /* Init Level */
+{
+
+ switch (Level) {
+ case SK_INIT_DATA:
+ return(SkI2cInit0(pAC)) ;
+ case SK_INIT_IO:
+ return(SkI2cInit1(pAC, IoC)) ;
+ case SK_INIT_RUN:
+ return(SkI2cInit2(pAC, IoC)) ;
+ default:
+ break;
+ }
+
+ return(0) ;
+}
+
+#ifndef SK_DIAG
+/*
+ * Interrupt service function for the I2c Interface
+ *
+ * Clears the Interrupt source
+ *
+ * Reads the register and check it for sending a trap.
+ *
+ * Starts the timer if necessary.
+ */
+void SkI2cIsr(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC) /* Io Context */
+{
+ SK_EVPARA Para;
+
+ /* Clear the interrupt source */
+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ) ;
+
+ Para.Para64 = 0;
+ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
+}
+
+/*
+ * Check this sensors Value against the threshold and send events.
+ */
+static void SkI2cCheckSensor(
+SK_AC *pAC, /* Adapters context */
+SK_SENSOR *pSen)
+{
+ SK_EVPARA ParaLocal;
+ SK_BOOL TooHigh; /* Is sensor too high? */
+ SK_BOOL TooLow; /* Is sensor too low? */
+ SK_U64 CurrTime; /* current Time */
+ SK_BOOL DoTrapSend; /* We need to send a trap */
+ SK_BOOL DoErrLog; /* We need to log the error */
+ SK_BOOL IsError; /* We need to log the error */
+
+ /* Check Dummy Reads first */
+ if (pAC->I2c.DummyReads > 0) {
+ pAC->I2c.DummyReads -- ;
+ return;
+ }
+
+ /* Get the current time */
+ CurrTime = SkOsGetTime(pAC) ;
+
+ /* Set para to the most usefull setting:
+ * The current sensor.
+ */
+ ParaLocal.Para64 = (SK_U64) pAC->I2c.CurrSens;
+
+ /* Check the Value against the thresholds */
+ /* First: Error Thresholds */
+ TooHigh = (pSen->SenValue > pSen->SenThreErrHigh) ;
+ TooLow = (pSen->SenValue < pSen->SenThreErrLow) ;
+
+ IsError = SK_FALSE ;
+ if (TooHigh || TooLow) {
+ /* Error condition is satiesfied */
+ DoTrapSend = SK_TRUE;
+ DoErrLog = SK_TRUE;
+
+ /* Now error condition is satisfied */
+ IsError = SK_TRUE ;
+
+ if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
+ /* This state is the former one */
+
+ /* So check first whether we have to send a trap */
+ if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD >
+ CurrTime) {
+ /*
+ * Do NOT send the Trap. The hold back time
+ * has to run out first.
+ */
+ DoTrapSend = SK_FALSE;
+ }
+
+ /* Check now whether we have to log an Error */
+ if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD >
+ CurrTime) {
+ /*
+ * Do NOT log the error. The hold back time
+ * has to run out first.
+ */
+ DoErrLog = SK_FALSE;
+ }
+ } else {
+ /* We came from a different state */
+ /* -> Set Begin Time Stamp */
+ pSen->SenBegErrTS = CurrTime;
+ pSen->SenErrFlag = SK_SEN_ERR_ERR ;
+ }
+
+ if (DoTrapSend) {
+ /* Set current Time */
+ pSen->SenLastErrTrapTS = CurrTime;
+ pSen->SenErrCts ++;
+
+ /* Queue PNMI Event */
+ SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
+ SK_PNMI_EVT_SEN_ERR_UPP :
+ SK_PNMI_EVT_SEN_ERR_LOW),
+ ParaLocal) ;
+ }
+
+ if (DoErrLog) {
+ /* Set current Time */
+ pSen->SenLastErrLogTS = CurrTime;
+
+ if (pSen->SenType == SK_SEN_TEMP) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011,
+ SKERR_I2C_E011MSG);
+ } else if (pSen->SenType == SK_SEN_VOLT) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012,
+ SKERR_I2C_E012MSG);
+ } else
+ {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015,
+ SKERR_I2C_E015MSG);
+ }
+ }
+ }
+
+ /* Check the Value against the thresholds */
+ /* 2nd: Warning thresholds */
+ TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh) ;
+ TooLow = (pSen->SenValue < pSen->SenThreWarnLow) ;
+
+
+ if (!IsError && (TooHigh || TooLow)) {
+ /* Error condition is satiesfied */
+ DoTrapSend = SK_TRUE;
+ DoErrLog = SK_TRUE;
+
+ if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
+ /* This state is the former one */
+
+ /* So check first whether we have to send a trap */
+ if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD >
+ CurrTime) {
+ /*
+ * Do NOT send the Trap. The hold back time
+ * has to run out first.
+ */
+ DoTrapSend = SK_FALSE;
+ }
+
+ /* Check now whether we have to log an Error */
+ if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD >
+ CurrTime) {
+ /*
+ * Do NOT log the error. The hold back time
+ * has to run out first.
+ */
+ DoErrLog = SK_FALSE;
+ }
+ } else {
+ /* We came from a different state */
+ /* -> Set Begin Time Stamp */
+ pSen->SenBegWarnTS = CurrTime;
+ pSen->SenErrFlag = SK_SEN_ERR_WARN ;
+ }
+
+ if (DoTrapSend) {
+ /* Set current Time */
+ pSen->SenLastWarnTrapTS = CurrTime;
+ pSen->SenWarnCts ++;
+
+ /* Queue PNMI Event */
+ SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
+ SK_PNMI_EVT_SEN_WAR_UPP :
+ SK_PNMI_EVT_SEN_WAR_LOW),
+ ParaLocal) ;
+ }
+
+ if (DoErrLog) {
+ /* Set current Time */
+ pSen->SenLastWarnLogTS = CurrTime;
+
+ if (pSen->SenType == SK_SEN_TEMP) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009,
+ SKERR_I2C_E009MSG);
+ } else if (pSen->SenType == SK_SEN_VOLT) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009,
+ SKERR_I2C_E009MSG);
+ } else
+ {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014,
+ SKERR_I2C_E014MSG);
+ }
+ }
+ }
+
+ /* Check for NO error at all */
+ if (!IsError && !TooHigh && !TooLow) {
+ /* Set o.k. Status if no error and no warning condition */
+ pSen->SenErrFlag = SK_SEN_ERR_OK ;
+ }
+
+ /* End of check against the thresholds */
+
+ /*
+ * Check initialization state:
+ * The VIO Thresholds need adaption
+ */
+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
+ pSen->SenValue > SK_SEN_WARNLOW2C &&
+ pSen->SenValue < SK_SEN_WARNHIGH2) {
+ pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
+ pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
+ pSen->SenInit = SK_TRUE;
+ }
+
+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
+ pSen->SenValue > SK_SEN_WARNLOW2 &&
+ pSen->SenValue < SK_SEN_WARNHIGH2C) {
+ pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
+ pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
+ pSen->SenInit = SK_TRUE;
+ }
+
+ if (!pSen->SenInit) {
+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
+ }
+}
+
+/*
+ * The only Event to be served is the timeout event
+ *
+ */
+int SkI2cEvent(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* Io Context */
+SK_U32 Event, /* Module specific Event */
+SK_EVPARA Para) /* Event specific Parameter */
+{
+ int ReadComplete;
+ SK_SENSOR *pSen;
+ SK_U32 Time;
+ SK_EVPARA ParaLocal;
+ int i;
+
+ switch (Event) {
+ case SK_I2CEV_IRQ:
+ case SK_I2CEV_TIM:
+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
+
+ if (ReadComplete) {
+ /* Check sensor against defined thresholds */
+ SkI2cCheckSensor (pAC, pSen) ;
+
+ /* Increment Current and set appropriate Timeout */
+ Time = SK_I2C_TIM_SHORT;
+
+ pAC->I2c.CurrSens ++;
+ if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
+ pAC->I2c.CurrSens = 0;
+ Time = SK_I2C_TIM_LONG;
+ }
+
+ /* Start Timer */
+ ParaLocal.Para64 = (SK_U64) 0;
+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal) ;
+ }
+ break;
+ case SK_I2CEV_CLEAR:
+ for (i=0; i < SK_MAX_SENSORS; i ++) {
+ pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
+ pAC->I2c.SenTable[i].SenErrCts = 0;
+ pAC->I2c.SenTable[i].SenWarnCts = 0;
+ pAC->I2c.SenTable[i].SenBegErrTS = 0;
+ pAC->I2c.SenTable[i].SenBegWarnTS = 0;
+ pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64) 0;
+ pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64) 0;
+ pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64) 0;
+ pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64) 0;
+ }
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
+ }
+
+ return(0);
+}
+#endif /* !SK_DIAG */
+/* End of File */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: sklm80.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.16 $
+ * Date: $Date: 1999/05/27 14:05:47 $
+ * Purpose: Funktions to access Voltage and Temperature Sensor (LM80)
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: sklm80.c,v $
+ * Revision 1.16 1999/05/27 14:05:47 malthoff
+ * Fans: Set SenVal to 0 if the fan value is 0 or 0xff. Both values
+ * are outside the limits (0: div zero error, 0xff: value not in
+ * range, assume 0).
+ *
+ * Revision 1.15 1999/05/27 13:38:51 malthoff
+ * Pervent from Division by zero errors.
+ *
+ * Revision 1.14 1999/05/20 09:20:01 cgoos
+ * Changes for 1000Base-T (Fan sensors).
+ *
+ * Revision 1.13 1998/10/22 09:48:14 gklug
+ * fix: SysKonnectFileId typo
+ *
+ * Revision 1.12 1998/10/09 06:12:06 malthoff
+ * Remove ID_sccs by SysKonnectFileId.
+ *
+ * Revision 1.11 1998/09/04 08:33:48 malthoff
+ * bug fix: SenState = SK_SEN_IDLE when
+ * leaving SK_SEN_VALEXT state
+ *
+ * Revision 1.10 1998/08/20 12:02:10 gklug
+ * fix: compiler warnings type mismatch
+ *
+ * Revision 1.9 1998/08/20 11:37:38 gklug
+ * chg: change Ioc to IoC
+ *
+ * Revision 1.8 1998/08/19 12:20:58 gklug
+ * fix: remove struct from C files (see CCC)
+ *
+ * Revision 1.7 1998/08/17 07:04:57 malthoff
+ * Take SkLm80RcvReg() function from ski2c.c.
+ * Add IoC parameter to BREAK_OR_WAIT() macro.
+ *
+ * Revision 1.6 1998/08/14 07:11:28 malthoff
+ * remove pAc with pAC.
+ *
+ * Revision 1.5 1998/08/14 06:46:55 gklug
+ * fix: temperature can get negative
+ *
+ * Revision 1.4 1998/08/13 08:27:04 gklug
+ * add: temperature reading now o.k.
+ * fix: pSen declaration, SK_ERR_LOG call, ADDR macro
+ *
+ * Revision 1.3 1998/08/13 07:28:21 gklug
+ * fix: pSen was wrong initialized
+ * add: correct conversion for voltage readings
+ *
+ * Revision 1.2 1998/08/11 07:52:14 gklug
+ * add: Lm80 read sensor function
+ *
+ * Revision 1.1 1998/07/17 09:57:12 gklug
+ * initial version
+ *
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ LM80 functions
+*/
+static const char SysKonnectFileId[] =
+ "$Id: sklm80.c,v 1.16 1999/05/27 14:05:47 malthoff Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/lm80.h"
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+#ifdef SK_DIAG
+#define BREAK_OR_WAIT(pAC,IoC,Event) SkI2cWait(pAC,IoC,Event)
+#else /* nSK_DIAG */
+#define BREAK_OR_WAIT(pAC,IoC,Event) break
+#endif /* nSK_DIAG */
+
+#ifdef SK_DIAG
+/*
+ * read the regeister 'reg' from the device 'device'
+ *
+ * return read error -1
+ * success the read value
+ */
+int SkLm80RcvReg(
+SK_IOC IoC, /* Adapter Context */
+int Dev, /* I2C device address */
+int Reg) /* register to read */
+{
+ int Val = 0;
+ int TempExt;
+
+ /* Signal device number */
+ if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) {
+ return(-1);
+ }
+
+ if (SkI2cSndByte(IoC, Reg)) {
+ return(-1);
+ }
+
+ /* repeat start */
+ if (SkI2cSndDev(IoC, Dev, I2C_READ)) {
+ return(-1);
+ }
+
+ switch(Reg) {
+ case LM80_TEMP_IN:
+ Val = (int)SkI2cRcvByte(IoC, 1) ;
+
+ /* First: correct the value: it might be negative */
+ if ((Val & 0x80) != 0) {
+ /* Value is negative */
+ Val = Val - 256;
+ }
+ Val = Val * SK_LM80_TEMP_LSB;
+ SkI2cStop(IoC);
+ TempExt = (int) SkLm80RcvReg(IoC,LM80_ADDR,LM80_TEMP_CTRL);
+ if (Val > 0) {
+ Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
+ }
+ else {
+ Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
+ }
+ return(Val);
+ break;
+ case LM80_VT0_IN:
+ case LM80_VT1_IN:
+ case LM80_VT2_IN:
+ case LM80_VT3_IN:
+ Val = (int) SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
+ break;
+ default:
+ Val = (int) SkI2cRcvByte(IoC, 1);
+ break;
+ }
+
+ SkI2cStop(IoC);
+ return(Val);
+}
+#endif /* SK_DIAG */
+
+/*
+ * read a sensors value (LM80 specific)
+ *
+ * This function reads a sensors value from the I2c sensor chip LM80. The
+ * sensor is defined by its index into the sensors database in the struct
+ * pAC points to.
+ *
+ * Returns 1 if the read is completed
+ * 0 if the read must be continued (I2c Bus still allocated)
+ */
+int SkLm80ReadSensor(
+SK_AC *pAC, /* Adapter Context */
+SK_IOC IoC, /* IoContext needed in level 1 and 2 */
+SK_SENSOR *pSen) /* Sensor to be read */
+{
+ SK_I32 Value;
+
+ switch(pSen->SenState) {
+ case SK_SEN_IDLE:
+ /* Send address to ADDR register */
+ SK_I2C_CTL(IoC,I2C_READ,pSen->SenDev,pSen->SenReg,0);
+
+ pSen->SenState = SK_SEN_VALUE ;
+ BREAK_OR_WAIT(pAC, IoC, I2C_READ) ;
+ case SK_SEN_VALUE:
+ /* Read value from data register */
+ SK_IN32(IoC,B2_I2C_DATA, ((SK_U32 *)&Value));
+ Value &= 0xff; /* only least significant byte is valid */
+
+ /* Do NOT check the Value against the thresholds */
+ /* Checking is done in the calling instance */
+
+ if (pSen->SenType == SK_SEN_VOLT) {
+ /* Voltage sensor */
+ pSen->SenValue = Value * SK_LM80_VT_LSB;
+ pSen->SenState = SK_SEN_IDLE ;
+ return(1);
+ }
+
+ if (pSen->SenType == SK_SEN_FAN) {
+ if (Value != 0 && Value != 0xff) {
+ /* Fan speed counter */
+ pSen->SenValue = SK_LM80_FAN_FAKTOR/Value;
+ }
+ else {
+ /* Indicate Fan error */
+ pSen->SenValue = 0;
+ }
+ pSen->SenState = SK_SEN_IDLE ;
+ return(1);
+ }
+
+ /* First: correct the value: it might be negative */
+ if ((Value & 0x80) != 0) {
+ /* Value is negative */
+ Value = Value - 256;
+ }
+
+ /* We have a temperature sensor and need to get the signed
+ * extension. For now we get the extension from the last
+ * reading, so in the normal case we won't see flickering
+ * temperatures.
+ */
+ pSen->SenValue = (Value * SK_LM80_TEMP_LSB) +
+ (pSen->SenValue % SK_LM80_TEMP_LSB);
+
+ /* Send address to ADDR register */
+ SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, LM80_TEMP_CTRL, 0);
+
+ pSen->SenState = SK_SEN_VALEXT ;
+ BREAK_OR_WAIT(pAC, IoC, I2C_READ) ;
+ case SK_SEN_VALEXT:
+ /* Read value from data register */
+ SK_IN32(IoC,B2_I2C_DATA,((SK_U32 *)&Value));
+ Value &= LM80_TEMP_LSB_9; /* only bit 7 is valid */
+
+ /* cut the LSB bit */
+ pSen->SenValue = ((pSen->SenValue / SK_LM80_TEMP_LSB) *
+ SK_LM80_TEMP_LSB) ;
+
+ if (pSen->SenValue < 0) {
+ /* Value negative: The bit value must be subtracted */
+ pSen->SenValue -= ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
+ } else {
+ /* Value positive: The bit value must be added */
+ pSen->SenValue += ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
+ }
+
+ pSen->SenState = SK_SEN_IDLE ;
+ return(1);
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007,
+ SKERR_I2C_E007MSG) ;
+ return(1);
+ }
+
+ /* Not completed */
+ return(0) ;
+}
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skqueue.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.14 $
+ * Date: $Date: 1998/10/15 15:11:35 $
+ * Purpose: Management of an event queue.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skqueue.c,v $
+ * Revision 1.14 1998/10/15 15:11:35 gklug
+ * fix: ID_sccs to SysKonnectFileId
+ *
+ * Revision 1.13 1998/09/08 08:47:52 gklug
+ * add: init level handling
+ *
+ * Revision 1.12 1998/09/08 07:43:20 gklug
+ * fix: Sirq Event function name
+ *
+ * Revision 1.11 1998/09/08 05:54:34 gklug
+ * chg: define SK_CSUM is replaced by SK_USE_CSUM
+ *
+ * Revision 1.10 1998/09/03 14:14:49 gklug
+ * add: CSUM and HWAC Eventclass and function.
+ *
+ * Revision 1.9 1998/08/19 09:50:50 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.8 1998/08/17 13:43:11 gklug
+ * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ * Revision 1.7 1998/08/14 07:09:11 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.6 1998/08/11 12:13:14 gklug
+ * add: return code feature of Event service routines
+ * add: correct Error log calls
+ *
+ * Revision 1.5 1998/08/07 12:53:45 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.4 1998/08/07 09:20:48 gklug
+ * adapt functions to C coding conventions.
+ *
+ * Revision 1.3 1998/08/05 11:29:32 gklug
+ * rmv: Timer event entry. Timer will queue event directly
+ *
+ * Revision 1.2 1998/07/31 11:22:40 gklug
+ * Initial version
+ *
+ * Revision 1.1 1998/07/30 15:14:01 gklug
+ * Initial version. Adapted from SMT
+ *
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ Event queue and dispatcher
+*/
+static const char SysKonnectFileId[] =
+ "$Header: /usr56/projects/ge/schedule/skqueue.c,v 1.14 1998/10/15 15:11:35 gklug Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/skqueue.h" /* Queue Definitions */
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+ Event queue management.
+
+ General Description:
+
+ */
+intro()
+{}
+#endif
+
+#define PRINTF(a,b,c)
+
+/*
+ * init event queue management
+ *
+ * Must be called during init level 0.
+ */
+void SkEventInit(
+SK_AC *pAC, /* Adapter context */
+SK_IOC Ioc, /* IO context */
+int Level) /* Init level */
+{
+ switch (Level) {
+ case SK_INIT_DATA:
+ pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue ;
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * add event to queue
+ */
+void SkEventQueue(
+SK_AC *pAC, /* Adapters context */
+SK_U32 Class, /* Event Class */
+SK_U32 Event, /* Event to be queued */
+SK_EVPARA Para) /* Event parameter */
+{
+ pAC->Event.EvPut->Class = Class ;
+ pAC->Event.EvPut->Event = Event ;
+ pAC->Event.EvPut->Para = Para ;
+ if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
+ pAC->Event.EvPut = pAC->Event.EvQueue ;
+
+ if (pAC->Event.EvPut == pAC->Event.EvGet) {
+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG) ;
+ }
+}
+
+/*
+ * event dispatcher
+ * while event queue is not empty
+ * get event from queue
+ * send command to state machine
+ * end
+ * return error reported by individual Event function
+ * 0 if no error occured.
+ */
+int SkEventDispatcher(
+SK_AC *pAC, /* Adapters Context */
+SK_IOC Ioc) /* Io context */
+{
+ SK_EVENTELEM *pEv ; /* pointer into queue */
+ SK_U32 Class ;
+ int Rtv ;
+
+ pEv = pAC->Event.EvGet ;
+ PRINTF("dispatch get %x put %x\n",pEv,pAC->Event.ev_put) ;
+ while (pEv != pAC->Event.EvPut) {
+ PRINTF("dispatch Class %d Event %d\n",pEv->Class,pEv->Event) ;
+ switch(Class = pEv->Class) {
+ case SKGE_DRV : /* Driver Event */
+ Rtv = SkDrvEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+ case SKGE_RLMT : /* RLMT Event */
+ Rtv = SkRlmtEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+ case SKGE_I2C : /* I2C Event */
+ Rtv = SkI2cEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+ case SKGE_PNMI :
+ Rtv = SkPnmiEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+ case SKGE_HWAC :
+ Rtv = SkGeSirqEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+#ifdef SK_USE_CSUM
+ case SKGE_CSUM :
+ Rtv = SkCsEvent(pAC,Ioc,pEv->Event,pEv->Para);
+ break ;
+#endif /* SK_USE_CSUM */
+ default :
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002,
+ SKERR_Q_E002MSG) ;
+ Rtv = 0;
+ }
+
+ if (Rtv != 0) {
+ return(Rtv) ;
+ }
+
+ if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT])
+ pEv = pAC->Event.EvQueue ;
+
+ /* Renew get: it is used in queue_events to detect overruns */
+ pAC->Event.EvGet = pEv;
+ }
+
+ return(0) ;
+}
+
+/* End of file */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skrlmt.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.48 $
+ * Date: $Date: 1999/10/04 14:01:17 $
+ * Purpose: Manage links on SK-NET Adapters, esp. redundant ones.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skrlmt.c,v $
+ * Revision 1.48 1999/10/04 14:01:17 rassmann
+ * Corrected reaction to reception of BPDU frames.
+ * Added parameter descriptions to "For Readme" section skrlmt.txt.
+ * Clarified usage of lookahead result *pForRlmt.
+ * Requested driver to present RLMT packets as soon as poosible.
+ *
+ * Revision 1.47 1999/07/20 12:53:36 rassmann
+ * Fixed documentation errors for lookahead macros.
+ *
+ * Revision 1.46 1999/05/28 13:29:16 rassmann
+ * Replaced C++-style comment.
+ *
+ * Revision 1.45 1999/05/28 13:28:08 rassmann
+ * Corrected syntax error (xxx).
+ *
+ * Revision 1.44 1999/05/28 11:15:54 rassmann
+ * Changed behaviour to reflect Design Spec v1.2.
+ * Controlling Link LED(s).
+ * Introduced RLMT Packet Version field in RLMT Packet.
+ * Newstyle lookahead macros (checking meta-information before looking at
+ * the packet).
+ *
+ * Revision 1.43 1999/01/28 13:12:43 rassmann
+ * Corrected Lookahead (bug introduced in previous Rev.).
+ *
+ * Revision 1.42 1999/01/28 12:50:41 rassmann
+ * Not using broadcast time stamps in CheckLinkState mode.
+ *
+ * Revision 1.41 1999/01/27 14:13:02 rassmann
+ * Monitoring broadcast traffic.
+ * Switching more reliably and not too early if switch is
+ * configured for spanning tree.
+ *
+ * Revision 1.40 1999/01/22 13:17:30 rassmann
+ * Informing PNMI of NET_UP.
+ * Clearing RLMT multicast addresses before first setting them.
+ * Reporting segmentation earlier, setting a "quiet time"
+ * after a report.
+ *
+ * Revision 1.39 1998/12/10 15:29:53 rassmann
+ * Corrected SuspectStatus in SkRlmtBuildCheckChain().
+ * Corrected CHECK_SEG mode.
+ *
+ * Revision 1.38 1998/12/08 13:11:23 rassmann
+ * Stopping SegTimer at RlmtStop.
+ *
+ * Revision 1.37 1998/12/07 16:51:42 rassmann
+ * Corrected comments.
+ *
+ * Revision 1.36 1998/12/04 10:58:56 rassmann
+ * Setting next pointer to NULL when receiving.
+ *
+ * Revision 1.35 1998/12/03 16:12:42 rassmann
+ * Ignoring/correcting illegal PrefPort values.
+ *
+ * Revision 1.34 1998/12/01 11:45:35 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.33 1998/12/01 10:29:32 rassmann
+ * Starting standby ports before getting the net up.
+ * Checking if a port is started when the link comes up.
+ *
+ * Revision 1.32 1998/11/30 16:19:50 rassmann
+ * New default for PortNoRx.
+ *
+ * Revision 1.31 1998/11/27 19:17:13 rassmann
+ * Corrected handling of LINK_DOWN coming shortly after LINK_UP.
+ *
+ * Revision 1.30 1998/11/24 12:37:31 rassmann
+ * Implemented segmentation check.
+ *
+ * Revision 1.29 1998/11/18 13:04:32 rassmann
+ * Secured PortUpTimer event.
+ * Waiting longer before starting standby port(s).
+ *
+ * Revision 1.28 1998/11/17 13:43:04 rassmann
+ * Handling (logical) tx failure.
+ * Sending packet on logical address after PORT_SWITCH.
+ *
+ * Revision 1.27 1998/11/13 17:09:50 rassmann
+ * Secured some events against being called in wrong state.
+ *
+ * Revision 1.26 1998/11/13 16:56:54 rassmann
+ * Added macro version of SkRlmtLookaheadPacket.
+ *
+ * Revision 1.25 1998/11/06 18:06:04 rassmann
+ * Corrected timing when RLMT checks fail.
+ * Clearing tx counter earlier in periodical checks.
+ *
+ * Revision 1.24 1998/11/05 10:37:27 rassmann
+ * Checking destination address in Lookahead.
+ *
+ * Revision 1.23 1998/11/03 13:53:49 rassmann
+ * RLMT should switch now (at least in mode 3).
+ *
+ * Revision 1.22 1998/10/29 14:34:49 rassmann
+ * Clearing SK_RLMT struct at startup.
+ * Initializing PortsUp during SK_RLMT_START.
+ *
+ * Revision 1.21 1998/10/28 11:30:17 rassmann
+ * Default mode is now SK_RLMT_CHECK_LOC_LINK.
+ *
+ * Revision 1.20 1998/10/26 16:02:03 rassmann
+ * Ignoring LINK_DOWN for links that are down.
+ *
+ * Revision 1.19 1998/10/22 15:54:01 rassmann
+ * Corrected EtherLen.
+ * Starting Link Check when second port comes up.
+ *
+ * Revision 1.18 1998/10/22 11:39:50 rassmann
+ * Corrected signed/unsigned mismatches.
+ * Corrected receive list handling and address recognition.
+ *
+ * Revision 1.17 1998/10/19 17:01:20 rassmann
+ * More detailed checking of received packets.
+ *
+ * Revision 1.16 1998/10/15 15:16:34 rassmann
+ * Finished Spanning Tree checking.
+ * Checked with lint.
+ *
+ * Revision 1.15 1998/09/24 19:16:07 rassmann
+ * Code cleanup.
+ * Introduced Timer for PORT_DOWN due to no RX.
+ *
+ * Revision 1.14 1998/09/18 20:27:14 rassmann
+ * Added address override.
+ *
+ * Revision 1.13 1998/09/16 11:31:48 rassmann
+ * Including skdrv1st.h again. :(
+ *
+ * Revision 1.12 1998/09/16 11:09:50 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.11 1998/09/15 12:32:03 rassmann
+ * Syntax correction.
+ *
+ * Revision 1.10 1998/09/15 11:28:49 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.9 1998/09/14 17:07:37 rassmann
+ * Added code for port checking via LAN.
+ * Changed Mbuf definition.
+ *
+ * Revision 1.8 1998/09/07 11:14:14 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.7 1998/09/07 09:06:07 rassmann
+ * Syntax corrections.
+ *
+ * Revision 1.6 1998/09/04 19:41:33 rassmann
+ * Syntax corrections.
+ * Started entering code for checking local links.
+ *
+ * Revision 1.5 1998/09/04 12:14:27 rassmann
+ * Interface cleanup.
+ *
+ * Revision 1.4 1998/09/02 16:55:28 rassmann
+ * Updated to reflect new DRV/HWAC/RLMT interface.
+ *
+ * Revision 1.3 1998/08/27 14:29:03 rassmann
+ * Code cleanup.
+ *
+ * Revision 1.2 1998/08/27 14:26:24 rassmann
+ * Updated interface.
+ *
+ * Revision 1.1 1998/08/21 08:26:49 rassmann
+ * First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This module contains code for Link ManagemenT (LMT) of SK-NET Adapters.
+ * It is mainly intended for adapters with more than one link.
+ * For such adapters, this module realizes Redundant Link ManagemenT (RLMT).
+ *
+ * Include File Hierarchy:
+ *
+ * "skdrv1st.h"
+ * "skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#ifndef lint
+static const char SysKonnectFileId[] =
+ "@(#) $Id: skrlmt.c,v 1.48 1999/10/04 14:01:17 rassmann Exp $ (C) SysKonnect.";
+#endif /* !defined(lint) */
+
+#define __SKRLMT_C
+
+#ifdef __cplusplus
+xxxx /* not supported yet - force error */
+extern "C" {
+#endif /* cplusplus */
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+#ifndef SK_HWAC_LINK_LED
+#define SK_HWAC_LINK_LED(a,b,c,d)
+#endif /* !defined(SK_HWAC_LINK_LED) */
+
+#ifndef DEBUG
+#define RLMT_STATIC static
+#else /* DEBUG */
+#define RLMT_STATIC
+
+#ifndef SK_LITTLE_ENDIAN
+/* First 32 bits */
+#define OFFS_LO32 1
+/* Second 32 bits */
+#define OFFS_HI32 0
+#else /* SK_LITTLE_ENDIAN */
+/* First 32 bits */
+#define OFFS_LO32 0
+/* Second 32 bits */
+#define OFFS_HI32 1
+#endif /* SK_LITTLE_ENDIAN */
+
+#endif /* DEBUG */
+
+/* ----- Private timeout values ----- */
+
+#define SK_RLMT_MIN_TO_VAL 125000 /* 1/8 sec. */
+#define SK_RLMT_DEF_TO_VAL 1000000 /* 1 sec. */
+#define SK_RLMT_PORTDOWN_TIM_VAL 900000 /* another 0.9 sec. */
+#define SK_RLMT_PORTSTART_TIM_VAL 100000 /* 0.1 sec. */
+#define SK_RLMT_PORTUP_TIM_VAL 2500000 /* 2.5 sec. */
+#define SK_RLMT_SEG_TO_VAL 900000000 /* 15 min. */
+
+/*
+ * Amount that a time stamp must be later to be recognized as "substantially
+ * later". This is about 1/128 sec.
+ */
+
+#define SK_RLMT_BC_DELTA ((SK_TICKS_PER_SEC >> 7) + 1)
+
+/* ----- Private RLMT defaults ----- */
+
+#define SK_RLMT_DEF_PREF_PORT 0 /* "Lower" port. */
+#define SK_RLMT_DEF_MODE SK_RLMT_CHECK_LINK /* Default RLMT Mode. */
+
+/* ----- Private RLMT checking states ----- */
+
+#define SK_RLMT_RCS_SEG 1 /* RLMT Check State: check seg. */
+#define SK_RLMT_RCS_START_SEG 2 /* RLMT Check State: start check seg. */
+#define SK_RLMT_RCS_SEND_SEG 4 /* RLMT Check State: send BPDU packet */
+#define SK_RLMT_RCS_REPORT_SEG 8 /* RLMT Check State: report seg. */
+
+/* ----- Private PORT checking states ----- */
+
+#define SK_RLMT_PCS_TX 1 /* Port Check State: check tx. */
+#define SK_RLMT_PCS_RX 2 /* Port Check State: check rx. */
+
+/* ----- Private PORT events ----- */
+
+/* Note: Update simulation when changing these. */
+
+#define SK_RLMT_PORTSTART_TIM 1100 /* Port start timeout. */
+#define SK_RLMT_PORTUP_TIM 1101 /* Port can now go up. */
+#define SK_RLMT_PORTDOWN_RX_TIM 1102 /* Port did not receive once ... */
+#define SK_RLMT_PORTDOWN 1103 /* Port went down. */
+#define SK_RLMT_PORTDOWN_TX_TIM 1104 /* Partner did not receive ... */
+
+/* ----- Private RLMT events ----- */
+
+/* Note: Update simulation when changing these. */
+
+#define SK_RLMT_TIM 2100 /* RLMT timeout. */
+#define SK_RLMT_SEG_TIM 2101 /* RLMT segmentation check timeout. */
+
+#define TO_SHORTEN(tim) ((tim) / 2)
+
+/* Error numbers and messages. */
+
+#define SKERR_RLMT_E001 (SK_ERRBASE_RLMT + 0)
+#define SKERR_RLMT_E001_MSG "No Packet."
+#define SKERR_RLMT_E002 (SKERR_RLMT_E001 + 1)
+#define SKERR_RLMT_E002_MSG "Short Packet."
+#define SKERR_RLMT_E003 (SKERR_RLMT_E002 + 1)
+#define SKERR_RLMT_E003_MSG "Unknown RLMT event."
+#define SKERR_RLMT_E004 (SKERR_RLMT_E003 + 1)
+#define SKERR_RLMT_E004_MSG "PortsUp incorrect."
+#define SKERR_RLMT_E005 (SKERR_RLMT_E004 + 1)
+#define SKERR_RLMT_E005_MSG \
+ "Net seems to be segmented (different root bridges are reported on the ports)."
+#define SKERR_RLMT_E006 (SKERR_RLMT_E005 + 1)
+#define SKERR_RLMT_E006_MSG "Duplicate MAC Address detected."
+#define SKERR_RLMT_E007 (SKERR_RLMT_E006 + 1)
+#define SKERR_RLMT_E007_MSG "LinksUp incorrect."
+#define SKERR_RLMT_E008 (SKERR_RLMT_E007 + 1)
+#define SKERR_RLMT_E008_MSG "Port not started but link came up."
+#define SKERR_RLMT_E009 (SKERR_RLMT_E008 + 1)
+#define SKERR_RLMT_E009_MSG "Corrected illegal setting of Preferred Port."
+#define SKERR_RLMT_E010 (SKERR_RLMT_E009 + 1)
+#define SKERR_RLMT_E010_MSG "Ignored illegal Preferred Port."
+
+/* LLC field values. */
+
+#define LLC_COMMAND_RESPONSE_BIT 1
+#define LLC_TEST_COMMAND 0xE3
+#define LLC_UI 0x03
+
+/* RLMT Packet fields. */
+
+#define SK_RLMT_DSAP 0
+#define SK_RLMT_SSAP 0
+#define SK_RLMT_CTRL (LLC_TEST_COMMAND)
+#define SK_RLMT_INDICATOR0 0x53 /* S */
+#define SK_RLMT_INDICATOR1 0x4B /* K */
+#define SK_RLMT_INDICATOR2 0x2D /* - */
+#define SK_RLMT_INDICATOR3 0x52 /* R */
+#define SK_RLMT_INDICATOR4 0x4C /* L */
+#define SK_RLMT_INDICATOR5 0x4D /* M */
+#define SK_RLMT_INDICATOR6 0x54 /* T */
+#define SK_RLMT_PACKET_VERSION 0
+
+/* RLMT SPT Flag values. */
+
+#define SK_RLMT_SPT_FLAG_CHANGE 0x01
+#define SK_RLMT_SPT_FLAG_CHANGE_ACK 0x80
+
+/* RLMT SPT Packet fields. */
+
+#define SK_RLMT_SPT_DSAP 0x42
+#define SK_RLMT_SPT_SSAP 0x42
+#define SK_RLMT_SPT_CTRL (LLC_UI)
+#define SK_RLMT_SPT_PROTOCOL_ID0 0x00
+#define SK_RLMT_SPT_PROTOCOL_ID1 0x00
+#define SK_RLMT_SPT_PROTOCOL_VERSION_ID 0x00
+#define SK_RLMT_SPT_BPDU_TYPE 0x00
+#define SK_RLMT_SPT_FLAGS 0x00 /* ?? */
+#define SK_RLMT_SPT_ROOT_ID0 0xFF /* Lowest possible priority. */
+#define SK_RLMT_SPT_ROOT_ID1 0xFF /* Lowest possible priority. */
+
+/* Remaining 6 bytes will be the current port address. */
+
+#define SK_RLMT_SPT_ROOT_PATH_COST0 0x00
+#define SK_RLMT_SPT_ROOT_PATH_COST1 0x00
+#define SK_RLMT_SPT_ROOT_PATH_COST2 0x00
+#define SK_RLMT_SPT_ROOT_PATH_COST3 0x00
+#define SK_RLMT_SPT_BRIDGE_ID0 0xFF /* Lowest possible priority. */
+#define SK_RLMT_SPT_BRIDGE_ID1 0xFF /* Lowest possible priority. */
+
+/* Remaining 6 bytes will be the current port address. */
+
+#define SK_RLMT_SPT_PORT_ID0 0xFF /* Lowest possible priority. */
+#define SK_RLMT_SPT_PORT_ID1 0xFF /* Lowest possible priority. */
+#define SK_RLMT_SPT_MSG_AGE0 0x00
+#define SK_RLMT_SPT_MSG_AGE1 0x00
+#define SK_RLMT_SPT_MAX_AGE0 0x00
+#define SK_RLMT_SPT_MAX_AGE1 0xFF
+#define SK_RLMT_SPT_HELLO_TIME0 0x00
+#define SK_RLMT_SPT_HELLO_TIME1 0xFF
+#define SK_RLMT_SPT_FWD_DELAY0 0x00
+#define SK_RLMT_SPT_FWD_DELAY1 0x40
+
+/* Size defines. */
+
+#define SK_RLMT_MIN_PACKET_SIZE 34
+#define SK_RLMT_MAX_PACKET_SIZE (SK_RLMT_MAX_TX_BUF_SIZE)
+#define SK_PACKET_DATA_LEN (SK_RLMT_MAX_PACKET_SIZE - \
+ SK_RLMT_MIN_PACKET_SIZE)
+
+/* ----- RLMT packet types ----- */
+
+#define SK_PACKET_ANNOUNCE 1 /* Port announcement. */
+#define SK_PACKET_ALIVE 2 /* Alive packet to port. */
+#define SK_PACKET_ADDR_CHANGED 3 /* Port address changed. */
+#define SK_PACKET_CHECK_TX 4 /* Check your tx line. */
+
+#ifdef SK_LITTLE_ENDIAN
+#define SK_U16_TO_NETWORK_ORDER(Val,Addr) { \
+ SK_U8 *_Addr = (SK_U8*)(Addr); \
+ SK_U16 _Val = (SK_U16)(Val); \
+ *_Addr++ = (SK_U8)(_Val >> 8); \
+ *_Addr = (SK_U8)(_Val & 0xFF); \
+}
+#endif /* SK_LITTLE_ENDIAN */
+
+#ifdef SK_BIG_ENDIAN
+#define SK_U16_TO_NETWORK_ORDER(Val,Addr) (*(SK_U16*)(Addr) = (SK_U16)(Val))
+#endif /* SK_BIG_ENDIAN */
+
+#define AUTONEG_FAILED SK_FALSE
+#define AUTONEG_SUCCESS SK_TRUE
+
+
+/* typedefs *******************************************************************/
+
+/* RLMT packet. Length: SK_RLMT_MAX_PACKET_SIZE (60) bytes. */
+
+typedef struct s_RlmtPacket {
+ SK_U8 DstAddr[SK_MAC_ADDR_LEN];
+ SK_U8 SrcAddr[SK_MAC_ADDR_LEN];
+ SK_U8 TypeLen[2];
+ SK_U8 DSap;
+ SK_U8 SSap;
+ SK_U8 Ctrl;
+ SK_U8 Indicator[7];
+ SK_U8 RlmtPacketType[2];
+ SK_U8 Align1[2];
+ SK_U8 Random[4]; /* Random value of requesting(!) station. */
+ SK_U8 RlmtPacketVersion[2]; /* RLMT Packet version */
+ SK_U8 Data[SK_PACKET_DATA_LEN];
+} SK_RLMT_PACKET;
+
+typedef struct s_SpTreeRlmtPacket {
+ SK_U8 DstAddr[SK_MAC_ADDR_LEN];
+ SK_U8 SrcAddr[SK_MAC_ADDR_LEN];
+ SK_U8 TypeLen[2];
+ SK_U8 DSap;
+ SK_U8 SSap;
+ SK_U8 Ctrl;
+ SK_U8 ProtocolId[2];
+ SK_U8 ProtocolVersionId;
+ SK_U8 BpduType;
+ SK_U8 Flags;
+ SK_U8 RootId[8];
+ SK_U8 RootPathCost[4];
+ SK_U8 BridgeId[8];
+ SK_U8 PortId[2];
+ SK_U8 MessageAge[2];
+ SK_U8 MaxAge[2];
+ SK_U8 HelloTime[2];
+ SK_U8 ForwardDelay[2];
+} SK_SPTREE_PACKET;
+
+/* global variables ***********************************************************/
+
+SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}};
+SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}};
+SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}};
+
+/* local variables ************************************************************/
+
+/* None. */
+
+/* functions ******************************************************************/
+
+RLMT_STATIC void SkRlmtCheckSwitch(
+ SK_AC *pAC,
+ SK_IOC IoC);
+RLMT_STATIC void SkRlmtCheckSeg(
+ SK_AC *pAC,
+ SK_IOC IoC);
+
+/******************************************************************************
+ *
+ * SkRlmtInit - initialize data, set state to init
+ *
+ * Description:
+ *
+ * SK_INIT_DATA
+ * ============
+ *
+ * This routine initializes all RLMT-related variables to a known state.
+ * The initial state is SK_RLMT_RS_INIT.
+ * All ports are initialized to SK_RLMT_PS_INIT.
+ *
+ *
+ * SK_INIT_IO
+ * ==========
+ *
+ * Nothing.
+ *
+ *
+ * SK_INIT_RUN
+ * ===========
+ *
+ * Determine the adapter's random value.
+ * Set the hw registers, the "logical adapter address", the
+ * RLMT multicast address, and eventually the BPDU multicast address.
+ *
+ * Context:
+ * init, pageable
+ *
+ * Returns:
+ * Nothing.
+ */
+void SkRlmtInit(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+int Level) /* initialization level */
+{
+ SK_U32 i, j;
+ SK_U64 Random;
+ SK_EVPARA Para;
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_INIT,
+ ("RLMT Init level %d.\n", Level))
+
+ switch (Level) {
+ case SK_INIT_DATA: /* Initialize data structures. */
+ SK_MEMSET((char *)&pAC->Rlmt, 0, sizeof(SK_RLMT));
+
+ for (i = 0; i < SK_MAX_MACS; i++) {
+ pAC->Rlmt.Port[i].PortState = SK_RLMT_PS_INIT;
+ pAC->Rlmt.Port[i].LinkDown = SK_TRUE;
+ pAC->Rlmt.Port[i].PortDown = SK_TRUE;
+ pAC->Rlmt.Port[i].PortStarted = SK_FALSE;
+ pAC->Rlmt.Port[i].PortNoRx = SK_FALSE;
+ pAC->Rlmt.Port[i].RootIdSet = SK_FALSE;
+ }
+
+ pAC->Rlmt.RlmtState = SK_RLMT_RS_INIT;
+ pAC->Rlmt.RootIdSet = SK_FALSE;
+ pAC->Rlmt.MacPreferred = 0xFFFFFFFF; /* Automatic. */
+ pAC->Rlmt.PrefPort = SK_RLMT_DEF_PREF_PORT;
+ pAC->Rlmt.MacActive = pAC->Rlmt.PrefPort; /* Just assuming. */
+ pAC->Rlmt.RlmtMode = SK_RLMT_DEF_MODE;
+ pAC->Rlmt.TimeoutValue = SK_RLMT_DEF_TO_VAL;
+ break;
+
+ case SK_INIT_IO: /* GIMacsFound first available here. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_INIT,
+ ("RLMT: %d MACs were detected.\n",
+ pAC->GIni.GIMacsFound))
+
+ /* Initialize HW registers? */
+
+ if (pAC->GIni.GIMacsFound < 2) {
+ Para.Para32[0] = SK_RLMT_CHECK_LINK;
+ (void)SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, Para);
+ }
+ break;
+
+ case SK_INIT_RUN:
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ Random = SkOsGetTime(pAC);
+ *(SK_U32*)&pAC->Rlmt.Port[i].Random = *(SK_U32*)&Random;
+
+ for (j = 0; j < 4; j++) {
+ pAC->Rlmt.Port[i].Random[j] ^= pAC->Addr.Port[i
+ ].CurrentMacAddress.a[SK_MAC_ADDR_LEN -
+ 1 - j];
+ }
+
+ (void)SkAddrMcClear(
+ pAC,
+ IoC,
+ i,
+ SK_ADDR_PERMANENT | SK_MC_SW_ONLY);
+
+ /* Add RLMT MC address. */
+
+ (void)SkAddrMcAdd(
+ pAC,
+ IoC,
+ i,
+ &SkRlmtMcAddr,
+ SK_ADDR_PERMANENT);
+
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) {
+ /* Add BPDU MC address. */
+
+ (void)SkAddrMcAdd(
+ pAC,
+ IoC,
+ i,
+ &BridgeMcAddr,
+ SK_ADDR_PERMANENT);
+ }
+
+ (void)SkAddrMcUpdate(pAC, IoC, i);
+ }
+ break;
+
+ default: /* error */
+ break;
+ }
+
+ return;
+
+} /* SkRlmtInit */
+
+
+/******************************************************************************
+ *
+ * SkRlmtBuildCheckChain - build the check chain
+ *
+ * Description:
+ * This routine builds the local check chain:
+ * - Each port that is up checks the next port.
+ * - The last port that is up checks the first port that is up.
+ *
+ * Notes:
+ * - Currently only local ports are considered when building the chain.
+ * - Currently the SuspectState is just reset;
+ * it would be better to save it ...
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing
+ */
+RLMT_STATIC void SkRlmtBuildCheckChain(
+SK_AC *pAC) /* adapter context */
+{
+ SK_U32 i;
+ SK_U32 NumMacsUp;
+ SK_U32 FirstMacUp=0;
+ SK_U32 PrevMacUp=0;
+
+ if (!(pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK)) {
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pAC->Rlmt.Port[i].PortsChecked = 0;
+ }
+ return; /* Nothing to build. */
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SkRlmtBuildCheckChain.\n"))
+
+ NumMacsUp = 0;
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pAC->Rlmt.Port[i].PortsChecked = 0;
+ pAC->Rlmt.Port[i].PortsSuspect = 0;
+ pAC->Rlmt.Port[i].CheckingState &=
+ ~(SK_RLMT_PCS_RX | SK_RLMT_PCS_TX);
+
+ /*
+ * If more than two links are detected we should consider
+ * checking at least two other ports:
+ * 1. the next port that is not LinkDown and
+ * 2. the next port that is not PortDown.
+ */
+
+ if (!pAC->Rlmt.Port[i].LinkDown) {
+ if (NumMacsUp == 0) {
+ FirstMacUp = i;
+ }
+ else {
+ pAC->Rlmt.Port[PrevMacUp].PortCheck[
+ pAC->Rlmt.Port[
+ PrevMacUp].PortsChecked].CheckAddr =
+ pAC->Addr.Port[i].CurrentMacAddress;
+ pAC->Rlmt.Port[PrevMacUp].PortCheck[
+ pAC->Rlmt.Port[
+ PrevMacUp].PortsChecked].SuspectTx =
+ SK_FALSE;
+ pAC->Rlmt.Port[PrevMacUp].PortsChecked++;
+ }
+ PrevMacUp = i;
+ NumMacsUp++;
+ }
+ }
+
+ if (NumMacsUp > 1) {
+ pAC->Rlmt.Port[PrevMacUp].PortCheck[pAC->Rlmt.Port[
+ PrevMacUp].PortsChecked].CheckAddr =
+ pAC->Addr.Port[FirstMacUp].CurrentMacAddress;
+ pAC->Rlmt.Port[PrevMacUp].PortCheck[pAC->Rlmt.Port[
+ PrevMacUp].PortsChecked].SuspectTx = SK_FALSE;
+ pAC->Rlmt.Port[PrevMacUp].PortsChecked++;
+ }
+
+#ifdef DEBUG
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Port %d checks %d other ports: %2X.\n",
+ i,
+ pAC->Rlmt.Port[i].PortsChecked,
+ pAC->Rlmt.Port[i].PortCheck[0].CheckAddr.a[5]))
+ }
+#endif /* DEBUG */
+
+ return;
+} /* SkRlmtBuildCheckChain */
+
+#ifdef SK_RLMT_SLOW_LOOKAHEAD
+
+/******************************************************************************
+ *
+ * SkRlmtLookaheadPacket - examine received packet shortly, count s-th
+ *
+ * Description:
+ * This routine examines each received packet fast and short and
+ * increments some counters.
+ * The received packet has to be stored virtually contiguous.
+ * This function does the following:
+ * - Increment some counters.
+ * - Ensure length is sufficient.
+ * - Ensure that destination address is physical port address,
+ * RLMT multicast, or BPDU multicast address.
+ *
+ * Notes:
+ * This function is fully reentrant while the fast path is not blocked.
+ *
+ * Context:
+ * isr/dpr, not pageable
+ *
+ * Returns:
+ * SK_FALSE packet for upper layers
+ * SK_TRUE packet for RLMT
+ */
+SK_BOOL SkRlmtLookaheadPacket(
+SK_AC *pAC, /* adapter context */
+SK_U32 PortIdx, /* receiving port */
+SK_U8 *pLaPacket, /* received packet's data */
+unsigned PacketLength, /* received packet's length */ /* Necessary? */
+unsigned LaLength) /* lookahead length */
+{
+ int i;
+ SK_BOOL IsBc; /* Broadcast address? */
+ int RxDest; /* Receive destination? */
+ int Offset; /* Offset of data to present to LOOKAHEAD. */
+ int NumBytes; /* #Bytes to present to LOOKAHEAD. */
+ SK_RLMT_PACKET *pRPacket;
+ SK_ADDR_PORT *pAPort;
+
+#ifdef DEBUG
+ PacketLength = PacketLength;
+#endif /* DEBUG */
+
+ pRPacket = (SK_RLMT_PACKET*)pLaPacket;
+ pAPort = &pAC->Addr.Port[PortIdx];
+
+#ifdef DEBUG
+ if (pLaPacket == NULL) {
+
+ /* Create error log entry. */
+
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E001,
+ SKERR_RLMT_E001_MSG);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtLookaheadPacket: NULL pointer.\n"))
+
+ return (SK_FALSE);
+ }
+#endif /* DEBUG */
+
+ /* Drivers should get IsBc from the descriptor. */
+
+ IsBc = SK_TRUE;
+ for (i = 0; IsBc && i < SK_MAC_ADDR_LEN; i++) {
+ IsBc = IsBc && (pLaPacket[i] == 0xFF);
+ }
+
+ SK_RLMT_PRE_LOOKAHEAD(
+ pAC,
+ PortIdx,
+ PacketLength,
+ IsBc,
+ &Offset,
+ &NumBytes)
+
+ if (NumBytes == 0) {
+ return (SK_FALSE);
+ }
+
+ SK_RLMT_LOOKAHEAD(
+ pAC,
+ PortIdx,
+ &pLaPacket[Offset],
+ IsBc,
+ pLaPacket[0] & 1, /* Drivers: Get info from descriptor. */
+ &RxDest)
+
+ if (RxDest & SK_RLMT_RX_RLMT) {
+ return (SK_TRUE);
+ }
+
+ return (SK_FALSE);
+} /* SkRlmtLookaheadPacket */
+
+#endif /* SK_RLMT_SLOW_LOOKAHEAD */
+
+/******************************************************************************
+ *
+ * SkRlmtBuildPacket - build an RLMT packet
+ *
+ * Description:
+ * This routine sets up an RLMT packet.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * NULL or pointer to RLMT mbuf
+ */
+RLMT_STATIC SK_MBUF *SkRlmtBuildPacket(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx, /* sending port */
+SK_U16 PacketType, /* RLMT packet type */
+SK_MAC_ADDR *SrcAddr, /* source address */
+SK_MAC_ADDR *DestAddr) /* destination address */
+{
+ int i;
+ SK_U16 Length;
+ SK_MBUF *pMb;
+ SK_RLMT_PACKET *pPacket;
+
+ if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) !=
+ NULL) {
+ pPacket = (SK_RLMT_PACKET*)pMb->pData;
+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
+ pPacket->DstAddr[i] = DestAddr->a[i];
+ pPacket->SrcAddr[i] = SrcAddr->a[i];
+ }
+ pPacket->DSap = SK_RLMT_DSAP;
+ pPacket->SSap = SK_RLMT_SSAP;
+ pPacket->Ctrl = SK_RLMT_CTRL;
+ pPacket->Indicator[0] = SK_RLMT_INDICATOR0;
+ pPacket->Indicator[1] = SK_RLMT_INDICATOR1;
+ pPacket->Indicator[2] = SK_RLMT_INDICATOR2;
+ pPacket->Indicator[3] = SK_RLMT_INDICATOR3;
+ pPacket->Indicator[4] = SK_RLMT_INDICATOR4;
+ pPacket->Indicator[5] = SK_RLMT_INDICATOR5;
+ pPacket->Indicator[6] = SK_RLMT_INDICATOR6;
+
+ SK_U16_TO_NETWORK_ORDER(
+ PacketType,
+ &pPacket->RlmtPacketType[0]);
+
+ for (i = 0; i < 4; i++) {
+ pPacket->Random[i] = pAC->Rlmt.Port[PortIdx].Random[i];
+ }
+
+ SK_U16_TO_NETWORK_ORDER(
+ SK_RLMT_PACKET_VERSION,
+ &pPacket->RlmtPacketVersion[0]);
+
+ for (i = 0; i < SK_PACKET_DATA_LEN; i++) {
+ pPacket->Data[i] = 0x00;
+ }
+
+ Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */
+ pMb->Length = Length;
+ pMb->PortIdx = PortIdx;
+ Length -= 14;
+ SK_U16_TO_NETWORK_ORDER(Length, &pPacket->TypeLen[0]);
+
+ if (PacketType == SK_PACKET_ALIVE) {
+ pAC->Rlmt.Port[PortIdx].TxHelloCts++;
+ }
+ }
+
+ return (pMb);
+} /* SkRlmtBuildPacket */
+
+
+/******************************************************************************
+ *
+ * SkRlmtBuildSpanningTreePacket - build spanning tree check packet
+ *
+ * Description:
+ * This routine sets up a BPDU packet for spanning tree check.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * NULL or pointer to RLMT mbuf
+ */
+RLMT_STATIC SK_MBUF *SkRlmtBuildSpanningTreePacket(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx) /* sending port */
+{
+ unsigned i;
+ SK_U16 Length;
+ SK_MBUF *pMb;
+ SK_SPTREE_PACKET *pSPacket;
+
+ if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) !=
+ NULL) {
+ pSPacket = (SK_SPTREE_PACKET*)pMb->pData;
+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
+ pSPacket->DstAddr[i] = BridgeMcAddr.a[i];
+ pSPacket->SrcAddr[i] =
+ pAC->Addr.Port[PortIdx].CurrentMacAddress.a[i];
+ }
+ pSPacket->DSap = SK_RLMT_SPT_DSAP;
+ pSPacket->SSap = SK_RLMT_SPT_SSAP;
+ pSPacket->Ctrl = SK_RLMT_SPT_CTRL;
+
+ pSPacket->ProtocolId[0] = SK_RLMT_SPT_PROTOCOL_ID0;
+ pSPacket->ProtocolId[1] = SK_RLMT_SPT_PROTOCOL_ID1;
+ pSPacket->ProtocolVersionId = SK_RLMT_SPT_PROTOCOL_VERSION_ID;
+ pSPacket->BpduType = SK_RLMT_SPT_BPDU_TYPE;
+ pSPacket->Flags = SK_RLMT_SPT_FLAGS;
+ pSPacket->RootId[0] = SK_RLMT_SPT_ROOT_ID0;
+ pSPacket->RootId[1] = SK_RLMT_SPT_ROOT_ID1;
+ pSPacket->RootPathCost[0] = SK_RLMT_SPT_ROOT_PATH_COST0;
+ pSPacket->RootPathCost[1] = SK_RLMT_SPT_ROOT_PATH_COST1;
+ pSPacket->RootPathCost[2] = SK_RLMT_SPT_ROOT_PATH_COST2;
+ pSPacket->RootPathCost[3] = SK_RLMT_SPT_ROOT_PATH_COST3;
+ pSPacket->BridgeId[0] = SK_RLMT_SPT_BRIDGE_ID0;
+ pSPacket->BridgeId[1] = SK_RLMT_SPT_BRIDGE_ID1;
+
+ /*
+ * Use virtual address as bridge ID and filter these packets
+ * on receive.
+ */
+
+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
+ pSPacket->BridgeId[i + 2] = pSPacket->RootId[i + 2] =
+ pAC->Addr.CurrentMacAddress.a[i];
+ }
+ pSPacket->PortId[0] = SK_RLMT_SPT_PORT_ID0;
+ pSPacket->PortId[1] = SK_RLMT_SPT_PORT_ID1;
+ pSPacket->MessageAge[0] = SK_RLMT_SPT_MSG_AGE0;
+ pSPacket->MessageAge[1] = SK_RLMT_SPT_MSG_AGE1;
+ pSPacket->MaxAge[0] = SK_RLMT_SPT_MAX_AGE0;
+ pSPacket->MaxAge[1] = SK_RLMT_SPT_MAX_AGE1;
+ pSPacket->HelloTime[0] = SK_RLMT_SPT_HELLO_TIME0;
+ pSPacket->HelloTime[1] = SK_RLMT_SPT_HELLO_TIME1;
+ pSPacket->ForwardDelay[0] = SK_RLMT_SPT_FWD_DELAY0;
+ pSPacket->ForwardDelay[1] = SK_RLMT_SPT_FWD_DELAY1;
+
+ Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */
+ pMb->Length = Length;
+ pMb->PortIdx = PortIdx;
+ Length -= 14;
+ SK_U16_TO_NETWORK_ORDER(Length, &pSPacket->TypeLen[0]);
+
+ pAC->Rlmt.Port[PortIdx].TxSpHelloReqCts++;
+ }
+
+ return (pMb);
+} /* SkRlmtBuildSpanningTreePacket */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSend - build and send check packets
+ *
+ * Description:
+ * Depending on the RLMT state and the checking state, several packets
+ * are sent through the indicated port.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing.
+ */
+RLMT_STATIC void SkRlmtSend(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx)
+{
+ unsigned j;
+ SK_EVPARA Para;
+ SK_RLMT_PORT *pRPort;
+
+ pRPort = &pAC->Rlmt.Port[PortIdx];
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) {
+ if (pRPort->CheckingState &
+ (SK_RLMT_PCS_TX | SK_RLMT_PCS_RX)) {
+
+ /*
+ * Port is suspicious. Send the RLMT packet to the
+ * RLMT multicast address.
+ */
+
+ if ((Para.pParaPtr = SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ PortIdx,
+ SK_PACKET_ALIVE,
+ &pAC->Addr.Port[PortIdx].CurrentMacAddress,
+ &SkRlmtMcAddr)) != NULL) {
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ }
+ else {
+ /*
+ * Send a directed RLMT packet to all ports that are
+ * checked by the indicated port.
+ */
+
+ for (j = 0; j < pRPort->PortsChecked; j++) {
+ if ((Para.pParaPtr =
+ SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ PortIdx,
+ SK_PACKET_ALIVE,
+ &pAC->Addr.Port[PortIdx].CurrentMacAddress,
+ &pRPort->PortCheck[j].CheckAddr)
+ ) != NULL) {
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ }
+ }
+ }
+
+ if ((pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) &&
+ (pAC->Rlmt.CheckingState & SK_RLMT_RCS_SEND_SEG)) {
+
+ /*
+ * Send a BPDU packet to make a connected switch tell us
+ * the correct root bridge.
+ */
+
+ if ((Para.pParaPtr =
+ SkRlmtBuildSpanningTreePacket(
+ pAC,
+ IoC,
+ PortIdx)
+ ) != NULL) {
+
+ pAC->Rlmt.CheckingState &= ~SK_RLMT_RCS_SEND_SEG;
+ pRPort->RootIdSet = SK_FALSE;
+
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_TX,
+ ("SkRlmtSend: BPDU Packet on Port %u.\n",
+ PortIdx))
+ }
+ }
+
+ return;
+
+} /* SkRlmtSend */
+
+
+/******************************************************************************
+ *
+ * SkRlmtPortReceives - check if port is (going) down and bring it up
+ *
+ * Description:
+ * This routine checks if a port who received a non-BPDU packet
+ * needs to go up or needs to be stopped going down.
+ *
+* Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing.
+ */
+RLMT_STATIC void SkRlmtPortReceives(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx) /* port to check */
+{
+ SK_RLMT_PORT *pRPort;
+ SK_EVPARA Para;
+
+ pRPort = &pAC->Rlmt.Port[PortIdx];
+ pRPort->PortNoRx = SK_FALSE;
+
+ if ((pRPort->PortState == SK_RLMT_PS_DOWN) &&
+ !(pRPort->CheckingState & SK_RLMT_PCS_TX)) {
+
+ /*
+ * Port is marked down (rx), but received a non-BPDU packet.
+ * Bring it up.
+ */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Received on PortDown.\n"))
+
+ pRPort->PortState = SK_RLMT_PS_GOING_UP;
+ pRPort->GuTimeStamp = SkOsGetTime(pAC);
+ Para.Para32[0] = PortIdx;
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pRPort->UpTimer,
+ SK_RLMT_PORTUP_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTUP_TIM,
+ Para);
+ SkRlmtCheckSwitch(pAC, IoC);
+ }
+ else if (pRPort->CheckingState & SK_RLMT_PCS_RX) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Stop bringing port down.\n"))
+ SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
+ SkRlmtCheckSwitch(pAC, IoC);
+ }
+
+ pRPort->CheckingState &= ~SK_RLMT_PCS_RX;
+ return;
+} /* SkRlmtPortReceives */
+
+
+/******************************************************************************
+ *
+ * SkRlmtPacketReceive - receive a packet for closer examination
+ *
+ * Description:
+ * This routine examines a packet more closely than SkRlmtLookahead*().
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing.
+ */
+RLMT_STATIC void SkRlmtPacketReceive(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_MBUF *pMb) /* received packet */
+{
+#ifdef xDEBUG
+ extern void DumpData(char *p, int size);
+#endif /* DEBUG */
+ int i;
+ unsigned j;
+ SK_U16 PacketType;
+ SK_U32 PortIdx;
+ SK_ADDR_PORT *pAPort;
+ SK_RLMT_PORT *pRPort;
+ SK_RLMT_PACKET *pRPacket;
+ SK_SPTREE_PACKET *pSPacket;
+ SK_EVPARA Para;
+
+ PortIdx = pMb->PortIdx;
+ pAPort = &pAC->Addr.Port[PortIdx];
+ pRPort = &pAC->Rlmt.Port[PortIdx];
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: PortIdx == %d.\n", PortIdx))
+
+ pRPacket = (SK_RLMT_PACKET*)pMb->pData;
+ pSPacket = (SK_SPTREE_PACKET*)pRPacket;
+
+#ifdef xDEBUG
+ DumpData((char *)pRPacket, 32);
+#endif /* DEBUG */
+
+ if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) != 0) {
+ SkRlmtPortReceives(pAC, IoC, PortIdx);
+ }
+
+ /* Check destination address. */
+
+ if (!SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->DstAddr) &&
+ !SK_ADDR_EQUAL(SkRlmtMcAddr.a, pRPacket->DstAddr) &&
+ !SK_ADDR_EQUAL(BridgeMcAddr.a, pRPacket->DstAddr)) {
+
+ /*
+ * Not sent to current MAC or registered MC address
+ * => Trash it.
+ */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Not for me.\n"))
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ return;
+ }
+ else if (SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->SrcAddr)) {
+
+ /*
+ * Was sent by same port (may happen during port switching
+ * or in case of duplicate MAC addresses).
+ */
+
+ /*
+ * Check for duplicate address here:
+ * If Packet.Random != My.Random => DupAddr.
+ */
+
+ for (i = 3; i >= 0; i--) {
+ if (pRPort->Random[i] !=
+ pRPacket->Random[i]) {
+ break;
+ }
+ }
+
+ /*
+ * CAUTION: Do not check for duplicate MAC
+ * address in RLMT Alive Reply packets.
+ */
+
+ if (i >= 0 && pRPacket->DSap == SK_RLMT_DSAP &&
+ pRPacket->Ctrl == SK_RLMT_CTRL &&
+ pRPacket->SSap == SK_RLMT_SSAP &&
+ pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 &&
+ pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 &&
+ pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 &&
+ pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 &&
+ pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 &&
+ pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
+ pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Duplicate MAC Address.\n"))
+
+ /* Error Log entry. */
+
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_COMM,
+ SKERR_RLMT_E006,
+ SKERR_RLMT_E006_MSG);
+ }
+ else {
+ /* Simply trash it. */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Sent by me.\n"))
+ }
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+
+ return;
+ }
+
+ /* Check SuspectTx entries. */
+
+ if (pRPort->PortsSuspect > 0) {
+ for (j = 0; j < pRPort->PortsChecked; j++) {
+ if (pRPort->PortCheck[j].SuspectTx &&
+ SK_ADDR_EQUAL(
+ pRPacket->SrcAddr,
+ pRPort->PortCheck[j].CheckAddr.a)) {
+ pRPort->PortCheck[j].SuspectTx = SK_FALSE;
+ pRPort->PortsSuspect--;
+ break;
+ }
+ }
+ }
+
+ /* Determine type of packet. */
+
+ if (pRPacket->DSap == SK_RLMT_DSAP &&
+ pRPacket->Ctrl == SK_RLMT_CTRL &&
+ (pRPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SSAP &&
+ pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 &&
+ pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 &&
+ pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 &&
+ pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 &&
+ pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 &&
+ pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
+ pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
+
+ /* It's an RLMT packet. */
+
+ PacketType = (SK_U16)((pRPacket->RlmtPacketType[0] << 8) |
+ pRPacket->RlmtPacketType[1]);
+
+ switch (PacketType) {
+ case SK_PACKET_ANNOUNCE: /* Not yet used. */
+#if 0
+ /* Build the check chain. */
+
+ SkRlmtBuildCheckChain(pAC);
+#endif /* 0 */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Announce.\n"))
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ break;
+
+ case SK_PACKET_ALIVE:
+ if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Alive Reply.\n"))
+
+ /* Alive Reply Packet. */
+
+#if 0
+ pRPort->RlmtAcksPerTimeSlot++;
+#endif /* 0 */
+
+ if (!(pAC->Addr.Port[PortIdx].PromMode &
+ SK_PROM_MODE_LLC) ||
+ SK_ADDR_EQUAL(
+ pRPacket->DstAddr,
+ pAPort->CurrentMacAddress.a)) {
+
+ /* Obviously we could send something. */
+
+ if (pRPort->CheckingState &
+ SK_RLMT_PCS_TX) {
+ pRPort->CheckingState &=
+ ~SK_RLMT_PCS_TX;
+ SkTimerStop(
+ pAC,
+ IoC,
+ &pRPort->DownTxTimer);
+ }
+
+ if ((pRPort->PortState ==
+ SK_RLMT_PS_DOWN) &&
+ !(pRPort->CheckingState &
+ SK_RLMT_PCS_RX)) {
+ pRPort->PortState =
+ SK_RLMT_PS_GOING_UP;
+ pRPort->GuTimeStamp =
+ SkOsGetTime(pAC);
+
+ SkTimerStop(
+ pAC,
+ IoC,
+ &pRPort->DownTxTimer);
+
+ Para.Para32[0] = PortIdx;
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pRPort->UpTimer,
+ SK_RLMT_PORTUP_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTUP_TIM,
+ Para);
+ }
+ }
+
+ /* Mark sending port as alive? */
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ }
+ else { /* Alive Request Packet. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Alive Request.\n"))
+
+ pRPort->RxHelloCts++;
+#if 0
+ pRPort->RlmtChksPerTimeSlot++;
+#endif /* 0 */
+
+ /* Answer. */
+
+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
+ pRPacket->DstAddr[i] =
+ pRPacket->SrcAddr[i];
+ pRPacket->SrcAddr[i] = pAC->Addr.Port[
+ PortIdx].CurrentMacAddress.a[i];
+ }
+ pRPacket->SSap |= LLC_COMMAND_RESPONSE_BIT;
+
+ Para.pParaPtr = pMb;
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ break;
+
+ case SK_PACKET_CHECK_TX:
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Check your tx line.\n"))
+
+ /*
+ * A port checking us requests us to check our tx line.
+ */
+
+ pRPort->CheckingState |= SK_RLMT_PCS_TX;
+
+ /* Start PortDownTx timer. */
+
+ Para.Para32[0] = PortIdx;
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pRPort->DownTxTimer,
+ SK_RLMT_PORTDOWN_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTDOWN_TX_TIM,
+ Para);
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+
+ if ((Para.pParaPtr = SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ PortIdx,
+ SK_PACKET_ALIVE,
+ &pAC->Addr.Port[PortIdx].CurrentMacAddress,
+ &SkRlmtMcAddr)) != NULL) {
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ break;
+
+ case SK_PACKET_ADDR_CHANGED:
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Address Change.\n"))
+
+ /* Build the check chain. */
+
+ SkRlmtBuildCheckChain(pAC);
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ break;
+
+ default:
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Unknown RLMT packet.\n"))
+
+ /* RA;:;: ??? */
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ }
+ }
+ else if (pSPacket->DSap == SK_RLMT_SPT_DSAP &&
+ pSPacket->Ctrl == SK_RLMT_SPT_CTRL &&
+ (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) ==
+ SK_RLMT_SPT_SSAP) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: BPDU Packet.\n"))
+
+ /* Spanning Tree packet. */
+
+ pRPort->RxSpHelloCts++;
+
+ if (!SK_ADDR_EQUAL(
+ &pSPacket->RootId[2],
+ &pAC->Addr.CurrentMacAddress.a[0])) {
+
+ /*
+ * Check segmentation if a new root bridge is set and
+ * the segmentation check is not currently running.
+ */
+
+ if (!SK_ADDR_EQUAL(
+ &pSPacket->RootId[2],
+ &pRPort->Root.Id[2]) &&
+ (pAC->Rlmt.LinksUp > 1) &&
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) &&
+ !(pAC->Rlmt.CheckingState & SK_RLMT_RCS_SEG)) {
+ pAC->Rlmt.CheckingState |=
+ SK_RLMT_RCS_START_SEG |
+ SK_RLMT_RCS_SEND_SEG;
+ }
+
+ /* Store tree view of this port. */
+
+ for (i = 0; i < 8; i++) {
+ pRPort->Root.Id[i] = pSPacket->RootId[i];
+ }
+ pRPort->RootIdSet = SK_TRUE;
+ }
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+
+ if (pAC->Rlmt.CheckingState & SK_RLMT_RCS_REPORT_SEG) {
+ SkRlmtCheckSeg(pAC, IoC);
+ }
+ }
+ else {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_RX,
+ ("SkRlmtPacketReceive: Unknown Packet Type.\n"))
+
+ /* Unknown packet. */
+
+ SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
+ }
+ return;
+} /* SkRlmtPacketReceive */
+
+
+/******************************************************************************
+ *
+ * SkRlmtCheckPort - check if a port works
+ *
+ * Description:
+ * This routine checks if a port whose link is up received something
+ * and if it seems to transmit successfully.
+ *
+ * # PortState: PsInit, PsLinkDown, PsDown, PsGoingUp, PsUp
+ * # PortCheckingState (Bitfield): ChkTx, ChkRx, ChkSeg
+ * # RlmtCheckingState (Bitfield): ChkSeg, StartChkSeg, ReportSeg
+ *
+ * if (Rx - RxBpdu == 0) { # No rx.
+ * if (state == PsUp) {
+ * PortCheckingState |= ChkRx
+ * }
+ * if (ModeCheckSeg && (Timeout ==
+ * TO_SHORTEN(RLMT_DEFAULT_TIMEOUT))) {
+ * RlmtCheckingState |= ChkSeg)
+ * PortCheckingState |= ChkSeg
+ * }
+ * NewTimeout = TO_SHORTEN(Timeout)
+ * if (NewTimeout < RLMT_MIN_TIMEOUT) {
+ * NewTimeout = RLMT_MIN_TIMEOUT
+ * PortState = PsDown
+ * ...
+ * }
+ * }
+ * else { # something was received
+ * # Set counter to 0 at LinkDown?
+ * # No - rx may be reported after LinkDown ???
+ * PortCheckingState &= ~ChkRx
+ * NewTimeout = RLMT_DEFAULT_TIMEOUT
+ * if (RxAck == 0) {
+ * possible reasons:
+ * is my tx line bad? --
+ * send RLMT multicast and report
+ * back internally? (only possible
+ * between ports on same adapter)
+ * }
+ * if (RxChk == 0) {
+ * possible reasons:
+ * - tx line of port set to check me
+ * maybe bad
+ * - no other port/adapter available or set
+ * to check me
+ * - adapter checking me has a longer
+ * timeout
+ * ??? anything that can be done here?
+ * }
+ * }
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * New timeout value.
+ */
+RLMT_STATIC SK_U32 SkRlmtCheckPort(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx) /* port to check */
+{
+ unsigned i;
+ SK_U32 NewTimeout;
+ SK_RLMT_PORT *pRPort;
+ SK_EVPARA Para;
+
+ pRPort = &pAC->Rlmt.Port[PortIdx];
+
+ if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n",
+ PortIdx,
+ pRPort->PacketsPerTimeSlot))
+
+ /*
+ * Check segmentation if there was no receive at least twice
+ * in a row (PortNoRx is already set) and the segmentation
+ * check is not currently running.
+ */
+
+ if (pRPort->PortNoRx && (pAC->Rlmt.LinksUp > 1) &&
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) &&
+ !(pAC->Rlmt.CheckingState & SK_RLMT_RCS_SEG)) {
+ pAC->Rlmt.CheckingState |=
+ SK_RLMT_RCS_START_SEG | SK_RLMT_RCS_SEND_SEG;
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n",
+ pRPort->PortsSuspect,
+ pRPort->CheckingState & SK_RLMT_PCS_RX))
+
+ if (pRPort->PortState != SK_RLMT_PS_DOWN) {
+ NewTimeout = TO_SHORTEN(pAC->Rlmt.TimeoutValue);
+ if (NewTimeout < SK_RLMT_MIN_TO_VAL) {
+ NewTimeout = SK_RLMT_MIN_TO_VAL;
+ }
+
+ if (!(pRPort->CheckingState & SK_RLMT_PCS_RX)) {
+ Para.Para32[0] = PortIdx;
+ pRPort->CheckingState |= SK_RLMT_PCS_RX;
+
+ /*
+ * What shall we do if the port checked
+ * by this one receives our request
+ * frames? What's bad - our rx line
+ * or his tx line?
+ */
+
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pRPort->DownRxTimer,
+ SK_RLMT_PORTDOWN_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTDOWN_RX_TIM,
+ Para);
+
+ for (i = 0; i < pRPort->PortsChecked; i++) {
+ if (pRPort->PortCheck[i].SuspectTx) {
+ continue;
+ }
+ pRPort->PortCheck[i].SuspectTx = SK_TRUE;
+ pRPort->PortsSuspect++;
+ if ((Para.pParaPtr =
+ SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ PortIdx,
+ SK_PACKET_CHECK_TX,
+ &pAC->Addr.Port[PortIdx].CurrentMacAddress,
+ &pRPort->PortCheck[i].CheckAddr)
+ ) != NULL) {
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ }
+ }
+ }
+ else { /* PortDown -- or all partners suspect. */
+ NewTimeout = SK_RLMT_DEF_TO_VAL;
+ }
+ pRPort->PortNoRx = SK_TRUE;
+ }
+ else { /* A non-BPDU packet was received. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n",
+ PortIdx,
+ pRPort->PacketsPerTimeSlot -
+ pRPort->BpduPacketsPerTimeSlot,
+ pRPort->PacketsPerTimeSlot))
+
+ SkRlmtPortReceives(pAC, IoC, PortIdx);
+ NewTimeout = SK_RLMT_DEF_TO_VAL;
+ }
+
+ return (NewTimeout);
+} /* SkRlmtCheckPort */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSelectBcRx - select new active port, criteria 1 (CLP)
+ *
+ * Description:
+ * This routine selects the port that received a broadcast frame
+ * substantially later than all other ports.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * SK_BOOL
+ */
+RLMT_STATIC SK_BOOL SkRlmtSelectBcRx(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 A, /* active port */
+SK_U32 P, /* preferred port */
+SK_U32 *N) /* new active port */
+{
+ SK_U64 BcTimeStamp;
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ BcTimeStamp = 0; /* Not totally necessary, but feeling better. */
+ PortFound = SK_FALSE;
+
+ /* Select port with the latest TimeStamp. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("TimeStamp Port %d: %.08x%.08x.\n",
+ i,
+ *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
+ *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
+ if (!pAC->Rlmt.Port[i].PortDown &&
+ !pAC->Rlmt.Port[i].PortNoRx) {
+ if (!PortFound ||
+ pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) {
+ BcTimeStamp = pAC->Rlmt.Port[i].BcTimeStamp;
+ *N = i;
+ PortFound = SK_TRUE;
+ }
+ }
+ }
+
+ if (PortFound) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Port %d received the last broadcast.\n", *N))
+
+ /* Look if another port's time stamp is similar. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (i == *N) {
+ continue;
+ }
+ if (!pAC->Rlmt.Port[i].PortDown &&
+ !pAC->Rlmt.Port[i].PortNoRx &&
+ (pAC->Rlmt.Port[i].BcTimeStamp >
+ BcTimeStamp - SK_RLMT_BC_DELTA ||
+ pAC->Rlmt.Port[i].BcTimeStamp
+ + SK_RLMT_BC_DELTA > BcTimeStamp)) {
+ PortFound = SK_FALSE;
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Port %d received a broadcast %s.\n",
+ i,
+ "at a similar time"))
+ break;
+ }
+ }
+ }
+
+#ifdef DEBUG
+ if (PortFound) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_CHECK_SWITCH found Port %d receiving %s.\n",
+ *N,
+ "the substantially latest broadcast"))
+ }
+#endif /* DEBUG */
+
+ return (PortFound);
+} /* SkRlmtSelectBcRx */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSelectNotSuspect - select new active port, criteria 2 (CLP)
+ *
+ * Description:
+ * This routine selects a good port (it is PortUp && !SuspectRx).
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * SK_BOOL
+ */
+RLMT_STATIC SK_BOOL SkRlmtSelectNotSuspect(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 A, /* active port */
+SK_U32 P, /* preferred port */
+SK_U32 *N) /* new active port */
+{
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ PortFound = SK_FALSE;
+
+ /* Select first port that is PortUp && !SuspectRx. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Rlmt.Port[i].PortDown &&
+ !(pAC->Rlmt.Port[i].CheckingState & SK_RLMT_PCS_RX)) {
+ *N = i;
+ if (!pAC->Rlmt.Port[A].PortDown &&
+ !(pAC->Rlmt.Port[A].CheckingState &
+ SK_RLMT_PCS_RX)) {
+ *N = A;
+ }
+ if (!pAC->Rlmt.Port[P].PortDown &&
+ !(pAC->Rlmt.Port[P].CheckingState &
+ SK_RLMT_PCS_RX)) {
+ *N = P;
+ }
+ PortFound = SK_TRUE;
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_CHECK_SWITCH found Port %d up and not check RX.\n",
+ *N))
+ break;
+ }
+ }
+
+ return (PortFound);
+} /* SkRlmtSelectNotSuspect */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSelectUp - select new active port, criteria 3, 4 (CLP)
+ *
+ * Description:
+ * This routine selects a port that is up.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * SK_BOOL
+ */
+RLMT_STATIC SK_BOOL SkRlmtSelectUp(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 A, /* active port */
+SK_U32 P, /* preferred port */
+SK_U32 *N, /* new active port */
+SK_BOOL AutoNegDone) /* successfully auto-negotiated? */
+{
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ PortFound = SK_FALSE;
+
+ /* Select first port that is PortUp. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_UP &&
+ pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) {
+ *N = i;
+ if (pAC->Rlmt.Port[A].PortState == SK_RLMT_PS_UP &&
+ pAC->GIni.GP[A].PAutoNegFail != AutoNegDone) {
+ *N = A;
+ }
+ if (pAC->Rlmt.Port[P].PortState == SK_RLMT_PS_UP &&
+ pAC->GIni.GP[P].PAutoNegFail != AutoNegDone) {
+ *N = P;
+ }
+ PortFound = SK_TRUE;
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_CHECK_SWITCH found Port %d up.\n",
+ *N))
+ break;
+ }
+ }
+
+ return (PortFound);
+} /* SkRlmtSelectUp */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSelectGoingUp - select new active port, criteria 5, 6 (CLP)
+ *
+ * Description:
+ * This routine selects the port that is going up for the longest time.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * SK_BOOL
+ */
+RLMT_STATIC SK_BOOL SkRlmtSelectGoingUp(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 A, /* active port */
+SK_U32 P, /* preferred port */
+SK_U32 *N, /* new active port */
+SK_BOOL AutoNegDone) /* successfully auto-negotiated? */
+{
+ SK_U64 GuTimeStamp=0;
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ PortFound = SK_FALSE;
+
+ /* Select port that is PortGoingUp for the longest time. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP &&
+ pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) {
+ GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp;
+ *N = i;
+ PortFound = SK_TRUE;
+ break;
+ }
+ }
+
+ if (!PortFound) {
+ return (SK_FALSE);
+ }
+
+ for (i = *N + 1; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP &&
+ pAC->Rlmt.Port[i].GuTimeStamp < GuTimeStamp &&
+ pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) {
+
+ GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp;
+ *N = i;
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_CHECK_SWITCH found Port %d going up.\n", *N))
+
+ return (SK_TRUE);
+} /* SkRlmtSelectGoingUp */
+
+
+/******************************************************************************
+ *
+ * SkRlmtSelectDown - select new active port, criteria 7, 8 (CLP)
+ *
+ * Description:
+ * This routine selects a port that is down.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * SK_BOOL
+ */
+RLMT_STATIC SK_BOOL SkRlmtSelectDown(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 A, /* active port */
+SK_U32 P, /* preferred port */
+SK_U32 *N, /* new active port */
+SK_BOOL AutoNegDone) /* successfully auto-negotiated? */
+{
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ PortFound = SK_FALSE;
+
+ /* Select first port that is PortDown. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_DOWN &&
+ pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) {
+ *N = i;
+ if (pAC->Rlmt.Port[A].PortState == SK_RLMT_PS_DOWN &&
+ pAC->GIni.GP[A].PAutoNegFail != AutoNegDone) {
+ *N = A;
+ }
+ if (pAC->Rlmt.Port[P].PortState == SK_RLMT_PS_DOWN &&
+ pAC->GIni.GP[P].PAutoNegFail != AutoNegDone) {
+ *N = P;
+ }
+ PortFound = SK_TRUE;
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_CHECK_SWITCH found Port %d down.\n",
+ *N))
+ break;
+ }
+ }
+
+ return (PortFound);
+} /* SkRlmtSelectDown */
+
+
+/******************************************************************************
+ *
+ * SkRlmtCheckSwitch - select new active port and switch to it
+ *
+ * Description:
+ * This routine decides which port should be the active one and queues
+ * port switching if necessary.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing.
+ */
+RLMT_STATIC void SkRlmtCheckSwitch(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* I/O context */
+{
+ SK_EVPARA Para;
+ SK_U32 A;
+ SK_U32 P;
+ SK_U32 i;
+ SK_BOOL PortFound;
+
+ if (pAC->Rlmt.RlmtState == SK_RLMT_RS_INIT) {
+ return;
+ }
+
+ A = pAC->Rlmt.MacActive; /* Index of active port. */
+ P = pAC->Rlmt.PrefPort; /* Index of preferred port. */
+ PortFound = SK_FALSE;
+
+ if (pAC->Rlmt.LinksUp == 0) {
+
+ /*
+ * Last link went down - shut down the net.
+ */
+
+ pAC->Rlmt.RlmtState = SK_RLMT_RS_NET_DOWN;
+ Para.Para32[0] = SK_RLMT_NET_DOWN_TEMP;
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_NET_DOWN,
+ Para);
+
+ return;
+ }
+ else if (pAC->Rlmt.LinksUp == 1 &&
+ pAC->Rlmt.RlmtState == SK_RLMT_RS_NET_DOWN) {
+
+ /* First link came up - get the net up. */
+
+ pAC->Rlmt.RlmtState = SK_RLMT_RS_NET_UP;
+
+ /*
+ * If pAC->Rlmt.MacActive != Para.Para32[0],
+ * the DRV switches to the port that came up.
+ */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Rlmt.Port[i].LinkDown) {
+ if (!pAC->Rlmt.Port[A].LinkDown) {
+ i = A;
+ }
+ if (!pAC->Rlmt.Port[P].LinkDown) {
+ i = P;
+ }
+ PortFound = SK_TRUE;
+ break;
+ }
+ }
+
+ if (PortFound) {
+ Para.Para32[0] = pAC->Rlmt.MacActive;
+ Para.Para32[1] = i;
+ SkEventQueue(
+ pAC,
+ SKGE_PNMI,
+ SK_PNMI_EVT_RLMT_PORT_SWITCH,
+ Para);
+
+ pAC->Rlmt.MacActive = i;
+ Para.Para32[0] = i;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
+
+ if ((Para.pParaPtr = SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ i,
+ SK_PACKET_ANNOUNCE,
+ &pAC->Addr.CurrentMacAddress,
+ &SkRlmtMcAddr)
+ ) != NULL) {
+
+ /*
+ * Send packet to RLMT multicast address
+ * to force switches to learn the new
+ * location of the address.
+ */
+
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ }
+ else {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E007,
+ SKERR_RLMT_E007_MSG);
+ }
+
+ return;
+ }
+ else {
+ Para.Para32[0] = A;
+
+ /*
+ * Preselection:
+ * If RLMT Mode != CheckLinkState
+ * select port that received a broadcast frame
+ * substantially later than all other ports
+ * else select first port that is not SuspectRx
+ * else select first port that is PortUp
+ * else select port that is PortGoingUp for the longest time
+ * else select first port that is PortDown
+ * else stop.
+ *
+ * For the preselected port:
+ * If ActivePort is equal in quality, select ActivePort.
+ *
+ * If PrefPort is equal in quality, select PrefPort.
+ *
+ * If MacActive != SelectedPort,
+ * If old ActivePort is LinkDown,
+ * SwitchHard
+ * else
+ * SwitchSoft
+ */
+
+ if (pAC->Rlmt.RlmtMode != SK_RLMT_CHECK_LINK) {
+ if (!PortFound) {
+ PortFound = SkRlmtSelectBcRx(pAC, IoC,
+ A, P, &Para.Para32[1]);
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectNotSuspect(pAC, IoC,
+ A, P, &Para.Para32[1]);
+ }
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectUp(pAC, IoC,
+ A, P, &Para.Para32[1], AUTONEG_SUCCESS);
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectUp(pAC, IoC,
+ A, P, &Para.Para32[1], AUTONEG_FAILED);
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectGoingUp(pAC, IoC,
+ A, P, &Para.Para32[1], AUTONEG_SUCCESS);
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectGoingUp(pAC, IoC,
+ A, P,&Para.Para32[1], AUTONEG_FAILED);
+ }
+
+ if (pAC->Rlmt.RlmtMode != SK_RLMT_CHECK_LINK) {
+ if (!PortFound) {
+ PortFound = SkRlmtSelectDown(pAC, IoC,
+ A, P,&Para.Para32[1], AUTONEG_SUCCESS);
+ }
+
+ if (!PortFound) {
+ PortFound = SkRlmtSelectDown(pAC, IoC,
+ A, P,&Para.Para32[1], AUTONEG_FAILED);
+ }
+ }
+
+ if (PortFound) {
+ if (Para.Para32[1] != A) {
+ pAC->Rlmt.MacActive = Para.Para32[1];
+ SK_HWAC_LINK_LED(
+ pAC,
+ IoC,
+ Para.Para32[1],
+ SK_LED_ACTIVE);
+ if (pAC->Rlmt.Port[A].LinkDown) {
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_SWITCH_HARD,
+ Para);
+ }
+ else {
+ SK_HWAC_LINK_LED(
+ pAC,
+ IoC,
+ Para.Para32[0],
+ SK_LED_STANDBY);
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_SWITCH_SOFT,
+ Para);
+ }
+ SkEventQueue(
+ pAC,
+ SKGE_PNMI,
+ SK_PNMI_EVT_RLMT_PORT_SWITCH,
+ Para);
+ if ((Para.pParaPtr = SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ Para.Para32[1],
+ SK_PACKET_ANNOUNCE,
+ &pAC->Addr.CurrentMacAddress,
+ &SkRlmtMcAddr)
+ ) != NULL) {
+
+ /*
+ * Send "new" packet to RLMT multicast
+ * address to force switches to learn
+ * the new location of the MAC address.
+ */
+
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para);
+ }
+ }
+ }
+ else {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E004,
+ SKERR_RLMT_E004_MSG);
+ }
+ }
+
+ return;
+} /* SkRlmtCheckSwitch */
+
+
+/******************************************************************************
+ *
+ * SkRlmtCheckSeg - Report if segmentation is detected
+ *
+ * Description:
+ * This routine checks if the ports see different root bridges and reports
+ * segmentation in such a case.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing.
+ */
+RLMT_STATIC void SkRlmtCheckSeg(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC) /* I/O context */
+{
+ SK_BOOL Equal;
+ SK_U32 i, j;
+
+ pAC->Rlmt.RootIdSet = SK_FALSE;
+ Equal = SK_TRUE;
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].LinkDown ||
+ !pAC->Rlmt.Port[i].RootIdSet) {
+ continue;
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Root ID %d: %02x %02x %02x %02x %02x %02x %02x %02x.\n",
+ i,
+ pAC->Rlmt.Port[i].Root.Id[0],
+ pAC->Rlmt.Port[i].Root.Id[1],
+ pAC->Rlmt.Port[i].Root.Id[2],
+ pAC->Rlmt.Port[i].Root.Id[3],
+ pAC->Rlmt.Port[i].Root.Id[4],
+ pAC->Rlmt.Port[i].Root.Id[5],
+ pAC->Rlmt.Port[i].Root.Id[6],
+ pAC->Rlmt.Port[i].Root.Id[7]))
+
+ if (!pAC->Rlmt.RootIdSet) {
+ pAC->Rlmt.Root = pAC->Rlmt.Port[i].Root;
+ pAC->Rlmt.RootIdSet = SK_TRUE;
+ continue;
+ }
+
+ for (j = 0; j < 8; j ++) {
+ Equal &= pAC->Rlmt.Port[i].Root.Id[j] ==
+ pAC->Rlmt.Root.Id[j];
+ if (!Equal) {
+ break;
+ }
+ }
+
+ if (!Equal) {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_COMM,
+ SKERR_RLMT_E005,
+ SKERR_RLMT_E005_MSG);
+#ifdef SK_PNMI_EVT_SEGMENTATION
+ SkEventQueue(
+ pAC,
+ SKGE_PNMI,
+ SK_PNMI_EVT_SEGMENTATION,
+ Para);
+#endif /* SK_PNMI_EVT_SEGMENTATION */
+ pAC->Rlmt.CheckingState &= ~SK_RLMT_RCS_REPORT_SEG;
+ break;
+ }
+ }
+} /* SkRlmtCheckSeg */
+
+
+/******************************************************************************
+ *
+ * SkRlmtPortStart - initialize port variables and start port
+ *
+ * Description:
+ * This routine initializes a port's variables and issues a PORT_START
+ * to the HWAC module. This handles retries if the start fails or the
+ * link eventually goes down.
+ *
+ * Context:
+ * runtime, pageable?
+ *
+ * Returns:
+ * Nothing
+ */
+RLMT_STATIC void SkRlmtPortStart(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 PortIdx) /* event code */
+{
+ SK_EVPARA Para;
+
+ pAC->Rlmt.Port[PortIdx].PortState = SK_RLMT_PS_LINK_DOWN;
+ pAC->Rlmt.Port[PortIdx].PortStarted = SK_TRUE;
+ pAC->Rlmt.Port[PortIdx].LinkDown = SK_TRUE;
+ pAC->Rlmt.Port[PortIdx].PortDown = SK_TRUE;
+ pAC->Rlmt.Port[PortIdx].CheckingState = 0;
+ pAC->Rlmt.Port[PortIdx].RootIdSet = SK_FALSE;
+ Para.Para32[0] = PortIdx;
+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+} /* SkRlmtPortStart */
+
+
+/******************************************************************************
+ *
+ * SkRlmtEvent - a PORT- or an RLMT-specific event happened
+ *
+ * Description:
+ * This routine handles PORT- and RLMT-specific events.
+ *
+ * Context:
+ * runtime, pageable?
+ * may be called after SK_INIT_IO
+ *
+ * Returns:
+ * 0
+ */
+int SkRlmtEvent(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* I/O context */
+SK_U32 Event, /* event code */
+SK_EVPARA Para) /* event-specific parameter */
+{
+ SK_U32 i, j;
+ SK_RLMT_PORT *pRPort;
+ SK_EVPARA Para2;
+ SK_MBUF *pMb;
+ SK_MBUF *pNextMb;
+ SK_MAC_ADDR *pOldMacAddr;
+ SK_MAC_ADDR *pNewMacAddr;
+ SK_U32 Timeout;
+ SK_U32 NewTimeout;
+ SK_U32 PrevRlmtMode;
+
+ switch (Event) {
+ case SK_RLMT_PORTSTART_TIM: /* From RLMT via TIME. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event (%d) BEGIN.\n", Para.Para32[0], Event))
+
+ /*
+ * Used to start non-preferred ports if the preferred one
+ * does not come up.
+ * This timeout needs only be set when starting the first
+ * (preferred) port.
+ */
+
+ if (pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
+
+ /* PORT_START failed. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Rlmt.Port[i].PortStarted) {
+ SkRlmtPortStart(pAC, IoC, i);
+ }
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTSTART_TIMEOUT Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_LINK_UP: /* From SIRQ. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_UP Port %d Event (%d) BEGIN.\n",
+ Para.Para32[0], Event))
+
+ pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
+
+ if (!pRPort->PortStarted) {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E008,
+ SKERR_RLMT_E008_MSG);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_UP Event (%d) EMPTY.\n", Event))
+ break;
+ }
+
+ if (!pRPort->LinkDown) {
+ /* RA;:;: Any better solution? */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_UP Event (%d) EMPTY.\n", Event))
+ break;
+ }
+
+ SkTimerStop(pAC, IoC, &pRPort->UpTimer);
+ SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
+ SkTimerStop(pAC, IoC, &pRPort->DownTxTimer);
+
+ /* Do something if timer already fired? */
+
+ pRPort->LinkDown = SK_FALSE;
+ pRPort->PortState = SK_RLMT_PS_GOING_UP;
+ pRPort->GuTimeStamp = SkOsGetTime(pAC);
+ pRPort->BcTimeStamp = 0;
+ if (pAC->Rlmt.LinksUp == 0) {
+ SK_HWAC_LINK_LED(
+ pAC,
+ IoC,
+ Para.Para32[0],
+ SK_LED_ACTIVE);
+ }
+ else {
+ SK_HWAC_LINK_LED(
+ pAC,
+ IoC,
+ Para.Para32[0],
+ SK_LED_STANDBY);
+ }
+ pAC->Rlmt.LinksUp++;
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (!pAC->Rlmt.Port[i].PortStarted) {
+ SkRlmtPortStart(pAC, IoC, i);
+ }
+ }
+
+ SkRlmtCheckSwitch(pAC, IoC);
+
+ if (pAC->Rlmt.LinksUp >= 2) {
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) {
+
+ /* Build the check chain. */
+
+ SkRlmtBuildCheckChain(pAC);
+ }
+ }
+
+ /*
+ * If the first link comes up, start the periodical
+ * RLMT timeout.
+ */
+
+ if (pAC->GIni.GIMacsFound > 1 && pAC->Rlmt.LinksUp == 1 &&
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_OTHERS)) {
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.LocTimer,
+ pAC->Rlmt.TimeoutValue,
+ SKGE_RLMT,
+ SK_RLMT_TIM,
+ Para);
+ }
+
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pRPort->UpTimer,
+ SK_RLMT_PORTUP_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTUP_TIM,
+ Para);
+
+ /*
+ * Later:
+ * if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) &&
+ */
+
+ if ((pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LINK) &&
+ (Para2.pParaPtr = SkRlmtBuildPacket(
+ pAC,
+ IoC,
+ Para.Para32[0],
+ SK_PACKET_ANNOUNCE,
+ &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress,
+ &SkRlmtMcAddr)
+ ) != NULL) {
+
+ /* Send "new" packet to RLMT multicast address. */
+
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
+ }
+
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) {
+ if ((Para2.pParaPtr =
+ SkRlmtBuildSpanningTreePacket(
+ pAC,
+ IoC,
+ Para.Para32[0])
+ ) != NULL) {
+
+ pAC->Rlmt.Port[Para.Para32[0]].RootIdSet =
+ SK_FALSE;
+ pAC->Rlmt.CheckingState |=
+ SK_RLMT_RCS_SEG |
+ SK_RLMT_RCS_REPORT_SEG;
+
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para2);
+
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.SegTimer,
+ SK_RLMT_SEG_TO_VAL,
+ SKGE_RLMT,
+ SK_RLMT_SEG_TIM,
+ Para);
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_UP Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_PORTUP_TIM: /* From RLMT via TIME. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTUP_TIM Port %d Event (%d) BEGIN.\n", Para.Para32[0], Event))
+
+ pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
+
+ if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTUP_TIM Port %d Event (%d) EMPTY.\n",
+ Para.Para32[0],
+ Event))
+ break;
+ }
+
+ pRPort->PortDown = SK_FALSE;
+ pRPort->PortState = SK_RLMT_PS_UP;
+ pAC->Rlmt.PortsUp++;
+
+ if (pAC->Rlmt.RlmtState != SK_RLMT_RS_INIT) {
+ SkRlmtCheckSwitch(pAC, IoC);
+
+ SkEventQueue(
+ pAC,
+ SKGE_PNMI,
+ SK_PNMI_EVT_RLMT_PORT_UP,
+ Para);
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTUP_TIM Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_PORTDOWN: /* From RLMT. */
+ case SK_RLMT_PORTDOWN_RX_TIM: /* From RLMT via TIME. */
+ case SK_RLMT_PORTDOWN_TX_TIM: /* From RLMT via TIME. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n", Para.Para32[0], Event))
+
+ pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
+
+ if (!pRPort->PortStarted ||
+ (Event == SK_RLMT_PORTDOWN_TX_TIM &&
+ !(pRPort->CheckingState & SK_RLMT_PCS_TX))) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
+ break;
+ }
+ /* Stop port's timers. */
+
+ SkTimerStop(pAC, IoC, &pRPort->UpTimer);
+ SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
+ SkTimerStop(pAC, IoC, &pRPort->DownTxTimer);
+
+ if (pRPort->PortState != SK_RLMT_PS_LINK_DOWN) {
+ pRPort->PortState = SK_RLMT_PS_DOWN;
+ }
+
+ if (!pRPort->PortDown) {
+ pAC->Rlmt.PortsUp--;
+ pRPort->PortDown = SK_TRUE;
+
+ SkEventQueue(
+ pAC,
+ SKGE_PNMI,
+ SK_PNMI_EVT_RLMT_PORT_DOWN,
+ Para);
+ }
+
+ pRPort->PacketsPerTimeSlot = 0;
+ pRPort->DataPacketsPerTimeSlot = 0;
+ pRPort->BpduPacketsPerTimeSlot = 0;
+#if 0
+ pRPort->RlmtChksPerTimeSlot = 0;
+ pRPort->RlmtAcksPerTimeSlot = 0;
+#endif /* 0 */
+
+ /*
+ * RA;:;: To be checked:
+ * - actions at RLMT_STOP: We should not switch anymore.
+ */
+
+ if (pAC->Rlmt.RlmtState != SK_RLMT_RS_INIT) {
+ if (Para.Para32[0] == pAC->Rlmt.MacActive) {
+
+ /* Active Port went down. */
+
+ SkRlmtCheckSwitch(pAC, IoC);
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_LINK_DOWN: /* From SIRQ. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_DOWN Port %d Event (%d) BEGIN.\n",
+ Para.Para32[0], Event))
+
+ if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
+ pAC->Rlmt.LinksUp--;
+ pAC->Rlmt.Port[Para.Para32[0]].LinkDown = SK_TRUE;
+ pAC->Rlmt.Port[Para.Para32[0]].PortState =
+ SK_RLMT_PS_LINK_DOWN;
+ SK_HWAC_LINK_LED(
+ pAC,
+ IoC,
+ Para.Para32[0],
+ SK_LED_OFF);
+
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) {
+
+ /* Build the check chain. */
+
+ SkRlmtBuildCheckChain(pAC);
+ }
+
+ /* Ensure that port is marked down. */
+
+ (void)SkRlmtEvent(
+ pAC,
+ IoC,
+ SK_RLMT_PORTDOWN,
+ Para);
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_LINK_DOWN Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_PORT_ADDR: /* From ADDR. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORT_ADDR Port %d Event (%d) BEGIN.\n", Para.Para32[0], Event))
+
+ /* Port's physical MAC address changed. */
+
+ pOldMacAddr =
+ &pAC->Addr.Port[Para.Para32[0]].PreviousMacAddress;
+ pNewMacAddr =
+ &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress;
+
+ /*
+ * NOTE: This is not scalable for solutions where ports are
+ * checked remotely. There, we need to send an RLMT
+ * address change packet - and how do we ensure delivery?
+ */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pRPort = &pAC->Rlmt.Port[i];
+ for (j = 0; j < pRPort->PortsChecked; j++) {
+ if (SK_ADDR_EQUAL(
+ pRPort->PortCheck[j].CheckAddr.a,
+ pOldMacAddr->a)) {
+ pRPort->PortCheck[j].CheckAddr =
+ *pNewMacAddr;
+ }
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PORT_ADDR Event (%d) END.\n", Event))
+ break;
+
+ /* ----- RLMT events ----- */
+
+ case SK_RLMT_START: /* From DRV. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_START Event (%d) BEGIN.\n", Event))
+
+ if (pAC->Rlmt.RlmtState != SK_RLMT_RS_INIT) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_START Event (%d) EMPTY.\n", Event))
+ break;
+ }
+
+ if (pAC->Rlmt.PrefPort >= (SK_U32)pAC->GIni.GIMacsFound) {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E009,
+ SKERR_RLMT_E009_MSG);
+
+ /* Change PrefPort to internal default. */
+
+ Para.Para32[0] = 0xFFFFFFFF;
+ (void)SkRlmtEvent(
+ pAC,
+ IoC,
+ SK_RLMT_PREFPORT_CHANGE,
+ Para);
+ }
+#if 0
+ if (pAC->GIni.GIMacsFound == 1 &&
+ pAC->Rlmt.RlmtMode != SK_RLMT_CHECK_LINK) {
+ Para.Para32[0] = SK_RLMT_CHECK_LINK;
+ (void)SkRlmtEvent(
+ pAC,
+ IoC,
+ SK_RLMT_MODE_CHANGE,
+ Para);
+ }
+#endif /* 0 */
+ pAC->Rlmt.LinksUp = 0;
+ pAC->Rlmt.PortsUp = 0;
+ pAC->Rlmt.CheckingState = 0;
+ pAC->Rlmt.RlmtState = SK_RLMT_RS_NET_DOWN;
+
+ SkRlmtPortStart(pAC, IoC, pAC->Rlmt.PrefPort);
+
+ /* Start Timer (for first port only). */
+
+ Para2.Para32[0] = pAC->Rlmt.PrefPort;
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.Port[pAC->Rlmt.PrefPort].UpTimer,
+ SK_RLMT_PORTSTART_TIM_VAL,
+ SKGE_RLMT,
+ SK_RLMT_PORTSTART_TIM,
+ Para2);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_START Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_STOP: /* From DRV. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STOP Event (%d) BEGIN.\n", Event))
+
+ if (pAC->Rlmt.RlmtState == SK_RLMT_RS_INIT) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STOP Event (%d) EMPTY.\n", Event))
+ break;
+ }
+
+ /* Stop RLMT timers. */
+
+ SkTimerStop(pAC, IoC, &pAC->Rlmt.LocTimer);
+ SkTimerStop(pAC, IoC, &pAC->Rlmt.SegTimer);
+
+ /* Stop Net. */
+
+ pAC->Rlmt.RlmtState = SK_RLMT_RS_INIT;
+ pAC->Rlmt.RootIdSet = SK_FALSE;
+ Para2.Para32[0] = SK_RLMT_NET_DOWN_FINAL;
+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_DOWN, Para2);
+
+ /* Stop ports. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ if (pAC->Rlmt.Port[i].PortState != SK_RLMT_PS_INIT) {
+ SkTimerStop(
+ pAC,
+ IoC,
+ &pAC->Rlmt.Port[i].UpTimer);
+ SkTimerStop(
+ pAC,
+ IoC,
+ &pAC->Rlmt.Port[i].DownRxTimer);
+ SkTimerStop(
+ pAC,
+ IoC,
+ &pAC->Rlmt.Port[i].DownTxTimer);
+
+ pAC->Rlmt.Port[i].PortState = SK_RLMT_PS_INIT;
+ pAC->Rlmt.Port[i].RootIdSet = SK_FALSE;
+ pAC->Rlmt.Port[i].PortStarted = SK_FALSE;
+ Para2.Para32[0] = i;
+ SkEventQueue(
+ pAC,
+ SKGE_HWAC,
+ SK_HWEV_PORT_STOP,
+ Para2);
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STOP Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_TIM: /* From RLMT via TIME. */
+#if 0
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_TIM Event (%d) BEGIN.\n", Event))
+#endif /* 0 */
+
+ if (!(pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_OTHERS) ||
+ pAC->Rlmt.LinksUp == 0) {
+
+ /*
+ * Mode changed or all links down:
+ * No more link checking.
+ */
+
+ break;
+ }
+
+#if 0
+ pAC->Rlmt.SwitchCheckCounter--;
+ if (pAC->Rlmt.SwitchCheckCounter == 0) {
+ pAC->Rlmt.SwitchCheckCounter;
+ }
+#endif /* 0 */
+
+ NewTimeout = SK_RLMT_DEF_TO_VAL;
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pRPort = &pAC->Rlmt.Port[i];
+ if (!pRPort->LinkDown) {
+ Timeout = SkRlmtCheckPort(pAC, IoC, i);
+ if (Timeout < NewTimeout) {
+ NewTimeout = Timeout;
+ }
+
+ /*
+ * This counter should be set to 0 for all
+ * ports before the first frame is sent in the
+ * next loop.
+ */
+
+ pRPort->PacketsPerTimeSlot = 0;
+ pRPort->DataPacketsPerTimeSlot = 0;
+ pRPort->BpduPacketsPerTimeSlot = 0;
+#if 0
+ pRPort->RlmtChksPerTimeSlot = 0;
+ pRPort->RlmtAcksPerTimeSlot = 0;
+#endif /* 0 */
+ }
+ }
+ pAC->Rlmt.TimeoutValue = NewTimeout;
+
+ if (pAC->Rlmt.LinksUp > 1) {
+ /*
+ * If checking remote ports, also send packets if
+ * (LinksUp == 1) &&
+ * this port checks at least one (remote) port.
+ */
+
+ /*
+ * Must be new loop, as SkRlmtCheckPort can request to
+ * check segmentation when e.g. checking the last port.
+ */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pRPort = &pAC->Rlmt.Port[i];
+ if (!pRPort->LinkDown) { /* !PortDown? */
+ SkRlmtSend(pAC, IoC, i);
+ }
+ }
+ }
+
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.LocTimer,
+ pAC->Rlmt.TimeoutValue,
+ SKGE_RLMT,
+ SK_RLMT_TIM,
+ Para);
+
+ if (pAC->Rlmt.LinksUp > 1 &&
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) &&
+ (pAC->Rlmt.CheckingState & SK_RLMT_RCS_START_SEG)) {
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.SegTimer,
+ SK_RLMT_SEG_TO_VAL,
+ SKGE_RLMT,
+ SK_RLMT_SEG_TIM,
+ Para);
+ pAC->Rlmt.CheckingState &=
+ ~SK_RLMT_RCS_START_SEG;
+ pAC->Rlmt.CheckingState |=
+ SK_RLMT_RCS_SEG | SK_RLMT_RCS_REPORT_SEG;
+ }
+
+#if 0
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_TIM Event (%d) END.\n", Event))
+#endif /* 0 */
+ break;
+
+ case SK_RLMT_SEG_TIM:
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_SEG_TIM Event (%d) BEGIN.\n", Event))
+
+#ifdef DEBUG
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ SK_U8 InAddr8[6];
+ SK_U16 *InAddr;
+ SK_ADDR_PORT *pAPort;
+
+ InAddr = (SK_U16 *)&InAddr8[0];
+ pAPort = &pAC->Addr.Port[i];
+ for (j = 0;
+ j < pAPort->NextExactMatchRlmt;
+ j++) {
+
+ /* Get exact match address j from port i. */
+
+ XM_INADDR(IoC, i, XM_EXM(j), InAddr);
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("MC address %d on Port %u: %02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x.\n",
+ j,
+ i,
+ InAddr8[0],
+ InAddr8[1],
+ InAddr8[2],
+ InAddr8[3],
+ InAddr8[4],
+ InAddr8[5],
+ pAPort->Exact[j].a[0],
+ pAPort->Exact[j].a[1],
+ pAPort->Exact[j].a[2],
+ pAPort->Exact[j].a[3],
+ pAPort->Exact[j].a[4],
+ pAPort->Exact[j].a[5]))
+ }
+ }
+#endif /* DEBUG */
+
+ pAC->Rlmt.CheckingState &= ~SK_RLMT_RCS_SEG;
+
+ SkRlmtCheckSeg(pAC, IoC);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_SEG_TIM Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_PACKET_RECEIVED: /* From DRV. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PACKET_RECEIVED Event (%d) BEGIN.\n", Event))
+
+ /* Should we ignore frames during port switching? */
+
+#ifdef DEBUG
+ pMb = Para.pParaPtr;
+ if (pMb == NULL) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("No mbuf.\n"))
+ }
+ else if (pMb->pNext != NULL) {
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("More than one mbuf or pMb->pNext not set.\n"))
+ }
+#endif /* DEBUG */
+
+ for (pMb = Para.pParaPtr; pMb != NULL; pMb = pNextMb) {
+ pNextMb = pMb->pNext;
+ pMb->pNext = NULL;
+ SkRlmtPacketReceive(pAC, IoC, pMb);
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PACKET_RECEIVED Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_STATS_CLEAR: /* From PNMI. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STATS_CLEAR Event (%d) BEGIN.\n", Event))
+
+ /* Clear statistics for virtual and physical ports. */
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ pAC->Rlmt.Port[i].TxHelloCts = 0;
+ pAC->Rlmt.Port[i].RxHelloCts = 0;
+ pAC->Rlmt.Port[i].TxSpHelloReqCts = 0;
+ pAC->Rlmt.Port[i].RxSpHelloCts = 0;
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STATS_CLEAR Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_STATS_UPDATE: /* From PNMI. */
+#if 0
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STATS_UPDATE Event (%d) BEGIN.\n", Event))
+
+ /* Update statistics. */
+
+ /* Currently always up-to-date. */
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_STATS_UPDATE Event (%d) END.\n", Event))
+#endif /* 0 */
+ break;
+
+ case SK_RLMT_PREFPORT_CHANGE: /* From PNMI. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PREFPORT_CHANGE to Port %d Event (%d) BEGIN.\n", Para.Para32[0], Event))
+
+ /* 0xFFFFFFFF == auto-mode. */
+
+ if (Para.Para32[0] == 0xFFFFFFFF) {
+ pAC->Rlmt.PrefPort = SK_RLMT_DEF_PREF_PORT;
+ }
+ else {
+ if (Para.Para32[0] >= (SK_U32)pAC->GIni.GIMacsFound) {
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E010,
+ SKERR_RLMT_E010_MSG);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PREFPORT_CHANGE Event (%d) EMPTY.\n", Event))
+ break;
+ }
+
+ pAC->Rlmt.PrefPort = Para.Para32[0];
+ }
+
+ pAC->Rlmt.MacPreferred = Para.Para32[0];
+
+ SkRlmtCheckSwitch(pAC, IoC);
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_PREFPORT_CHANGE Event (%d) END.\n", Event))
+ break;
+
+ case SK_RLMT_MODE_CHANGE: /* From PNMI. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_MODE_CHANGE Event (%d) BEGIN.\n", Event))
+
+ if (pAC->GIni.GIMacsFound < 2) {
+ pAC->Rlmt.RlmtMode = SK_RLMT_CHECK_LINK;
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Forced RLMT mode to CLS on single link adapter.\n"))
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_MODE_CHANGE Event (%d) EMPTY.\n",
+ Event))
+ break;
+ }
+
+ /* Update RLMT mode. */
+
+ PrevRlmtMode = pAC->Rlmt.RlmtMode;
+ pAC->Rlmt.RlmtMode = Para.Para32[0] | SK_RLMT_CHECK_LINK;
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("RLMT: Changed Mode to %X.\n", pAC->Rlmt.RlmtMode))
+
+ if ((PrevRlmtMode & SK_RLMT_CHECK_LOC_LINK) !=
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK)) {
+ if (!(PrevRlmtMode & SK_RLMT_CHECK_OTHERS) &&
+ pAC->GIni.GIMacsFound > 1 &&
+ pAC->Rlmt.PortsUp == 1) {
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.LocTimer,
+ pAC->Rlmt.TimeoutValue,
+ SKGE_RLMT,
+ SK_RLMT_TIM,
+ Para);
+ }
+ }
+
+ if ((PrevRlmtMode & SK_RLMT_CHECK_SEG) !=
+ (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG)) {
+
+ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
+ (void)SkAddrMcClear(
+ pAC,
+ IoC,
+ i,
+ SK_ADDR_PERMANENT | SK_MC_SW_ONLY);
+
+ /* Add RLMT MC address. */
+
+ (void)SkAddrMcAdd(
+ pAC,
+ IoC,
+ i,
+ &SkRlmtMcAddr,
+ SK_ADDR_PERMANENT);
+
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) {
+ /* Add BPDU MC address. */
+
+ (void)SkAddrMcAdd(
+ pAC,
+ IoC,
+ i,
+ &BridgeMcAddr,
+ SK_ADDR_PERMANENT);
+
+ if (pAC->Rlmt.RlmtState !=
+ SK_RLMT_RS_INIT) {
+ if (!pAC->Rlmt.Port[i].LinkDown &&
+ (Para2.pParaPtr =
+ SkRlmtBuildSpanningTreePacket(
+ pAC,
+ IoC,
+ i)
+ ) != NULL) {
+
+ pAC->Rlmt.Port[i
+ ].RootIdSet =
+ SK_FALSE;
+
+ SkEventQueue(
+ pAC,
+ SKGE_DRV,
+ SK_DRV_RLMT_SEND,
+ Para2);
+ }
+ }
+ }
+
+ (void)SkAddrMcUpdate(pAC, IoC, i);
+ }
+
+ if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_SEG) {
+ SkTimerStart(
+ pAC,
+ IoC,
+ &pAC->Rlmt.SegTimer,
+ SK_RLMT_SEG_TO_VAL,
+ SKGE_RLMT,
+ SK_RLMT_SEG_TIM,
+ Para);
+ }
+ }
+
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("SK_RLMT_MODE_CHANGE Event (%d) END.\n", Event))
+ break;
+
+ default: /* Create error log entry. */
+ SK_DBG_MSG(
+ pAC,
+ SK_DBGMOD_RLMT,
+ SK_DBGCAT_CTRL,
+ ("Unknown RLMT Event %d.\n", Event))
+
+ SK_ERR_LOG(
+ pAC,
+ SK_ERRCL_SW,
+ SKERR_RLMT_E003,
+ SKERR_RLMT_E003_MSG);
+ break;
+ }
+
+ return (0);
+} /* SkRlmtEvent */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: sktimer.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.11 $
+ * Date: $Date: 1998/12/17 13:24:13 $
+ * Purpose: High level timer functions.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: sktimer.c,v $
+ * Revision 1.11 1998/12/17 13:24:13 gklug
+ * fix: restart problem: do NOT destroy timer queue if init 1 is done
+ *
+ * Revision 1.10 1998/10/15 15:11:36 gklug
+ * fix: ID_sccs to SysKonnectFileId
+ *
+ * Revision 1.9 1998/09/15 15:15:04 cgoos
+ * Changed TRUE/FALSE to SK_TRUE/SK_FALSE
+ *
+ * Revision 1.8 1998/09/08 08:47:55 gklug
+ * add: init level handling
+ *
+ * Revision 1.7 1998/08/19 09:50:53 gklug
+ * fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ * Revision 1.6 1998/08/17 13:43:13 gklug
+ * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ * Revision 1.5 1998/08/14 07:09:14 gklug
+ * fix: chg pAc -> pAC
+ *
+ * Revision 1.4 1998/08/07 12:53:46 gklug
+ * fix: first compiled version
+ *
+ * Revision 1.3 1998/08/07 09:31:53 gklug
+ * fix: delta spelling
+ *
+ * Revision 1.2 1998/08/07 09:31:02 gklug
+ * adapt functions to new c coding conventions
+ * rmv: "fast" handling
+ * chg: inserting of new timer in queue.
+ * chg: event queue generation when timer runs out
+ *
+ * Revision 1.1 1998/08/05 11:27:55 gklug
+ * first version: adapted from SMT
+ *
+ *
+ *
+ *
+ ******************************************************************************/
+
+
+/*
+ Event queue and dispatcher
+*/
+static const char SysKonnectFileId[] =
+ "$Header: /usr56/projects/ge/schedule/sktimer.c,v 1.11 1998/12/17 13:24:13 gklug Exp $" ;
+
+#include "h/skdrv1st.h" /* Driver Specific Definitions */
+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+ Event queue management.
+
+ General Description:
+
+ */
+intro()
+{}
+#endif
+
+
+/* Forward declaration */
+static void timer_done(SK_AC *pAC,SK_IOC Ioc,int Restart);
+
+
+/*
+ * Inits the software timer
+ *
+ * needs to be called during Init level 1.
+ */
+void SkTimerInit(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc, /* IoContext */
+int Level) /* Init Level */
+{
+ switch (Level) {
+ case SK_INIT_DATA:
+ pAC->Tim.StQueue = 0 ;
+ break;
+ case SK_INIT_IO:
+ SkHwtInit(pAC,Ioc) ;
+ SkTimerDone(pAC, Ioc);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Stops a high level timer
+ * - If a timer is not in the queue the function returns normally, too.
+ */
+void SkTimerStop(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc, /* IoContext */
+SK_TIMER *pTimer) /* Timer Pointer to be started */
+{
+ SK_TIMER **ppTimPrev ;
+ SK_TIMER *pTm ;
+
+ /*
+ * remove timer from queue
+ */
+ pTimer->TmActive = SK_FALSE ;
+ if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
+ SkHwtStop(pAC,Ioc) ;
+ }
+ for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ;
+ ppTimPrev = &pTm->TmNext ) {
+ if (pTm == pTimer) {
+ /*
+ * Timer found in queue
+ * - dequeue it and
+ * - correct delta of the next timer
+ */
+ *ppTimPrev = pTm->TmNext ;
+
+ if (pTm->TmNext) {
+ /* correct delta of next timer in queue */
+ pTm->TmNext->TmDelta += pTm->TmDelta ;
+ }
+ return ;
+ }
+ }
+}
+
+/*
+ * Start a high level software timer
+ */
+void SkTimerStart(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc, /* IoContext */
+SK_TIMER *pTimer, /* Timer Pointer to be started */
+SK_U32 Time, /* Time value */
+SK_U32 Class, /* Event Class for this timer */
+SK_U32 Event, /* Event Value for this timer */
+SK_EVPARA Para) /* Event Parameter for this timer */
+{
+ SK_TIMER **ppTimPrev ;
+ SK_TIMER *pTm ;
+ SK_U32 Delta ;
+
+ Time /= 16 ; /* input is uS, clock ticks are 16uS */
+ if (!Time)
+ Time = 1 ;
+
+ SkTimerStop(pAC,Ioc,pTimer) ;
+
+ pTimer->TmClass = Class ;
+ pTimer->TmEvent = Event ;
+ pTimer->TmPara = Para ;
+ pTimer->TmActive = SK_TRUE ;
+
+ if (!pAC->Tim.StQueue) {
+ /* First Timer to be started */
+ pAC->Tim.StQueue = pTimer ;
+ pTimer->TmNext = 0 ;
+ pTimer->TmDelta = Time ;
+ SkHwtStart(pAC,Ioc,Time) ;
+ return ;
+ }
+
+ /*
+ * timer correction
+ */
+ timer_done(pAC,Ioc,0) ;
+
+ /*
+ * find position in queue
+ */
+ Delta = 0 ;
+ for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ;
+ ppTimPrev = &pTm->TmNext ) {
+ if (Delta + pTm->TmDelta > Time) {
+ /* Position found */
+ /* Here the timer needs to be inserted. */
+ break ;
+ }
+ Delta += pTm->TmDelta ;
+ }
+
+ /* insert in queue */
+ *ppTimPrev = pTimer ;
+ pTimer->TmNext = pTm ;
+ pTimer->TmDelta = Time - Delta ;
+
+ if (pTm) {
+ /* There is a next timer
+ * -> correct its Delta value.
+ */
+ pTm->TmDelta -= pTimer->TmDelta ;
+ }
+
+ /*
+ * start new with first
+ */
+ SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ;
+}
+
+
+void SkTimerDone(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc) /* IoContext */
+{
+ timer_done(pAC,Ioc,1) ;
+}
+
+
+static void timer_done(
+SK_AC *pAC, /* Adapters context */
+SK_IOC Ioc, /* IoContext */
+int Restart) /* Do we need to restart the Hardware timer ? */
+{
+ SK_U32 Delta ;
+ SK_TIMER *pTm ;
+ SK_TIMER *pTComp ; /* Timer completed now now */
+ SK_TIMER **ppLast ; /* Next field of Last timer to be deq */
+ int Done = 0 ;
+
+ Delta = SkHwtRead(pAC,Ioc) ;
+ ppLast = &pAC->Tim.StQueue ;
+ pTm = pAC->Tim.StQueue ;
+ while (pTm && !Done) {
+ if (Delta >= pTm->TmDelta) {
+ /* Timer ran out */
+ pTm->TmActive = SK_FALSE ;
+ Delta -= pTm->TmDelta ;
+ ppLast = &pTm->TmNext ;
+ pTm = pTm->TmNext ;
+ } else {
+ /* We found the first timer that did not run out */
+ pTm->TmDelta -= Delta ;
+ Delta = 0 ;
+ Done = 1 ;
+ }
+ }
+ *ppLast = 0 ;
+ /*
+ * pTm points to the first Timer that did not run out.
+ * StQueue points to the first Timer that run out.
+ */
+
+ for ( pTComp = pAC->Tim.StQueue ; pTComp ; pTComp = pTComp->TmNext) {
+ SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent,
+ pTComp->TmPara) ;
+ }
+
+ /* Set head of timer queue to the first timer that did not run out */
+ pAC->Tim.StQueue = pTm ;
+
+ if (Restart && pAC->Tim.StQueue) {
+ /* Restart HW timer */
+ SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ;
+ }
+}
+
+/* End of file */
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skvpd.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.24 $
+ * Date: $Date: 1999/03/11 14:25:49 $
+ * Purpose: Shared software to read and write VPD data
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skvpd.c,v $
+ * Revision 1.24 1999/03/11 14:25:49 malthoff
+ * Replace __STDC__ with SK_KR_PROTO.
+ *
+ * Revision 1.23 1999/01/11 15:13:11 gklug
+ * fix: syntax error
+ *
+ * Revision 1.22 1998/10/30 06:41:15 gklug
+ * rmv: WARNING
+ *
+ * Revision 1.21 1998/10/29 07:15:14 gklug
+ * fix: Write Stream function needs verify.
+ *
+ * Revision 1.20 1998/10/28 18:05:08 gklug
+ * chg: no DEBUG in VpdMayWrite
+ *
+ * Revision 1.19 1998/10/28 15:56:11 gklug
+ * fix: Return len at end of ReadStream
+ * fix: Write even less than 4 bytes correctly
+ *
+ * Revision 1.18 1998/10/28 09:00:47 gklug
+ * fix: unreferenced local vars
+ *
+ * Revision 1.17 1998/10/28 08:25:45 gklug
+ * fix: WARNING
+ *
+ * Revision 1.16 1998/10/28 08:17:30 gklug
+ * fix: typo
+ *
+ * Revision 1.15 1998/10/28 07:50:32 gklug
+ * fix: typo
+ *
+ * Revision 1.14 1998/10/28 07:20:38 gklug
+ * chg: Interface functions to use IoC as parameter as well
+ * fix: VpdRead/WriteDWord now return SK_U32
+ * chg: VPD_IN/OUT names conform to SK_IN/OUT
+ * add: usage of VPD_IN/OUT8 macros
+ * add: VpdRead/Write Stream functions to r/w a stream of data
+ * fix: VpdTransferBlock swapped illeagal
+ * add: VpdMayWrite
+ *
+ * Revision 1.13 1998/10/22 10:02:37 gklug
+ * fix: SysKonnectFileId typo
+ *
+ * Revision 1.12 1998/10/20 10:01:01 gklug
+ * fix: parameter to SkOsGetTime
+ *
+ * Revision 1.11 1998/10/15 12:51:48 malthoff
+ * Remove unrequired parameter p in vpd_setup_para().
+ *
+ * Revision 1.10 1998/10/08 14:52:43 malthoff
+ * Remove CvsId by SysKonnectFileId.
+ *
+ * Revision 1.9 1998/09/16 07:33:52 malthoff
+ * remove memcmp() by SK_MEMCMP and
+ * memcpy() by SK_MEMCPY() to be
+ * independant from the 'C' Standard Library.
+ *
+ * Revision 1.8 1998/08/19 12:52:35 malthoff
+ * compiler fix: use SK_VPD_KEY instead of S_VPD.
+ *
+ * Revision 1.7 1998/08/19 08:14:01 gklug
+ * fix: remove struct keyword as much as possible from the c-code (see CCC)
+ *
+ * Revision 1.6 1998/08/18 13:03:58 gklug
+ * SkOsGetTime now returns SK_U64
+ *
+ * Revision 1.5 1998/08/18 08:17:29 malthoff
+ * Ensure we issue a VPD read in vpd_read_dword().
+ * Discard all VPD keywords other than Vx or Yx, where
+ * x is '0..9' or 'A..Z'.
+ *
+ * Revision 1.4 1998/07/03 14:52:19 malthoff
+ * Add category SK_DBGCAT_FATAL to some debug macros.
+ * bug fix: correct the keyword name check in vpd_write().
+ *
+ * Revision 1.3 1998/06/26 11:16:53 malthoff
+ * Correct the modified File Identifier.
+ *
+ * Revision 1.2 1998/06/26 11:13:43 malthoff
+ * Modify the File Identifier.
+ *
+ * Revision 1.1 1998/06/19 14:11:08 malthoff
+ * Created, Tests with AIX were performed successfully
+ *
+ *
+ ******************************************************************************/
+
+/*
+ Please refer skvpd.txt for infomation how to include this module
+ */
+static const char SysKonnectFileId[] =
+ "@(#)$Id: skvpd.c,v 1.24 1999/03/11 14:25:49 malthoff Exp $ (C) SK" ;
+
+#include "h/skdrv1st.h"
+#include "h/sktypes.h"
+#include "h/skdebug.h"
+#include "h/skdrv2nd.h"
+
+/*
+ * Static functions
+ */
+#ifndef SK_KR_PROTO
+static SK_VPD_PARA *vpd_find_para(
+ SK_AC *pAC,
+ char *key,
+ SK_VPD_PARA *p) ;
+#else /* SK_KR_PROTO */
+static SK_VPD_PARA *vpd_find_para() ;
+#endif /* SK_KR_PROTO */
+
+/*
+ * waits for a completetion of a VPD transfer
+ * The VPD transfer must complete within SK_TICKS_PER_SEC/16
+ *
+ * returns 0: success, transfer completes
+ * error exit(9) with a error message
+ */
+static int VpdWait(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int event) /* event to wait for (VPD_READ / VPD_write) completion*/
+{
+ SK_U64 start_time ;
+ SK_U16 state ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd wait for %s\n",event?"Write":"Read")) ;
+ start_time = SkOsGetTime(pAC) ;
+ do {
+ if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC/16) {
+ VPD_STOP(pAC,IoC) ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,
+ SK_DBGCAT_FATAL|SK_DBGCAT_ERR,
+ ("ERROR:vpd wait timeout\n")) ;
+ return(1) ;
+ }
+ VPD_IN16(pAC,IoC,PCI_VPD_ADR_REG,&state) ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("state = %x, event %x\n",state,event)) ;
+ } while((int)(state & PCI_VPD_FLAG) == event) ;
+
+ return(0) ;
+}
+
+
+/*
+ * Read the dword at address 'addr' from the VPD EEPROM.
+ *
+ * Needed Time: MIN 1,3 ms MAX 2,6 ms
+ *
+ * Note: The DWord is returned in the endianess of the machine the routine
+ * is running on.
+ *
+ * Returns the data read.
+ */
+SK_U32 VpdReadDWord(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+int addr) /* VPD address */
+{
+ SK_U32 Rtv ;
+
+ /* start VPD read */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd read dword at 0x%x\n",addr)) ;
+ addr &= ~VPD_WRITE ; /* ensure the R/W bit is set to read */
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, (SK_U16) addr) ;
+
+ /* ignore return code here */
+ (void)VpdWait(pAC,IoC,VPD_READ) ;
+
+ /* Don't swap here, it's a data stream of bytes */
+ Rtv = 0 ;
+
+ VPD_IN32(pAC,IoC,PCI_VPD_DAT_REG,&Rtv) ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd read dword data = 0x%x\n",Rtv)) ;
+ return (Rtv) ;
+}
+
+/*
+ Write the dword 'data' at address 'addr' into the VPD EEPROM, and
+ verify that the data is written.
+
+ Needed Time:
+
+. MIN MAX
+. -------------------------------------------------------------------
+. write 1.8 ms 3.6 ms
+. internal write cyles 0.7 ms 7.0 ms
+. -------------------------------------------------------------------
+. over all program time 2.5 ms 10.6 ms
+. read 1.3 ms 2.6 ms
+. -------------------------------------------------------------------
+. over all 3.8 ms 13.2 ms
+.
+
+
+ Returns 0: success
+ 1: error, I2C transfer does not terminate
+ 2: error, data verify error
+
+ */
+static int VpdWriteDWord(
+SK_AC *pAC, /* pAC pointer */
+SK_IOC IoC, /* IO Context */
+int addr, /* VPD address */
+SK_U32 data) /* VPD data to write */
+{
+ /* start VPD write */
+ /* Don't swap here, it's a data stream of bytes */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd write dword at addr 0x%x, data = 0x%x\n",addr,data)) ;
+ VPD_OUT32(pAC,IoC,PCI_VPD_DAT_REG, (SK_U32)data) ;
+ /* But do it here */
+ addr |= VPD_WRITE ;
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE)) ;
+
+ /* this may take up to 10,6 ms */
+ if (VpdWait(pAC,IoC,VPD_WRITE)) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("Write Timed Out\n")) ;
+ return(1) ;
+ } ;
+
+ /* verify data */
+ if (VpdReadDWord(pAC,IoC,addr) != data) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR|SK_DBGCAT_FATAL,
+ ("Data Verify Error\n")) ;
+ return(2) ;
+ }
+ return(0) ;
+}
+
+/*
+ * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
+ * or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdWriteStream(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+char *buf, /* data buffer */
+int Addr, /* VPD start address */
+int Len) /* number of bytes to read / to write */
+{
+ int i ;
+ int j ;
+ SK_U16 AdrReg ;
+ int Rtv ;
+ SK_U8 * pComp; /* Compare pointer */
+ SK_U8 Data ; /* Input Data for Compare */
+
+ /* Init Compare Pointer */
+ pComp = (SK_U8 *) buf;
+
+ for (i=0; i < Len; i ++, buf++) {
+ if ((i%sizeof(SK_U32)) == 0) {
+ /*
+ * At the begin of each cycle read the Data Reg
+ * So it is initialized even if only a few bytes
+ * are written.
+ */
+ AdrReg = (SK_U16) Addr ;
+ AdrReg &= ~VPD_WRITE ; /* READ operation */
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, AdrReg) ;
+
+ /* ignore return code here */
+ Rtv = VpdWait(pAC,IoC,VPD_READ) ;
+ if (Rtv != 0) {
+ return(i) ;
+ }
+ }
+
+ /* Write current Byte */
+ VPD_OUT8(pAC,IoC,PCI_VPD_DAT_REG+(i%sizeof(SK_U32)),
+ *(SK_U8*)buf) ;
+
+ if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) {
+ /* New Address needs to be written to VPD_ADDR reg */
+ AdrReg = (SK_U16) Addr ;
+ Addr += sizeof(SK_U32);
+ AdrReg |= VPD_WRITE ; /* WRITE operation */
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, AdrReg) ;
+
+ /* Wait for termination */
+ Rtv = VpdWait(pAC,IoC,VPD_WRITE) ;
+ if (Rtv != 0) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("Write Timed Out\n")) ;
+ return(i - (i%sizeof(SK_U32))) ;
+ }
+
+ /*
+ * Now re-read to verify
+ */
+ AdrReg &= ~VPD_WRITE ; /* READ operation */
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, AdrReg) ;
+
+ /* Wait for termination */
+ Rtv = VpdWait(pAC,IoC,VPD_READ) ;
+ if (Rtv != 0) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("Verify Timed Out\n")) ;
+ return(i - (i%sizeof(SK_U32))) ;
+ }
+
+ for (j = 0; j <= (int) (i%sizeof(SK_U32));
+ j ++, pComp ++ ) {
+ VPD_IN8(pAC,IoC,PCI_VPD_DAT_REG+j, &Data) ;
+ if (Data != *pComp) {
+ /* Verify Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,
+ SK_DBGCAT_ERR,
+ ("WriteStream Verify Error\n"));
+ return(i - (i%sizeof(SK_U32)) + j);
+ }
+ }
+
+ }
+ }
+
+ return(Len);
+}
+
+
+/*
+ * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
+ * or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdReadStream(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+char *buf, /* data buffer */
+int Addr, /* VPD start address */
+int Len) /* number of bytes to read / to write */
+{
+ int i ;
+ SK_U16 AdrReg ;
+ int Rtv ;
+
+ for (i=0; i < Len; i ++, buf++) {
+ if ((i%sizeof(SK_U32)) == 0) {
+ /* New Address needs to be written to VPD_ADDR reg */
+ AdrReg = (SK_U16) Addr ;
+ Addr += sizeof(SK_U32);
+ AdrReg &= ~VPD_WRITE ; /* READ operation */
+
+ VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG, AdrReg) ;
+
+ /* ignore return code here */
+ Rtv = VpdWait(pAC,IoC,VPD_READ) ;
+ if (Rtv != 0) {
+ return(i) ;
+ }
+
+ }
+ VPD_IN8(pAC,IoC,PCI_VPD_DAT_REG+(i%sizeof(SK_U32)),
+ (SK_U8 *)buf) ;
+ }
+
+ return(Len) ;
+}
+
+/*
+ * Read ore wirtes 'len' bytes of VPD data, starting at 'addr' from
+ * or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdTransferBlock(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC, /* IO Context */
+char *buf, /* data buffer */
+int addr, /* VPD start address */
+int len, /* number of bytes to read / to write */
+int dir) /* transfer direction may be VPD_READ or VPD_WRITE */
+{
+ int Rtv ; /* Return value */
+ int vpd_rom_size ;
+ SK_U32 our_reg2 ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd %s block, addr = 0x%x, len = %d\n",
+ dir?"write":"read",addr,len)) ;
+
+ if (len == 0)
+ return (0) ;
+
+ VPD_IN32(pAC,IoC,PCI_OUR_REG_2,&our_reg2) ;
+ vpd_rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
+ if (addr > vpd_rom_size - 4) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR|SK_DBGCAT_FATAL,
+ ("Address error: 0x%x, exp. < 0x%x\n",
+ addr, vpd_rom_size - 4)) ;
+ return (0) ;
+ }
+ if (addr + len > vpd_rom_size) {
+ len = vpd_rom_size - addr ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("Warning: len was cut to %d\n",len)) ;
+ }
+
+ if (dir == VPD_READ) {
+ Rtv = VpdReadStream(pAC, IoC, buf, addr, len);
+ } else {
+ Rtv = VpdWriteStream(pAC, IoC, buf, addr, len);
+ }
+
+ return (Rtv) ;
+}
+
+#ifdef SKDIAG
+
+/*
+ * Read 'len' bytes of VPD data, starting at 'addr'.
+ *
+ * Returns number of bytes read.
+ */
+int VpdReadBlock(
+SK_AC *pAC, /* pAC pointer */
+SK_IOC IoC, /* IO Context */
+char *buf, /* buffer were the data should be stored */
+int addr, /* start reading at the VPD address */
+int len) /* number of bytes to read */
+{
+ return (VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ)) ;
+}
+
+/*
+ * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'.
+ *
+ * Returns number of bytes writes.
+ */
+int VpdWriteBlock(
+SK_AC *pAC, /* pAC pointer */
+SK_IOC IoC, /* IO Context */
+char *buf, /* buffer, holds the data to write */
+int addr, /* start writing at the VPD address */
+int len) /* number of bytes to write */
+{
+ return (VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE)) ;
+}
+#endif /* SKDIAG */
+
+/*
+ * (re)initialize the VPD buffer
+ *
+ * Reads the VPD data from the EEPROM into the VPD buffer.
+ * Get the remaining read only and read / write space.
+ *
+ * return 0: success
+ * 1: fatal VPD error
+ */
+static int VpdInit(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC) /* IO Context */
+{
+ SK_VPD_PARA *r, rp ; /* RW or RV */
+ int i ;
+ unsigned char x ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_INIT,("VpdInit .. ")) ;
+ /* read the VPD data into the VPD buffer */
+ if (VpdTransferBlock(pAC,IoC,pAC->vpd.vpd_buf,0,VPD_SIZE,VPD_READ)
+ != VPD_SIZE) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("Block Read Error\n")) ;
+ return(1) ;
+ }
+
+ /* find the end tag of the RO area */
+ if (!(r = vpd_find_para(pAC,VPD_RV,&rp))) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Encoding Error: RV Tag not found\n")) ;
+ return (1) ;
+ }
+ if (r->p_val + r->p_len > pAC->vpd.vpd_buf + VPD_SIZE/2) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Encoding Error: Invalid VPD struct size\n")) ;
+ return (1) ;
+ }
+ pAC->vpd.v.vpd_free_ro = r->p_len - 1 ;
+
+ /* test the checksum */
+ for (i = 0, x = 0; (unsigned)i<=(unsigned)VPD_SIZE/2 - r->p_len; i++) {
+ x += pAC->vpd.vpd_buf[i] ;
+ }
+ if (x != 0) {
+ /* checksum error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("VPD Checksum Error\n")) ;
+ return (1) ;
+ }
+
+ /* find and check the end tag of the RW area */
+ if (!(r = vpd_find_para(pAC,VPD_RW,&rp))) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Encoding Error: RV Tag not found\n")) ;
+ return (1) ;
+ }
+ if (r->p_val < pAC->vpd.vpd_buf + VPD_SIZE/2) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Encoding Error: Invalid VPD struct size\n")) ;
+ return (1) ;
+ }
+ pAC->vpd.v.vpd_free_rw = r->p_len ;
+
+ /* everything seems to be ok */
+ pAC->vpd.v.vpd_status |= VPD_VALID ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_INIT,
+ ("done. Free RO = %d, Free RW = %d\n",
+ pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)) ;
+
+ return(0) ;
+}
+
+/*
+ * find the Keyword 'key' in the VPD buffer and fills the
+ * parameter sturct 'p' with it's values
+ *
+ * returns *p success
+ * 0: parameter was not found or VPD encoding error
+ */
+static SK_VPD_PARA *vpd_find_para(
+SK_AC *pAC, /* common data base */
+char *key, /* keyword to find (e.g. "MN") */
+SK_VPD_PARA *p) /* parameter description struct */
+{
+ char *v ; /* points to vpd buffer */
+ int max ; /* Maximum Number of Iterations */
+
+ v = pAC->vpd.vpd_buf ;
+ max = 128 ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd find para %s .. ",key)) ;
+
+ /* check mandatory resource type ID string (Product Name) */
+ if (*v != (char) RES_ID) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Error: 0x%x missing\n",RES_ID)) ;
+ return (0) ;
+ }
+
+ if (strcmp(key,VPD_NAME) == 0) {
+ p->p_len = VPD_GET_RES_LEN(v) ;
+ p->p_val = VPD_GET_VAL(v) ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("found, len = %d\n",p->p_len)) ;
+ return(p) ;
+ }
+
+ v += 3 + VPD_GET_RES_LEN(v) + 3 ;
+ for ( ; ; ) {
+ if (SK_MEMCMP(key,v,2) == 0) {
+ p->p_len = VPD_GET_VPD_LEN(v) ;
+ p->p_val = VPD_GET_VAL(v) ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("found, len = %d\n",p->p_len)) ;
+ return (p) ;
+ }
+
+ /* exit when reaching the "RW" Tag or the maximum of itera. */
+ max-- ;
+ if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) {
+ break ;
+ }
+
+ if (SK_MEMCMP(VPD_RV,v,2) == 0) {
+ v += 3 + VPD_GET_VPD_LEN(v) + 3 ; /* skip VPD-W */
+ } else {
+ v += 3 + VPD_GET_VPD_LEN(v) ;
+ }
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("scanning '%c%c' len = %d\n",v[0],v[1],v[2])) ;
+ }
+
+#ifdef DEBUG
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,("not found\n")) ;
+ if (max == 0) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Key/Len Encoding error\n")) ;
+ }
+#endif
+ return (0) ;
+}
+
+/*
+ * Move 'n' bytes. Begin with the last byte if 'n' is > 0,
+ * Start with the last byte if n is < 0.
+ *
+ * returns nothing
+ */
+static void vpd_move_para(
+char *start, /* start of memory block */
+char *end, /* end of memory block to move */
+int n) /* number of bytes the memory block has to be moved */
+{
+ char *p ;
+ int i ; /* number of byte copied */
+
+ if (n == 0)
+ return ;
+
+ i = end - start + 1 ;
+ if (n < 0) {
+ p = start + n ;
+ while (i != 0) {
+ *p++ = *start++ ;
+ i-- ;
+ }
+ } else {
+ p = end + n ;
+ while (i != 0) {
+ *p-- = *end-- ;
+ i-- ;
+ }
+ }
+}
+
+/*
+ * setup the VPD keyword 'key' at 'ip'.
+ *
+ * returns nothing
+ */
+static void vpd_insert_key(
+char *key, /* keyword to insert */
+char *buf, /* buffer with the keyword value */
+int len, /* length of the value string */
+char *ip) /* inseration point */
+{
+ SK_VPD_KEY *p ;
+
+ p = (SK_VPD_KEY *) ip ;
+ p->p_key[0] = key[0] ;
+ p->p_key[1] = key[1] ;
+ p->p_len = (unsigned char) len ;
+ SK_MEMCPY(&p->p_val,buf,len) ;
+}
+
+/*
+ * Setup the VPD end tag "RV" / "RW".
+ * Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
+ *
+ * returns 0: success
+ * 1: encoding error
+ */
+static int vpd_mod_endtag(
+SK_AC *pAC, /* common data base */
+char *etp) /* end pointer input position */
+{
+ SK_VPD_KEY *p ;
+ unsigned char x ;
+ int i ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd modify endtag at 0x%x = '%c%c'\n",etp,etp[0],etp[1])) ;
+
+ p = (SK_VPD_KEY *) etp ;
+
+ if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
+ /* something wrong here, encoding error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+ ("Encoding Error: invalid end tag\n")) ;
+ return(1) ;
+ }
+ if (etp > pAC->vpd.vpd_buf + VPD_SIZE/2) {
+ /* create "RW" tag */
+ p->p_len = (unsigned char)(pAC->vpd.vpd_buf+VPD_SIZE-etp-3-1) ;
+ pAC->vpd.v.vpd_free_rw = (int) p->p_len ;
+ i = pAC->vpd.v.vpd_free_rw ;
+ etp += 3 ;
+ } else {
+ /* create "RV" tag */
+ p->p_len = (unsigned char)(pAC->vpd.vpd_buf+VPD_SIZE/2-etp-3) ;
+ pAC->vpd.v.vpd_free_ro = (int) p->p_len - 1 ;
+
+ /* setup checksum */
+ for (i = 0, x = 0; i < VPD_SIZE/2 - p->p_len; i++) {
+ x += pAC->vpd.vpd_buf[i] ;
+ }
+ p->p_val = (char) 0 - x ;
+ i = pAC->vpd.v.vpd_free_ro ;
+ etp += 4 ;
+ }
+ while (i) {
+ *etp++ = 0x00 ;
+ i-- ;
+ }
+
+ return (0) ;
+}
+
+/*
+ * Insert a VPD keyword into the VPD buffer.
+ *
+ * The keyword 'key' is inserted at the position 'ip' in the
+ * VPD buffer.
+ * The keywords behind the input position will
+ * be moved. The VPD end tag "RV" or "RW" is generated again.
+ *
+ * returns 0: success
+ * 2: value string was cut
+ * 4: VPD full, keyword was not written
+ * 6: fatal VPD error
+ *
+ */
+int VpdSetupPara(
+SK_AC *pAC, /* common data base */
+char *key, /* keyword to insert */
+char *buf, /* buffer with the keyword value */
+int len, /* length of the keyword value */
+int type, /* VPD_RO_KEY or VPD_RW_KEY */
+int op) /* operation to do: ADD_KEY or OWR_KEY */
+{
+ SK_VPD_PARA vp ;
+ char *etp ; /* end tag position */
+ int free ; /* remaining space in selected area */
+ char *ip ; /* input position inside the VPD buffer */
+ int rtv ; /* return code */
+ int head ; /* additional haeder bytes to move */
+ int found ; /* additinoal bytes if the keyword was found */
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("vpd setup para key = %s, val = %s\n",key,buf)) ;
+
+ rtv = 0 ;
+ ip = 0 ;
+ if (type == VPD_RW_KEY) {
+ /* end tag is "RW" */
+ free = pAC->vpd.v.vpd_free_rw ;
+ etp = pAC->vpd.vpd_buf + (VPD_SIZE - free - 1 - 3) ;
+ } else {
+ /* end tag is "RV" */
+ free = pAC->vpd.v.vpd_free_ro ;
+ etp = pAC->vpd.vpd_buf + (VPD_SIZE/2 - free - 4) ;
+ }
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("Free RO = %d, Free RW = %d\n",
+ pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)) ;
+
+ head = 0 ;
+ found = 0 ;
+ if (op == OWR_KEY) {
+ if (vpd_find_para(pAC,key,&vp)) {
+ found = 3 ;
+ ip = vp.p_val - 3 ;
+ free += vp.p_len + 3 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("Overwrite Key\n")) ;
+ } else {
+ op = ADD_KEY ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_CTRL,
+ ("Add Key\n")) ;
+ }
+ }
+ if (op == ADD_KEY) {
+ ip = etp ;
+ vp.p_len = 0 ;
+ head = 3 ;
+ }
+
+ if (len + 3 > free) {
+ if (free < 7) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("VPD Buffer Overflow, keyword not written\n"));
+ return (4) ;
+ }
+ /* cut it again */
+ len = free - 3 ;
+ rtv = 2 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("VPD Buffer Full, Keyword was cut\n")) ;
+ }
+
+ vpd_move_para(ip + vp.p_len + found, etp+2, len-vp.p_len+head) ;
+ vpd_insert_key(key, buf, len, ip) ;
+ if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) {
+ pAC->vpd.v.vpd_status &= ~VPD_VALID ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("VPD Encoding Error\n")) ;
+ return(6) ;
+ }
+
+ return (rtv) ;
+}
+
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the
+ * VPD buffer if not already done.
+ *
+ * return: A pointer to the vpd_status structure. The structure contain
+ * this fields.
+ */
+SK_VPD_STATUS *VpdStat(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC) /* IO Context */
+{
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ (void)VpdInit(pAC,IoC) ;
+ }
+ return(&pAC->vpd.v) ;
+}
+
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the VPD
+ * buffer if not already done.
+ * Scan the VPD buffer for VPD keywords and create the VPD
+ * keyword list by copying the keywords to 'buf', all after
+ * each other and terminated with a '\0'.
+ *
+ * Exceptions: o The Resource Type ID String (product name) is called "Name"
+ * o The VPD end tags 'RV' and 'RW' are not listed
+ *
+ * The number of copied keywords is counted in 'elements'.
+ *
+ * returns 0: success
+ * 2: buffer overfull, one or more keywords are missing
+ * 6: fatal VPD error
+ *
+ * example values after returning:
+ *
+ * buf = "Name\0PN\0EC\0MN\0SN\0CP\0VF\0VL\0YA\0"
+ * *len = 30
+ * *elements = 9
+ */
+int VpdKeys(
+SK_AC *pAC, /* common data base */
+SK_IOC IoC, /* IO Context */
+char *buf, /* buffer where to copy the keywords */
+int *len, /* buffer length */
+int *elements) /* number of keywords returned */
+{
+ char *v ;
+ int n ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,("list vpd keys .. ")) ;
+ *elements = 0 ;
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ if (VpdInit(pAC,IoC) != 0 ) {
+ *len = 0 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("VPD Init Error, terminated\n")) ;
+ return(6) ;
+ }
+ }
+
+ if ((signed)strlen(VPD_NAME) + 1 <= *len) {
+ v = pAC->vpd.vpd_buf ;
+ strcpy(buf,VPD_NAME) ;
+ n = strlen(VPD_NAME) + 1 ;
+ buf += n ;
+ *elements = 1 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,
+ ("'%c%c' ",v[0],v[1])) ;
+ } else {
+ *len = 0 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("buffer overflow\n")) ;
+ return(2) ;
+ }
+
+ v += 3 + VPD_GET_RES_LEN(v) + 3 ;
+ for ( ; ; ) {
+ /* exit when reaching the "RW" Tag */
+ if (SK_MEMCMP(VPD_RW,v,2) == 0) {
+ break ;
+ }
+
+ if (SK_MEMCMP(VPD_RV,v,2) == 0) {
+ v += 3 + VPD_GET_VPD_LEN(v) + 3 ; /* skip VPD-W */
+ continue ;
+ }
+
+ if (n+3 <= *len) {
+ SK_MEMCPY(buf,v,2) ;
+ buf += 2 ;
+ *buf++ = '\0' ;
+ n += 3 ;
+ v += 3 + VPD_GET_VPD_LEN(v) ;
+ *elements += 1 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,
+ ("'%c%c' ",v[0],v[1])) ;
+ } else {
+ *len = n ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("buffer overflow\n")) ;
+ return (2) ;
+ }
+ }
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,("\n")) ;
+ *len = n ;
+ return(0) ;
+}
+
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the
+ * VPD buffer if not already done. Search for the VPD keyword
+ * 'key' and copy its value to 'buf'. Add a terminating '\0'.
+ * If the value does not fit into the buffer cut it after
+ * 'len' - 1 bytes.
+ *
+ * returns 0: success
+ * 1: keyword not found
+ * 2: value string was cut
+ * 3: VPD transfer timeout
+ * 6: fatal VPD error
+ */
+int VpdRead(
+SK_AC *pAC, /* common data base */
+SK_IOC IoC, /* IO Context */
+char *key, /* keyword to read (e.g. "MN") */
+char *buf, /* buffer where to copy the keyword value */
+int *len) /* buffer length */
+{
+ SK_VPD_PARA *p, vp ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,("vpd read %s .. ",key)) ;
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ if (VpdInit(pAC,IoC) != 0 ) {
+ *len = 0 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd init error\n")) ;
+ return(6) ;
+ }
+ }
+
+ if ((p = vpd_find_para(pAC,key,&vp))) {
+ if (p->p_len > (*(unsigned *)len)-1) {
+ p->p_len = *len - 1 ;
+ }
+ SK_MEMCPY(buf,p->p_val,p->p_len) ;
+ buf[p->p_len] = '\0' ;
+ *len = p->p_len ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_RX,
+ ("%c%c%c%c.., len = %d\n",
+ buf[0],buf[1],buf[2],buf[3],*len)) ;
+ } else {
+ *len = 0 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,("not found\n")) ;
+ return (1) ;
+ }
+ return (0) ;
+}
+
+
+/*
+ * Check whether a given key may be written
+ *
+ * returns
+ * SK_TRUE Yes it may be written
+ * SK_FALSE No it may be written
+ */
+SK_BOOL VpdMayWrite(
+char *key) /* keyword to write (allowed values "Yx", "Vx") */
+{
+ if ((*key != 'Y' && *key != 'V') ||
+ key[1] < '0' || key[1] > 'Z' ||
+ (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
+
+ return (SK_FALSE) ;
+ }
+ return (SK_TRUE) ;
+}
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the VPD
+ * buffer if not already done. Insert/overwrite the keyword 'key'
+ * in the VPD buffer. Cut the keyword value if it does not fit
+ * into the VPD read / write area.
+ *
+ * returns 0: success
+ * 2: value string was cut
+ * 3: VPD transfer timeout
+ * 4: VPD full, keyword was not written
+ * 5: keyword cannot be written
+ * 6: fatal VPD error
+ */
+int VpdWrite(
+SK_AC *pAC, /* common data base */
+SK_IOC IoC, /* IO Context */
+char *key, /* keyword to write (allowed values "Yx", "Vx") */
+char *buf) /* buffer where the keyword value can be read from */
+{
+ int len ; /* lenght of the keyword to write */
+ int rtv ; /* return code */
+ int rtv2 ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,
+ ("vpd write %s = %s\n",key,buf)) ;
+
+ if ((*key != 'Y' && *key != 'V') ||
+ key[1] < '0' || key[1] > 'Z' ||
+ (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("illegal key tag, keyword not written\n")) ;
+ return (5) ;
+ }
+
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ if (VpdInit(pAC,IoC) != 0 ) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd init error\n")) ;
+ return(6) ;
+ }
+ }
+
+ rtv = 0 ;
+ len = strlen(buf) ;
+ if (len > VPD_MAX_LEN) {
+ /* cut it */
+ len = VPD_MAX_LEN ;
+ rtv = 2 ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("keyword to long, cut after %d bytes\n",VPD_MAX_LEN)) ;
+ }
+ if ((rtv2 = VpdSetupPara(pAC,key,buf,len,VPD_RW_KEY,OWR_KEY)) != 0) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd write error\n")) ;
+ return(rtv2) ;
+ }
+
+ return (rtv) ;
+}
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the
+ * VPD buffer if not already done. Remove the VPD keyword
+ * 'key' from the VPD buffer.
+ * Only the keywords in the read/write area can be deleted.
+ * Keywords in the read only area cannot be deleted.
+ *
+ * returns 0: success, keyword was removed
+ * 1: keyword not found
+ * 5: keyword cannot be deleted
+ * 6: fatal VPD error
+ */
+int VpdDelete(
+SK_AC *pAC, /* common data base */
+SK_IOC IoC, /* IO Context */
+char *key) /* keyword to read (e.g. "MN") */
+{
+ SK_VPD_PARA *p, vp ;
+ char *etp ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("vpd delete key %s\n",key)) ;
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ if (VpdInit(pAC,IoC) != 0 ) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd init error\n")) ;
+ return(6) ;
+ }
+ }
+
+ if ((p = vpd_find_para(pAC,key,&vp))) {
+ if (p->p_val < pAC->vpd.vpd_buf + VPD_SIZE/2) {
+ /* try to delete read only keyword */
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("cannot delete RO keyword\n")) ;
+ return (5) ;
+ }
+
+ etp = pAC->vpd.vpd_buf + (VPD_SIZE-pAC->vpd.v.vpd_free_rw-1-3) ;
+
+ vpd_move_para(vp.p_val+vp.p_len, etp+2,
+ - ((int)(vp.p_len + 3))) ;
+ if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) {
+ pAC->vpd.v.vpd_status &= ~VPD_VALID ;
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd encoding error\n")) ;
+ return(6) ;
+ }
+ } else {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("keyword not found\n")) ;
+ return (1) ;
+ }
+
+ return (0) ;
+}
+
+/*
+ * If the VPD buffer contains valid data write the VPD
+ * read/write area back to the VPD EEPROM.
+ *
+ * returns 0: success
+ * 3: VPD transfer timeout
+ */
+int VpdUpdate(
+SK_AC *pAC, /* Adapters context */
+SK_IOC IoC) /* IO Context */
+{
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("vpd update .. ")) ;
+ if (pAC->vpd.v.vpd_status & VPD_VALID) {
+ if (VpdTransferBlock(pAC,IoC,pAC->vpd.vpd_buf + VPD_SIZE/2,
+ VPD_SIZE/2, VPD_SIZE/2, VPD_WRITE) != VPD_SIZE/2) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("transfer timed out\n")) ;
+ return(3) ;
+ }
+ }
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("done\n")) ;
+ return (0) ;
+}
+
+
+
+/*
+ * Read the contents of the VPD EEPROM and copy it to the VPD buffer
+ * if not already done. If the keyword "VF" is not present it will be
+ * created and the error log message will be stored to this keyword.
+ * If "VF" is not present the error log message will be stored to the
+ * keyword "VL". "VL" will created or overwritten if "VF" is present.
+ * The VPD read/write area is saved to the VPD EEPROM.
+ *
+ * returns nothing, errors will be ignored.
+ */
+void VpdErrLog(
+SK_AC *pAC, /* common data base */
+SK_IOC IoC, /* IO Context */
+char *msg) /* error log message */
+{
+ SK_VPD_PARA *v, vf ; /* VF */
+ int len ;
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,
+ ("vpd error log msg %s\n",msg)) ;
+ if (!(pAC->vpd.v.vpd_status & VPD_VALID)) {
+ if (VpdInit(pAC,IoC) != 0 ) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
+ ("vpd init error\n")) ;
+ return ;
+ }
+ }
+
+ len = strlen(msg) ;
+ if (len > VPD_MAX_LEN) {
+ /* cut it */
+ len = VPD_MAX_LEN ;
+ }
+ if ((v = vpd_find_para(pAC,VPD_VF,&vf))) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("overwrite VL\n")) ;
+ (void)VpdSetupPara(pAC,VPD_VL,msg,len,VPD_RW_KEY,OWR_KEY) ;
+ } else {
+ SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("write VF\n")) ;
+ (void)VpdSetupPara(pAC,VPD_VF,msg,len,VPD_RW_KEY,ADD_KEY) ;
+ }
+
+ (void)VpdUpdate(pAC,IoC) ;
+}
+
--- /dev/null
+/******************************************************************************
+ *
+ * Name: skxmac2.c
+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
+ * Version: $Revision: 1.49 $
+ * Date: $Date: 1999/11/22 08:12:13 $
+ * Purpose: Contains functions to initialize the XMAC II
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * See the file "skge.c" for further information.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ * $Log: skxmac2.c,v $
+ * Revision 1.49 1999/11/22 08:12:13 malthoff
+ * Add workaround for power consumption feature of Bcom C0 chip.
+ *
+ * Revision 1.48 1999/11/16 08:39:01 malthoff
+ * Fix: MDIO preamble suppression is port dependend.
+ *
+ * Revision 1.47 1999/08/27 08:55:35 malthoff
+ * 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble.
+ *
+ * Revision 1.46 1999/08/13 11:01:12 malthoff
+ * Fix for 1000BT: pFlowCtrlMode was not set correctly.
+ *
+ * Revision 1.45 1999/08/12 19:18:28 malthoff
+ * 1000BT Fixes: Do not owerwrite XM_MMU_CMD.
+ * Do not execute BCOM A1 workaround for B1 chips.
+ * Fix pause frame setting.
+ * Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL.
+ *
+ * Revision 1.44 1999/08/03 15:23:48 cgoos
+ * Fixed setting of PHY interrupt mask in half duplex mode.
+ *
+ * Revision 1.43 1999/08/03 15:22:17 cgoos
+ * Added some debug output.
+ * Disabled XMac GP0 interrupt for external PHYs.
+ *
+ * Revision 1.42 1999/08/02 08:39:23 malthoff
+ * BCOM PHY: TX LED: To get the mono flop behaviour it is required
+ * to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL.
+ *
+ * Revision 1.41 1999/07/30 06:54:31 malthoff
+ * Add temp. workarounds for the BCOM Phy revision A1.
+ *
+ * Revision 1.40 1999/06/01 07:43:26 cgoos
+ * Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to
+ * AUTOFULL/AUTOHALF.
+ *
+ * Revision 1.39 1999/05/19 07:29:51 cgoos
+ * Changes for 1000Base-T.
+ *
+ * Revision 1.38 1999/04/08 14:35:10 malthoff
+ * Add code for enabling signal detect. Enabling signal
+ * detect is disabled.
+ *
+ * Revision 1.37 1999/03/12 13:42:54 malthoff
+ * Add: Jumbo Frame Support.
+ * Add: Receive modes SK_LENERR_OK_ON/OFF and
+ * SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd().
+ *
+ * Revision 1.36 1999/03/08 10:10:55 gklug
+ * fix: AutoSensing did switch to next mode even if LiPa indicated offline
+ *
+ * Revision 1.35 1999/02/22 15:16:41 malthoff
+ * Remove some compiler warnings.
+ *
+ * Revision 1.34 1999/01/22 09:19:59 gklug
+ * fix: Init DupMode and InitPauseMd are now called in RxTxEnable
+ *
+ * Revision 1.33 1998/12/11 15:19:11 gklug
+ * chg: lipa autoneg stati
+ * chg: debug messages
+ * chg: do NOT use spurious XmIrq
+ *
+ * Revision 1.32 1998/12/10 11:08:44 malthoff
+ * bug fix: pAC has been used for IOs in SkXmHardRst().
+ * SkXmInitPhy() is also called for the Diag in SkXmInitMac().
+ *
+ * Revision 1.31 1998/12/10 10:39:11 gklug
+ * fix: do 4 RESETS of the XMAC at the beginning
+ * fix: dummy read interrupt source register BEFORE initializing the Phy
+ * add: debug messages
+ * fix: Linkpartners autoneg capability cannot be shown by TX_PAGE interrupt
+ *
+ * Revision 1.30 1998/12/07 12:18:32 gklug
+ * add: refinement of autosense mode: take into account the autoneg cap of LiPa
+ *
+ * Revision 1.29 1998/12/07 07:12:29 gklug
+ * fix: if page is received the link is down.
+ *
+ * Revision 1.28 1998/12/01 10:12:47 gklug
+ * chg: if spurious IRQ from XMAC encountered, save it
+ *
+ * Revision 1.27 1998/11/26 07:33:38 gklug
+ * add: InitPhy call is now in XmInit function
+ *
+ * Revision 1.26 1998/11/18 13:38:24 malthoff
+ * 'Imsk' is also unused in SkXmAutoNegDone.
+ *
+ * Revision 1.25 1998/11/18 13:28:01 malthoff
+ * Remove unused variable 'Reg' in SkXmAutoNegDone().
+ *
+ * Revision 1.24 1998/11/18 13:18:45 gklug
+ * add: workaround for xmac errata #1
+ * add: detect Link Down also when Link partner requested config
+ * chg: XMIrq is only used when link is up
+ *
+ * Revision 1.23 1998/11/04 07:07:04 cgoos
+ * Added function SkXmRxTxEnable.
+ *
+ * Revision 1.22 1998/10/30 07:35:54 gklug
+ * fix: serve LinkDown interrupt when link is already down
+ *
+ * Revision 1.21 1998/10/29 15:32:03 gklug
+ * fix: Link Down signaling
+ *
+ * Revision 1.20 1998/10/29 11:17:27 gklug
+ * fix: AutoNegDone bug
+ *
+ * Revision 1.19 1998/10/29 10:14:43 malthoff
+ * Add endainesss comment for reading/writing MAC addresses.
+ *
+ * Revision 1.18 1998/10/28 07:48:55 cgoos
+ * Fix: ASS somtimes signaled although link is up.
+ *
+ * Revision 1.17 1998/10/26 07:55:39 malthoff
+ * Fix in SkXmInitPauseMd(): Pause Mode
+ * was disabled and not enabled.
+ * Fix in SkXmAutoNegDone(): Checking Mode bits
+ * always failed, becaues of some missing braces.
+ *
+ * Revision 1.16 1998/10/22 09:46:52 gklug
+ * fix SysKonnectFileId typo
+ *
+ * Revision 1.15 1998/10/21 05:51:37 gklug
+ * add: para DoLoop to InitPhy function for loopback set-up
+ *
+ * Revision 1.14 1998/10/16 10:59:23 malthoff
+ * Remove Lint warning for dummy reads.
+ *
+ * Revision 1.13 1998/10/15 14:01:20 malthoff
+ * Fix: SkXmAutoNegDone() is (int) but does not return a value.
+ *
+ * Revision 1.12 1998/10/14 14:45:04 malthoff
+ * Remove SKERR_SIRQ_E0xx and SKERR_SIRQ_E0xxMSG by
+ * SKERR_HWI_Exx and SKERR_HWI_E0xxMSG to be independant
+ * from the Sirq module.
+ *
+ * Revision 1.11 1998/10/14 13:59:01 gklug
+ * add: InitPhy function
+ *
+ * Revision 1.10 1998/10/14 11:20:57 malthoff
+ * Make SkXmAutoNegDone() public, because it's
+ * used in diagnostics, too.
+ * The Link Up event to the RLMT is issued in
+ * SkXmIrq(). SkXmIrq() is not available in
+ * diagnostics. Use PHY_READ when reading
+ * PHY registers.
+ *
+ * Revision 1.9 1998/10/14 05:50:10 cgoos
+ * Added definition for Para.
+ *
+ * Revision 1.8 1998/10/14 05:41:28 gklug
+ * add: Xmac IRQ
+ * add: auto negotiation done function
+ *
+ * Revision 1.7 1998/10/09 06:55:20 malthoff
+ * The configuration of the XMACs Tx Request Threshold
+ * depends from the drivers port usage now. The port
+ * usage is configured in GIPortUsage.
+ *
+ * Revision 1.6 1998/10/05 07:48:00 malthoff
+ * minor changes
+ *
+ * Revision 1.5 1998/10/01 07:03:54 gklug
+ * add: dummy function for XMAC ISR
+ *
+ * Revision 1.4 1998/09/30 12:37:44 malthoff
+ * Add SkXmSetRxCmd() and related code.
+ *
+ * Revision 1.3 1998/09/28 13:26:40 malthoff
+ * Add SkXmInitMac(), SkXmInitDupMd(), and SkXmInitPauseMd()
+ *
+ * Revision 1.2 1998/09/16 14:34:21 malthoff
+ * Add SkXmClrExactAddr(), SkXmClrSrcCheck(),
+ * SkXmClrHashAddr(), SkXmFlushTxFifo(),
+ * SkXmFlushRxFifo(), and SkXmHardRst().
+ * Finish Coding of SkXmSoftRst().
+ * The sources may be compiled now.
+ *
+ * Revision 1.1 1998/09/04 10:05:56 malthoff
+ * Created.
+ *
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/xmac_ii.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+/* typedefs *******************************************************************/
+/* global variables ***********************************************************/
+
+/* local variables ************************************************************/
+
+static const char SysKonnectFileId[] =
+ "@(#)$Id: skxmac2.c,v 1.49 1999/11/22 08:12:13 malthoff Exp $ (C) SK ";
+
+/* BCOM PHY magic pattern list */
+typedef struct s_PhyHack {
+ int PhyReg; /* Phy register */
+ SK_U16 PhyVal; /* Value to write */
+} BCOM_HACK;
+
+BCOM_HACK BcomRegA1Hack[] = {
+ { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
+ { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
+ { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
+ { 0, 0 }
+};
+BCOM_HACK BcomRegC0Hack[] = {
+ { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 },
+ { 0x15, 0x0A04 }, { 0x18, 0x0420 },
+ { 0, 0 }
+};
+
+/* function prototypes ********************************************************/
+static void SkXmInitPhyXmac(SK_AC*, SK_IOC, int, SK_BOOL);
+static void SkXmInitPhyBcom(SK_AC*, SK_IOC, int, SK_BOOL);
+static void SkXmInitPhyLone(SK_AC*, SK_IOC, int, SK_BOOL);
+static void SkXmInitPhyNat (SK_AC*, SK_IOC, int, SK_BOOL);
+static int SkXmAutoNegDoneXmac(SK_AC*, SK_IOC, int);
+static int SkXmAutoNegDoneBcom(SK_AC*, SK_IOC, int);
+static int SkXmAutoNegDoneLone(SK_AC*, SK_IOC, int);
+static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int);
+
+/******************************************************************************
+ *
+ * SkXmSetRxCmd() - Modify the value of the XMACs Rx Command Register
+ *
+ * Description:
+ * The features
+ * o FCS stripping, SK_STRIP_FCS_ON/OFF
+ * o pad byte stripping, SK_STRIP_PAD_ON/OFF
+ * o don't set XMR_FS_ERR in frame SK_LENERR_OK_ON/OFF
+ * status for inrange length error
+ * frames, and
+ * o don't set XMR_FS_ERR in frame SK_BIG_PK_OK_ON/OFF
+ * status for frames > 1514 bytes
+ *
+ * for incomming packets may be enabled/disabled by this function.
+ * Additional modes may be added later.
+ * Multiple modes can be enabled/disabled at the same time.
+ * The new configuration is stored into the HWAC port configuration
+ * and is written to the Receive Command register immediatlely.
+ * The new configuration is saved over any SkGePortStop() and
+ * SkGeInitPort() calls. The configured value will be overwritten
+ * when SkGeInit(Level 0) is executed.
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmSetRxCmd(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* The XMAC to handle with belongs to this Port */
+int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
+ SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 OldRxMode;
+
+ pPrt = &pAC->GIni.GP[Port];
+ OldRxMode = pPrt->PRxCmd;
+
+ switch(Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
+ case SK_STRIP_FCS_ON:
+ pPrt->PRxCmd |= XM_RX_STRIP_FCS;
+ break;
+ case SK_STRIP_FCS_OFF:
+ pPrt->PRxCmd &= ~XM_RX_STRIP_FCS;
+ break;
+ }
+
+ switch(Mode & (SK_STRIP_PAD_ON | SK_STRIP_PAD_OFF)) {
+ case SK_STRIP_PAD_ON:
+ pPrt->PRxCmd |= XM_RX_STRIP_PAD;
+ break;
+ case SK_STRIP_PAD_OFF:
+ pPrt->PRxCmd &= ~XM_RX_STRIP_PAD;
+ break;
+ }
+
+ switch(Mode & (SK_LENERR_OK_ON | SK_LENERR_OK_OFF)) {
+ case SK_LENERR_OK_ON:
+ pPrt->PRxCmd |= XM_RX_LENERR_OK;
+ break;
+ case SK_LENERR_OK_OFF:
+ pPrt->PRxCmd &= ~XM_RX_LENERR_OK;
+ break;
+ }
+
+ switch(Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) {
+ case SK_BIG_PK_OK_ON:
+ pPrt->PRxCmd |= XM_RX_BIG_PK_OK;
+ break;
+ case SK_BIG_PK_OK_OFF:
+ pPrt->PRxCmd &= ~XM_RX_BIG_PK_OK;
+ break;
+ }
+
+ /* Write the new mode to the receive command register if required */
+ if (OldRxMode != pPrt->PRxCmd) {
+ XM_OUT16(IoC, Port, XM_RX_CMD, pPrt->PRxCmd);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmClrExactAddr() - Clear Exact Match Address Registers
+ *
+ * Description:
+ * All Exact Match Address registers of the XMAC 'Port' will be
+ * cleared starting with 'StartNum' up to (and including) the
+ * Exact Match address number of 'StopNum'.
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmClrExactAddr(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* The XMAC to handle with belongs to this Port */
+int StartNum, /* Begin with this Address Register Index (0..15) */
+int StopNum) /* Stop after finished with this Register Idx (0..15) */
+{
+ int i;
+ SK_U16 ZeroAddr[3] = { 0x0000, 0x0000, 0x0000 };
+
+ if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
+ StartNum > StopNum) {
+
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E001, SKERR_HWI_E001MSG);
+ return;
+ }
+
+ for (i = StartNum; i <= StopNum; i++) {
+ XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmClrSrcCheck() - Clear Source Check Address Register
+ *
+ * Description:
+ * The Source Check Address Register of the XMAC 'Port' number
+ * will be cleared.
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmClrSrcCheck(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* The XMAC to handle with belongs to this Port (MAC_1 + n) */
+{
+ SK_U16 ZeroAddr[3] = { 0x0000, 0x0000, 0x0000 };
+
+ XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
+}
+
+/******************************************************************************
+ *
+ * SkXmClrHashAddr() - Clear Hash Address Registers
+ *
+ * Description:
+ * The Hash Address Register of the XMAC 'Port' will be cleared.
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmClrHashAddr(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* The XMAC to handle with belongs to this Port (MAC_1 + n) */
+{
+ SK_U16 ZeroAddr[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
+
+ XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
+}
+
+/******************************************************************************
+ *
+ * SkXmFlushTxFifo() - Flush the XMACs transmit FIFO
+ *
+ * Description:
+ * Flush the transmit FIFO of the XMAC specified by the index 'Port'
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmFlushTxFifo(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* The XMAC to handle with belongs to this Port (MAC_1 + n) */
+{
+ SK_U32 MdReg;
+
+ XM_IN32(IoC, Port, XM_MODE, &MdReg);
+ MdReg |= XM_MD_FTF;
+ XM_OUT32(IoC, Port, XM_MODE, MdReg);
+}
+
+/******************************************************************************
+ *
+ * SkXmFlushRxFifo() - Flush the XMACs receive FIFO
+ *
+ * Description:
+ * Flush the receive FIFO of the XMAC specified by the index 'Port'
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmFlushRxFifo(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* The XMAC to handle with belongs to this Port (MAC_1 + n) */
+{
+ SK_U32 MdReg;
+
+ XM_IN32(IoC, Port, XM_MODE, &MdReg);
+ MdReg |= XM_MD_FRF;
+ XM_OUT32(IoC, Port, XM_MODE, MdReg);
+}
+
+/******************************************************************************
+ *
+ * SkXmSoftRst() - Do a XMAC software reset
+ *
+ * Description:
+ * The PHY registers should not be destroyed during this
+ * kind of software reset. Therefore the XMAC Software Reset
+ * (XM_GP_RES_MAC bit in XM_GP_PORT) must not be used!
+ *
+ * The software reset is done by
+ * - disabling the Rx and Tx state maschine,
+ * - reseting the statistics module,
+ * - clear all other significant XMAC Mode,
+ * Command, and Control Registers
+ * - clearing the Hash Register and the
+ * Exact Match Address registers, and
+ * - flushing the XMAC's Rx and Tx FIFOs.
+ *
+ * Note:
+ * Another requirement when stopping the XMAC is to
+ * avoid sending corrupted frames on the network.
+ * Disabling the Tx state maschine will NOT interrupt
+ * the currently transmitted frame. But we must take care
+ * that the tx FIFO is cleared AFTER the current frame
+ * is complete sent to the network.
+ *
+ * It takes about 12ns to send a frame with 1538 bytes.
+ * One PCI clock goes at least 15ns (66MHz). Therefore
+ * after reading XM_GP_PORT back, we are sure that the
+ * transmitter is disabled AND idle. And this means
+ * we may flush the transmit FIFO now.
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmSoftRst(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* port to stop (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Word;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* disable the receiver and transmitter */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX|XM_MMU_ENA_TX));
+
+ /* reset the statistics module */
+ XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
+
+ /*
+ * clear all other significant XMAC Mode,
+ * Command, and Control Registers
+ */
+ XM_OUT16(IoC, Port, XM_IMSK, 0xffff); /* disable all IRQs */
+ XM_OUT32(IoC, Port, XM_MODE, 0x00000000); /* clear Mode Reg */
+ XM_OUT16(IoC, Port, XM_TX_CMD, 0x0000); /* reset TX CMD Reg */
+ XM_OUT16(IoC, Port, XM_RX_CMD, 0x0000); /* reset RX CMD Reg */
+
+ /* disable all PHY IRQs */
+ switch (pAC->GIni.GP[Port].PhyType) {
+ case SK_PHY_BCOM:
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_INT_MASK,
+ 0xffff);
+ break;
+ case SK_PHY_LONE:
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_INT_ENAB,
+ 0x0);
+ break;
+ case SK_PHY_NAT:
+ /* todo: National
+ PHY_WRITE(IoC, pPrt, Port, PHY_NAT_INT_MASK,
+ 0xffff); */
+ break;
+ }
+
+ /* clear the Hash Register */
+ SkXmClrHashAddr(pAC, IoC, Port);
+
+ /* clear the Exact Match Address registers */
+ SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
+ SkXmClrSrcCheck(pAC, IoC, Port);
+
+ /* flush the XMAC's Rx and Tx FIFOs */
+ SkXmFlushTxFifo(pAC, IoC, Port);
+ SkXmFlushRxFifo(pAC, IoC, Port);
+
+ pAC->GIni.GP[Port].PState = SK_PRT_STOP;
+}
+
+/******************************************************************************
+ *
+ * SkXmHardRst() - Do a XMAC hardware reset
+ *
+ * Description:
+ * The XMAC of the specified 'Port' and all connected devices
+ * (PHY and SERDES) will receive a reset signal on its *Reset
+ * pins.
+ * External PHYs must be reset be clearing a bit in the GPIO
+ * register (Timing requirements: Broadcom: 400ns, Level One:
+ * none, National: 80ns).
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmHardRst(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* port to stop (MAC_1 + n) */
+{
+ SK_U16 Word;
+ int i;
+ SK_U32 Reg;
+
+ for (i=0; i<4; i++) {
+ /* TX_MFF_CTRL1 is a 32 bit register but only the lowest 16 */
+ /* bit contains buttoms to press */
+ SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1),
+ (SK_U16) MFF_CLR_MAC_RST);
+ SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1),
+ (SK_U16) MFF_SET_MAC_RST);
+ do {
+ SK_IN16(IoC,MR_ADDR(Port,TX_MFF_CTRL1), &Word);
+ } while ((Word & MFF_SET_MAC_RST) == 0);
+ }
+ if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
+
+ /* reset external PHY */
+ SK_IN32(IoC, B2_GP_IO, &Reg);
+ if (Port == 0) {
+ Reg |= GP_DIR_0; /* set to output */
+ Reg &= ~GP_IO_0;
+ }
+ else {
+ Reg |= GP_DIR_2; /* set to output */
+ Reg &= ~GP_IO_2;
+ }
+ SK_OUT32(IoC, B2_GP_IO, Reg);
+
+ /* short delay */
+ SK_IN32(IoC, B2_GP_IO, &Reg);
+ }
+
+ pAC->GIni.GP[Port].PState = SK_PRT_RESET;
+}
+
+/******************************************************************************
+ *
+ * SkXmInitMac() - Initialize the XMAC II
+ *
+ * Description:
+ * Initialize all the XMAC of the specified port.
+ * The XMAC must be reset or stopped before calling this function.
+ *
+ * Note:
+ * The XMACs Rx and Tx state machine is still disabled when
+ * returning.
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmInitMac(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 SWord;
+ int i;
+ SK_U32 Reg;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PState == SK_PRT_STOP) {
+ /* Port State: SK_PRT_STOP */
+ /* Verify that the reset bit is cleared */
+ SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
+ if (SWord & (SK_U16) MFF_SET_MAC_RST) {
+ /* PState does not match HW state */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006,
+ SKERR_HWI_E006MSG);
+ /* correct it */
+ pPrt->PState = SK_PRT_RESET;
+ }
+ }
+ if (pPrt->PState == SK_PRT_RESET) {
+ /*
+ * clear HW reset
+ * Note: The SW reset is self clearing, therefore there is
+ * nothing to do here.
+ */
+ SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1),
+ (SK_U16) MFF_CLR_MAC_RST);
+
+ /*
+ * clear PHY reset
+ */
+ if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
+
+ SK_IN32(IoC, B2_GP_IO, &Reg);
+ if (Port == 0) {
+ Reg |= GP_DIR_0; /* set to output */
+ Reg |= GP_IO_0;
+ }
+ else {
+ Reg |= GP_DIR_2; /* set to output */
+ Reg |= GP_IO_2;
+ }
+ SK_OUT32(IoC, B2_GP_IO, Reg);
+
+ /* enable GMII interface */
+ XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
+
+ /* optimize MDIO transfer by oppressing preamble */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
+ XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
+
+ /* Workaround BCOM Errata for the A1 type */
+ /* Write magic patterns to reserved registers */
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_ID1, &SWord);
+ if (SWord == 0x6041) {
+ i = 0;
+ while (BcomRegA1Hack[i].PhyReg != 0) {
+ PHY_WRITE(IoC, pPrt, Port,
+ BcomRegA1Hack[i].PhyReg,
+ BcomRegA1Hack[i].PhyVal);
+ i++;
+ }
+ }
+ /* Workaround BCOM Errata for the C0 type */
+ /* Write magic patterns to reserved registers */
+ if (SWord == 0x6044) {
+ i = 0;
+ while (BcomRegC0Hack[i].PhyReg != 0) {
+ PHY_WRITE(IoC, pPrt, Port,
+ BcomRegC0Hack[i].PhyReg,
+ BcomRegC0Hack[i].PhyVal);
+ i++;
+ }
+ }
+
+ /*
+ * PHY LED initialization is performed in
+ * SkGeXmitLED() (but not here).
+ */
+ }
+
+ /* Dummy read the Interrupt source register */
+ XM_IN16(IoC, Port, XM_ISRC, &SWord);
+
+ /*
+ * The autonegotiation process starts immediately after
+ * clearing the reset. Autonegotiation process should be
+ * started by the SIRQ, therefore stop it here immediately.
+ */
+ SkXmInitPhy(pAC, IoC, Port, SK_FALSE);
+
+#if 0
+ /* temp. code: enable signal detect */
+ /* WARNING: do not override GMII setting above */
+ XM_OUT16(pAC, Port, XM_HW_CFG, XM_HW_COM4SIG);
+#endif
+ }
+
+ /*
+ * configure the XMACs Station Address
+ * B2_MAC_2 = xx xx xx xx xx x1 is programed to XMAC A
+ * B2_MAC_3 = xx xx xx xx xx x2 is programed to XMAC B
+ */
+ for (i = 0; i < 3; i++) {
+ /*
+ * The following 2 statements are together endianess
+ * independant. Remember this when changing.
+ */
+ SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
+ XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
+ }
+
+ /* Tx Inter Packet Gap (XM_TX_IPG): use default */
+ /* Tx High Water Mark (XM_TX_HI_WM): use default */
+ /* Tx Low Water Mark (XM_TX_LO_WM): use default */
+ /* Host Request Threshold (XM_HT_THR): use default */
+ /* Rx Request Threshold (XM_RX_THR): use default */
+ /* Rx Low Water Mark (XM_RX_LO_WM): use default */
+
+ /* configure Rx High Water Mark (XM_RX_HI_WM) */
+ XM_OUT16(IoC, Port, XM_RX_HI_WM, 0x05aa);
+
+ if (pAC->GIni.GIMacsFound > 1) {
+ switch (pAC->GIni.GIPortUsage) {
+ case SK_RED_LINK:
+ /* Configure Tx Request Threshold for red. link */
+ XM_OUT16(IoC, Port, XM_TX_THR, SK_XM_THR_REDL);
+ break;
+ case SK_MUL_LINK:
+ /* Configure Tx Request Threshold for load bal. */
+ XM_OUT16(IoC, Port, XM_TX_THR, SK_XM_THR_MULL);
+ break;
+ case SK_JUMBO_LINK:
+ /* Configure Tx Request Threshold for jumbo frames */
+ XM_OUT16(IoC, Port, XM_TX_THR, SK_XM_THR_JUMBO);
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E014,
+ SKERR_HWI_E014MSG);
+ break;
+ }
+ }
+ else {
+ /* Configure Tx Request Threshold for single port */
+ XM_OUT16(IoC, Port, XM_TX_THR, SK_XM_THR_SL);
+ }
+
+ /*
+ * setup register defaults for the Rx Command Register
+ * - Enable Automatic Frame Padding on Tx side
+ */
+ XM_OUT16(IoC, Port, XM_TX_CMD, XM_TX_AUTO_PAD);
+
+ /*
+ * setup register defaults for the Rx Command Register,
+ * program value of PRxCmd
+ */
+ XM_OUT16(IoC, Port, XM_RX_CMD, pPrt->PRxCmd);
+
+ /*
+ * setup register defaults for the Mode Register
+ * - Don't strip error frames to avoid Store & Forward
+ * on the rx side.
+ * - Enable 'Check Station Address' bit
+ * - Enable 'Check Address Array' bit
+ */
+ XM_OUT32(IoC, Port, XM_MODE, XM_DEF_MODE);
+
+ /*
+ * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
+ * - Enable all bits excepting 'Octets Rx OK Low CntOv'
+ * and 'Octets Rx OK Hi Cnt Ov'.
+ */
+ XM_OUT32(IoC, Port, XM_RX_EV_MSK, XMR_DEF_MSK);
+
+ /*
+ * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
+ * - Enable all bits excepting 'Octets Tx OK Low CntOv'
+ * and 'Octets Tx OK Hi Cnt Ov'.
+ */
+ XM_OUT32(IoC, Port, XM_TX_EV_MSK, XMT_DEF_MSK);
+
+ /*
+ * Do NOT init XMAC interrupt mask here.
+ * All interrupts remain disable until link comes up!
+ */
+ pPrt->PState = SK_PRT_INIT;
+
+ /*
+ * Any additional configuration changes may be done now.
+ * The last action is to enable the rx and tx state machine.
+ * This should be done after the autonegotiation process
+ * has been completed successfully.
+ */
+}
+
+/******************************************************************************
+ *
+ * SkXmInitDupMd() - Initialize the XMACs Duplex Mode
+ *
+ * Description:
+ * This function initilaizes the XMACs Duplex Mode.
+ * It should be called after successfully finishing
+ * the Autonegotiation Process
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmInitDupMd(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ switch (pAC->GIni.GP[Port].PLinkModeStatus) {
+ case SK_LMODE_STAT_AUTOHALF:
+ case SK_LMODE_STAT_HALF:
+ /* Configuration Actions for Half Duplex Mode */
+ /*
+ * XM_BURST = default value. We are propable not quick
+ * enough at the 'XMAC' bus to burst 8kB.
+ * The XMAC stopps bursting if no transmit frames
+ * are available or the burst limit is exceeded.
+ */
+ /* XM_TX_RT_LIM = default value (15) */
+ /* XM_TX_STIME = default value (0xff = 4096 bit times) */
+ break;
+ case SK_LMODE_STAT_AUTOFULL:
+ case SK_LMODE_STAT_FULL:
+ /* Configuration Actions for Full Duplex Mode */
+ /*
+ * The duplex mode is configured by the PHY,
+ * therefore it seems to be that there is nothing
+ * to do here.
+ */
+ break;
+ case SK_LMODE_STAT_UNKNOWN:
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E007, SKERR_HWI_E007MSG);
+ break;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmInitPauseMd() - initialize the Pause Mode to be used for this port
+ *
+ * Description:
+ * This function initilaizes the Pause Mode which should
+ * be used for this port.
+ * It should be called after successfully finishing
+ * the Autonegotiation Process
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmInitPauseMd(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Word;
+ SK_U32 DWord;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
+ pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
+
+ /* Disable Pause Frame Reception */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_IGN_PF);
+ }
+ else {
+ /*
+ * enabling pause frame reception is required for 1000BT
+ * because the XMAC is not reset if the link is going down
+ */
+ /* Enable Pause Frame Reception */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~XM_MMU_IGN_PF);
+ }
+
+ if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC ||
+ pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
+
+ /*
+ * Configure Pause Frame Generation
+ * Use internal and external Pause Frame Generation.
+ * Sending pause frames is edge triggert. Send a
+ * Pause frame with the maximum pause time if
+ * internal oder external FIFO full condition
+ * occurs. Send a zero pause time frame to
+ * start transmission again.
+ */
+
+ /* XM_PAUSE_DA = '010000C28001' (default) */
+
+ /* XM_MAC_PTIME = 0xffff (maximum) */
+ /* remember this value is defined in big endian (!) */
+ XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
+
+ /* Set Pause Mode in Mode Register */
+ XM_IN32(IoC, Port, XM_MODE, &DWord);
+ XM_OUT32(IoC, Port, XM_MODE, DWord | XM_PAUSE_MODE);
+
+ /* Set Pause Mode in MAC Rx FIFO */
+ SK_OUT16(IoC, MR_ADDR(Port,RX_MFF_CTRL1), MFF_ENA_PAUSE);
+ }
+ else {
+ /*
+ * disable pause frame generation is required for 1000BT
+ * because the XMAC is not reset if the link is going down
+ */
+ /* Disable Pause Mode in Mode Register */
+ XM_IN32(IoC, Port, XM_MODE, &DWord);
+ XM_OUT32(IoC, Port, XM_MODE, DWord & ~XM_PAUSE_MODE);
+
+ /* Disable Pause Mode in MAC Rx FIFO */
+ SK_OUT16(IoC, MR_ADDR(Port,RX_MFF_CTRL1), MFF_DIS_PAUSE);
+ }
+
+}
+
+
+/******************************************************************************
+ *
+ * SkXmInitPhy() - Initialize the XMAC II Phy registers
+ *
+ * Description:
+ * Initialize all the XMACs Phy registers
+ *
+ * Note:
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmInitPhy(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL DoLoop) /* Should a Phy LOOback be set-up? */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+ switch (pPrt->PhyType) {
+ case SK_PHY_XMAC:
+ SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
+ break;
+ case SK_PHY_BCOM:
+ SkXmInitPhyBcom(pAC, IoC, Port, DoLoop);
+ break;
+ case SK_PHY_LONE:
+ SkXmInitPhyLone(pAC, IoC, Port, DoLoop);
+ break;
+ case SK_PHY_NAT:
+ SkXmInitPhyNat(pAC, IoC, Port, DoLoop);
+ break;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmInitPhyXmac() - Initialize the XMAC II Phy registers
+ *
+ * Description:
+ * Initialize all the XMACs Phy registers
+ *
+ * Note:
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmInitPhyXmac(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL DoLoop) /* Should a Phy LOOback be set-up? */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Crtl;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Autonegotiation ? */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyXmac: no autonegotiation Port %d\n", Port));
+ /* No Autonegiotiation */
+ /* Set DuplexMode in Config register */
+ Crtl = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);
+
+ /*
+ * Do NOT enable Autonegotiation here. This would hold
+ * the link down because no IDLES are transmitted
+ */
+ } else {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyXmac: with autonegotiation Port %d\n", Port));
+ /* Set Autonegotiation advertisement */
+ Crtl = 0;
+
+ /* Set Full/half duplex capabilities */
+ switch (pPrt->PLinkMode) {
+ case SK_LMODE_AUTOHALF:
+ Crtl |= PHY_X_AN_HD;
+ break;
+ case SK_LMODE_AUTOFULL:
+ Crtl |= PHY_X_AN_FD;
+ break;
+ case SK_LMODE_AUTOBOTH:
+ Crtl |= PHY_X_AN_FD | PHY_X_AN_HD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E015, SKERR_HWI_E015MSG) ;
+ }
+
+ switch (pPrt->PFlowCtrlMode) {
+ case SK_FLOW_MODE_NONE:
+ Crtl |= PHY_X_P_NO_PAUSE;
+ break;
+ case SK_FLOW_MODE_LOC_SEND:
+ Crtl |= PHY_X_P_ASYM_MD;
+ break;
+ case SK_FLOW_MODE_SYMMETRIC:
+ Crtl |= PHY_X_P_SYM_MD;
+ break;
+ case SK_FLOW_MODE_SYM_OR_REM:
+ Crtl |= PHY_X_P_BOTH_MD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E016, SKERR_HWI_E016MSG) ;
+ }
+
+ /* Write AutoNeg Advertisement Register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_XMAC_AUNE_ADV, Crtl) ;
+
+ /* Restart Autonegotiation */
+ Crtl = PHY_CT_ANE | PHY_CT_RE_CFG;
+ }
+
+ if (DoLoop) {
+ /* Set the Phy Loopback bit, too */
+ Crtl |= PHY_CT_LOOP;
+ }
+
+ /* Write to the Phy control register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_XMAC_CTRL, Crtl) ;
+}
+
+/******************************************************************************
+ *
+ * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers
+ *
+ * Description:
+ * Initialize all the Broadcom Phy registers
+ *
+ * Note:
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmInitPhyBcom(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL DoLoop) /* Should a Phy LOOback be set-up? */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Crtl1 = PHY_B_CT_SP1000;
+ SK_U16 Crtl2 = 0;
+ SK_U16 Crtl3 = PHY_SEL_TYPE;
+ SK_U16 Crtl4 = PHY_B_PEC_EN_LTR;
+ SK_U16 Crtl5 = PHY_B_AC_TX_TST;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* manuell Master/Slave ? */
+ if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
+ Crtl2 |= PHY_B_1000C_MSE;
+ if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
+ Crtl2 |= PHY_B_1000C_MSC;
+ }
+ }
+ /* Autonegotiation ? */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyBcom: no autonegotiation Port %d\n", Port));
+ /* No Autonegiotiation */
+ /* Set DuplexMode in Config register */
+ Crtl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);
+
+ /* Determine Master/Slave manuell if not already done */
+ if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
+ Crtl2 |= PHY_B_1000C_MSE; /* set it to Slave */
+ }
+
+ /*
+ * Do NOT enable Autonegotiation here. This would hold
+ * the link down because no IDLES are transmitted
+ */
+ } else {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyBcom: with autonegotiation Port %d\n", Port));
+ /* Set Autonegotiation advertisement */
+
+ /* Set Full/half duplex capabilities */
+ switch (pPrt->PLinkMode) {
+ case SK_LMODE_AUTOHALF:
+ Crtl2 |= PHY_B_1000C_AHD;
+ break;
+ case SK_LMODE_AUTOFULL:
+ Crtl2 |= PHY_B_1000C_AFD;
+ break;
+ case SK_LMODE_AUTOBOTH:
+ Crtl2 |= PHY_B_1000C_AFD | PHY_B_1000C_AHD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E015, SKERR_HWI_E015MSG) ;
+ }
+
+ switch (pPrt->PFlowCtrlMode) {
+ case SK_FLOW_MODE_NONE:
+ Crtl3 |= PHY_B_P_NO_PAUSE;
+ break;
+ case SK_FLOW_MODE_LOC_SEND:
+ Crtl3 |= PHY_B_P_ASYM_MD;
+ break;
+ case SK_FLOW_MODE_SYMMETRIC:
+ Crtl3 |= PHY_B_P_SYM_MD;
+ break;
+ case SK_FLOW_MODE_SYM_OR_REM:
+ Crtl3 |= PHY_B_P_BOTH_MD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E016, SKERR_HWI_E016MSG);
+ }
+
+ /* Restart Autonegotiation */
+ Crtl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
+
+ }
+
+ /* Initialize LED register here? */
+ /* No. Please do it in SkDgXmitLed() (if required) and swap
+ init order of LEDs and XMAC. (MAl) */
+
+ /* Write 1000Base-T Control Register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_1000T_CTRL, Crtl2);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("1000Base-T Control Reg = %x\n", Crtl2));
+
+ /* Write AutoNeg Advertisement Register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_AUNE_ADV, Crtl3);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg Advertisment Reg = %x\n", Crtl3));
+
+
+ if (DoLoop) {
+ /* Set the Phy Loopback bit, too */
+ Crtl1 |= PHY_CT_LOOP;
+ }
+
+ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
+ /* configure fifo to high latency for xmission of ext. packets*/
+ Crtl4 |= PHY_B_PEC_HIGH_LA;
+
+ /* configure reception of extended packets */
+ Crtl5 |= PHY_B_AC_LONG_PACK;
+
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_AUX_CTRL, Crtl5);
+ }
+
+ /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_P_EXT_CTRL, Crtl4);
+
+ /* Write to the Phy control register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_CTRL, Crtl1);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("PHY Control Reg = %x\n", Crtl1));
+}
+
+/******************************************************************************
+ *
+ * SkXmInitPhyLone() - Initialize the Level One Phy registers
+ *
+ * Description:
+ * Initialize all the Level One Phy registers
+ *
+ * Note:
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmInitPhyLone(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL DoLoop) /* Should a Phy LOOback be set-up? */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Crtl1 = PHY_L_CT_SP1000;
+ SK_U16 Crtl2 = 0;
+ SK_U16 Crtl3 = PHY_SEL_TYPE;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* manuell Master/Slave ? */
+ if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
+ Crtl2 |= PHY_L_1000C_MSE;
+ if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
+ Crtl2 |= PHY_L_1000C_MSC;
+ }
+ }
+ /* Autonegotiation ? */
+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
+ pPrt->PLinkMode == SK_LMODE_FULL) {
+ /*
+ * level one spec say: "1000Mbps: manual mode not allowed"
+ * but lets see what happens...
+ */
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ 0, "Level One PHY only works with Autoneg");
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyLone: no autonegotiation Port %d\n", Port));
+ /* No Autonegiotiation */
+ /* Set DuplexMode in Config register */
+ Crtl1 = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);
+
+ /* Determine Master/Slave manuell if not already done */
+ if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
+ Crtl2 |= PHY_L_1000C_MSE; /* set it to Slave */
+ }
+
+ /*
+ * Do NOT enable Autonegotiation here. This would hold
+ * the link down because no IDLES are transmitted
+ */
+ } else {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("InitPhyLone: with autonegotiation Port %d\n", Port));
+ /* Set Autonegotiation advertisement */
+
+ /* Set Full/half duplex capabilities */
+ switch (pPrt->PLinkMode) {
+ case SK_LMODE_AUTOHALF:
+ Crtl2 |= PHY_L_1000C_AHD;
+ break;
+ case SK_LMODE_AUTOFULL:
+ Crtl2 |= PHY_L_1000C_AFD;
+ break;
+ case SK_LMODE_AUTOBOTH:
+ Crtl2 |= PHY_L_1000C_AFD | PHY_L_1000C_AHD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E015, SKERR_HWI_E015MSG) ;
+ }
+
+ switch (pPrt->PFlowCtrlMode) {
+ case SK_FLOW_MODE_NONE:
+ Crtl3 |= PHY_L_P_NO_PAUSE;
+ break;
+ case SK_FLOW_MODE_LOC_SEND:
+ Crtl3 |= PHY_L_P_ASYM_MD;
+ break;
+ case SK_FLOW_MODE_SYMMETRIC:
+ Crtl3 |= PHY_L_P_SYM_MD;
+ break;
+ case SK_FLOW_MODE_SYM_OR_REM:
+ Crtl3 |= PHY_L_P_BOTH_MD;
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E016, SKERR_HWI_E016MSG);
+ }
+
+ /* Restart Autonegotiation */
+ Crtl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
+
+ }
+
+ /* Initialize LED register here ? */
+ /* No. Please do it in SkDgXmitLed() (if required) and swap
+ init order of LEDs and XMAC. (MAl) */
+
+ /* Write 1000Base-T Control Register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_1000T_CTRL, Crtl2);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("1000Base-T Control Reg = %x\n", Crtl2));
+
+ /* Write AutoNeg Advertisement Register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_AUNE_ADV, Crtl3);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNeg Advertisment Reg = %x\n", Crtl3));
+
+
+ if (DoLoop) {
+ /* Set the Phy Loopback bit, too */
+ Crtl1 |= PHY_CT_LOOP;
+ }
+
+ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
+ /*
+ * nothing to do for Level one.
+ * PHY supports frames up to 10k.
+ */
+ }
+
+ /* Write to the Phy control register */
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_CTRL, Crtl1);
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("PHY Control Reg = %x\n", Crtl1));
+}
+
+/******************************************************************************
+ *
+ * SkXmInitPhyNat() - Initialize the National Phy registers
+ *
+ * Description:
+ * Initialize all the National Phy registers
+ *
+ * Note:
+ *
+ * Returns:
+ * nothing
+ */
+static void SkXmInitPhyNat(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_BOOL DoLoop) /* Should a Phy LOOback be set-up? */
+{
+/* todo: National */
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do autoneg
+ *
+ * This function analyses the Interrupt status word. If any of the
+ * Autonegotiating interrupt bits are set, the PLipaAutoNeg variable
+ * is set true.
+ */
+void SkXmAutoNegLipaXmac(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U16 IStatus) /* Interrupt Status word to analyse */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
+ (IStatus & (XM_IS_LIPA_RC|XM_IS_RX_PAGE|XM_IS_AND))) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegLipa: AutoNeg detected on port %d %x\n", Port, IStatus));
+ pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegLipaBcom() - Decides whether Link Partner could do autoneg
+ *
+ * This function analyses the PHY status word. If any of the
+ * Autonegotiating bits are set, The PLipaAutoNeg variable
+ * is set true.
+ */
+void SkXmAutoNegLipaBcom(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U16 PhyStat) /* PHY Status word to analyse */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
+ (PhyStat & (PHY_ST_AN_OVER))) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegLipa: AutoNeg detected on port %d %x\n", Port, PhyStat));
+ pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegLipaLone() - Decides whether Link Partner could do autoneg
+ *
+ * This function analyses the PHY status word. If any of the
+ * Autonegotiating bits are set, The PLipaAutoNeg variable
+ * is set true.
+ */
+void SkXmAutoNegLipaLone(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U16 PhyStat) /* PHY Status word to analyse */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
+ (PhyStat & (PHY_ST_AN_OVER))) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegLipa: AutoNeg detected on port %d %x\n", Port, PhyStat));
+ pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+ }
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegLipaNat() - Decides whether Link Partner could do autoneg
+ *
+ * This function analyses the PHY status word. If any of the
+ * Autonegotiating bits are set, The PLipaAutoNeg variable
+ * is set true.
+ */
+void SkXmAutoNegLipaNat(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U16 PhyStat) /* PHY Status word to analyse */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
+ (PhyStat & (PHY_ST_AN_OVER))) {
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegLipa: AutoNeg detected on port %d %x\n", Port, PhyStat));
+ pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+ }
+}
+/******************************************************************************
+ *
+ * SkXmAutoNegDone() - Auto negotiation handling
+ *
+ * Description:
+ * This function handles the autonegotiation if the Done bit is set.
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ * o This function is public because it is used in the diagnostics
+ * tool, too.
+ *
+ * Returns:
+ * SK_AND_OK o.k.
+ * SK_AND_DUP_CAP Duplex capability error happened
+ * SK_AND_OTHER Other error happened
+ */
+int SkXmAutoNegDone(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ switch (pPrt->PhyType) {
+ case SK_PHY_XMAC:
+ return (SkXmAutoNegDoneXmac(pAC, IoC, Port));
+ case SK_PHY_BCOM:
+ return (SkXmAutoNegDoneBcom(pAC, IoC, Port));
+ case SK_PHY_LONE:
+ return (SkXmAutoNegDoneLone(pAC, IoC, Port));
+ case SK_PHY_NAT:
+ return (SkXmAutoNegDoneNat(pAC, IoC, Port));
+ }
+ return(SK_AND_OTHER);
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegDoneXmac() - Auto negotiation handling
+ *
+ * Description:
+ * This function handles the autonegotiation if the Done bit is set.
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ *
+ * Returns:
+ * SK_AND_OK o.k.
+ * SK_AND_DUP_CAP Duplex capability error happened
+ * SK_AND_OTHER Other error happened
+ */
+static int SkXmAutoNegDoneXmac(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 ResAb ; /* Resolved Ability */
+ SK_U16 LPAb ; /* Link Partner Ability */
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL, ("AutoNegDoneXmac"
+ "Port %d\n",Port));
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Get PHY parameters */
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_AUNE_LP, &LPAb);
+ PHY_READ(IoC, pPrt, Port, PHY_XMAC_RES_ABI, &ResAb);
+
+ if (LPAb & PHY_X_AN_RFB) {
+ /* At least one of the remote fault bit is set */
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegFail: Remote fault bit set Port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE ;
+ return (SK_AND_OTHER) ;
+ }
+
+ /* Check Duplex mismatch */
+ if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_FD) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL ;
+ } else if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_HD) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF ;
+ } else {
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegFail: Duplex mode mismatch port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE ;
+ return (SK_AND_DUP_CAP) ;
+ }
+
+ /* Check PAUSE mismatch */
+ /* We are NOT using chapter 4.23 of the Xaqti manual */
+ /* We are using IEEE 802.3z/D5.0 Table 37-4 */
+ if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
+ pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
+ (LPAb & PHY_X_P_SYM_MD)) {
+ /* Symmetric PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+ } else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
+ (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
+ /* Enable PAUSE receive, disable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
+ } else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
+ (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
+ /* Disable PAUSE receive, enable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
+ } else {
+ /* PAUSE mismatch -> no PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+ }
+
+ /* We checked everything and may now enable the link */
+ pPrt->PAutoNegFail = SK_FALSE ;
+
+ SkXmRxTxEnable(pAC, IoC, Port);
+ return(SK_AND_OK) ;
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegDoneBcom() - Auto negotiation handling
+ *
+ * Description:
+ * This function handles the autonegotiation if the Done bit is set.
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ *
+ * Returns:
+ * SK_AND_OK o.k.
+ * SK_AND_DUP_CAP Duplex capability error happened
+ * SK_AND_OTHER Other error happened
+ */
+static int SkXmAutoNegDoneBcom(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 ResAb ; /* Resolved Ability */
+ SK_U16 LPAb ; /* Link Partner Ability */
+ SK_U16 AuxStat; /* Auxiliary Status */
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL, ("AutoNegDoneBcom,"
+ " Port %d\n",Port));
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Get PHY parameters */
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_AUNE_LP, &LPAb);
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_1000T_STAT, &ResAb);
+ PHY_READ(IoC, pPrt, Port, PHY_BCOM_AUX_STAT, &AuxStat);
+
+ if (LPAb & PHY_B_AN_RF) {
+ /* Remote fault bit is set */
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegFail: Remote fault bit set Port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE ;
+ return (SK_AND_OTHER) ;
+ }
+
+ /* Check Duplex mismatch */
+ if ((AuxStat & PHY_B_AS_AN_RES) == PHY_B_RES_1000FD) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL ;
+ } else if ((AuxStat & PHY_B_AS_AN_RES) == PHY_B_RES_1000HD) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF ;
+ } else {
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegFail: Duplex mode mismatch port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE ;
+ return (SK_AND_DUP_CAP) ;
+ }
+
+ /* Check Master/Slave resolution */
+ if (ResAb & (PHY_B_1000S_MSF)) {
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("Master/Slave Fault port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE;
+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
+ return (SK_AND_OTHER);
+ } else if (ResAb & PHY_B_1000S_MSR) {
+ pPrt->PMSStatus = SK_MS_STAT_MASTER ;
+ } else {
+ pPrt->PMSStatus = SK_MS_STAT_SLAVE ;
+ }
+
+ /* Check PAUSE mismatch */
+ /* We are NOT using chapter 4.23 of the Xaqti manual */
+ /* We are using IEEE 802.3z/D5.0 Table 37-4 */
+ if ((AuxStat & (PHY_B_AS_PRR | PHY_B_AS_PRT)) ==
+ (PHY_B_AS_PRR | PHY_B_AS_PRT)) {
+ /* Symmetric PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+ } else if ((AuxStat & (PHY_B_AS_PRR | PHY_B_AS_PRT)) == PHY_B_AS_PRR) {
+ /* Enable PAUSE receive, disable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
+ } else if ((AuxStat & (PHY_B_AS_PRR | PHY_B_AS_PRT)) == PHY_B_AS_PRT) {
+ /* Disable PAUSE receive, enable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
+ } else {
+ /* PAUSE mismatch -> no PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+ }
+
+ /* We checked everything and may now enable the link */
+ pPrt->PAutoNegFail = SK_FALSE ;
+
+ SkXmRxTxEnable(pAC, IoC, Port);
+ return(SK_AND_OK) ;
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegDoneLone() - Auto negotiation handling
+ *
+ * Description:
+ * This function handles the autonegotiation if the Done bit is set.
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ *
+ * Returns:
+ * SK_AND_OK o.k.
+ * SK_AND_DUP_CAP Duplex capability error happened
+ * SK_AND_OTHER Other error happened
+ */
+static int SkXmAutoNegDoneLone(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 ResAb ; /* Resolved Ability */
+ SK_U16 LPAb ; /* Link Partner Ability */
+ SK_U16 QuickStat; /* Auxiliary Status */
+
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL, ("AutoNegDoneLone"
+ "Port %d\n",Port));
+ pPrt = &pAC->GIni.GP[Port];
+
+ /* Get PHY parameters */
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_AUNE_LP, &LPAb);
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_1000T_STAT, &ResAb);
+ PHY_READ(IoC, pPrt, Port, PHY_LONE_Q_STAT, &QuickStat);
+
+ if (LPAb & PHY_L_AN_RF) {
+ /* Remote fault bit is set */
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("AutoNegFail: Remote fault bit set Port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE ;
+ return (SK_AND_OTHER) ;
+ }
+
+ /* Check Duplex mismatch */
+ if (QuickStat & PHY_L_QS_DUP_MOD) {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL ;
+ } else {
+ pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF ;
+ }
+
+ /* Check Master/Slave resolution */
+ if (ResAb & (PHY_L_1000S_MSF)) {
+ /* Error */
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_CTRL,
+ ("Master/Slave Fault port %d\n", Port));
+ pPrt->PAutoNegFail = SK_TRUE;
+ pPrt->PMSStatus = SK_MS_STAT_FAULT ;
+ return (SK_AND_OTHER);
+ } else if (ResAb & PHY_L_1000S_MSR) {
+ pPrt->PMSStatus = SK_MS_STAT_MASTER ;
+ } else {
+ pPrt->PMSStatus = SK_MS_STAT_SLAVE ;
+ }
+
+ /* Check PAUSE mismatch */
+ /* We are NOT using chapter 4.23 of the Xaqti manual */
+ /* We are using IEEE 802.3z/D5.0 Table 37-4 */
+ /* we must manually resolve the abilities here */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+ switch (pPrt->PFlowCtrlMode) {
+ case SK_FLOW_MODE_NONE:
+ /* default */
+ break;
+ case SK_FLOW_MODE_LOC_SEND:
+ if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
+ (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
+ /* Disable PAUSE receive, enable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
+ }
+ break;
+ case SK_FLOW_MODE_SYMMETRIC:
+ if ((QuickStat & PHY_L_QS_PAUSE) == PHY_L_QS_PAUSE) {
+ /* Symmetric PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+ }
+ break;
+ case SK_FLOW_MODE_SYM_OR_REM:
+ if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
+ PHY_L_QS_AS_PAUSE) {
+ /* Enable PAUSE receive, disable PAUSE transmit */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
+ }
+ else if ((QuickStat & PHY_L_QS_PAUSE) == PHY_L_QS_PAUSE) {
+ /* Symmetric PAUSE */
+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+ }
+ break;
+ default:
+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT,
+ SKERR_HWI_E016, SKERR_HWI_E016MSG);
+ }
+
+ /* We checked everything and may now enable the link */
+ pPrt->PAutoNegFail = SK_FALSE ;
+
+ SkXmRxTxEnable(pAC, IoC, Port);
+ return(SK_AND_OK);
+}
+
+/******************************************************************************
+ *
+ * SkXmAutoNegDoneNat() - Auto negotiation handling
+ *
+ * Description:
+ * This function handles the autonegotiation if the Done bit is set.
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ * o This function is public because it is used in the diagnostics
+ * tool, too.
+ *
+ * Returns:
+ * SK_AND_OK o.k.
+ * SK_AND_DUP_CAP Duplex capability error happened
+ * SK_AND_OTHER Other error happened
+ */
+static int SkXmAutoNegDoneNat(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+/* todo: National */
+ return(SK_AND_OK);
+}
+
+/******************************************************************************
+ *
+ * SkXmRxTxEnable() - Enable RxTx activity if port is up
+ *
+ * Description:
+ *
+ * Note:
+ * o The XMACs interrupt source register is NOT read here.
+ *
+ * Returns:
+ * 0 o.k.
+ * != 0 Error happened
+ */
+int SkXmRxTxEnable(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port) /* Port Index (MAC_1 + n) */
+{
+ SK_GEPORT *pPrt;
+ SK_U16 Reg ; /* 16bit register value */
+ SK_U16 IntMask; /* XMac interrupt mask */
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (!pPrt->PHWLinkUp) {
+ /* The Hardware link is NOT up */
+ return(0) ;
+ }
+
+ if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
+ pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
+ pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
+ pPrt->PAutoNegFail) {
+ /* Autonegotiation is not done or failed */
+ return(0) ;
+ }
+
+ /* Set Dup Mode and Pause Mode */
+ SkXmInitDupMd (pAC, IoC, Port);
+ SkXmInitPauseMd (pAC, IoC, Port);
+
+ /*
+ * Initialize the Interrupt Mask Register. Default IRQs are...
+ * - Link Asynchronous Event
+ * - Link Partner requests config
+ * - Auto Negotiation Done
+ * - Rx Counter Event Overflow
+ * - Tx Counter Event Overflow
+ * - Transmit FIFO Underrun
+ */
+ if (pPrt->PhyType == SK_PHY_XMAC) {
+ IntMask = XM_DEF_MSK;
+ }
+ else {
+ /* disable GP0 interrupt bit */
+ IntMask = XM_DEF_MSK | XM_IS_INP_ASS;
+ }
+ XM_OUT16(IoC, Port, XM_IMSK, IntMask);
+
+ /* RX/TX enable */
+ XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
+ if (pPrt->PhyType != SK_PHY_XMAC &&
+ (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
+ pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
+ Reg |= XM_MMU_GMII_FD;
+ }
+ switch (pPrt->PhyType) {
+ case SK_PHY_BCOM:
+ PHY_WRITE(IoC, pPrt, Port, PHY_BCOM_INT_MASK,
+ PHY_B_DEF_MSK);
+ break;
+ case SK_PHY_LONE:
+ PHY_WRITE(IoC, pPrt, Port, PHY_LONE_INT_ENAB,
+ PHY_L_DEF_MSK);
+ break;
+ case SK_PHY_NAT:
+ /* todo National:
+ PHY_WRITE(IoC, pPrt, Port, PHY_NAT_INT_MASK,
+ PHY_N_DEF_MSK); */
+ /* no interrupts possible from National ??? */
+ break;
+ }
+ XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
+
+ return (0);
+}
+
+#ifndef SK_DIAG
+/******************************************************************************
+ *
+ * SkXmIrq() - Interrupt service routine
+ *
+ * Description:
+ * Services an Interrupt of the XMAC II
+ *
+ * Note:
+ * The XMACs interrupt source register is NOT read here.
+ * With an external PHY, some interrupt bits are not meaningfull
+ * any more:
+ * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
+ * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC
+ * - Page Received (bit #9) XM_IS_RX_PAGE
+ * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE
+ * - AutoNegDone (bit #7) XM_IS_AND
+ * Also probably not valid any more is the GP0 input bit:
+ * - GPRegisterBit0set XM_IS_INP_ASS
+ *
+ * Returns:
+ * nothing
+ */
+void SkXmIrq(
+SK_AC *pAC, /* adapter context */
+SK_IOC IoC, /* IO context */
+int Port, /* Port Index (MAC_1 + n) */
+SK_U16 IStatus) /* Interrupt status read from the XMAC */
+{
+ SK_GEPORT *pPrt;
+ SK_EVPARA Para;
+
+ pPrt = &pAC->GIni.GP[Port];
+
+ if (pPrt->PhyType != SK_PHY_XMAC) {
+ /* mask bits that are not used with ext. PHY */
+ IStatus &= ~(XM_IS_LNK_AE | XM_IS_LIPA_RC |
+ XM_IS_RX_PAGE | XM_IS_TX_PAGE |
+ XM_IS_AND | XM_IS_INP_ASS);
+ }
+
+ /*
+ * LinkPartner Autonegable ?
+ */
+ if (pPrt->PhyType == SK_PHY_XMAC) {
+ SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
+ }
+
+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+ ("XmacIrq Port %d Isr %x\n", Port, IStatus));
+
+ if (!pPrt->PHWLinkUp) {
+ /* Spurious XMAC interrupt */
+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+ ("SkXmIrq: spurious interrupt on port %d\n",
+ Port));
+ return;
+ }
+
+ if (IStatus & XM_IS_LNK_AE) {
+ /* not used GP0 is used instead */
+ }
+
+ if (IStatus & XM_IS_TX_ABORT) {
+ /* not used */
+ }
+
+ if (IStatus & XM_IS_FRC_INT) {
+ /* not used. use ASIC IRQ instead if needed */
+ }
+
+ if (IStatus & (XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE)) {
+ SkHWLinkDown(pAC, IoC, Port);
+
+ /* Signal to RLMT */
+ Para.Para32[0] = (SK_U32) Port;
+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+ /* Start workaround Errata #2 timer */
+ SkTimerStart(pAC, IoC, &pAC->GIni.GP[Port].PWaTimer,
+ SK_WA_INA_TIME,SKGE_HWAC,SK_HWEV_WATIM,Para);
+ }
+
+ if (IStatus & XM_IS_RX_PAGE) {
+ /* not used */
+ }
+
+ if (IStatus & XM_IS_TX_PAGE) {
+ /* not used */
+ }
+
+ if (IStatus & XM_IS_AND) {
+ SK_DBG_MSG(pAC,SK_DBGMOD_HWM,SK_DBGCAT_IRQ,
+ ("SkXmIrq: AND on link that is up port %d\n", Port));
+ }
+
+ if (IStatus & XM_IS_TSC_OV) {
+ /* not used */
+ }
+
+ if (IStatus & XM_IS_RXC_OV) {
+ Para.Para32[0] = (SK_U32) Port;
+ Para.Para32[1] = (SK_U32) IStatus;
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
+ }
+
+ if (IStatus & XM_IS_TXC_OV) {
+ Para.Para32[0] = (SK_U32) Port;
+ Para.Para32[1] = (SK_U32) IStatus;
+ SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
+ }
+
+ if (IStatus & XM_IS_RXF_OV) {
+ /* normal situation -> no effect */
+ }
+
+ if (IStatus & XM_IS_TXF_UR) {
+ /* may NOT happen -> error log */
+ SK_ERR_LOG(pAC, SK_ERRCL_HW , SKERR_SIRQ_E020,
+ SKERR_SIRQ_E020MSG) ;
+ }
+
+ if (IStatus & XM_IS_TX_COMP) {
+ /* not served here */
+ }
+
+ if (IStatus & XM_IS_RX_COMP) {
+ /* not served here */
+ }
+
+}
+#endif /* !SK_DIAG */
+
+/* End of file */
This is only in the support-all-kernels source code. */
#include <linux/version.h> /* Evil, but neccessary */
-#if defined (LINUX_VERSION_CODE) && LINUX_VERSION_CODE < 0x10300
-#define RUN_AT(x) (x) /* What to put in timer->expires. */
-#define DEV_ALLOC_SKB(len) alloc_skb(len, GFP_ATOMIC)
-#define virt_to_bus(addr) ((unsigned long)addr)
-#define bus_to_virt(addr) ((void*)addr)
-
-#else /* 1.3.0 and later */
#define RUN_AT(x) (jiffies + (x))
#define DEV_ALLOC_SKB(len) dev_alloc_skb(len + 2)
-#endif
-#if (LINUX_VERSION_CODE >= 0x10344)
#define NEW_MULTICAST
#include <linux/delay.h>
-#endif
+
#ifdef SA_SHIRQ
#define IRQ(irq, dev_id, pt_regs) (irq, dev_id, pt_regs)
#else
if (skb == NULL)
break; /* Bad news! */
skb->dev = dev; /* Mark as being used by this device. */
-#if LINUX_VERSION_CODE > 0x10300
tp->rx_ring[i].buffer1 = virt_to_bus(skb->tail);
-#else
- tp->rx_ring[i].buffer1 = virt_to_bus(skb->data);
-#endif
}
tp->rx_ring[i].buffer2 = virt_to_bus(&tp->rx_ring[i+1]);
}
&& (skb = DEV_ALLOC_SKB(pkt_len+2)) != NULL) {
skb->dev = dev;
skb_reserve(skb, 2); /* 16 byte align the IP header */
-#if LINUX_VERSION_CODE < 0x10300
- memcpy(skb->data, tp->rx_ring[entry].buffer1, pkt_len);
-#elif LINUX_VERSION_CODE < 0x20200 || defined(__alpha__)
+#if LINUX_VERSION_CODE < 0x20200 || defined(__alpha__)
memcpy(skb_put(skb, pkt_len),
bus_to_virt(tp->rx_ring[entry].buffer1), pkt_len);
#else
skb_put(skb, pkt_len);
#endif
}
-#if LINUX_VERSION_CODE > 0x10300
skb->protocol = eth_type_trans(skb, dev);
-#else
- skb->len = pkt_len;
-#endif
netif_rx(skb);
dev->last_rx = jiffies;
tp->stats.rx_packets++;
if (skb == NULL)
break;
skb->dev = dev; /* Mark as being used by this device. */
-#if LINUX_VERSION_CODE > 0x10300
tp->rx_ring[entry].buffer1 = virt_to_bus(skb->tail);
-#else
- tp->rx_ring[entry].buffer1 = virt_to_bus(skb->data);
-#endif
work_done++;
}
tp->rx_ring[entry].status = 0x80000000;
our interrupt handler called. */
if (count && no_irq) {
parport_release (dev);
- set_current_state (TASK_INTERRUPTIBLE);
+ __set_current_state (TASK_INTERRUPTIBLE);
schedule_timeout (wait);
parport_claim_or_block (dev);
}
/* Yield the port for a while. */
if (count && dev->port->irq != PARPORT_IRQ_NONE) {
parport_release (dev);
- set_current_state (TASK_INTERRUPTIBLE);
+ __set_current_state (TASK_INTERRUPTIBLE);
schedule_timeout ((HZ + 24) / 25);
parport_claim_or_block (dev);
}
dev = dev_cache;
memset(dev, 0, sizeof(*dev));
dev->bus = bus;
+ dev->sysdata = bus->sysdata;
dev->devfn = devfn;
if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
child->self = dev;
child->parent = bus;
child->ops = bus->ops;
+ child->sysdata = bus->sysdata;
/*
* Set up the primary, secondary and subordinate
1148 5843 FDDI SK-5843 (SK-NET FDDI-LP64)
1148 5844 FDDI SK-5844 (SK-NET FDDI-LP64 DAS)
4200 Token ring adaptor
- 4300 GE
+ 4300 Gigabit Ethernet
+ 1148 9821 SK-9821 (1000Base-T single link)
+ 1148 9822 SK-9822 (1000Base-T dual link)
+ 1148 9841 SK-9841 (1000Base-LX single link)
+ 1148 9842 SK-9842 (1000Base-LX dual link)
+ 1148 9843 SK-9843 (1000Base-SX single link)
+ 1148 9844 SK-9844 (1000Base-SX dual link)
1149 Win System Corporation
114a VMIC
7587 VMIVME-7587
* Support routines for initializing a PCI subsystem.
*/
+/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
+
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
int err;
err = -EINVAL;
- if (root != NULL) {
- /* If `dev' is on a secondary pci bus, `root' may not be
- at the origin. In that case, adjust the resource into
- range. */
- res->start += root->start;
- res->end += root->start;
-
+ if (root != NULL)
err = request_resource(root, res);
- }
if (err) {
printk(KERN_ERR "PCI: Address space collision on region %d "
"of device %s\n", resource, dev->name);
DBGC((" for root[%lx:%lx] min[%lx] size[%lx]\n",
root->start, root->end, min, size));
- if (allocate_resource(root, res, size, min, -1, size) < 0) {
+ if (allocate_resource(root, res, size, min, -1, size, dev) < 0) {
printk(KERN_ERR
"PCI: Failed to allocate resource %d for %s\n",
i, dev->name);
pdev_assign_unassigned_resources(dev, min_io, min_mem);
}
-struct pbus_set_ranges_data
-{
- int found_vga;
- unsigned int io_start, io_end;
- unsigned int mem_start, mem_end;
-};
-
#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
#define ROUND_DOWN(x, a) ((x) & ~((a) - 1))
struct pci_dev *dev;
inner.found_vga = 0;
- inner.mem_start = inner.io_start = ~0;
+ inner.mem_start = inner.io_start = ~0UL;
inner.mem_end = inner.io_end = 0;
/* Collect information about how our direct children are layed out. */
inner.mem_start = ROUND_DOWN(inner.mem_start, 1*1024*1024);
inner.mem_end = ROUND_UP(inner.mem_end, 1*1024*1024);
+ pcibios_fixup_pbus_ranges(bus, &inner);
+
/* Configure the bridge, if possible. */
if (bus->self) {
struct pci_dev *bridge = bus->self;
* without warnings.
*/
-#if !defined(LINUX_1_2) && !defined(LINUX_1_3)
#include <linux/version.h>
-#if LINUX_VERSION_CODE > 65536 + 3 * 256
-#define LINUX_1_3
-#else
-#define LINUX_1_2
-#endif
-#endif
-
-#ifdef LINUX_1_2
-#define u32 bogus_u32
-#define s32 bogus_s32
-#include <asm/types.h>
-#undef u32
-#undef s32
-typedef __signed__ int s32;
-typedef unsigned int u32;
-#endif /* def LINUX_1_2 */
#ifdef MODULE
#include <linux/module.h>
printk (KERN_ALERT "target %d is host ID\n", target);
return -1;
}
-#ifndef LINUX_1_2
else if (target > h->max_id) {
printk (KERN_ALERT "target %d exceeds maximum of %d\n", target,
h->max_id);
return -1;
}
-#endif
hostdata = (struct NCR53c7x0_hostdata *)h->hostdata;
save_flags(flags);
ncr_pci_init (Scsi_Host_Template *tpnt, int board, int chip,
unsigned char bus, unsigned char device_fn, long long options){
unsigned short command;
-#ifdef LINUX_1_2
- unsigned long
-#else
- unsigned int
-#endif
- base, io_port;
+ unsigned int base, io_port;
unsigned char revision;
int error, expected_chip;
int expected_id = -1, max_revision = -1, min_revision = -1;
* 1.2.x), do so now.
*/
if (!(hostdata->cmd_allocated[cmd->target] & (1 << cmd->lun)) &&
-#ifdef LINUX_1_2
- !in_scan_scsis
-#else
cmd->device && cmd->device->has_cmdblocks
-#endif
) {
if ((hostdata->extra_allocate + hostdata->num_cmds) < host->can_queue)
hostdata->extra_allocate += host->cmd_per_lun;
tmp = ROUNDUP(real, void *);
tmp->real = real;
tmp->size = size;
-#ifdef LINUX_1_2
- tmp->free = ((void (*)(void *, int)) kfree_s);
-#else
tmp->free = ((void (*)(void *, int)) kfree);
-#endif
save_flags (flags);
cli();
tmp->next = hostdata->free;
if ((hostdata->options & (OPTION_DEBUG_INIT_ONLY|OPTION_DEBUG_PROBE_ONLY))
|| ((hostdata->options & OPTION_DEBUG_TARGET_LIMIT) &&
!(hostdata->debug_lun_limit[cmd->target] & (1 << cmd->lun)))
-#ifdef LINUX_1_2
- || cmd->target > 7
-#else
|| cmd->target > host->max_id
-#endif
|| cmd->target == host->this_id
|| hostdata->state == STATE_DISABLED) {
printk("scsi%d : disabled or bad target %d lun %d\n", host->host_no,
#ifndef NCR53c7x0_H
#define NCR53c7x0_H
-#if !defined(LINUX_1_2) && !defined(LINUX_1_3)
#include <linux/version.h>
-#if LINUX_VERSION_CODE > 65536 + 3 * 256
-#define LINUX_1_3
-#else
-#define LINUX_1_2
-#endif
-#endif
/*
* Prevent name space pollution in hosts.c, and only provide the
#ifndef NCR53c710_H
#define NCR53c710_H
-#if !defined(LINUX_1_2) && !defined(LINUX_1_3)
#include <linux/version.h>
-#if LINUX_VERSION_CODE > 65536 + 3 * 256
-#define LINUX_1_3
-#else
-#define LINUX_1_2
-#endif
-#endif
/*
* Prevent name space pollution in hosts.c, and only provide the
#define NCR53c7xx_release NULL
#endif
-#ifdef LINUX_1_2
-#define NCR53c7xx {NULL, NULL, "NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
- NULL, /* info */ NULL, /* command, deprecated */ NULL, \
- NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
- NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
- /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
- /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
-#else
#define NCR53c7xx {NULL, NULL, NULL, NULL, \
"NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
NULL, /* info */ NULL, /* command, deprecated */ NULL, \
NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
/* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
/* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
-#endif
#endif /* defined(HOSTS_C) || defined(MODULE) */
#ifndef HOSTS_C
-#ifdef LINUX_1_2
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/i386 mapping (but if we ever
- * make the kernel segment mapped at 0, we need to do translation
- * on the i386 as well)
- */
-extern inline unsigned long virt_to_phys(volatile void * address)
-{
- return (unsigned long) address;
-}
-
-extern inline void * phys_to_virt(unsigned long address)
-{
- return (void *) address;
-}
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the x86 architecture, we just read/write the
- * memory location directly.
- */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
-
-#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
-
-#define mb()
-
-#endif /* def LINUX_1_2 */
/* SCSI control 0 rw, default = 0xc0 */
#define SCNTL0_REG 0x00
-/* $Id: advansys.c,v 1.59 1999/09/08 18:50:51 bobf Exp bobf $ */
-#define ASC_VERSION "3.2G" /* AdvanSys Driver Version */
+/* $Id: advansys.c,v 1.67 1999/11/18 20:13:15 bobf Exp bobf $ */
+#define ASC_VERSION "3.2K" /* AdvanSys Driver Version */
/*
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
* ftp://ftp.advansys.com/pub/linux/linux.tgz
*
* Please send questions, comments, bug reports to:
- * bobf@advansys.com (Bob Frey)
+ * linux@advansys.com
*/
/*
A. Linux Kernel Testing
This driver has been tested in the following Linux kernels: v1.2.13,
- v1.3.57, v2.0.38, v2.2.12, and v2.3.16. These kernel versions are major
+ v1.3.57, v2.0.38, v2.2.13, and v2.3.28. These kernel versions are major
releases of Linux or the latest Linux kernel versions available when
this version of the driver was released. The driver should also work
in earlier versions of the Linux kernel. Beginning with v1.3.58 the
AdvanSys driver is included with all Linux kernels. Please refer to
sections C, D, and E for instructions on adding or upgrading the
- AdvanSys driver.
+ AdvanSys driver. The driver is supported for x86 and alpha systems.
B. Adapters Supported by this Driver
ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
+ ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
C. Linux v1.2.X - Directions for Adding the AdvanSys Driver
1. Fix PCI board detection in v2.3.13 and greater kernels.
2. Fix comiple errors in v2.3.X with debugging enabled.
+ 3.2H (9/13/99):
+ 1. Add 64-bit address, long support for Alpha and UltraSPARC.
+ The driver has been verified to work on an Alpha system.
+ 2. Add partial byte order handling support for Power PC and
+ other big-endian platforms. This support has not yet been
+ completed or verified.
+ 3. For wide boards replace block zeroing of request and
+ scatter-gather structures with individual field initialization
+ to improve performance.
+ 4. Correct and clarify ROM BIOS version detection.
+
+ 3.2I (10/8/99):
+ 1. Update to Adv Library 5.4.
+ 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
+ adv_isr_callback(). Remove DID_UNDERRUN constant and other
+ no longer needed code that previously documented the lack
+ of underrun handling.
+
+ 3.2J (10/14/99):
+ 1. Eliminate compile errors for v2.0 and earlier kernels.
+
+ 3.2K (11/15/99):
+ 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
+ 2. Update Adv Library to 5.5.
+ 3. Add ifdef handling for /proc changes added in v2.3.28.
+ 4. Increase Wide board scatter-gather list maximum length to
+ 255 when the driver is compiled into the kernel.
+
J. Known Problems/Fix List (XXX)
1. Need to add memory mapping workaround. Test the memory mapping.
6. Need to fix sti/cli code in Asc Library.
7. Need to fix abort code in Adv Library.
8. Reduce io_request_lock hold time.
- 9. Add big-endian support for Alpha.
K. Credits
Doug Gilbert <dgilbert@interlog.com> has made changes and
suggestions to improve the driver and done testing.
+ Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
+ in 3.2K.
+
L. AdvanSys Contact Information
Mail: Advanced System Products, Inc.
#include <linux/blk.h>
#include <linux/stat.h>
#endif /* version >= v1.3.0 */
-#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,1,95)
+#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,3,18)
#include <linux/spinlock.h>
+#elif LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,1,95)
+#include <asm/spinlock.h>
#endif /* version >= 2.1.95 */
#include "scsi.h"
#include "hosts.h"
#define ASC_CONFIG_PCI
#endif /* version < v2.1.93 */
-/*
- * If Linux eventually defines a DID_UNDERRUN, the constant here can be
- * removed. The current value of zero for DID_UNDERRUN results in underrun
- * conditions being ignored.
- */
-#define DID_UNDERRUN 0
+#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,1,0)
+#define cpu_to_le16(word) (word)
+#define le16_to_cpu(word) (word)
+#define cpu_to_le32(dword) (dword)
+#define le32_to_cpu(dword) (dword)
+#endif /* version < v2.1.0 */
/*
#define ASC_LIB_VERSION_MINOR 24
#define ASC_LIB_SERIAL_NUMBER 121
+/*
+ * Portable Data Types
+ *
+ * Any instance where a 32-bit long or pointer type is assumed
+ * for precision or HW defined structures, the following define
+ * types must be used. In Linux the char, short, and int types
+ * are all consistent at 8, 16, and 32 bits respectively. Pointers
+ * and long types are 64 bits on Alpha and UltraSPARC.
+ */
+#define ASC_PADDR __u32 /* Physical/Bus address data type. */
+#define ASC_VADDR __u32 /* Virtual address data type. */
+#define ASC_DCNT __u32 /* Unsigned Data count type. */
+#define ASC_SDCNT __s32 /* Signed Data count type. */
+
+/*
+ * These macros are used to convert a virtual address to a
+ * 32-bit value. This currently can be used on Linux Alpha
+ * which uses 64-bit virtual address but a 32-bit bus address.
+ * This is likely to break in the future, but doing this now
+ * will give us time to change the HW and FW to handle 64-bit
+ * addresses.
+ */
+#define ASC_VADDR_TO_U32 virt_to_bus
+#define ASC_U32_TO_VADDR bus_to_virt
+
typedef unsigned char uchar;
#ifndef NULL
#ifndef FALSE
#define FALSE (0)
#endif
-#define REG register
-#define rchar REG __s8
-#define rshort REG __s16
-#define rint REG __s32
-#define rlong REG __s32
-#define ruchar REG __u8
-#define rushort REG __u16
-#define ruint REG __u32
-#define rulong REG __u32
-#define NULLPTR (void *)0
-#define FNULLPTR (void *)0UL
+
#define EOF (-1)
-#define EOS '\0'
#define ERR (-1)
-#define UB_ERR (uchar)(0xFF)
#define UW_ERR (uint)(0xFFFF)
-#define UL_ERR (ulong)(0xFFFFFFFFUL)
-#define iseven_word(val) ((((uint)val) & (uint)0x0001) == 0)
#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
-#define toeven_word(val) (((uint)val) & (uint)0xFFFE)
-#define biton(val, bits) (((uint)(val >> bits) & (uint)0x0001) != 0)
-#define bitoff(val, bits) (((uint)(val >> bits) & (uint)0x0001) == 0)
-#define lbiton(val, bits) (((ulong)(val >> bits) & (ulong)0x00000001UL) != 0)
-#define lbitoff(val, bits) (((ulong)(val >> bits) & (ulong)0x00000001UL) == 0)
-#define absh(val) ((val) < 0 ? -(val) : (val))
-#define swapbyte(ch) ((((ch) << 4) | ((ch) >> 4)))
-#ifndef GBYTE
-#define GBYTE (0x40000000UL)
-#endif
-#ifndef MBYTE
-#define MBYTE (0x100000UL)
-#endif
-#ifndef KBYTE
-#define KBYTE (0x400)
-#endif
-#define HI_BYTE(x) (*((__u8 *)(&x)+1))
-#define LO_BYTE(x) (*((__u8 *)&x))
-#define HI_WORD(x) (*((__u16 *)(&x)+1))
-#define LO_WORD(x) (*((__u16 *)&x))
-#ifndef MAKEWORD
-#define MAKEWORD(lo, hi) ((__u16) (((__u16) lo) | ((__u16) hi << 8)))
-#endif
-#ifndef MAKELONG
-#define MAKELONG(lo, hi) ((__u32) (((__u32) lo) | ((__u32) hi << 16)))
-#endif
-#define SwapWords(dWord) ((__u32) ((dWord >> 16) | (dWord << 16)))
-#define SwapBytes(word) ((__u16) ((word >> 8) | (word << 8)))
-#define BigToLittle(dWord) ((__u32) (SwapWords(MAKELONG(SwapBytes(LO_WORD(dWord)), SwapBytes(HI_WORD(dWord))))))
-#define LittleToBig(dWord) BigToLittle(dWord)
#define AscPCIConfigVendorIDRegister 0x0000
#define AscPCIConfigDeviceIDRegister 0x0002
#define AscPCIConfigCommandRegister 0x0004
#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
#define PortAddr unsigned short /* port address size */
-#define Ptr2Func ulong
#define inp(port) inb(port)
#define inpw(port) inw(port)
#define inpl(port) inl(port)
#define outp(port, byte) outb((byte), (port))
#define outpw(port, word) outw((word), (port))
-#define outpl(port, long) outl((long), (port))
+#define outpl(port, dword) outl((dword), (port))
#define ASC_MAX_SG_QUEUE 7
-#define ASC_MAX_SG_LIST SG_ALL
+#define ASC_MAX_SG_LIST 255
#define ASC_CS_TYPE unsigned short
-#ifndef asc_ptr_type
-#define asc_ptr_type
-#endif
-#ifndef ASC_GET_PTR2FUNC
-#define ASC_GET_PTR2FUNC(fun) (Ptr2Func)(fun)
-#endif
-#define FLIP_BYTE_NIBBLE(x) (((x<<4)& 0xFF) | (x>>4))
#define ASC_IS_ISA (0x0001)
#define ASC_IS_ISAPNP (0x0081)
#define ASC_IS_EISA (0x0002)
#define ASC_SCSI_ID_BITS 3
#define ASC_SCSI_TIX_TYPE uchar
#define ASC_ALL_DEVICE_BIT_SET 0xFF
-#ifdef ASC_WIDESCSI_16
-#undef ASC_SCSI_ID_BITS
-#define ASC_SCSI_ID_BITS 4
-#define ASC_ALL_DEVICE_BIT_SET 0xFFFF
-#endif
-#ifdef ASC_WIDESCSI_32
-#undef ASC_SCSI_ID_BITS
-#define ASC_SCSI_ID_BITS 5
-#define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL
-#endif
-#if ASC_SCSI_ID_BITS == 3
#define ASC_SCSI_BIT_ID_TYPE uchar
#define ASC_MAX_TID 7
#define ASC_MAX_LUN 7
#define ASC_SCSI_WIDTH_BIT_SET 0xFF
-#elif ASC_SCSI_ID_BITS == 4
-#define ASC_SCSI_BIT_ID_TYPE ushort
-#define ASC_MAX_TID 15
-#define ASC_MAX_LUN 7
-#define ASC_SCSI_WIDTH_BIT_SET 0xFFFF
-#elif ASC_SCSI_ID_BITS == 5
-#define ASC_SCSI_BIT_ID_TYPE ulong
-#define ASC_MAX_TID 31
-#define ASC_MAX_LUN 7
-#define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF
-#else
-#error ASC_SCSI_ID_BITS definition is wrong
-#endif
#define ASC_MAX_SENSE_LEN 32
#define ASC_MIN_SENSE_LEN 14
#define ASC_MAX_CDB_LEN 12
uchar sg_queue_cnt;
uchar target_id;
uchar target_lun;
- ulong data_addr;
- ulong data_cnt;
- ulong sense_addr;
+ ASC_PADDR data_addr;
+ ASC_DCNT data_cnt;
+ ASC_PADDR sense_addr;
uchar sense_len;
uchar extra_bytes;
} ASC_SCSIQ_1;
typedef struct asc_scisq_2 {
- ulong srb_ptr;
+ ASC_VADDR srb_ptr;
uchar target_ix;
uchar flag;
uchar cdb_len;
uchar y_res;
ushort x_req_count;
ushort x_reconnect_rtn;
- ulong x_saved_data_addr;
- ulong x_saved_data_cnt;
+ ASC_PADDR x_saved_data_addr;
+ ASC_DCNT x_saved_data_cnt;
} ASC_SCSIQ_4;
typedef struct asc_q_done_info {
uchar sense_len;
uchar extra_bytes;
uchar res;
- ulong remain_bytes;
+ ASC_DCNT remain_bytes;
} ASC_QDONE_INFO;
typedef struct asc_sg_list {
- ulong addr;
- ulong bytes;
+ ASC_PADDR addr;
+ ASC_DCNT bytes;
} ASC_SG_LIST;
typedef struct asc_sg_head {
#define ASC_MIN_TAGGED_CMD 7
#define ASC_MAX_SCSI_RESET_WAIT 30
+struct asc_dvc_var; /* Forward Declaration. */
+
+typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
+typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
+
typedef struct asc_dvc_var {
PortAddr iop_base;
ushort err_code;
ushort dvc_cntl;
ushort bug_fix_cntl;
ushort bus_type;
- Ptr2Func isr_callback;
- Ptr2Func exe_callback;
+ ASC_ISR_CALLBACK isr_callback;
+ ASC_EXE_CALLBACK exe_callback;
ASC_SCSI_BIT_ID_TYPE init_sdtr;
ASC_SCSI_BIT_ID_TYPE sdtr_done;
ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
ASC_DVC_CFG *cfg;
- Ptr2Func saved_ptr2func;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
char redo_scam;
ushort res2;
uchar dos_int13_table[ASC_MAX_TID + 1];
- ulong max_dma_count;
+ ASC_DCNT max_dma_count;
ASC_SCSI_BIT_ID_TYPE no_scam;
ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
uchar max_sdtr_index;
uchar host_init_sdtr_index;
- ulong drv_ptr;
- ulong uc_break;
- ulong res7;
- ulong res8;
+ struct asc_board *drv_ptr;
+ ASC_DCNT uc_break;
} ASC_DVC_VAR;
-typedef int (* ASC_ISR_CALLBACK) (ASC_DVC_VAR asc_ptr_type *, ASC_QDONE_INFO *);
-typedef int (* ASC_EXE_CALLBACK) (ASC_DVC_VAR asc_ptr_type *, ASC_SCSI_Q *);
-
typedef struct asc_dvc_inq_info {
uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
} ASC_DVC_INQ_INFO;
typedef struct asc_cap_info {
- ulong lba;
- ulong blk_size;
+ ASC_DCNT lba;
+ ASC_DCNT blk_size;
} ASC_CAP_INFO;
typedef struct asc_cap_info_array {
STATIC uchar AscGetIsaDmaSpeed(PortAddr);
STATIC uchar AscReadLramByte(PortAddr, ushort);
STATIC ushort AscReadLramWord(PortAddr, ushort);
-STATIC ulong AscReadLramDWord(PortAddr, ushort);
+STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
-STATIC void AscWriteLramDWord(PortAddr, ushort, ulong);
+STATIC void AscWriteLramDWord(PortAddr, ushort, ASC_DCNT);
STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
-STATIC ulong AscMemSumLramWord(PortAddr, ushort, rint);
-STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, rint);
+STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
+STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
STATIC void AscMemWordCopyToLram(PortAddr, ushort, ushort *, int);
-STATIC void AscMemDWordCopyToLram(PortAddr, ushort, ulong *, int);
+STATIC void AscMemDWordCopyToLram(PortAddr, ushort, ASC_DCNT *, int);
STATIC void AscMemWordCopyFromLram(PortAddr, ushort, ushort *, int);
-STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitFromEEP(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR asc_ptr_type * asc_dvc);
-STATIC int AscTestExternalLram(ASC_DVC_VAR asc_ptr_type *);
-STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR asc_ptr_type *, uchar, uchar);
-STATIC uchar AscCalSDTRData(ASC_DVC_VAR asc_ptr_type *, uchar, uchar);
+STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
+STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
+STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
+STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
+STATIC int AscTestExternalLram(ASC_DVC_VAR *);
+STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
+STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
-STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR asc_ptr_type *, ruchar);
+STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
-STATIC int AscRiscHaltedAbortSRB(ASC_DVC_VAR asc_ptr_type *, ulong);
+STATIC int AscRiscHaltedAbortSRB(ASC_DVC_VAR *, ASC_DCNT);
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
-STATIC int AscRiscHaltedAbortTIX(ASC_DVC_VAR asc_ptr_type *, uchar);
+STATIC int AscRiscHaltedAbortTIX(ASC_DVC_VAR *, uchar);
#endif /* version >= v1.3.89 */
STATIC int AscHostReqRiscHalt(PortAddr);
STATIC int AscStopQueueExe(PortAddr);
STATIC int AscCleanUpDiscQueue(PortAddr);
#endif /* version >= v1.3.89 */
STATIC int AscCleanUpBusyQueue(PortAddr);
-STATIC int AscWaitTixISRDone(ASC_DVC_VAR asc_ptr_type *, uchar);
-STATIC int AscWaitISRDone(ASC_DVC_VAR asc_ptr_type *);
-STATIC ulong AscGetOnePhyAddr(ASC_DVC_VAR asc_ptr_type *, uchar *,
- ulong);
-STATIC int AscSendScsiQueue(ASC_DVC_VAR asc_ptr_type * asc_dvc,
+STATIC int AscWaitTixISRDone(ASC_DVC_VAR *, uchar);
+STATIC int AscWaitISRDone(ASC_DVC_VAR *);
+STATIC ASC_PADDR AscGetOnePhyAddr(ASC_DVC_VAR *, uchar *,
+ ASC_DCNT);
+STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
ASC_SCSI_Q * scsiq,
uchar n_q_required);
-STATIC int AscPutReadyQueue(ASC_DVC_VAR asc_ptr_type *,
+STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
ASC_SCSI_Q *, uchar);
-STATIC int AscPutReadySgListQueue(ASC_DVC_VAR asc_ptr_type *,
+STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
ASC_SCSI_Q *, uchar);
STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
-STATIC ushort AscInitLram(ASC_DVC_VAR asc_ptr_type *);
-STATIC int AscReInitLram(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitQLinkVar(ASC_DVC_VAR asc_ptr_type *);
-STATIC int AscSetLibErrorCode(ASC_DVC_VAR asc_ptr_type *, ushort);
+STATIC ushort AscInitLram(ASC_DVC_VAR *);
+STATIC int AscReInitLram(ASC_DVC_VAR *);
+STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
+STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
STATIC int _AscWaitQDone(PortAddr, ASC_SCSI_Q *);
#endif /* version >= v1.3.89 */
-STATIC int AscIsrChipHalted(ASC_DVC_VAR asc_ptr_type *);
+STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
- ASC_QDONE_INFO *, ulong);
-STATIC int AscIsrQDone(ASC_DVC_VAR asc_ptr_type *);
+ ASC_QDONE_INFO *, ASC_DCNT);
+STATIC int AscIsrQDone(ASC_DVC_VAR *);
STATIC int AscCompareString(uchar *, uchar *, int);
STATIC ushort AscGetEisaChipCfg(PortAddr);
-STATIC ulong AscGetEisaProductID(PortAddr);
+STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
STATIC uchar AscGetChipScsiCtrl(PortAddr);
STATIC uchar AscSetChipScsiID(PortAddr, uchar);
STATIC uchar AscGetChipVersion(PortAddr, ushort);
STATIC ushort AscGetChipBusType(PortAddr);
-STATIC ulong AscLoadMicroCode(PortAddr, ushort, ushort *, ushort);
+STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, ushort *, ushort);
STATIC int AscFindSignature(PortAddr);
STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
STATIC void AscToggleIRQAct(PortAddr);
STATIC void DvcLeaveCritical(int);
STATIC void DvcInPortWords(PortAddr, ushort *, int);
STATIC void DvcOutPortWords(PortAddr, ushort *, int);
-STATIC void DvcOutPortDWords(PortAddr, ulong *, int);
-STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR asc_ptr_type *, ushort);
-STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR asc_ptr_type *,
+STATIC void DvcOutPortDWords(PortAddr, ASC_DCNT *, int);
+STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
+STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
ushort, uchar);
STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
-STATIC void DvcSleepMilliSecond(ulong);
-STATIC void DvcDelayNanoSecond(ASC_DVC_VAR asc_ptr_type *, ulong);
-STATIC ulong DvcGetSGList(ASC_DVC_VAR asc_ptr_type *, uchar *,
- ulong, ASC_SG_HEAD *);
+STATIC void DvcSleepMilliSecond(ASC_DCNT);
+STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
+STATIC ASC_DCNT DvcGetSGList(ASC_DVC_VAR *, uchar *,
+ ASC_DCNT, ASC_SG_HEAD *);
STATIC void DvcPutScsiQ(PortAddr, ushort, ushort *, int);
STATIC void DvcGetQinfo(PortAddr, ushort, ushort *, int);
STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
-STATIC ushort AscInitGetConfig(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitSetConfig(ASC_DVC_VAR asc_ptr_type *);
-STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR asc_ptr_type *);
-STATIC void AscAsyncFix(ASC_DVC_VAR asc_ptr_type *, uchar,
+STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
+STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
+STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
+STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
ASC_SCSI_INQUIRY *);
STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
-STATIC void AscInquiryHandling(ASC_DVC_VAR asc_ptr_type *,
+STATIC void AscInquiryHandling(ASC_DVC_VAR *,
uchar, ASC_SCSI_INQUIRY *);
-STATIC int AscExeScsiQueue(ASC_DVC_VAR asc_ptr_type *, ASC_SCSI_Q *);
-STATIC int AscISR(ASC_DVC_VAR asc_ptr_type *);
-STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR asc_ptr_type *, uchar,
+STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
+STATIC int AscISR(ASC_DVC_VAR *);
+STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
uchar);
STATIC int AscSgListToQueue(int);
-STATIC int AscAbortSRB(ASC_DVC_VAR asc_ptr_type *, ulong);
+STATIC int AscAbortSRB(ASC_DVC_VAR *, ASC_VADDR);
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
-STATIC int AscResetDevice(ASC_DVC_VAR asc_ptr_type *, uchar);
+STATIC int AscResetDevice(ASC_DVC_VAR *, uchar);
#endif /* version >= v1.3.89 */
-STATIC int AscResetSB(ASC_DVC_VAR asc_ptr_type *);
+STATIC int AscResetSB(ASC_DVC_VAR *);
STATIC void AscEnableIsaDma(uchar);
-STATIC ulong AscGetMaxDmaCount(ushort);
+STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
/*
*/
#define ADV_LIB_VERSION_MAJOR 5
-#define ADV_LIB_VERSION_MINOR 2
+#define ADV_LIB_VERSION_MINOR 5
/* d_os_dep.h */
#define ADV_OS_LINUX
/*
* Define Adv Library required special types.
*/
+
+/*
+ * Portable Data Types
+ *
+ * Any instance where a 32-bit long or pointer type is assumed
+ * for precision or HW defined structures, the following define
+ * types must be used. In Linux the char, short, and int types
+ * are all consistent at 8, 16, and 32 bits respectively. Pointers
+ * and long types are 64 bits on Alpha and UltraSPARC.
+ */
+#define ADV_PADDR __u32 /* Physical address data type. */
+#define ADV_VADDR __u32 /* Virtual address data type. */
+#define ADV_DCNT __u32 /* Unsigned Data count type. */
+#define ADV_SDCNT __s32 /* Signed Data count type. */
+
+/*
+ * These macros are used to convert a virtual address to a
+ * 32-bit value. This currently can be used on Linux Alpha
+ * which uses 64-bit virtual address but a 32-bit bus address.
+ * This is likely to break in the future, but doing this now
+ * will give us time to change the HW and FW to handle 64-bit
+ * addresses.
+ */
+#define ADV_VADDR_TO_U32 virt_to_bus
+#define ADV_U32_TO_VADDR bus_to_virt
+
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(1,3,0)
#define AdvPortAddr unsigned short /* I/O Port address size */
#else /* version >= v1,3,0 */
-#define AdvPortAddr unsigned long /* Virtual memory address size */
+#define AdvPortAddr ulong /* Virtual memory address size */
#endif /* version >= v1,3,0 */
/*
/*
* Define total number of simultaneous maximum element scatter-gather
- * requests, i.e. ADV_TOT_SG_LIST * ADV_MAX_SG_LIST is the total number
- * of simultaneous scatter-gather elements supported per wide adapter.
+ * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
+ * maximum number of outstanding commands per wide host adapter. Each
+ * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
+ * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
+ * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
+ * structures or 255 scatter-gather elements.
+ *
*/
-#define ADV_TOT_SG_LIST 64
+#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
/*
- * Define Adv Library required per request scatter-gather element limit.
+ * Define Adv Library required maximum number of scatter-gather
+ * elements per request.
*/
-#define ADV_MAX_SG_LIST 64
+#define ADV_MAX_SG_LIST 255
/* Number of SG blocks needed. */
#define ADV_NUM_SG_BLOCK \
#define ADV_NUM_PAGE_CROSSING \
((ADV_SG_TOTAL_MEM_SIZE + (ASC_PAGE_SIZE - 1))/ASC_PAGE_SIZE)
-#define ADV_ASSERT(a) ASC_ASSERT(a)
-
/* a_condor.h */
#define ADV_PCI_VENDOR_ID 0x10CD
#define ADV_PCI_DEVICE_ID_REV_A 0x2300
#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
+/*
+ * For the ASC3550 Bit 13 is Termination Polarity control bit.
+ * For later ICs Bit 13 controls whether the CIS (Card Information
+ * Service Section) is loaded from EEPROM.
+ */
#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
-#define ADV_EEPROM_CIS_LD 0x1000 /* EEPROM Bit 12 */
+#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
typedef struct adveep_3550_config
{
/* Word Offset, Description */
ushort cfg_lsw; /* 00 power up initialization */
- /* bit 12 set - CIS Load */
- /* bit 13 set - Term Polarity Control */
+ /* bit 13 set - Load CIS */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
ushort cfg_msw; /* 01 unused */
#define IOPB_SOFT_OVER_WR 0x0E
#define IOPB_RES_ADDR_F 0x0F
#define IOPB_MEM_CFG 0x10
-#define IOPB_GPIO_CNTL 0x11
+#define IOPB_RES_ADDR_11 0x11
#define IOPB_GPIO_DATA 0x12
#define IOPB_RES_ADDR_13 0x13
#define IOPB_FLASH_PAGE 0x14
#define IOPB_RES_ADDR_15 0x15
-#define IOPB_RES_ADDR_16 0x16
+#define IOPB_GPIO_CNTL 0x16
#define IOPB_RES_ADDR_17 0x17
#define IOPB_FLASH_DATA 0x18
#define IOPB_RES_ADDR_19 0x19
#define IOPB_RES_ADDR_37 0x37
#define IOPB_RAM_BIST 0x38
#define IOPB_PLL_TEST 0x39
-#define IOPB_RES_ADDR_3A 0x3A
+#define IOPB_PCI_INT_CFG 0x3A
#define IOPB_RES_ADDR_3B 0x3B
#define IOPB_RFIFO_CNT 0x3C
#define IOPB_RES_ADDR_3D 0x3D
typedef struct adv_carr_t
{
- ulong carr_va; /* Carrier Virtual Address */
- ulong carr_pa; /* Carrier Physical Address */
- ulong areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
+ ADV_VADDR carr_va; /* Carrier Virtual Address */
+ ADV_PADDR carr_pa; /* Carrier Physical Address */
+ ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
/*
* next_vpa [31:4] Carrier Virtual or Physical Next Pointer
*
* next_vpa [3:1] Reserved Bits
* next_vpa [0] Done Flag set in Response Queue.
*/
- ulong next_vpa;
+ ADV_VADDR next_vpa;
} ADV_CARR_T;
/*
#define ASC_RQ_DONE 0x00000001
#define ASC_CQ_STOPPER 0x00000000
-#define ASC_GET_CARRP(carrp) ((ADV_CARR_T *) ((carrp) & ASC_NEXT_VPA_MASK))
+#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
#define ADV_PAGE_SIZE 4096 /* Assume 4KB page size. */
uchar max_host_qng; /* maximum number of Q'ed command allowed */
uchar irq_no; /* IRQ number */
ushort no_scam; /* scam_tolerant of EEPROM */
- ulong drv_ptr; /* driver pointer to private structure */
+ struct asc_board *drv_ptr; /* driver pointer to private structure */
uchar chip_scsi_id; /* chip SCSI target ID */
uchar chip_type;
uchar bist_err_code;
uchar reserved2;
uchar reserved3;
uchar sg_cnt; /* Valid entries in block. */
- struct asc_sg_block *sg_ptr; /* links to the next sg block */
+ ADV_PADDR sg_ptr; /* Pointer to next sg block. */
struct {
- ulong sg_addr; /* SG element address. */
- ulong sg_count; /* SG element count. */
+ ADV_PADDR sg_addr; /* SG element address. */
+ ADV_DCNT sg_count; /* SG element count. */
} sg_list[NO_OF_SG_PER_BLOCK];
} ADV_SG_BLOCK;
*/
typedef struct adv_scsi_req_q {
uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
- uchar reserved;
+ uchar target_cmd;
uchar target_id; /* Device target identifier. */
uchar target_lun; /* Device target logical unit number. */
- ulong data_addr; /* Data buffer physical address. */
- ulong data_cnt; /* Data count. Ucode sets to residual. */
- ulong sense_addr;
- ulong carr_pa;
+ ADV_PADDR data_addr; /* Data buffer physical address. */
+ ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
+ ADV_PADDR sense_addr;
+ ADV_PADDR carr_pa;
uchar mflag;
uchar sense_len;
uchar cdb_len; /* SCSI CDB length. */
uchar host_status; /* Ucode host status. */
uchar sg_working_ix;
uchar cdb[12]; /* SCSI command block. */
- ulong sg_real_addr; /* SG list physical address. */
- ulong scsiq_rptr;
- ulong sg_working_data_cnt;
- struct adv_scsi_req_q *scsiq_ptr;
- ulong carr_va;
+ ADV_PADDR sg_real_addr; /* SG list physical address. */
+ ADV_PADDR scsiq_rptr;
+ ADV_DCNT sg_working_data_cnt;
+ ADV_VADDR scsiq_ptr;
+ ADV_VADDR carr_va;
/*
* End of microcode structure - 60 bytes. The rest of the structure
* is used by the Adv Library and ignored by the microcode.
*/
- ulong srb_ptr;
+ ADV_VADDR srb_ptr;
ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
- ulong vdata_addr; /* Data buffer virtual address. */
+ char *vdata_addr; /* Data buffer virtual address. */
uchar a_flag;
} ADV_SCSI_REQ_Q;
*/
STATIC int DvcEnterCritical(void);
STATIC void DvcLeaveCritical(int);
-STATIC void DvcSleepMilliSecond(ulong);
+STATIC void DvcSleepMilliSecond(ADV_DCNT);
STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
-STATIC ulong DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
- uchar *, long *, int);
+STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
+ uchar *, ASC_SDCNT *, int);
STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
/*
* Adv Library functions available to drivers.
*/
-STATIC int AdvExeScsiQueue(ADV_DVC_VAR *,
- ADV_SCSI_REQ_Q *);
+STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
STATIC int AdvISR(ADV_DVC_VAR *);
STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
/*
* Internal Adv Library functions.
*/
-STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ulong);
+STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(1,3,0)
/* Read byte from a register. */
-#define AdvReadByteRegister(iop_base, reg_off) (inp((iop_base) + (reg_off)))
+#define AdvReadByteRegister(iop_base, reg_off) \
+ (inp((iop_base) + (reg_off)))
/* Write byte to a register. */
-#define AdvWriteByteRegister(iop_base, reg_off, byte) (outp((iop_base) + (reg_off), (byte)))
+#define AdvWriteByteRegister(iop_base, reg_off, byte) \
+ (outp((iop_base) + (reg_off), (byte)))
/* Read word (2 bytes) from a register. */
-#define AdvReadWordRegister(iop_base, reg_off) (inpw((iop_base) + (reg_off)))
+#define AdvReadWordRegister(iop_base, reg_off) \
+ (le16_to_cpu(inpw((iop_base) + (reg_off))))
/* Write word (2 bytes) to a register. */
-#define AdvWriteWordRegister(iop_base, reg_off, word) (outpw((iop_base) + (reg_off), (word)))
+#define AdvWriteWordRegister(iop_base, reg_off, word) \
+ (outpw((iop_base) + (reg_off), cpu_to_le16(word)))
/* Read byte from LRAM. */
#define AdvReadByteLram(iop_base, addr, byte) \
#define AdvReadWordLram(iop_base, addr, word) \
do { \
outpw((iop_base) + IOPW_RAM_ADDR, (addr)); \
- (word) = inpw((iop_base) + IOPW_RAM_DATA); \
+ (word) = le16_to_cpu(inpw((iop_base) + IOPW_RAM_DATA)); \
} while (0)
/* Write word (2 bytes) to LRAM. */
#define AdvWriteWordLram(iop_base, addr, word) \
(outpw((iop_base) + IOPW_RAM_ADDR, (addr)), \
- outpw((iop_base) + IOPW_RAM_DATA, (word)))
+ outpw((iop_base) + IOPW_RAM_DATA, cpu_to_le16(word)))
/* Write double word (4 bytes) to LRAM */
/* Because of unspecified C language ordering don't use auto-increment. */
#define AdvWriteDWordLram(iop_base, addr, dword) \
((outpw((iop_base) + IOPW_RAM_ADDR, (addr)), \
- outpw((iop_base) + IOPW_RAM_DATA, (ushort) ((dword) & 0xFFFF))), \
+ outpw((iop_base) + IOPW_RAM_DATA, \
+ cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
(outpw((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
- outpw((iop_base) + IOPW_RAM_DATA, (ushort) ((dword >> 16) & 0xFFFF))))
+ outpw((iop_base) + IOPW_RAM_DATA, \
+ cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
/* Read word (2 bytes) from LRAM assuming that the address is already set. */
#define AdvReadWordAutoIncLram(iop_base) \
- (inpw((iop_base) + IOPW_RAM_DATA))
+ (le16_to_cpu(inpw((iop_base) + IOPW_RAM_DATA)))
/* Write word (2 bytes) to LRAM assuming that the address is already set. */
#define AdvWriteWordAutoIncLram(iop_base, word) \
- (outpw((iop_base) + IOPW_RAM_DATA, (word)))
+ (outpw((iop_base) + IOPW_RAM_DATA, cpu_to_le16(word)))
#else /* version >= v1,3,0 */
/* Read word (2 bytes) from a register. */
#define AdvReadWordRegister(iop_base, reg_off) \
- (ADV_MEM_READW((iop_base) + (reg_off)))
+ le16_to_cpu(ADV_MEM_READW((iop_base) + (reg_off)))
/* Write word (2 bytes) to a register. */
#define AdvWriteWordRegister(iop_base, reg_off, word) \
- (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
+ (ADV_MEM_WRITEW((iop_base) + (reg_off), cpu_to_le16(word)))
/* Read byte from LRAM. */
#define AdvReadByteLram(iop_base, addr, byte) \
#define AdvReadWordLram(iop_base, addr, word) \
do { \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
- (word) = ADV_MEM_READW((iop_base) + IOPW_RAM_DATA); \
+ (word) = le16_to_cpu(ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
} while (0)
/* Write word (2 bytes) to LRAM. */
#define AdvWriteWordLram(iop_base, addr, word) \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
- ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
+ ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, cpu_to_le16(word)))
/* Write double word (4 bytes) to LRAM */
/* Because of unspecified C language ordering don't use auto-increment. */
#define AdvWriteDWordLram(iop_base, addr, dword) \
((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
- (ushort) ((dword) & 0xFFFF))), \
+ cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
(ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
- (ushort) ((dword >> 16) & 0xFFFF))))
+ cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
/* Read word (2 bytes) from LRAM assuming that the address is already set. */
#define AdvReadWordAutoIncLram(iop_base) \
- (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
+ le16_to_cpu(ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
/* Write word (2 bytes) to LRAM assuming that the address is already set. */
#define AdvWriteWordAutoIncLram(iop_base, word) \
- (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
+ (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, cpu_to_le16(word)))
#endif /* version >= v1,3,0 */
*/
#define AdvAbortQueue(asc_dvc, scsiq) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
- (ulong) (scsiq))
+ (ADV_DCNT) (scsiq))
/*
* Send a Bus Device Reset Message to the specified target ID.
*/
#define AdvResetDevice(asc_dvc, target_id) \
AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
- (ulong) (target_id))
+ (ADV_DCNT) (target_id))
/*
* SCSI Wide Type definition.
(sizeof(ADV_SG_BLOCK) * \
((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
-/*
- * A driver may optionally define the assertion macro ADV_ASSERT() in
- * its d_os_dep.h file. If the macro has not already been defined,
- * then define the macro to a no-op.
- */
-#ifndef ADV_ASSERT
-#define ADV_ASSERT(a)
-#endif /* ADV_ASSERT */
-
typedef struct {
uchar peri_dvc_type : 5; /* peripheral device type */
uchar peri_qualifier : 3; /* peripheral qualifier */
/* Per board statistics structure */
struct asc_stats {
/* Driver Entrypoint Statistics */
- ulong command; /* # calls to advansys_command() */
- ulong queuecommand; /* # calls to advansys_queuecommand() */
- ulong abort; /* # calls to advansys_abort() */
- ulong reset; /* # calls to advansys_reset() */
- ulong biosparam; /* # calls to advansys_biosparam() */
- ulong interrupt; /* # advansys_interrupt() calls */
- ulong callback; /* # calls to asc/adv_isr_callback() */
- ulong done; /* # calls to request's scsi_done function */
- ulong build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
- ulong adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
- ulong adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
+ ADV_DCNT command; /* # calls to advansys_command() */
+ ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
+ ADV_DCNT abort; /* # calls to advansys_abort() */
+ ADV_DCNT reset; /* # calls to advansys_reset() */
+ ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
+ ADV_DCNT interrupt; /* # advansys_interrupt() calls */
+ ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
+ ADV_DCNT done; /* # calls to request's scsi_done function */
+ ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
+ ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
+ ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
/* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
- ulong exe_noerror; /* # ASC_NOERROR returns. */
- ulong exe_busy; /* # ASC_BUSY returns. */
- ulong exe_error; /* # ASC_ERROR returns. */
- ulong exe_unknown; /* # unknown returns. */
+ ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
+ ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
+ ADV_DCNT exe_error; /* # ASC_ERROR returns. */
+ ADV_DCNT exe_unknown; /* # unknown returns. */
/* Data Transfer Statistics */
- ulong cont_cnt; /* # non-scatter-gather I/O requests received */
- ulong cont_xfer; /* # contiguous transfer 512-bytes */
- ulong sg_cnt; /* # scatter-gather I/O requests received */
- ulong sg_elem; /* # scatter-gather elements */
- ulong sg_xfer; /* # scatter-gather transfer 512-bytes */
+ ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
+ ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
+ ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
+ ADV_DCNT sg_elem; /* # scatter-gather elements */
+ ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
};
#endif /* ADVANSYS_STATS */
#ifdef ADVANSYS_STATS
short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
- ulong q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
- ulong q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
+ ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
+ ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
#endif /* ADVANSYS_STATS */
/*
* Adv Library Request Structures
*
- * The following two se structures are used to process Wide Board requests.
- * One structure is needed for each command received from the Mid-Level SCSI
- * driver.
+ * The following two structures are used to process Wide Board requests.
*
* The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
* and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
* adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
* Mid-Level SCSI request structure.
*
- * The adv_sgblk_t structure is used to handle requests that include
- * scatter-gather elements.
+ * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
+ * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
+ * up to 255 scatter-gather elements may be used per request or
+ * ADV_SCSI_REQ_Q.
*/
typedef struct adv_sgblk {
- ADV_SG_BLOCK sg_block[ADV_NUM_SG_BLOCK + ADV_NUM_PAGE_CROSSING];
+ ADV_SG_BLOCK sg_block; /* Sgblock structure. */
uchar align2[4]; /* Sgblock structure padding. */
struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
} adv_sgblk_t;
ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
adv_req_t *orig_reqp; /* adv_req_t memory block. */
adv_req_t *adv_reqp; /* Request structures. */
- adv_sgblk_t *orig_sgblkp; /* adv_sgblk_t memory block. */
adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
ushort bios_signature; /* BIOS Signature. */
ushort bios_version; /* BIOS Version. */
uchar latencyTimer;
uchar headerType;
uchar bist;
- ulong baseAddress[6];
+ ADV_PADDR baseAddress[6];
ushort reserved[4];
- ulong optionRomAddr;
+ ADV_PADDR optionRomAddr;
ushort reserved2[4];
uchar irqLine;
uchar irqPin;
* --- Driver Data
*/
+/* Note: All driver global data should be initialized. */
+
+#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,3,28) && \
+ LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,0)
+struct proc_dir_entry proc_scsi_advansys =
+{
+ PROC_SCSI_ADVANSYS, /* unsigned short low_ino */
+ 8, /* unsigned short namelen */
+ "advansys", /* const char *name */
+ S_IFDIR | S_IRUGO | S_IXUGO, /* mode_t mode */
+ 2 /* nlink_t nlink */
+};
+#endif /* v2.3.28 > version >= v1.3.0 */
+
/* Number of boards detected in system. */
STATIC int asc_board_count = 0;
STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
*/
uchar adv_carr_buf[20 * sizeof(ADV_CARR_T)] = { 0 };
uchar adv_req_buf[16 * sizeof(adv_req_t)] = { 0 };
-uchar adv_sgblk_buf[16 * sizeof(adv_sgblk_t)] = { 0 };
+#define ADV_SGBLK_BUF_CNT 32
+uchar adv_sgblk_buf[ADV_SGBLK_BUF_CNT * sizeof(adv_sgblk_t)] = { 0 };
#endif /* version >= v1,3,0 */
#ifdef ADVANSYS_DEBUG
"ASC_IS_PCI",
};
-STATIC int asc_dbglvl = 0;
+STATIC int asc_dbglvl = 2;
#endif /* ADVANSYS_DEBUG */
/* Declaration for Asc Library internal data referenced by driver. */
STATIC int asc_execute_scsi_cmnd(Scsi_Cmnd *);
STATIC int asc_build_req(asc_board_t *, Scsi_Cmnd *);
STATIC int adv_build_req(asc_board_t *, Scsi_Cmnd *, ADV_SCSI_REQ_Q **);
-STATIC int adv_get_sglist(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *, Scsi_Cmnd *);
+STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, Scsi_Cmnd *);
STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
asc_board_t *boardp = NULL;
ASC_DVC_VAR *asc_dvc_varp = NULL;
ADV_DVC_VAR *adv_dvc_varp = NULL;
+ adv_sgblk_t *sgp = NULL;
int ioport = 0;
int share_irq = FALSE;
int iolen = 0;
PCI_DEVICE pciDevice;
PCI_CONFIG_SPACE pciConfig;
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,0)
- unsigned long pci_memory_address;
+ ADV_PADDR pci_memory_address;
#endif /* version >= v1,3,0 */
#endif /* ASC_CONFIG_PCI */
#else /* version >= v2.1.93 */
ASC_PCI_DEVICE_ID_2300,
ASC_PCI_DEVICE_ID_2500
};
- unsigned long pci_memory_address;
+ ADV_PADDR pci_memory_address;
#endif /* CONFIG_PCI */
#endif /* version >= v2.1.93 */
int warn_code, err_code;
ASC_DBG(1, "advansys_detect: begin\n");
+#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,3,28)
tpnt->proc_name = "advansys";
+#elif LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,0)
+ tpnt->proc_dir = &proc_scsi_advansys;
+#endif /* version >= v1.3.0 */
asc_board_count = 0;
ASC_DBG(1, "advansys_detect: narrow board\n");
asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
asc_dvc_varp->bus_type = asc_bus[bus];
- asc_dvc_varp->drv_ptr = (ulong) boardp;
+ asc_dvc_varp->drv_ptr = boardp;
asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
asc_dvc_varp->iop_base = iop;
- asc_dvc_varp->isr_callback = (Ptr2Func) asc_isr_callback;
+ asc_dvc_varp->isr_callback = asc_isr_callback;
} else {
ASC_DBG(1, "advansys_detect: wide board\n");
adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
- adv_dvc_varp->drv_ptr = (ulong) boardp;
+ adv_dvc_varp->drv_ptr = boardp;
adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
adv_dvc_varp->isr_callback = adv_isr_callback;
adv_dvc_varp->async_callback = adv_async_callback;
#ifdef ASC_CONFIG_PCI
pci_memory_address = pciConfig.baseAddress[1];
ASC_DBG1(1, "advansys_detect: pci_memory_address: %lu\n",
- pci_memory_address);
+ (ulong) pci_memory_address);
if ((boardp->ioremap_addr =
ioremap(pci_memory_address & PAGE_MASK,
PAGE_SIZE)) == 0) {
ASC_PRINT3(
-"advansys_detect: board %d: ioremap(%lx, %d) returned NULL\n",
- boardp->id, pci_memory_address, iolen);
+"advansys_detect: board %d: ioremap(%lu, %x) returned NULL\n",
+ boardp->id, (ulong) pci_memory_address, iolen);
scsi_unregister(shp);
asc_board_count--;
continue;
#else /* version >= v2.3.13 */
pci_memory_address = pci_devp->resource[1].start;
#endif /* version >= v2.3.13 */
- ASC_DBG1(1, "advansys_detect: pci_memory_address: %lu\n",
+ ASC_DBG1(1, "advansys_detect: pci_memory_address: %x\n",
pci_memory_address);
if ((boardp->ioremap_addr =
ioremap(pci_memory_address & PAGE_MASK,
PAGE_SIZE)) == 0) {
ASC_PRINT3(
-"advansys_detect: board %d: ioremap(%lx, %d) returned NULL\n",
+"advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
boardp->id, pci_memory_address, iolen);
scsi_unregister(shp);
asc_board_count--;
*/
boardp->ioport = iop;
- ASC_DBG2(1, "iopb_chip_id_1 %x, iopw_chip_id_0 %x\n",
+ ASC_DBG2(1,
+ "advansys_detect: iopb_chip_id_1 %x, iopw_chip_id_0 %x\n",
(ushort) inp(iop + 1), (ushort) inpw(iop));
}
shp->sg_tablesize = ADV_MAX_SG_LIST;
}
+#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
#ifdef MODULE
/*
* If the driver is compiled as a module, set a limit on the
shp->sg_tablesize = 64;
}
#endif /* MODULE */
+#endif /* version < v2.0.0 */
/*
* The value of 'sg_tablesize' can not exceed the SCSI
int req_cnt;
adv_req_t *reqp = NULL;
int sg_cnt = 0;
- adv_sgblk_t *sgp = NULL;
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(1,3,0)
carrp = (ADV_CARR_T *) &adv_carr_buf[0];
req_cnt = sizeof(adv_req_buf)/sizeof(adv_req_t);
sg_cnt = sizeof(adv_sgblk_buf)/sizeof(adv_sgblk_t);
reqp = (adv_req_t *) &adv_req_buf[0];
- sgp = (adv_sgblk_t *) &adv_sgblk_buf[0];
+ boardp->adv_sgblkp = NULL;
+ for (sg_cnt = 0; sg_cnt < ADV_SGBLK_BUF_CNT; sg_cnt++) {
+ sgp = (adv_sgblk_t *) &adv_sgblk_buf[sg_cnt];
+ sgp->next_sgblkp = boardp->adv_sgblkp;
+ boardp->adv_sgblkp = sgp;
+ }
#else /* version >= v1.3.0 */
/*
- * Allocate buffer carrier structures.
+ * Allocate buffer carrier structures. The total size
+ * is about 4 KB, so allocate all at once.
*/
carrp =
(ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
- ASC_DBG1(1, "advansys_detect: carrp %x\n", (unsigned) carrp);
+ ASC_DBG1(1, "advansys_detect: carrp %lx\n", (ulong) carrp);
if (carrp == NULL) {
goto kmalloc_error;
/*
* Allocate up to 'max_host_qng' request structures for
- * the Wide board.
+ * the Wide board. The total size is about 16 KB, so
+ * allocate all at once. If the allocation fails decrement
+ * and try again.
*/
for (req_cnt = adv_dvc_varp->max_host_qng;
req_cnt > 0; req_cnt--) {
kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
ASC_DBG3(1,
- "advansys_detect: reqp %x, req_cnt %d, bytes %d\n",
- (unsigned) reqp, req_cnt, sizeof(adv_req_t) * req_cnt);
+ "advansys_detect: reqp %lx, req_cnt %d, bytes %lu\n",
+ (ulong) reqp, req_cnt,
+ (ulong) sizeof(adv_req_t) * req_cnt);
if (reqp != NULL) {
break;
}
/*
- * Allocate up to ADV_TOT_SG_LIST request structures for
- * the Wide board.
+ * Allocate up to ADV_TOT_SG_BLOCK request structures for
+ * the Wide board. Each structure is about 136 bytes.
*/
- for (sg_cnt = ADV_TOT_SG_LIST; sg_cnt > 0; sg_cnt--) {
+ boardp->adv_sgblkp = NULL;
+ for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
sgp = (adv_sgblk_t *)
- kmalloc(sizeof(adv_sgblk_t) * sg_cnt, GFP_ATOMIC);
-
- ASC_DBG3(1,
- "advansys_detect: sgp %x, sg_cnt %d, bytes %d\n",
- (unsigned) sgp, sg_cnt, sizeof(adv_sgblk_t) * sg_cnt);
+ kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
- if (sgp != NULL) {
+ if (sgp == NULL) {
break;
}
+
+ sgp->next_sgblkp = boardp->adv_sgblkp;
+ boardp->adv_sgblkp = sgp;
+
}
+ ASC_DBG3(1,
+ "advansys_detect: sg_cnt %d * %u = %u bytes\n",
+ sg_cnt, sizeof(adv_sgblk_t),
+ (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
/*
* If no request structures or scatter-gather structures could
"advansys_detect: board %d: error: failed to kmalloc() adv_req_t buffer.\n",
boardp->id);
err_code = ADV_ERROR;
- } else if (sgp == NULL) {
+ } else if (boardp->adv_sgblkp == NULL) {
kfree(carrp);
kfree(reqp);
ASC_PRINT1(
-"advansys_detect: board %d: error: failed to kmalloc() adv_sgblk_t buffer.\n",
+"advansys_detect: board %d: error: failed to kmalloc() adv_sgblk_t buffers.\n",
boardp->id);
err_code = ADV_ERROR;
} else {
* driver is built as a module and can be unloaded.
*/
boardp->orig_reqp = reqp;
-
- /*
- * Save original pointer for kfree() in case the
- * driver is built as a module and can be unloaded.
- */
- boardp->orig_sgblkp = sgp;
#endif /* version >= v1.3.0 */
adv_dvc_varp->carrier_buf = carrp;
}
boardp->adv_reqp = &reqp[0];
- /*
- * Point 'adv_sgblkp' to the request structures and
- * link them together.
- */
- sg_cnt--;
- sgp[sg_cnt].next_sgblkp = NULL;
- for (; sg_cnt > 0; sg_cnt--) {
- sgp[sg_cnt - 1].next_sgblkp = &sgp[sg_cnt];
- }
- boardp->adv_sgblkp = &sgp[0];
-
if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
{
ASC_DBG(2,
if (warn_code || err_code) {
ASC_PRINT3(
"AdvInitAsc3550/38C0800Driver: board %d: error: warn %x, error %x\n",
- boardp->id, warn_code, adv_dvc_varp->err_code);
+ boardp->id, warn_code, err_code);
}
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,0)
}
kfree(boardp->orig_reqp);
boardp->orig_reqp = boardp->adv_reqp = NULL;
}
- if (boardp->orig_sgblkp) {
- kfree(boardp->orig_sgblkp);
- boardp->orig_sgblkp = boardp->adv_sgblkp = NULL;
+ while ((sgp = boardp->adv_sgblkp) != NULL)
+ {
+ boardp->adv_sgblkp = sgp->next_sgblkp;
+ kfree(sgp);
}
}
#endif /* version >= v1,3,0 */
release_region(shp->io_port, shp->n_io_port);
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,0)
if (ASC_WIDE_BOARD(boardp)) {
+ adv_sgblk_t *sgp = NULL;
+
iounmap(boardp->ioremap_addr);
if (boardp->orig_carrp) {
kfree(boardp->orig_carrp);
kfree(boardp->orig_reqp);
boardp->orig_reqp = boardp->adv_reqp = NULL;
}
- if (boardp->orig_sgblkp) {
- kfree(boardp->orig_sgblkp);
- boardp->orig_sgblkp = boardp->adv_sgblkp = NULL;
+ while ((sgp = boardp->adv_sgblkp) != NULL)
+ {
+ boardp->adv_sgblkp = sgp->next_sgblkp;
+ kfree(sgp);
}
}
ASC_ASSERT(boardp->prtbuf != NULL);
}
sprintf(info,
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,1,92)
-"AdvanSys SCSI %s: %s %u CDB: BIOS %X, IO %X/%X, IRQ %u, DMA %u",
+"AdvanSys SCSI %s: %s %u CDB: BIOS %lX, IO %lX/%X, IRQ %u, DMA %u",
#else /* version >= v2.1.92 */
-"AdvanSys SCSI %s: %s %u CDB: BIOS %X, IO %lX/%X, IRQ %u, DMA %u",
+"AdvanSys SCSI %s: %s %u CDB: BIOS %lX, IO %lX/%X, IRQ %u, DMA %u",
#endif /* version >= v2.1.92 */
ASC_VERSION, busname, asc_dvc_varp->max_total_qng,
- (unsigned) shp->base,
- shp->io_port, shp->n_io_port - 1,
+ (ulong) shp->base,
+ (ulong) shp->io_port, shp->n_io_port - 1,
shp->irq, shp->dma_channel);
} else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
}
sprintf(info,
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,1,92)
- "AdvanSys SCSI %s: %s %u CDB: BIOS %X, IO %X/%X, IRQ %u",
+ "AdvanSys SCSI %s: %s %u CDB: BIOS %lX, IO %X/%X, IRQ %u",
#else /* version >= v2.1.92 */
- "AdvanSys SCSI %s: %s %u CDB: BIOS %X, IO %lX/%X, IRQ %u",
+ "AdvanSys SCSI %s: %s %u CDB: BIOS %lX, IO %lX/%X, IRQ %u",
#endif /* version >= v2.1.92 */
ASC_VERSION, busname, asc_dvc_varp->max_total_qng,
- (unsigned) shp->base, shp->io_port - 1,
+ (ulong) shp->base, shp->io_port - 1,
shp->n_io_port, shp->irq);
}
} else {
int
advansys_command(Scsi_Cmnd *scp)
{
- ASC_DBG1(1, "advansys_command: scp %x\n", (unsigned) scp);
+ ASC_DBG1(1, "advansys_command: scp %lx\n", (ulong) scp);
ASC_STATS(scp->host, command);
scp->SCp.Status = 0; /* Set to a known state */
advansys_queuecommand(scp, advansys_command_done);
if (boardp->flags & (ASC_HOST_IN_RESET | ASC_HOST_IN_ABORT)) {
if (boardp->flags & ASC_HOST_IN_RESET) {
ASC_DBG1(1,
- "advansys_queuecommand: scp %x blocked for reset request\n",
- (unsigned) scp);
+ "advansys_queuecommand: scp %lx blocked for reset request\n",
+ (ulong) scp);
scp->result = HOST_BYTE(DID_RESET);
} else {
ASC_DBG1(1,
- "advansys_queuecommand: scp %x blocked for abort request\n",
- (unsigned) scp);
+ "advansys_queuecommand: scp %lx blocked for abort request\n",
+ (ulong) scp);
scp->result = HOST_BYTE(DID_ABORT);
}
save_flags(flags);
cli();
- ASC_DBG1(1, "advansys_abort: scp %x\n", (unsigned) scp);
+ ASC_DBG1(1, "advansys_abort: scp %lx\n", (ulong) scp);
#ifdef ADVANSYS_STATS
if (scp->host != NULL) {
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
if (scp->serial_number != scp->serial_number_at_timeout) {
ASC_PRINT1(
-"advansys_abort: timeout serial number changed for request %x\n",
- (unsigned) scp);
+"advansys_abort: timeout serial number changed for request %lx\n",
+ (ulong) scp);
do_scsi_done = ASC_FALSE;
scp_found = ASC_FALSE;
ret = SCSI_ABORT_NOT_RUNNING;
* queue, it had not been sent to the device. After
* the queue is removed, no other handling is required.
*/
- ASC_DBG1(1, "advansys_abort: scp %x found on waiting queue\n",
- (unsigned) scp);
+ ASC_DBG1(1, "advansys_abort: scp %lx found on waiting queue\n",
+ (ulong) scp);
scp_found = ASC_TRUE;
scp->result = HOST_BYTE(DID_ABORT);
ret = SCSI_ABORT_SUCCESS;
scp->result = HOST_BYTE(DID_ABORT);
/* sti(); XXX */ /* Enable interrupts for AscAbortSRB(). */
- ASC_DBG1(1, "advansys_abort: before AscAbortSRB(), scp %x\n",
- (unsigned) scp);
- switch (AscAbortSRB(asc_dvc_varp, (ulong) scp)) {
+ ASC_DBG1(1, "advansys_abort: before AscAbortSRB(), scp %lx\n",
+ (ulong) scp);
+ /* XXX */
+ switch (AscAbortSRB(asc_dvc_varp, ASC_VADDR_TO_U32(scp))) {
case ASC_TRUE:
/* asc_isr_callback() will be called */
ASC_DBG(1, "advansys_abort: AscAbortSRB() TRUE\n");
adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
scp->result = HOST_BYTE(DID_ABORT);
- ASC_DBG1(1, "advansys_abort: before AdvAbortQueue(), scp %x\n",
- (unsigned) scp);
+ ASC_DBG1(1,
+ "advansys_abort: before AdvAbortQueue(), scp %lx\n",
+ (ulong) scp);
#if 0 /* XXX */
- switch (AdvAbortQueue(adv_dvc_varp, (ulong) XXX)) {
+ switch (AdvAbortQueue(adv_dvc_varp, (ADV_VADDR) XXX)) {
case ASC_TRUE:
/* asc_isr_callback() will be called */
ASC_DBG(1, "advansys_abort: AdvAbortQueue() TRUE\n");
if (do_scsi_done == ASC_TRUE) {
if (scp->scsi_done == NULL) {
ASC_PRINT1(
-"advansys_abort: aborted request scsi_done() is NULL, %x\n",
- (unsigned) scp);
+"advansys_abort: aborted request scsi_done() is NULL, %lx\n",
+ (ulong) scp);
} else {
if (scp_found == ASC_FALSE) {
ASC_PRINT1(
-"advansys_abort: abort request not active or waiting, completing anyway %x\n",
- (unsigned) scp);
+"advansys_abort: abort request not active or waiting, completing anyway %lx\n",
+ (ulong) scp);
}
ASC_STATS(scp->host, done);
scp->scsi_done(scp);
save_flags(flags);
cli();
- ASC_DBG1(1, "advansys_reset: %x\n", (unsigned) scp);
+ ASC_DBG1(1, "advansys_reset: %lx\n", (ulong) scp);
#ifdef ADVANSYS_STATS
if (scp->host != NULL) {
if ((reset_flags & SCSI_RESET_ASYNCHRONOUS) &&
(scp->serial_number != scp->serial_number_at_timeout)) {
ASC_PRINT1(
-"advansys_reset: timeout serial number changed for request %x\n",
- (unsigned) scp);
+"advansys_reset: timeout serial number changed for request %lx\n",
+ (ulong) scp);
do_scsi_done = ASC_FALSE;
scp_found = ASC_FALSE;
ret = SCSI_RESET_NOT_RUNNING;
if (do_scsi_done == ASC_TRUE) {
if (scp->scsi_done == NULL) {
ASC_PRINT1(
-"advansys_reset: reset request scsi_done() is NULL, %x\n",
- (unsigned) scp);
+"advansys_reset: reset request scsi_done() is NULL, %lx\n",
+ (ulong) scp);
} else {
if (scp_found == ASC_FALSE) {
ASC_PRINT1(
-"advansys_reset: reset request not active or waiting, completing anyway %x\n",
- (unsigned) scp);
+"advansys_reset: reset request not active or waiting, completing anyway %lx\n",
+ (ulong) scp);
}
ASC_STATS(scp->host, done);
scp->scsi_done(scp);
device->queue_depth =
boardp->dvc_var.adv_dvc_var.max_dvc_qng;
}
- ASC_DBG3(1, "advansys_select_queue_depths: shp %x, id %d, depth %d\n",
- (unsigned) shp, device->id, device->queue_depth);
+ ASC_DBG3(1, "advansys_select_queue_depths: shp %lx, id %d, depth %d\n",
+ (ulong) shp, device->id, device->queue_depth);
}
}
#endif /* version >= v1.3.89 */
STATIC void
advansys_command_done(Scsi_Cmnd *scp)
{
- ASC_DBG1(1, "advansys_command_done: scp %x\n", (unsigned) scp);
+ ASC_DBG1(1, "advansys_command_done: scp %lx\n", (ulong) scp);
scp->SCp.Status = 1;
}
ASC_DBG(2, "asc_scsi_done_list: begin\n");
while (scp != NULL) {
- ASC_DBG1(3, "asc_scsi_done_list: scp %x\n", (unsigned) scp);
+ ASC_DBG1(3, "asc_scsi_done_list: scp %lx\n", (ulong) scp);
tscp = REQPNEXT(scp);
REQPNEXT(scp) = NULL;
ASC_STATS(scp->host, done);
int ret;
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
- ASC_DBG2(1, "asc_execute_scsi_cmnd: scp %x, done %x\n",
- (unsigned) scp, (unsigned) scp->scsi_done);
+ ASC_DBG2(1, "asc_execute_scsi_cmnd: scp %lx, done %lx\n",
+ (ulong) scp, (ulong) scp->scsi_done);
boardp = ASC_BOARDP(scp->host);
device = boardp->device[scp->target];
/*
* Point the ASC_SCSI_Q to the 'Scsi_Cmnd'.
*/
- asc_scsi_q.q2.srb_ptr = (ulong) scp;
+ asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
/*
* Build the ASC_SCSI_Q request.
asc_scsi_q.q1.target_lun = scp->lun;
asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->target, scp->lun);
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- asc_scsi_q.q1.sense_addr = (ulong) &scp->sense_buffer[0];
+ asc_scsi_q.q1.sense_addr = (ADV_PADDR) &scp->sense_buffer[0];
#else /* version >= v2.0.0 */
- asc_scsi_q.q1.sense_addr = virt_to_bus(&scp->sense_buffer[0]);
+ asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
#endif /* version >= v2.0.0 */
asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
*/
ASC_STATS(scp->host, cont_cnt);
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- asc_scsi_q.q1.data_addr = (ulong) scp->request_buffer;
+ asc_scsi_q.q1.data_addr = (ADV_PADDR) scp->request_buffer;
#else /* version >= v2.0.0 */
- asc_scsi_q.q1.data_addr = virt_to_bus(scp->request_buffer);
+ asc_scsi_q.q1.data_addr =
+ cpu_to_le32(virt_to_bus(scp->request_buffer));
#endif /* version >= v2.0.0 */
asc_scsi_q.q1.data_cnt = scp->request_bufflen;
ASC_STATS_ADD(scp->host, cont_xfer,
slp = (struct scatterlist *) scp->request_buffer;
for (sgcnt = 0; sgcnt < scp->use_sg; sgcnt++, slp++) {
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- asc_sg_head.sg_list[sgcnt].addr = (ulong) slp->address;
+ asc_sg_head.sg_list[sgcnt].addr = (ADV_PADDR) slp->address;
#else /* version >= v2.0.0 */
- asc_sg_head.sg_list[sgcnt].addr = virt_to_bus(slp->address);
+ asc_sg_head.sg_list[sgcnt].addr =
+ cpu_to_le32(virt_to_bus(slp->address));
#endif /* version >= v2.0.0 */
- asc_sg_head.sg_list[sgcnt].bytes = slp->length;
+ asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(slp->length);
ASC_STATS_ADD(scp->host, sg_xfer, ASC_CEILING(slp->length, 512));
}
}
*
* If an adv_req_t can not be allocated to issue the request,
* then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
+ *
+ * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
+ * microcode for DMA addresses or math operations are byte swapped
+ * to little-endian order.
*/
STATIC int
adv_build_req(asc_board_t *boardp, Scsi_Cmnd *scp,
adv_req_t *reqp;
ADV_SCSI_REQ_Q *scsiqp;
int i;
+ int ret;
/*
* Allocate an adv_req_t structure from the board to execute
* Get 4-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
*/
scsiqp = (ADV_SCSI_REQ_Q *) ADV_DWALIGN(&reqp->scsi_req_q);
- memset(scsiqp, 0, sizeof(ADV_SCSI_REQ_Q));
+
+ /*
+ * Initialize the structure.
+ */
+ scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
/*
* Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
*/
- scsiqp->srb_ptr = (ulong) reqp;
+ scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
/*
* Set the adv_req_t 'cmndp' to point to the Scsi_Cmnd structure.
scsiqp->target_lun = scp->lun;
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- scsiqp->sense_addr = (ulong) &scp->sense_buffer[0];
+ scsiqp->sense_addr = (ADV_PADDR) &scp->sense_buffer[0];
#else /* version >= v2.0.0 */
- scsiqp->sense_addr = virt_to_bus(&scp->sense_buffer[0]);
+ scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
#endif /* version >= v2.0.0 */
scsiqp->sense_len = sizeof(scp->sense_buffer);
* Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
* buffer command.
*/
- scsiqp->data_cnt = scp->request_bufflen;
- scsiqp->vdata_addr = (ulong) scp->request_buffer;
+ scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
+ scsiqp->vdata_addr = scp->request_buffer;
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- scsiqp->data_addr = (ulong) scp->request_buffer;
+ scsiqp->data_addr = (ADV_PADDR) scp->request_buffer;
#else /* version >= v2.0.0 */
- scsiqp->data_addr = virt_to_bus(scp->request_buffer);
+ scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
#endif /* version >= v2.0.0 */
if (scp->use_sg == 0) {
*/
reqp->sgblkp = NULL;
scsiqp->sg_list_ptr = NULL;
+ scsiqp->sg_real_addr = 0;
ASC_STATS(scp->host, cont_cnt);
ASC_STATS_ADD(scp->host, cont_xfer,
ASC_CEILING(scp->request_bufflen, 512));
return ASC_ERROR;
}
- /*
- * Allocate an 'adv_sgblk_t' structure from the board to
- * execute the command.
- */
- if (boardp->adv_sgblkp == NULL) {
- ASC_DBG(1, "adv_build_req: no free adv_sgblk_t\n");
- ASC_STATS(scp->host, adv_build_nosg);
- /*
- * Free the 'adv_req_t' structure by adding it back to the
- * board free list.
- */
- reqp->next_reqp = boardp->adv_reqp;
- boardp->adv_reqp = reqp;
- return ASC_BUSY;
- } else {
- reqp->sgblkp = boardp->adv_sgblkp;
- boardp->adv_sgblkp = reqp->sgblkp->next_sgblkp;
- reqp->sgblkp->next_sgblkp = NULL;
- }
-
- /*
- * Build scatter-gather list.
- */
- scsiqp->sg_list_ptr = (ADV_SG_BLOCK *)
- ADV_DWALIGN(&reqp->sgblkp->sg_block[0]);
-
- memset(scsiqp->sg_list_ptr, 0, sizeof(ADV_SG_BLOCK) *
- (ADV_NUM_SG_BLOCK + ADV_NUM_PAGE_CROSSING));
-
- if (adv_get_sglist(&boardp->dvc_var.adv_dvc_var, scsiqp, scp) ==
- ADV_ERROR) {
-
- /*
- * Free the adv_sgblk_t structure, if any, by adding it back
- * to the board free list.
- */
- ASC_ASSERT(reqp->sgblkp != NULL);
- reqp->sgblkp->next_sgblkp = boardp->adv_sgblkp;
- boardp->adv_sgblkp = reqp->sgblkp;
-
+ if ((ret = adv_get_sglist(boardp, reqp, scp)) != ADV_SUCCESS) {
/*
* Free the adv_req_t structure by adding it back to the
* board free list.
reqp->next_reqp = boardp->adv_reqp;
boardp->adv_reqp = reqp;
- return ADV_ERROR;
+ return ret;
}
ASC_STATS(scp->host, sg_cnt);
/*
* Build scatter-gather list for Adv Library (Wide Board).
*
+ * Additional ADV_SG_BLOCK structures will need to be allocated
+ * if the total number of scatter-gather elements exceeds
+ * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
+ * assumed to be physically contiguous.
+ *
* Return:
* ADV_SUCCESS(1) - SG List successfully created
* ADV_ERROR(-1) - SG List creation failed
*/
STATIC int
-adv_get_sglist(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp,
- Scsi_Cmnd *scp)
+adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, Scsi_Cmnd *scp)
{
- ADV_SG_BLOCK *sg_block; /* virtual address of a SG */
- ulong sg_block_next_addr; /* block and its next */
- ulong sg_block_physical_addr;
- int i;
+ adv_sgblk_t *sgblkp;
+ ADV_SCSI_REQ_Q *scsiqp;
struct scatterlist *slp;
int sg_elem_cnt;
+ ADV_SG_BLOCK *sg_block, *prev_sg_block;
+ ADV_PADDR sg_block_paddr;
+ int i;
+ scsiqp = (ADV_SCSI_REQ_Q *) ADV_DWALIGN(&reqp->scsi_req_q);
slp = (struct scatterlist *) scp->request_buffer;
sg_elem_cnt = scp->use_sg;
+ prev_sg_block = NULL;
+
+ ASC_ASSERT(reqp->sgblkp == NULL);
+ do
+ {
+ /*
+ * Allocate a 'adv_sgblk_t' structure from the board free
+ * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
+ * (15) scatter-gather elements.
+ */
+ if ((sgblkp = boardp->adv_sgblkp) == NULL) {
+ ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
+ ASC_STATS(scp->host, adv_build_nosg);
+
+ /*
+ * Allocation failed. Free 'adv_sgblk_t' structures already
+ * allocated for the request.
+ */
+ while ((sgblkp = reqp->sgblkp) != NULL)
+ {
+ /* Remove 'sgblkp' from the request list. */
+ reqp->sgblkp = sgblkp->next_sgblkp;
- sg_block = scsiqp->sg_list_ptr;
- sg_block_next_addr = (ulong) sg_block; /* allow math operation */
- sg_block_physical_addr =
+ /* Add 'sgblkp' to the board free list. */
+ sgblkp->next_sgblkp = boardp->adv_sgblkp;
+ boardp->adv_sgblkp = sgblkp;
+ }
+ return ASC_BUSY;
+ } else {
+ /* Complete 'adv_sgblk_t' board allocation. */
+ boardp->adv_sgblkp = sgblkp->next_sgblkp;
+ sgblkp->next_sgblkp = NULL;
+
+ /*
+ * Get 4 byte aligned virtual and physical addresses for
+ * the allocated ADV_SG_BLOCK structure.
+ */
+ sg_block = (ADV_SG_BLOCK *) ADV_DWALIGN(&sgblkp->sg_block);
+ sg_block_paddr =
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- (ulong) scsiqp->sg_list_ptr;
+ (ADV_PADDR) sg_block;
#else /* version >= v2.0.0 */
- virt_to_bus(scsiqp->sg_list_ptr);
+ virt_to_bus(sg_block);
#endif /* version >= v2.0.0 */
- ADV_ASSERT(ADV_DWALIGN(sg_block_physical_addr) ==
- sg_block_physical_addr);
- scsiqp->sg_real_addr = sg_block_physical_addr;
- do
- {
+ /*
+ * Check if this is the first 'adv_sgblk_t' for the request.
+ */
+ if (reqp->sgblkp == NULL)
+ {
+ /* Request's first scatter-gather block. */
+ reqp->sgblkp = sgblkp;
+
+ /*
+ * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
+ * address pointers.
+ */
+ scsiqp->sg_list_ptr = sg_block;
+ scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
+ } else
+ {
+ /* Request's second or later scatter-gather block. */
+ sgblkp->next_sgblkp = reqp->sgblkp;
+ reqp->sgblkp = sgblkp;
+
+ /*
+ * Point the previous ADV_SG_BLOCK structure to
+ * the newly allocated ADV_SG_BLOCK structure.
+ */
+ ASC_ASSERT(prev_sg_block != NULL);
+ prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
+ }
+ }
+
for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
{
sg_block->sg_list[i].sg_addr =
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- (ulong) slp->address;
+ (ADV_PADDR) slp->address;
#else /* version >= v2.0.0 */
- virt_to_bus(slp->address);
+ cpu_to_le32(virt_to_bus(slp->address));
#endif /* version >= v2.0.0 */
- sg_block->sg_list[i].sg_count = slp->length;
+ sg_block->sg_list[i].sg_count = cpu_to_le32(slp->length);
ASC_STATS_ADD(scp->host, sg_xfer, ASC_CEILING(slp->length, 512));
if (--sg_elem_cnt == 0)
- { /* last entry, get out */
+ { /* Last ADV_SG_BLOCK and scatter-gather entry. */
sg_block->sg_cnt = i + 1;
- sg_block->sg_ptr = 0L; /* next link = NULL */
+ sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
return ADV_SUCCESS;
}
slp++;
- }
+ }
sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
- sg_block_next_addr += sizeof(ADV_SG_BLOCK);
- sg_block_physical_addr += sizeof(ADV_SG_BLOCK);
- ADV_ASSERT(ADV_DWALIGN(sg_block_physical_addr) ==
- sg_block_physical_addr);
-
- sg_block->sg_ptr = (ADV_SG_BLOCK *) sg_block_physical_addr;
- sg_block = (ADV_SG_BLOCK *) sg_block_next_addr; /* virtual addr */
+ prev_sg_block = sg_block;
}
while (1);
/* NOTREACHED */
asc_board_t *boardp;
Scsi_Cmnd *scp;
struct Scsi_Host *shp;
- int underrun = ASC_FALSE;
int i;
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
- ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp %x, qdonep %x\n",
- (unsigned) asc_dvc_varp, (unsigned) qdonep);
+ ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp %lx, qdonep %lx\n",
+ (ulong) asc_dvc_varp, (ulong) qdonep);
ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
/*
* Get the Scsi_Cmnd structure and Scsi_Host structure for the
* command that has been completed.
*/
- scp = (Scsi_Cmnd *) qdonep->d2.srb_ptr;
- ASC_DBG1(1, "asc_isr_callback: scp %x\n", (unsigned) scp);
+ scp = (Scsi_Cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
+ ASC_DBG1(1, "asc_isr_callback: scp %lx\n", (ulong) scp);
if (scp == NULL) {
ASC_PRINT("asc_isr_callback: scp is NULL\n");
}
}
if (i == asc_board_count) {
- ASC_PRINT2("asc_isr_callback: scp %x has bad host pointer, host %x\n",
- (unsigned) scp, (unsigned) shp);
+ ASC_PRINT2(
+ "asc_isr_callback: scp %lx has bad host pointer, host %lx\n",
+ (ulong) scp, (ulong) shp);
return;
}
ASC_STATS(shp, callback);
- ASC_DBG1(1, "asc_isr_callback: shp %x\n", (unsigned) shp);
+ ASC_DBG1(1, "asc_isr_callback: shp %lx\n", (ulong) shp);
/*
* If the request isn't found on the active queue, it may
boardp = ASC_BOARDP(shp);
ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
- ASC_PRINT2("asc_isr_callback: board %d: scp %x not on active queue\n",
- boardp->id, (unsigned) scp);
+ ASC_PRINT2(
+ "asc_isr_callback: board %d: scp %lx not on active queue\n",
+ boardp->id, (ulong) scp);
return;
}
- /*
- * Check for an underrun condition.
- */
- if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
- qdonep->remain_bytes <= scp->request_bufflen != 0) {
- ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
- (unsigned) qdonep->remain_bytes);
- underrun = ASC_TRUE;
- }
-
/*
* 'qdonep' contains the command's ending status.
*/
switch (qdonep->d3.done_stat) {
case QD_NO_ERROR:
ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
- switch (qdonep->d3.host_stat) {
- case QHSTA_NO_ERROR:
- scp->result = 0;
- break;
- default:
- /* QHSTA error occurred */
- scp->result = HOST_BYTE(DID_ERROR);
- break;
- }
+ scp->result = 0;
/*
* If an INQUIRY command completed successfully, then call
(ASC_SCSI_INQUIRY *) scp->request_buffer);
}
+#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,3,19)
/*
- * If there was an underrun without any other error,
- * set DID_ERROR to indicate the underrun error.
+ * Check for an underrun condition.
*
- * Note: There is no way yet to indicate the number
- * of underrun bytes.
+ * If there was no error and an underrun condition, then
+ * then return the number of underrun bytes.
*/
- if (scp->result == 0 && underrun == ASC_TRUE) {
- scp->result = HOST_BYTE(DID_UNDERRUN);
+ if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
+ qdonep->remain_bytes <= scp->request_bufflen != 0) {
+ ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
+ (unsigned) qdonep->remain_bytes);
+ scp->resid = qdonep->remain_bytes;
}
+#endif /* version >= v2.3.19 */
break;
case QD_WITH_ERROR:
{
asc_board_t *boardp;
adv_req_t *reqp;
+ adv_sgblk_t *sgblkp;
Scsi_Cmnd *scp;
struct Scsi_Host *shp;
- int underrun = ASC_FALSE;
int i;
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
- ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp %x, scsiqp %x\n",
- (unsigned) adv_dvc_varp, (unsigned) scsiqp);
+ ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp %lx, scsiqp %lx\n",
+ (ulong) adv_dvc_varp, (ulong) scsiqp);
ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
/*
* completed. The adv_req_t structure actually contains the
* completed ADV_SCSI_REQ_Q structure.
*/
- reqp = (adv_req_t *) scsiqp->srb_ptr;
- ASC_DBG1(1, "adv_isr_callback: reqp %x\n", (unsigned) reqp);
+ reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
+ ASC_DBG1(1, "adv_isr_callback: reqp %lx\n", (ulong) reqp);
if (reqp == NULL) {
ASC_PRINT("adv_isr_callback: reqp is NULL\n");
return;
* determined.
*/
scp = reqp->cmndp;
- ASC_DBG1(1, "adv_isr_callback: scp %x\n", (unsigned) scp);
+ ASC_DBG1(1, "adv_isr_callback: scp %lx\n", (ulong) scp);
if (scp == NULL) {
ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
return;
* structure and adv_sgblk_t structure, if any, is dropped.
*/
if (i == asc_board_count) {
- ASC_PRINT2("adv_isr_callback: scp %x has bad host pointer, host %x\n",
- (unsigned) scp, (unsigned) shp);
+ ASC_PRINT2(
+ "adv_isr_callback: scp %lx has bad host pointer, host %lx\n",
+ (ulong) scp, (ulong) shp);
return;
}
ASC_STATS(shp, callback);
- ASC_DBG1(1, "adv_isr_callback: shp %x\n", (unsigned) shp);
+ ASC_DBG1(1, "adv_isr_callback: shp %lx\n", (ulong) shp);
/*
* If the request isn't found on the active queue, it may have been
boardp = ASC_BOARDP(shp);
ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
- ASC_PRINT2("adv_isr_callback: board %d: scp %x not on active queue\n",
- boardp->id, (unsigned) scp);
+ ASC_PRINT2(
+ "adv_isr_callback: board %d: scp %lx not on active queue\n",
+ boardp->id, (ulong) scp);
return;
}
- /*
- * Check for an underrun condition.
- */
- if (scp->request_bufflen != 0 && scsiqp->data_cnt != 0) {
- ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
- scsiqp->data_cnt);
- underrun = ASC_TRUE;
- }
-
/*
* 'done_status' contains the command's ending status.
*/
switch (scsiqp->done_status) {
case QD_NO_ERROR:
ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
- switch (scsiqp->host_status) {
- case QHSTA_NO_ERROR:
- scp->result = 0;
- break;
- default:
- /* QHSTA error occurred. */
- ASC_DBG1(2, "adv_isr_callback: host_status %x\n",
- scsiqp->host_status);
- scp->result = HOST_BYTE(DID_ERROR);
- break;
- }
+ scp->result = 0;
+
+#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,3,19)
/*
- * If there was an underrun without any other error,
- * set DID_ERROR to indicate the underrun error.
+ * Check for an underrun condition.
*
- * Note: There is no way yet to indicate the number
- * of underrun bytes.
+ * If there was no error and an underrun condition, then
+ * then return the number of underrun bytes.
*/
- if (scp->result == 0 && underrun == ASC_TRUE) {
- scp->result = HOST_BYTE(DID_UNDERRUN);
+ if (scp->request_bufflen != 0 && scsiqp->data_cnt != 0 &&
+ scsiqp->data_cnt <= scp->request_bufflen) {
+ ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
+ (ulong) scsiqp->data_cnt);
+ scp->resid = scsiqp->data_cnt;
}
+#endif /* version >= v2.3.19 */
break;
case QD_WITH_ERROR:
asc_enqueue(&boardp->done, scp, ASC_BACK);
/*
- * Free the adv_sgblk_t structure, if any, by adding it back
- * to the board free list.
+ * Free all 'adv_sgblk_t' structures allocated for the request.
*/
- if (reqp->sgblkp != NULL) {
- reqp->sgblkp->next_sgblkp = boardp->adv_sgblkp;
- boardp->adv_sgblkp = reqp->sgblkp;
+ while ((sgblkp = reqp->sgblkp) != NULL)
+ {
+ /* Remove 'sgblkp' from the request list. */
+ reqp->sgblkp = sgblkp->next_sgblkp;
+
+ /* Add 'sgblkp' to the board free list. */
+ sgblkp->next_sgblkp = boardp->adv_sgblkp;
+ boardp->adv_sgblkp = sgblkp;
}
/*
)
{
ushort tmp;
- ulong address;
- ulong lbus = pciData->bus;
- ulong lslot = pciData->slot;
- ulong lfunc = pciData->func;
+ ADV_DCNT address;
+ ADV_DCNT lbus = pciData->bus;
+ ADV_DCNT lslot = pciData->slot;
+ ADV_DCNT lfunc = pciData->func;
uchar t2CFA, t2CF8;
- ulong t1CF8, t1CFC;
+ ADV_DCNT t1CF8, t1CFC;
- ASC_DBG4(4, "asc_get_cfg_word: type %d, bus %lu, slot %lu, func %lu\n",
- pciData->type, lbus, lslot, lfunc);
+ ASC_DBG4(4, "asc_get_cfg_word: type %d, bus %u, slot %u, func %u\n",
+ pciData->type, (unsigned) lbus, (unsigned) lslot, (unsigned) lfunc);
/*
* Check type of configuration mechanism.
* enable <31>, bus = <23:16>, slot = <15:11>,
* func = <10:8>, reg = <7:2>
*/
- address = (ulong) ((lbus << 16) | (lslot << 11) |
+ address = (ADV_DCNT) ((lbus << 16) | (lslot << 11) |
(lfunc << 8) | (pciData->offset & 0xFC) | 0x80000000L);
/*
asc_get_cfg_byte(PCI_DATA *pciData)
)
{
- uchar tmp;
- ulong address;
- ulong lbus = pciData->bus, lslot = pciData->slot, lfunc = pciData->func;
- uchar t2CFA, t2CF8;
- ulong t1CF8, t1CFC;
+ uchar tmp;
+ ADV_DCNT address;
+ ADV_DCNT lbus = pciData->bus, lslot = pciData->slot, lfunc = pciData->func;
+ ADV_DCNT t2CFA, t2CF8;
+ ADV_DCNT t1CF8, t1CFC;
ASC_DBG1(4, "asc_get_cfg_byte: type: %d\n", pciData->type);
* enable <31>, bus = <23:16>, slot = <15:11>, func = <10:8>,
* reg = <7:2>
*/
- address = (ulong) ((lbus << 16) | (lslot << 11) |
+ address = (ADV_DCNT) ((lbus << 16) | (lslot << 11) |
(lfunc << 8) | (pciData->offset & 0xFC) | 0x80000000L);
/*
asc_put_cfg_byte(PCI_DATA *pciData, uchar byte_data)
)
{
- ulong tmpl;
- ulong address;
- ulong lbus = pciData->bus, lslot = pciData->slot, lfunc = pciData->func;
- uchar t2CFA, t2CF8;
- ulong t1CF8, t1CFC;
+ ADV_DCNT tmpl;
+ ADV_DCNT address;
+ ADV_DCNT lbus = pciData->bus, lslot = pciData->slot, lfunc = pciData->func;
+ uchar t2CFA, t2CF8;
+ ADV_DCNT t1CF8, t1CFC;
ASC_DBG2(4, "asc_put_cfg_byte: type: %d, byte_data %x\n",
pciData->type, byte_data);
* enable <31>, bus = <23:16>, slot = <15:11>, func = <10:8>,
* reg = <7:2>
*/
- address = (ulong) ((lbus << 16) | (lslot << 11) | (lfunc << 8) |
+ address = (ADV_DCNT) ((lbus << 16) | (lslot << 11) | (lfunc << 8) |
(pciData->offset & 0xFC) | 0x80000000L);
/*
* Write out address to CONFIG_ADDRESS.
{
int tid;
- ASC_DBG3(3, "asc_enqueue: ascq %x, reqp %x, flag %d\n",
- (unsigned) ascq, (unsigned) reqp, flag);
+ ASC_DBG3(3, "asc_enqueue: ascq %lx, reqp %lx, flag %d\n",
+ (ulong) ascq, (ulong) reqp, flag);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
ASC_ASSERT(reqp != NULL);
ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
}
REQPTIME(reqp) = REQTIMESTAMP();
#endif /* ADVANSYS_STATS */
- ASC_DBG1(3, "asc_enqueue: reqp %x\n", (unsigned) reqp);
+ ASC_DBG1(3, "asc_enqueue: reqp %lx\n", (ulong) reqp);
return;
}
{
REQP reqp;
- ASC_DBG2(3, "asc_dequeue: ascq %x, tid %d\n", (unsigned) ascq, tid);
+ ASC_DBG2(3, "asc_dequeue: ascq %lx, tid %d\n", (ulong) ascq, tid);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
if ((reqp = ascq->q_first[tid]) != NULL) {
REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
#endif /* ADVANSYS_STATS */
}
- ASC_DBG1(3, "asc_dequeue: reqp %x\n", (unsigned) reqp);
+ ASC_DBG1(3, "asc_dequeue: reqp %lx\n", (ulong) reqp);
return reqp;
}
REQP firstp, lastp;
int i;
- ASC_DBG2(3, "asc_dequeue_list: ascq %x, tid %d\n", (unsigned) ascq, tid);
+ ASC_DBG2(3, "asc_dequeue_list: ascq %lx, tid %d\n", (ulong) ascq, tid);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
if (lastpp) {
*lastpp = lastp;
}
- ASC_DBG1(3, "asc_dequeue_list: firstp %x\n", (unsigned) firstp);
+ ASC_DBG1(3, "asc_dequeue_list: firstp %lx\n", (ulong) firstp);
return firstp;
}
int tid;
int ret = ASC_FALSE;
- ASC_DBG2(3, "asc_rmqueue: ascq %x, reqp %x\n",
- (unsigned) ascq, (unsigned) reqp);
+ ASC_DBG2(3, "asc_rmqueue: ascq %lx, reqp %lx\n",
+ (ulong) ascq, (ulong) reqp);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
ASC_ASSERT(reqp != NULL);
}
ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
#endif /* ADVANSYS_STATS */
- ASC_DBG2(3, "asc_rmqueue: reqp %x, ret %d\n", (unsigned) reqp, ret);
+ ASC_DBG2(3, "asc_rmqueue: reqp %lx, ret %d\n", (ulong) reqp, ret);
return ret;
}
int tid;
int ret = ASC_FALSE;
- ASC_DBG2(3, "asc_isqueued: ascq %x, reqp %x\n",
- (unsigned) ascq, (unsigned) reqp);
+ ASC_DBG2(3, "asc_isqueued: ascq %lx, reqp %lx\n",
+ (ulong) ascq, (ulong) reqp);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
ASC_ASSERT(reqp != NULL);
REQP reqp;
int i;
- ASC_DBG1(1, "asc_execute_queue: ascq %x\n", (unsigned) ascq);
+ ASC_DBG1(1, "asc_execute_queue: ascq %lx\n", (ulong) ascq);
ASC_ASSERT(interrupts_enabled() == ASC_FALSE);
/*
* Execute queued commands for devices attached to
int leftlen;
int totlen;
int len;
- int upgrade = ASC_FALSE;
ushort major, minor, letter;
boardp = ASC_BOARDP(shp);
* the BIOS code segment base address.
*/
if (boardp->bios_signature != 0x55AA) {
- len = asc_prt_line(cp, leftlen, "Pre-3.1\n");
+ len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
+ ASC_PRT_NEXT();
+ len = asc_prt_line(cp, leftlen,
+"BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
+ ASC_PRT_NEXT();
+ len = asc_prt_line(cp, leftlen,
+"can be found at the AdvanSys FTP site: ftp://ftp.advansys.com/pub\n");
ASC_PRT_NEXT();
- upgrade = ASC_TRUE;
} else {
major = (boardp->bios_version >> 12) & 0xF;
minor = (boardp->bios_version >> 8) & 0xF;
major, minor, letter >= 26 ? '?' : letter + 'A');
ASC_PRT_NEXT();
- /* Current available ROM BIOS release is 3.1C. */
+ /*
+ * Current available ROM BIOS release is 3.1I for UW
+ * and 3.2I for U2W. This code doesn't differentiate
+ * UW and U2W boards.
+ */
if (major < 3 || (major <= 3 && minor < 1) ||
- (major <= 3 && minor <= 1 && letter < ('C'- 'A'))) {
- upgrade = ASC_TRUE;
- }
- }
- if (upgrade == ASC_TRUE) {
- len = asc_prt_line(cp, leftlen,
-"Newer version of ROM BIOS available: ftp://ftp.advansys.com/pub\n");
+ (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
+ len = asc_prt_line(cp, leftlen,
+"Newer version of ROM BIOS is available at the AdvanSys FTP site:\n");
+ ASC_PRT_NEXT();
+ len = asc_prt_line(cp, leftlen,
+"ftp://ftp.advansys.com/pub\n");
ASC_PRT_NEXT();
+ }
}
return totlen;
if (offset <= advoffset) {
/* Read offset below current offset, copy everything. */
cnt = ASC_MIN(cplen, leftlen);
- ASC_DBG3(2, "asc_proc_copy: curbuf %x, cp %x, cnt %d\n",
- (unsigned) curbuf, (unsigned) cp, cnt);
+ ASC_DBG3(2, "asc_proc_copy: curbuf %lx, cp %lx, cnt %d\n",
+ (ulong) curbuf, (ulong) cp, cnt);
memcpy(curbuf, cp, cnt);
} else if (offset < advoffset + cplen) {
/* Read offset within current range, partial copy. */
cnt = (advoffset + cplen) - offset;
cp = (cp + cplen) - cnt;
cnt = ASC_MIN(cnt, leftlen);
- ASC_DBG3(2, "asc_proc_copy: curbuf %x, cp %x, cnt %d\n",
- (unsigned) curbuf, (unsigned) cp, cnt);
+ ASC_DBG3(2, "asc_proc_copy: curbuf %lx, cp %lx, cnt %d\n",
+ (ulong) curbuf, (ulong) cp, cnt);
memcpy(curbuf, cp, cnt);
}
return cnt;
* called when interrupts are disabled.
*/
STATIC void
-DvcSleepMilliSecond(ulong n)
+DvcSleepMilliSecond(ADV_DCNT n)
{
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,1,0)
- ulong i;
+ ADV_DCNT i;
#endif /* version < v2.1.0 */
- ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", n);
+ ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(2,1,0)
mdelay(n);
#else /* version < v2.1.0 */
restore_flags(flags);
}
-STATIC ulong
-DvcGetSGList(ASC_DVC_VAR *asc_dvc_sg, uchar *buf_addr, ulong buf_len,
+STATIC ADV_DCNT
+DvcGetSGList(ASC_DVC_VAR *asc_dvc_sg, uchar *buf_addr, ADV_DCNT buf_len,
ASC_SG_HEAD *asc_sg_head_ptr)
{
- ulong buf_size;
+ ADV_DCNT buf_size;
buf_size = buf_len;
asc_sg_head_ptr->entry_cnt = 1;
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- asc_sg_head_ptr->sg_list[0].addr = (ulong) buf_addr;
+ asc_sg_head_ptr->sg_list[0].addr = (ADV_PADDR) buf_addr;
#else /* version >= v2.0.0 */
asc_sg_head_ptr->sg_list[0].addr = virt_to_bus(buf_addr);
#endif /* version >= v2.0.0 */
}
/*
- * void DvcOutPortDWords(PortAddr port, ulong *pdw, int dwords)
+ * void DvcOutPortDWords(PortAddr port, ADV_DCNT *pdw, int dwords)
*
* Calling/Exit State:
* none
* 16 bit integer units
*/
STATIC void
-DvcOutPortDWords(PortAddr port, ulong *pdw, int dwords)
+DvcOutPortDWords(PortAddr port, ADV_DCNT *pdw, int dwords)
{
- int i;
- int words;
+ int i;
+ int words;
ushort *pw;
pw = (ushort *) pdw;
ASC_INITFUNC(
STATIC uchar,
DvcReadPCIConfigByte(
- ASC_DVC_VAR asc_ptr_type *asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
ushort offset)
)
{
ASC_INITFUNC(
STATIC void,
DvcWritePCIConfigByte(
- ASC_DVC_VAR asc_ptr_type *asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
ushort offset,
uchar byte_data)
)
* Note: Because Linux currently doesn't page the kernel and all
* kernel buffers are physically contiguous, leave '*lenp' unchanged.
*/
-ulong
+ADV_PADDR
DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
- uchar *vaddr, long *lenp, int flag)
+ uchar *vaddr, ADV_SDCNT *lenp, int flag)
{
- ulong paddr;
+ ADV_PADDR paddr;
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(2,0,0)
- paddr = (ulong) vaddr;
+ paddr = (ADV_PADDR) vaddr;
#else /* version >= v2.0.0 */
paddr = virt_to_bus(vaddr);
#endif /* version >= v2.0.0 */
ASC_DBG4(4,
"DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
- (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), paddr);
+ (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
return paddr;
}
boardp = ASC_BOARDP(s);
- printk("Scsi_Host at addr %x\n", (unsigned) s);
+ printk("Scsi_Host at addr %lx\n", (ulong) s);
printk(
-" next %x, extra_bytes %u, host_busy %u, host_no %d, last_reset %d,\n",
- (unsigned) s->next, s->extra_bytes, s->host_busy, s->host_no,
+" next %lx, extra_bytes %u, host_busy %u, host_no %d, last_reset %d,\n",
+ (ulong) s->next, s->extra_bytes, s->host_busy, s->host_no,
(unsigned) s->last_reset);
printk(
-" host_queue %x, hostt %x, block %x,\n",
- (unsigned) s->host_queue, (unsigned) s->hostt, (unsigned) s->block);
+" host_queue %lx, hostt %lx, block %lx,\n",
+ (ulong) s->host_queue, (ulong) s->hostt, (ulong) s->block);
printk(
" wish_block %d, base %lu, io_port %lu, n_io_port %u, irq %d,\n",
STATIC void
asc_prt_scsi_cmnd(Scsi_Cmnd *s)
{
- printk("Scsi_Cmnd at addr %x\n", (unsigned) s);
+ printk("Scsi_Cmnd at addr %lx\n", (ulong) s);
#if LINUX_VERSION_CODE < ASC_LINUX_VERSION(1,3,0)
printk(
(unsigned) s->host, (unsigned) s->device, s->target, s->lun);
#else /* version >= v1.3.0 */
printk(
-" host %x, device %x, target %u, lun %u, channel %u,\n",
- (unsigned) s->host, (unsigned) s->device, s->target, s->lun,
+" host %lx, device %lx, target %u, lun %u, channel %u,\n",
+ (ulong) s->host, (ulong) s->device, s->target, s->lun,
s->channel);
#endif /* version >= v1.3.0 */
s->internal_timeout, s->flags, s->this_count);
printk(
-" scsi_done %x, done %x, host_scribble %x, result %x\n",
- (unsigned) s->scsi_done, (unsigned) s->done,
- (unsigned) s->host_scribble, s->result);
+" scsi_done %lx, done %lx, host_scribble %lx, result %x\n",
+ (ulong) s->scsi_done, (ulong) s->done,
+ (ulong) s->host_scribble, s->result);
printk(
" tag %u, pid %u\n",
STATIC void
asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
{
- printk("ASC_DVC_VAR at addr %x\n", (unsigned) h);
+ printk("ASC_DVC_VAR at addr %lx\n", (ulong) h);
printk(
" iop_base %x, err_code %x, dvc_cntl %x, bug_fix_cntl %d,\n",
h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
printk(
-" bus_type %d, isr_callback %x, exe_callback %x, init_sdtr %x,\n",
- h->bus_type, (unsigned) h->isr_callback, (unsigned) h->exe_callback,
+" bus_type %d, isr_callback %lx, exe_callback %lx, init_sdtr %x,\n",
+ h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
(unsigned) h->init_sdtr);
printk(
(unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
printk(
-" cfg %x, saved_ptr2func %x\n",
- (unsigned) h->cfg, (unsigned) h->saved_ptr2func);
+" cfg %lx\n",
+ (ulong) h->cfg);
}
/*
STATIC void
asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
{
- printk("ASC_DVC_CFG at addr %x\n", (unsigned) h);
+ printk("ASC_DVC_CFG at addr %lx\n", (ulong) h);
printk(
" can_tagged_qng %x, cmd_qng_enabled %x, disc_enable %x, sdtr_enable %x,\n",
h->pci_device_id, h->lib_serial_no, h->lib_version, h->mcode_date);
printk(
-" mcode_version %d, overrun_buf %x\n",
- h->mcode_version, (unsigned) h->overrun_buf);
+" mcode_version %d, overrun_buf %lx\n",
+ h->mcode_version, (ulong) h->overrun_buf);
}
/*
ASC_SG_HEAD *sgp;
int i;
- printk("ASC_SCSI_Q at addr %x\n", (unsigned) q);
+ printk("ASC_SCSI_Q at addr %lx\n", (ulong) q);
printk(
" target_ix %u, target_lun %u, srb_ptr %x, tag_code %u,\n",
(unsigned) q->q2.srb_ptr, q->q2.tag_code);
printk(
-" data_addr %x, data_cnt %lu, sense_addr %x, sense_len %u,\n",
- (unsigned) q->q1.data_addr, q->q1.data_cnt,
- (unsigned) q->q1.sense_addr, q->q1.sense_len);
+" data_addr %lx, data_cnt %lu, sense_addr %lx, sense_len %u,\n",
+ (ulong) q->q1.data_addr, (ulong) q->q1.data_cnt,
+ (ulong) q->q1.sense_addr, q->q1.sense_len);
printk(
-" cdbptr %x, cdb_len %u, sg_head %x, sg_queue_cnt %u\n",
- (unsigned) q->cdbptr, q->q2.cdb_len,
- (unsigned) q->sg_head, q->q1.sg_queue_cnt);
+" cdbptr %lx, cdb_len %u, sg_head %lx, sg_queue_cnt %u\n",
+ (ulong) q->cdbptr, q->q2.cdb_len,
+ (ulong) q->sg_head, q->q1.sg_queue_cnt);
if (q->sg_head) {
sgp = q->sg_head;
- printk("ASC_SG_HEAD at addr %x\n", (unsigned) sgp);
+ printk("ASC_SG_HEAD at addr %lx\n", (ulong) sgp);
printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
for (i = 0; i < sgp->entry_cnt; i++) {
- printk(" [%u]: addr %x, bytes %lu\n",
- i, (unsigned) sgp->sg_list[i].addr, sgp->sg_list[i].bytes);
+ printk(" [%u]: addr %lx, bytes %lu\n",
+ i, (ulong) sgp->sg_list[i].addr,
+ (ulong) sgp->sg_list[i].bytes);
}
}
STATIC void
asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
{
- printk("ASC_QDONE_INFO at addr %x\n", (unsigned) q);
+ printk("ASC_QDONE_INFO at addr %lx\n", (ulong) q);
printk(
" srb_ptr %x, target_ix %u, cdb_len %u, tag_code %u, done_stat %x\n",
(unsigned) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
(ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
printk(
-" isr_callback 0x%x, sdtr_able 0x%x, wdtr_able 0x%x\n",
- (unsigned) h->isr_callback, (unsigned) h->wdtr_able,
+" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
+ (ulong) h->isr_callback, (unsigned) h->wdtr_able,
(unsigned) h->sdtr_able);
printk(
(unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
(ulong) h->carr_freelist);
-
printk(
" icq_sp %lx, irq_sp %lx\n",
- (ulong) h->icq_sp,
- (ulong) h->irq_sp);
+ (ulong) h->icq_sp, (ulong) h->irq_sp);
printk(
" no_scam 0x%x, tagqng_able 0x%x\n",
int sg_blk_cnt;
struct asc_sg_block *sg_ptr;
- printk("ADV_SCSI_REQ_Q at addr %x\n", (unsigned) q);
+ printk("ADV_SCSI_REQ_Q at addr %lx\n", (ulong) q);
printk(
" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
- q->target_id, q->target_lun, q->srb_ptr, q->a_flag);
+ q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
- q->cntl, q->data_addr, q->vdata_addr);
-
- printk(
-" cntl 0x%x, data_addr %lx, vdata_addr %lx\n",
- q->cntl, q->data_addr, q->vdata_addr);
+ q->cntl, (ulong) q->data_addr, (ulong) q->vdata_addr);
printk(
" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
- q->data_cnt, q->sense_addr, q->sense_len);
+ (ulong) q->data_cnt, (ulong) q->sense_addr, q->sense_len);
printk(
" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
q->cdb_len, q->done_status, q->host_status, q->scsi_status);
printk(
-" sg_working_ix %x, sg_working_data_cnt %lx, reserved %u\n",
- q->sg_working_ix, q->sg_working_data_cnt, q->reserved);
+" sg_working_ix %x, sg_working_data_cnt %lx, target_cmd %u\n",
+ q->sg_working_ix, (ulong) q->sg_working_data_cnt, q->target_cmd);
printk(
" scsiq_rptr %lx, sg_real_addr %lx, sg_list_ptr %lx\n",
- q->scsiq_rptr, q->sg_real_addr, (ulong) q->sg_list_ptr);
+ (ulong) q->scsiq_rptr, (ulong) q->sg_real_addr,
+ (ulong) q->sg_list_ptr);
/* Display the request's ADV_SG_BLOCK structures. */
if (q->sg_list_ptr != NULL)
*/
sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
- if (sg_ptr->sg_ptr == NULL)
+ if (sg_ptr->sg_ptr == 0)
{
break;
}
printk(" sg_cnt %u, sg_ptr %lx\n",
b->sg_cnt, (ulong) b->sg_ptr);
ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
- if (b->sg_ptr != NULL)
+ if (b->sg_ptr != 0)
{
ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
}
for (i = 0; i < b->sg_cnt; i++) {
printk(" [%u]: sg_addr %lx, sg_count %lx\n",
- i, b->sg_list[i].sg_addr, b->sg_list[i].sg_count);
+ i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
}
}
}
ASC_INITFUNC(
-STATIC ulong,
+STATIC ASC_DCNT,
AscLoadMicroCode(
PortAddr iop_base,
ushort s_addr,
)
)
{
- ulong chksum;
+ ASC_DCNT chksum;
ushort mcode_word_size;
ushort mcode_chksum;
STATIC int
AscIsrChipHalted(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
EXT_MSG ext_msg;
uchar cur_dvc_qng;
uchar asyn_sdtr;
uchar scsi_status;
- asc_board_t *boardp;
+ asc_board_t *boardp;
- ASC_ASSERT(asc_dvc->drv_ptr != 0);
- boardp = (asc_board_t *) asc_dvc->drv_ptr;
+ ASC_ASSERT(asc_dvc->drv_ptr != NULL);
+ boardp = asc_dvc->drv_ptr;
iop_base = asc_dvc->iop_base;
int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
return (0);
} else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
{
- uchar q_no;
- ushort q_addr;
- ulong srb_ptr;
- uchar sg_wk_q_no;
- uchar first_sg_wk_q_no;
- ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
- ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
- ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
- ushort sg_list_dwords;
- ushort sg_entry_cnt;
- uchar next_qp;
- int i;
-
- q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
- if (q_no == ASC_QLINK_END)
- {
- return(0);
- }
-
- q_addr = ASC_QNO_TO_QADDR(q_no);
-
- /* Read request's SRB pointer. */
- srb_ptr = AscReadLramDWord(iop_base,
- (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR));
+ uchar q_no;
+ ushort q_addr;
+ uchar sg_wk_q_no;
+ uchar first_sg_wk_q_no;
+ ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
+ ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
+ ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
+ ushort sg_list_dwords;
+ ushort sg_entry_cnt;
+ uchar next_qp;
+ int i;
+
+ q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
+ if (q_no == ASC_QLINK_END)
+ {
+ return(0);
+ }
- /*
- * Get request's first and working SG queue.
- */
- sg_wk_q_no = AscReadLramByte(iop_base,
- (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
+ q_addr = ASC_QNO_TO_QADDR(q_no);
- first_sg_wk_q_no = AscReadLramByte(iop_base,
- (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
+ /*
+ * Convert the request's SRB pointer to a host ASC_SCSI_REQ
+ * structure pointer using a macro provided by the driver.
+ * The ASC_SCSI_REQ pointer provides a pointer to the
+ * host ASC_SG_HEAD structure.
+ */
+ /* Read request's SRB pointer. */
+ scsiq = (ASC_SCSI_Q *)
+ ASC_SRB2SCSIQ(
+ ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
+ (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
- /*
- * Reset request's working SG queue back to the
- * first SG queue.
- */
- AscWriteLramByte(iop_base,
- (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
- first_sg_wk_q_no);
+ /*
+ * Get request's first and working SG queue.
+ */
+ sg_wk_q_no = AscReadLramByte(iop_base,
+ (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
- /*
- * Convert the request's SRB pointer to a host ASC_SCSI_REQ
- * structure pointer using a macro provided by the driver.
- * The ASC_SCSI_REQ pointer provides a pointer to the
- * host ASC_SG_HEAD structure.
- */
- scsiq = (ASC_SCSI_Q *) ASC_SRB2SCSIQ(srb_ptr);
+ first_sg_wk_q_no = AscReadLramByte(iop_base,
+ (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
- sg_head = scsiq->sg_head;
+ /*
+ * Reset request's working SG queue back to the
+ * first SG queue.
+ */
+ AscWriteLramByte(iop_base,
+ (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
+ first_sg_wk_q_no);
- /*
- * Set sg_entry_cnt to the number of SG elements
- * that will be completed on this interrupt.
- *
- * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
- * SG elements. The data_cnt and data_addr fields which
- * add 1 to the SG element capacity are not used when
- * restarting SG handling after a halt.
- */
- if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
- {
- sg_entry_cnt = ASC_MAX_SG_LIST - 1;
-
- /*
- * Keep track of remaining number of SG elements that will
- * need to be handled on the next interrupt.
- */
- scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
- } else
- {
- sg_entry_cnt = scsiq->remain_sg_entry_cnt;
- scsiq->remain_sg_entry_cnt = 0;
- }
+ sg_head = scsiq->sg_head;
- /*
- * Copy SG elements into the list of allocated SG queues.
- *
- * Last index completed is saved in scsiq->next_sg_index.
- */
- next_qp = first_sg_wk_q_no;
- q_addr = ASC_QNO_TO_QADDR(next_qp);
- scsi_sg_q.sg_head_qp = q_no;
- scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
- for( i = 0; i < sg_head->queue_cnt; i++)
- {
- scsi_sg_q.seq_no = i + 1;
- if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
- {
- sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
- sg_entry_cnt -= ASC_SG_LIST_PER_Q;
- /*
- * After very first SG queue RISC FW uses next
- * SG queue first element then checks sg_list_cnt
- * against zero and then decrements, so set
- * sg_list_cnt 1 less than number of SG elements
- * in each SG queue.
- */
- scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
- scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
- } else {
- /*
- * This is the last SG queue in the list of
- * allocated SG queues. If there are more
- * SG elements than will fit in the allocated
- * queues, then set the QCSG_SG_XFER_MORE flag.
- */
- if (scsiq->remain_sg_entry_cnt != 0)
- {
- scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
- } else
- {
- scsi_sg_q.cntl |= QCSG_SG_XFER_END;
- }
- /* equals sg_entry_cnt * 2 */
- sg_list_dwords = sg_entry_cnt << 1;
- scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
- scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
- sg_entry_cnt = 0;
- }
-
- scsi_sg_q.q_no = next_qp;
- AscMemWordCopyToLram(iop_base,
- (ushort) (q_addr+ASC_SCSIQ_SGHD_CPY_BEG),
- (ushort *) &scsi_sg_q,
- (ushort) (sizeof(ASC_SG_LIST_Q) >> 1));
-
- AscMemDWordCopyToLram( iop_base,
- (ushort) (q_addr+ASC_SGQ_LIST_BEG ),
- (ulong *) &sg_head->sg_list[scsiq->next_sg_index],
- (ushort) sg_list_dwords);
-
- scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
-
- /*
- * If the just completed SG queue contained the
- * last SG element, then no more SG queues need
- * to be written.
- */
- if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
- {
- break;
- }
-
- next_qp = AscReadLramByte( iop_base,
- ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
- q_addr = ASC_QNO_TO_QADDR( next_qp );
- }
+ /*
+ * Set sg_entry_cnt to the number of SG elements
+ * that will be completed on this interrupt.
+ *
+ * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
+ * SG elements. The data_cnt and data_addr fields which
+ * add 1 to the SG element capacity are not used when
+ * restarting SG handling after a halt.
+ */
+ if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
+ {
+ sg_entry_cnt = ASC_MAX_SG_LIST - 1;
- /*
- * Clear the halt condition so the RISC will be restarted
- * after the return.
- */
- AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
- return(0);
+ /*
+ * Keep track of remaining number of SG elements that will
+ * need to be handled on the next interrupt.
+ */
+ scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
+ } else
+ {
+ sg_entry_cnt = scsiq->remain_sg_entry_cnt;
+ scsiq->remain_sg_entry_cnt = 0;
+ }
+
+ /*
+ * Copy SG elements into the list of allocated SG queues.
+ *
+ * Last index completed is saved in scsiq->next_sg_index.
+ */
+ next_qp = first_sg_wk_q_no;
+ q_addr = ASC_QNO_TO_QADDR(next_qp);
+ scsi_sg_q.sg_head_qp = q_no;
+ scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
+ for( i = 0; i < sg_head->queue_cnt; i++)
+ {
+ scsi_sg_q.seq_no = i + 1;
+ if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
+ {
+ sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
+ sg_entry_cnt -= ASC_SG_LIST_PER_Q;
+ /*
+ * After very first SG queue RISC FW uses next
+ * SG queue first element then checks sg_list_cnt
+ * against zero and then decrements, so set
+ * sg_list_cnt 1 less than number of SG elements
+ * in each SG queue.
+ */
+ scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
+ scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
+ } else {
+ /*
+ * This is the last SG queue in the list of
+ * allocated SG queues. If there are more
+ * SG elements than will fit in the allocated
+ * queues, then set the QCSG_SG_XFER_MORE flag.
+ */
+ if (scsiq->remain_sg_entry_cnt != 0)
+ {
+ scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
+ } else
+ {
+ scsi_sg_q.cntl |= QCSG_SG_XFER_END;
+ }
+ /* equals sg_entry_cnt * 2 */
+ sg_list_dwords = sg_entry_cnt << 1;
+ scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
+ scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
+ sg_entry_cnt = 0;
+ }
+
+ scsi_sg_q.q_no = next_qp;
+ AscMemWordCopyToLram(iop_base,
+ (ushort) (q_addr+ASC_SCSIQ_SGHD_CPY_BEG),
+ (ushort *) &scsi_sg_q,
+ (ushort) (sizeof(ASC_SG_LIST_Q) >> 1));
+
+ AscMemDWordCopyToLram( iop_base,
+ (ushort) (q_addr+ASC_SGQ_LIST_BEG ),
+ (ADV_PADDR *)
+ &sg_head->sg_list[scsiq->next_sg_index],
+ (ushort) sg_list_dwords);
+
+ scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
+
+ /*
+ * If the just completed SG queue contained the
+ * last SG element, then no more SG queues need
+ * to be written.
+ */
+ if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
+ {
+ break;
+ }
+
+ next_qp = AscReadLramByte( iop_base,
+ ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
+ q_addr = ASC_QNO_TO_QADDR( next_qp );
+ }
+
+ /*
+ * Clear the halt condition so the RISC will be restarted
+ * after the return.
+ */
+ AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
+ return(0);
}
return (0);
}
_AscCopyLramScsiDoneQ(
PortAddr iop_base,
ushort q_addr,
- REG ASC_QDONE_INFO * scsiq,
- ulong max_dma_count
+ ASC_QDONE_INFO * scsiq,
+ ASC_DCNT max_dma_count
)
{
ushort _val;
/*
* Read high word of remain bytes from alternate location.
*/
- scsiq->remain_bytes = (((ulong) AscReadLramWord( iop_base,
+ scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
(ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
/*
* Read low word of remain bytes from original location.
STATIC int
AscIsrQDone(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
uchar next_qp;
ushort sg_q_addr;
uchar cur_target_qng;
ASC_QDONE_INFO scsiq_buf;
- REG ASC_QDONE_INFO *scsiq;
+ ASC_QDONE_INFO *scsiq;
int false_overrun;
ASC_ISR_CALLBACK asc_isr_callback;
iop_base = asc_dvc->iop_base;
- asc_isr_callback = (ASC_ISR_CALLBACK) asc_dvc->isr_callback;
+ asc_isr_callback = asc_dvc->isr_callback;
n_q_used = 1;
scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
} else if (scsiq->q_status == QS_DONE) {
false_overrun = FALSE;
if (scsiq->extra_bytes != 0) {
- scsiq->remain_bytes += (ulong) scsiq->extra_bytes;
+ scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
}
if (scsiq->d3.done_stat == QD_WITH_ERROR) {
if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
STATIC int
AscISR(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
ASC_CS_TYPE chipstat;
};
STATIC ushort _asc_mcode_size ASC_INITDATA = sizeof(_asc_mcode_buf);
-STATIC ulong _asc_mcode_chksum ASC_INITDATA = 0x012C453FUL;
+STATIC ADV_DCNT _asc_mcode_chksum ASC_INITDATA = 0x012C453FUL;
#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
STATIC int
AscExeScsiQueue(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- REG ASC_SCSI_Q * scsiq
+ ASC_DVC_VAR *asc_dvc,
+ ASC_SCSI_Q *scsiq
)
{
PortAddr iop_base;
int n_q_required;
int disable_syn_offset_one_fix;
int i;
- ulong addr;
+ ASC_PADDR addr;
ASC_EXE_CALLBACK asc_exe_callback;
ushort sg_entry_cnt = 0;
ushort sg_entry_cnt_minus_one = 0;
uchar extra_bytes;
uchar scsi_cmd;
uchar disable_cmd;
- ASC_SG_HEAD *sg_head;
- ulong data_cnt;
+ ASC_SG_HEAD *sg_head;
+ ASC_DCNT data_cnt;
iop_base = asc_dvc->iop_base;
sg_head = scsiq->sg_head;
- asc_exe_callback = (ASC_EXE_CALLBACK) asc_dvc->exe_callback;
+ asc_exe_callback = asc_dvc->exe_callback;
if (asc_dvc->err_code != 0)
return (ERR);
if (scsiq == (ASC_SCSI_Q *) 0L) {
}
#endif /* !CC_VERY_LONG_SG_LIST */
if (sg_entry_cnt == 1) {
- scsiq->q1.data_addr = (ulong) sg_head->sg_list[0].addr;
- scsiq->q1.data_cnt = (ulong) sg_head->sg_list[0].bytes;
+ scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
+ scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
}
sg_entry_cnt_minus_one = sg_entry_cnt - 1;
if (scsiq->q1.cntl & QC_SG_HEAD) {
data_cnt = 0;
for (i = 0; i < sg_entry_cnt; i++) {
- data_cnt += (ulong) sg_head->sg_list[i].bytes;
+ data_cnt += (ADV_DCNT) sg_head->sg_list[i].bytes;
}
} else {
data_cnt = scsiq->q1.data_cnt;
if ((scsi_cmd == SCSICMD_Read6) ||
(scsi_cmd == SCSICMD_Read10)) {
addr =
- (ulong) sg_head->sg_list[sg_entry_cnt_minus_one].addr +
- (ulong) sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
+ (ADV_PADDR)
+ sg_head->sg_list[sg_entry_cnt_minus_one].addr +
+ (ADV_DCNT)
+ sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
extra_bytes = (uchar) ((ushort) addr & 0x0003);
if ((extra_bytes != 0) &&
((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
scsiq->q1.extra_bytes = extra_bytes;
sg_head->sg_list[sg_entry_cnt_minus_one].bytes -=
- (ulong) extra_bytes;
+ (ASC_DCNT) extra_bytes;
}
}
}
== 0)) {
if (((ushort) scsiq->q1.data_cnt & 0x01FF) == 0) {
scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
- scsiq->q1.data_cnt -= (ulong) extra_bytes;
+ scsiq->q1.data_cnt -= (ASC_DCNT) extra_bytes;
scsiq->q1.extra_bytes = extra_bytes;
}
}
STATIC int
AscSendScsiQueue(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- REG ASC_SCSI_Q * scsiq,
+ ASC_DVC_VAR *asc_dvc,
+ ASC_SCSI_Q *scsiq,
uchar n_q_required
)
{
STATIC uint
AscGetNumOfFreeQueue(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar target_ix,
uchar n_qs
)
STATIC int
AscPutReadyQueue(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- REG ASC_SCSI_Q * scsiq,
+ ASC_DVC_VAR *asc_dvc,
+ ASC_SCSI_Q *scsiq,
uchar q_no
)
{
STATIC int
AscPutReadySgListQueue(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- REG ASC_SCSI_Q * scsiq,
+ ASC_DVC_VAR *asc_dvc,
+ ASC_SCSI_Q *scsiq,
uchar q_no
)
{
int i;
ASC_SG_HEAD *sg_head;
ASC_SG_LIST_Q scsi_sg_q;
- ulong saved_data_addr;
- ulong saved_data_cnt;
+ ASC_DCNT saved_data_addr;
+ ASC_DCNT saved_data_cnt;
PortAddr iop_base;
ushort sg_list_dwords;
ushort sg_index;
sg_head = scsiq->sg_head;
saved_data_addr = scsiq->q1.data_addr;
saved_data_cnt = scsiq->q1.data_cnt;
- scsiq->q1.data_addr = (ulong) sg_head->sg_list[0].addr;
- scsiq->q1.data_cnt = (ulong) sg_head->sg_list[0].bytes;
+ scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
+ scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
/*
* If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
* then not all SG elements will fit in the allocated queues.
(ushort) (sizeof (ASC_SG_LIST_Q) >> 1));
AscMemDWordCopyToLram(iop_base,
(ushort) (q_addr + ASC_SGQ_LIST_BEG),
- (ulong *) & sg_head->sg_list[sg_index],
+ (ADV_PADDR *) &sg_head->sg_list[sg_index],
(ushort) sg_list_dwords);
sg_index += ASC_SG_LIST_PER_Q;
scsiq->next_sg_index = sg_index;
STATIC int
AscAbortSRB(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- ulong srb_ptr
+ ASC_DVC_VAR *asc_dvc,
+ ADV_VADDR srb_ptr
)
{
int sta;
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
STATIC int
AscResetDevice(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar target_ix
)
{
STATIC int
AscResetSB(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
int sta;
AscStopQueueExe(iop_base);
asc_dvc->sdtr_done = 0;
AscResetChipAndScsiBus(asc_dvc);
- DvcSleepMilliSecond((ulong) ((ushort) asc_dvc->scsi_reset_wait * 1000));
+ DvcSleepMilliSecond((ASC_DCNT) ((ushort) asc_dvc->scsi_reset_wait * 1000));
AscReInitLram(asc_dvc);
for (i = 0; i <= ASC_MAX_TID; i++) {
asc_dvc->cur_dvc_qng[i] = 0;
STATIC int
AscReInitLram(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
AscInitLram(asc_dvc);
STATIC ushort
AscInitLram(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
uchar i;
STATIC ushort
AscInitQLinkVar(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
PortAddr iop_base;
STATIC int
AscSetLibErrorCode(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
ushort err_code
)
{
STATIC int
_AscWaitQDone(
PortAddr iop_base,
- REG ASC_SCSI_Q * scsiq
+ ASC_SCSI_Q * scsiq
)
{
ushort q_addr;
STATIC uchar
AscMsgOutSDTR(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar sdtr_period,
uchar sdtr_offset
)
STATIC uchar
AscCalSDTRData(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar sdtr_period,
uchar syn_offset
)
STATIC uchar
AscGetSynPeriodIndex(
- ASC_DVC_VAR asc_ptr_type * asc_dvc,
- ruchar syn_time
+ ASC_DVC_VAR *asc_dvc,
+ uchar syn_time
)
{
- ruchar *period_table;
+ uchar *period_table;
int max_index;
int min_index;
int i;
STATIC int
AscRiscHaltedAbortSRB(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
- ulong srb_ptr
+ ASC_DVC_VAR *asc_dvc,
+ ASC_VADDR srb_ptr
)
{
PortAddr iop_base;
int last_int_level;
iop_base = asc_dvc->iop_base;
- asc_isr_callback = (ASC_ISR_CALLBACK) asc_dvc->isr_callback;
+ asc_isr_callback = asc_dvc->isr_callback;
last_int_level = DvcEnterCritical();
scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= asc_dvc->max_total_qng;
#if LINUX_VERSION_CODE >= ASC_LINUX_VERSION(1,3,89)
STATIC int
AscRiscHaltedAbortTIX(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar target_ix
)
{
int last_int_level;
iop_base = asc_dvc->iop_base;
- asc_isr_callback = (ASC_ISR_CALLBACK) asc_dvc->isr_callback;
+ asc_isr_callback = asc_dvc->isr_callback;
last_int_level = DvcEnterCritical();
scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= asc_dvc->max_total_qng;
STATIC int
AscWaitTixISRDone(
- ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar target_ix
)
{
STATIC int
AscWaitISRDone(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
{
int tid;
return (1);
}
-STATIC ulong
+STATIC ASC_PADDR
AscGetOnePhyAddr(
- REG ASC_DVC_VAR asc_ptr_type * asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar * buf_addr,
- ulong buf_size
+ ASC_DCNT buf_size
)
{
ASC_MIN_SG_HEAD sg_head;
sg_head.entry_cnt = ASC_MIN_SG_LIST;
if (DvcGetSGList(asc_dvc, (uchar *) buf_addr,
- buf_size, (ASC_SG_HEAD *) & sg_head) != buf_size) {
+ buf_size, (ASC_SG_HEAD *) &sg_head) != buf_size) {
return (0L);
}
if (sg_head.entry_cnt > 1) {
return (0L);
}
- return ((ulong) sg_head.sg_list[0].addr);
+ return ((ASC_PADDR) sg_head.sg_list[0].addr);
}
STATIC void
}
STATIC void
-DvcDelayNanoSecond(ASC_DVC_VAR asc_ptr_type * asc_dvc, ulong nano_sec)
+DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
{
udelay((nano_sec + 999)/1000);
}
ASC_INITFUNC(
-STATIC ulong,
+STATIC ASC_DCNT,
AscGetEisaProductID(
PortAddr iop_base
)
{
PortAddr eisa_iop;
ushort product_id_high, product_id_low;
- ulong product_id;
+ ASC_DCNT product_id;
eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
product_id_low = inpw(eisa_iop);
product_id_high = inpw(eisa_iop + 2);
- product_id = ((ulong) product_id_high << 16) | (ulong) product_id_low;
+ product_id = ((ASC_DCNT) product_id_high << 16) |
+ (ASC_DCNT) product_id_low;
return (product_id);
}
)
)
{
- ulong eisa_product_id;
+ ASC_DCNT eisa_product_id;
if (iop_base == 0) {
iop_base = ASC_EISA_MIN_IOP_ADDR;
}
ASC_INITFUNC(
-STATIC ulong,
+STATIC ASC_DCNT,
AscGetMaxDmaCount(
ushort bus_type
)
ASC_INITFUNC(
STATIC ushort,
AscReadPCIConfigWord(
- ASC_DVC_VAR asc_ptr_type *asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
ushort pci_config_offset)
)
{
ASC_INITFUNC(
STATIC ushort,
AscInitGetConfig(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
ASC_INITFUNC(
STATIC ushort,
AscInitSetConfig(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
ASC_INITFUNC(
STATIC ushort,
AscInitFromAscDvcVar(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
ASC_INITFUNC(
STATIC ushort,
AscInitAsc1000Driver(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
!(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
AscResetChipAndScsiBus(asc_dvc);
- DvcSleepMilliSecond((ulong) ((ushort) asc_dvc->scsi_reset_wait * 1000));
+ DvcSleepMilliSecond((ASC_DCNT)
+ ((ushort) asc_dvc->scsi_reset_wait * 1000));
}
asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
if (asc_dvc->err_code != 0)
ASC_INITFUNC(
STATIC ushort,
AscInitAscDvcVar(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
asc_dvc->redo_scam = 0;
asc_dvc->res2 = 0;
asc_dvc->host_init_sdtr_index = 0;
- asc_dvc->res7 = 0;
- asc_dvc->res8 = 0;
asc_dvc->cfg->can_tagged_qng = 0;
asc_dvc->cfg->cmd_qng_enabled = 0;
asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
ASC_INITFUNC(
STATIC ushort,
AscInitFromEEP(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
(AscGetChipScsiCtrl(iop_base) != 0)) {
asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
AscResetChipAndScsiBus(asc_dvc);
- DvcSleepMilliSecond((ulong) ((ushort) asc_dvc->scsi_reset_wait * 1000));
+ DvcSleepMilliSecond((ASC_DCNT)
+ ((ushort) asc_dvc->scsi_reset_wait * 1000));
}
if (AscIsChipHalted(iop_base) == FALSE) {
asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
ASC_INITFUNC(
STATIC ushort,
AscInitMicroCodeVar(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
int i;
ushort warn_code;
PortAddr iop_base;
- ulong phy_addr;
+ ASC_PADDR phy_addr;
iop_base = asc_dvc->iop_base;
warn_code = 0;
ASC_OVERRUN_BSIZE)) == 0L) {
asc_dvc->err_code |= ASC_IERR_GET_PHY_ADDR;
} else {
- phy_addr = (phy_addr & 0xFFFFFFF8UL) + 8;
+ /* Align on an 8 byte boundary. */
+ phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
AscWriteLramDWord(iop_base, ASCV_OVERRUN_PADDR_D, phy_addr);
AscWriteLramDWord(iop_base, ASCV_OVERRUN_BSIZE_D,
ASC_OVERRUN_BSIZE - 8);
ASC_INITFUNC(
STATIC int,
AscTestExternalLram(
- ASC_DVC_VAR asc_ptr_type * asc_dvc
+ ASC_DVC_VAR *asc_dvc
)
)
{
{
ushort wval;
ushort sum;
- ushort *wbuf;
+ ushort *wbuf;
int cfg_beg;
int cfg_end;
int s_addr;
STATIC void
AscAsyncFix(
- ASC_DVC_VAR asc_ptr_type *asc_dvc,
+ ASC_DVC_VAR *asc_dvc,
uchar tid_no,
ASC_SCSI_INQUIRY *inq)
{
}
STATIC void
-AscInquiryHandling(ASC_DVC_VAR asc_ptr_type *asc_dvc,
+AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
uchar tid_no, ASC_SCSI_INQUIRY *inq)
{
ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
STATIC int
AscCompareString(
- ruchar * str1,
- ruchar * str2,
+ uchar *str1,
+ uchar *str2,
int len
)
{
return (word_data);
}
-STATIC ulong
+STATIC ASC_DCNT
AscReadLramDWord(
PortAddr iop_base,
ushort addr
)
{
ushort val_low, val_high;
- ulong dword_data;
+ ASC_DCNT dword_data;
AscSetChipLramAddr(iop_base, addr);
val_low = AscGetChipLramData(iop_base);
val_high = AscGetChipLramData(iop_base);
- dword_data = ((ulong) val_high << 16) | (ulong) val_low;
+ dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
return (dword_data);
}
AscWriteLramDWord(
PortAddr iop_base,
ushort addr,
- ulong dword_val
+ ASC_DCNT dword_val
)
{
ushort word_val;
AscMemDWordCopyToLram(
PortAddr iop_base,
ushort s_addr,
- ulong * s_buffer,
+ ASC_DCNT *s_buffer,
int dwords
)
{
return;
}
-STATIC ulong
+STATIC ASC_DCNT
AscMemSumLramWord(
PortAddr iop_base,
ushort s_addr,
- rint words
+ int words
)
{
- ulong sum;
- int i;
+ ASC_DCNT sum;
+ int i;
sum = 0L;
for (i = 0; i < words; i++, s_addr += 2) {
PortAddr iop_base,
ushort s_addr,
ushort set_wval,
- rint words
+ int words
)
{
- rint i;
+ int i;
AscSetChipLramAddr(iop_base, s_addr);
for (i = 0; i < words; i++) {
/* a_mcode.h */
STATIC unsigned char _adv_asc3550_buf[] = {
- 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48, 0xe4, 0x01, 0x00, 0x01, 0xf6,
- 0x00, 0xf6, 0x18, 0xe4, 0x0a, 0x19, 0x18, 0x80, 0x02, 0x00, 0xff, 0xff, 0x03, 0xf6, 0x00, 0xfa,
- 0xff, 0x00, 0x82, 0xe7, 0x9e, 0xe7, 0x01, 0xfa, 0x06, 0x0e, 0x09, 0xe7, 0x00, 0xea, 0x01, 0xe6,
- 0x03, 0x00, 0x08, 0x00, 0x18, 0xf4, 0x55, 0xf0, 0x3e, 0x01, 0x3e, 0x57, 0x04, 0x00, 0x1e, 0xf0,
- 0x85, 0xf0, 0x00, 0xe6, 0x00, 0xec, 0x32, 0xf0, 0x86, 0xf0, 0xa4, 0x0c, 0xd0, 0x01, 0xd5, 0xf0,
- 0xf6, 0x18, 0x38, 0x54, 0x98, 0x57, 0xbc, 0x00, 0xb1, 0xf0, 0xb4, 0x00, 0x01, 0xfc, 0x02, 0x13,
- 0x03, 0xfc, 0x9e, 0x0c, 0x00, 0x57, 0x01, 0xf0, 0x03, 0xe6, 0x0c, 0x1c, 0x10, 0x00, 0x18, 0x40,
- 0x30, 0x12, 0x3e, 0x1c, 0xbd, 0x00, 0xe0, 0x00, 0x02, 0x48, 0x02, 0x80, 0x3c, 0x00, 0x4e, 0x01,
- 0x66, 0x15, 0x6c, 0x01, 0x6e, 0x01, 0xbb, 0x00, 0xda, 0x12, 0x00, 0x4e, 0x01, 0x01, 0x01, 0xea,
- 0x08, 0x12, 0x30, 0xe4, 0x6a, 0x0f, 0xa8, 0x0c, 0xae, 0x0f, 0xb6, 0x00, 0xb9, 0x54, 0x00, 0x80,
- 0x04, 0x12, 0x06, 0xf7, 0x24, 0x01, 0x28, 0x01, 0x32, 0x00, 0x3c, 0x01, 0x3c, 0x56, 0x3e, 0x00,
- 0x4b, 0xe4, 0x4c, 0x1c, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
- 0x78, 0x01, 0x00, 0x01, 0x02, 0xee, 0x02, 0xfc, 0x03, 0x58, 0x03, 0xf7, 0x04, 0x80, 0x05, 0xfc,
- 0x08, 0x44, 0x09, 0xf0, 0x0a, 0x15, 0x10, 0x44, 0x1b, 0x80, 0x20, 0x01, 0x38, 0x1c, 0x40, 0x00,
- 0x4b, 0xf4, 0x4e, 0x1c, 0x5b, 0xf0, 0x5d, 0xf0, 0x80, 0x00, 0xaa, 0x00, 0xaa, 0x14, 0xb6, 0x08,
- 0xb8, 0x0f, 0xbb, 0x55, 0xbd, 0x56, 0xbe, 0x00, 0xc0, 0x00, 0x00, 0x4c, 0x00, 0xdc, 0x02, 0x4a,
- 0x05, 0xf0, 0x05, 0xf8, 0x06, 0x13, 0x08, 0x13, 0x0c, 0x00, 0x0e, 0x47, 0x0e, 0xf7, 0x0f, 0x00,
- 0x19, 0x00, 0x20, 0x00, 0x2a, 0x01, 0x32, 0x1c, 0x36, 0x00, 0x38, 0x12, 0x3c, 0x0b, 0x45, 0x5a,
- 0x56, 0x14, 0x59, 0xf0, 0x62, 0x0a, 0x69, 0x08, 0x83, 0x59, 0xae, 0x17, 0xb8, 0xf0, 0xba, 0x0f,
- 0xba, 0x17, 0xf0, 0x00, 0xf6, 0x0d, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0x10, 0x04, 0xea, 0x04, 0xf6,
- 0x04, 0xfc, 0x05, 0x00, 0x06, 0x00, 0x06, 0x12, 0x0a, 0x10, 0x0b, 0xf0, 0x0c, 0xf0, 0x12, 0x10,
- 0x30, 0x1c, 0x33, 0x00, 0x34, 0x00, 0x38, 0x44, 0x40, 0x5c, 0x4a, 0xe4, 0x5a, 0x14, 0x62, 0x1a,
- 0x64, 0x0a, 0x68, 0x08, 0x68, 0x54, 0x83, 0x55, 0x83, 0x5a, 0x91, 0x44, 0x98, 0x12, 0x9a, 0x16,
- 0xa4, 0x00, 0xb0, 0x57, 0xb5, 0x00, 0xba, 0x00, 0xce, 0x45, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
- 0xec, 0x0d, 0x00, 0x54, 0x01, 0x48, 0x01, 0x58, 0x02, 0x10, 0x02, 0xe6, 0x03, 0xa1, 0x04, 0x13,
- 0x05, 0xe6, 0x06, 0x0b, 0x06, 0x83, 0x06, 0xf0, 0x07, 0x00, 0x0a, 0x00, 0x0a, 0x12, 0x0a, 0xf0,
- 0x0c, 0x04, 0x0c, 0x10, 0x0c, 0x12, 0x0e, 0x13, 0x10, 0x10, 0x12, 0x1c, 0x17, 0x00, 0x18, 0x0e,
- 0x19, 0xe4, 0x1a, 0x10, 0x1c, 0x00, 0x1c, 0x12, 0x1c, 0x14, 0x1d, 0xf7, 0x1e, 0x13, 0x20, 0x1c,
- 0x20, 0xe7, 0x22, 0x01, 0x26, 0x01, 0x2a, 0x12, 0x30, 0xe7, 0x41, 0x58, 0x43, 0x48, 0x44, 0x55,
- 0x46, 0x1c, 0x4e, 0xe4, 0x5c, 0xf0, 0x72, 0x02, 0x74, 0x03, 0x77, 0x57, 0x88, 0x12, 0x89, 0x48,
- 0x92, 0x13, 0x99, 0x00, 0x9b, 0x00, 0x9c, 0x32, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x12, 0xb9, 0x00,
- 0xba, 0x06, 0xbf, 0x57, 0xc0, 0x01, 0xc0, 0x08, 0xc2, 0x01, 0xfe, 0x9c, 0xf0, 0x26, 0x02, 0xfe,
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+ 0x00, 0x64, 0x2f, 0x03, 0x64, 0x2f, 0xfe, 0x12, 0x45, 0x27, 0xfe, 0xdc, 0x16, 0x17, 0x06, 0x4a,
+ 0xf4, 0xdd, 0x02, 0x26, 0xfe, 0x39, 0xf0, 0xfe, 0x30, 0x17, 0x2d, 0x03, 0xfe, 0x7e, 0x18, 0x1b,
+ 0x19, 0x83, 0x08, 0x0d, 0x03, 0x6f, 0x04, 0xdf, 0x1b, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
+ 0x1d, 0x0e, 0x1c, 0x01, 0x15, 0x05, 0x10, 0x40, 0x3e, 0xfe, 0x78, 0x14, 0xfe, 0x34, 0x12, 0x50,
+ 0x86, 0x36, 0x37, 0xbf, 0xfe, 0xe9, 0x13, 0x1d, 0x0e, 0x3d, 0x01, 0x15, 0x05, 0x10, 0x40, 0x3e,
+ 0xfe, 0x56, 0x14, 0xe1, 0x50, 0x86, 0x36, 0x37, 0xbf, 0xfe, 0xe9, 0x13, 0x09, 0x0c, 0x03, 0xfe,
+ 0x9c, 0xe7, 0x0c, 0x13, 0xfe, 0x15, 0x00, 0x90, 0x9f, 0x2f, 0x01, 0xea, 0x09, 0x06, 0x03, 0x0a,
+ 0x41, 0x37, 0x38, 0x08, 0x3d, 0x09, 0x99, 0x01, 0x46, 0x11, 0x47, 0x08, 0x1c, 0x09, 0x43, 0x01,
+ 0x7b, 0x09, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x65, 0xf7, 0x31, 0x76, 0xfe, 0x48,
+ 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x03, 0x21, 0xbe, 0x52, 0x16, 0xbe, 0x03, 0x0e, 0xc0, 0x01, 0x15,
+ 0xe6, 0x0e, 0x79, 0x01, 0x15, 0xfe, 0x49, 0x44, 0x27, 0xfe, 0x26, 0x18, 0x0e, 0x1c, 0x01, 0x15,
+ 0x05, 0x10, 0x40, 0x0e, 0x56, 0x01, 0xab, 0x0e, 0x79, 0x01, 0x15, 0x52, 0x7d, 0x03, 0xfe, 0x40,
+ 0x5e, 0xfe, 0xe2, 0x08, 0xfe, 0xc0, 0x4c, 0x21, 0x3c, 0x05, 0x10, 0xfe, 0x52, 0x12, 0x3e, 0x05,
+ 0x00, 0xfe, 0x18, 0x12, 0xfe, 0xe1, 0x18, 0xfe, 0x19, 0xf4, 0xfe, 0x7f, 0x00, 0xd4, 0xfe, 0xe2,
+ 0x08, 0x52, 0x3e, 0x3f, 0x05, 0x76, 0xa5, 0xfe, 0x82, 0x48, 0xfe, 0x01, 0x80, 0xfe, 0xd7, 0x10,
+ 0xfe, 0xc4, 0x48, 0x08, 0x2a, 0x09, 0x3c, 0xfe, 0x40, 0x5f, 0x1d, 0x01, 0x46, 0x11, 0xfe, 0xdd,
+ 0x00, 0xfe, 0x14, 0x46, 0x08, 0x2a, 0x09, 0x3c, 0x01, 0x46, 0x11, 0xfe, 0xdd, 0x00, 0xfe, 0x40,
+ 0x4a, 0x6a, 0xfe, 0x06, 0x17, 0xfe, 0x01, 0x07, 0xfe, 0x82, 0x48, 0xfe, 0x04, 0x17, 0x03, 0xeb,
+ 0x19, 0x74, 0xfe, 0xae, 0x18, 0x04, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xeb,
+ 0xcc, 0x74, 0xfe, 0xc0, 0x18, 0x04, 0xfe, 0x92, 0x00, 0xc7, 0x1e, 0xd8, 0xeb, 0xfe, 0x0b, 0x00,
+ 0x74, 0xfe, 0xd2, 0x18, 0x04, 0xfe, 0x94, 0x00, 0xc7, 0x1a, 0xfe, 0x08, 0x10, 0x04, 0xfe, 0x96,
+ 0x00, 0xc7, 0x85, 0xfe, 0x4e, 0x45, 0xd1, 0xfe, 0x0a, 0x45, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
+ 0x10, 0x1b, 0x6c, 0x03, 0x05, 0x80, 0xfe, 0x5a, 0xf0, 0xfe, 0xfe, 0x18, 0x20, 0xfe, 0x09, 0x00,
+ 0xfe, 0x34, 0x10, 0x05, 0x1e, 0xfe, 0x5a, 0xf0, 0xfe, 0x0c, 0x19, 0x20, 0xcd, 0xfe, 0x26, 0x10,
+ 0x05, 0x19, 0x83, 0x20, 0x85, 0xd8, 0x05, 0x0c, 0x83, 0x20, 0x88, 0xfe, 0x0e, 0x10, 0x05, 0x06,
+ 0x83, 0x20, 0x55, 0xc6, 0xaf, 0x03, 0x17, 0xfe, 0x09, 0x00, 0x01, 0x44, 0x2e, 0xfe, 0x3c, 0x19,
+ 0x04, 0x6e, 0xb0, 0x03, 0x22, 0xfe, 0x54, 0x19, 0xfe, 0x14, 0xf0, 0x0b, 0x2e, 0xfe, 0x50, 0x19,
+ 0x03, 0xff, 0x15, 0x00, 0x00,
+};
STATIC unsigned short _adv_asc3550_size =
- sizeof(_adv_asc3550_buf); /* 0x13AA */
-STATIC unsigned long _adv_asc3550_chksum =
- 0x04F4788EUL; /* Expanded checksum. */
+ sizeof(_adv_asc3550_buf); /* 0x13E5 */
+STATIC ADV_DCNT _adv_asc3550_chksum =
+ 0x04FFFF0E; /* Expanded checksum. */
STATIC unsigned char _adv_asc38C0800_buf[] = {
- 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48, 0xe4, 0x01, 0x00, 0x00, 0xf6,
- 0x18, 0xe4, 0x01, 0xf6, 0x18, 0x80, 0x02, 0x00, 0x02, 0x1a, 0xff, 0xff, 0x00, 0xfa, 0x03, 0xf6,
- 0xff, 0x00, 0x82, 0xe7, 0x01, 0xfa, 0x9e, 0xe7, 0x09, 0xe7, 0xe6, 0x0e, 0x00, 0xea, 0x01, 0xe6,
- 0x03, 0x00, 0x1e, 0xf0, 0x55, 0xf0, 0x18, 0xf4, 0x3e, 0x57, 0x04, 0x00, 0x3e, 0x01, 0x85, 0xf0,
- 0x00, 0xe6, 0x03, 0xfc, 0x08, 0x00, 0x32, 0xf0, 0x38, 0x54, 0x84, 0x0d, 0x86, 0xf0, 0xd4, 0x01,
- 0xd5, 0xf0, 0xee, 0x19, 0x00, 0xec, 0x01, 0xfc, 0x98, 0x57, 0xbc, 0x00, 0x10, 0x13, 0xb1, 0xf0,
- 0x02, 0x13, 0x3c, 0x00, 0x7e, 0x0d, 0xb4, 0x00, 0x00, 0x57, 0x01, 0xf0, 0x02, 0xfc, 0x03, 0xe6,
- 0x0c, 0x1c, 0x10, 0x00, 0x18, 0x40, 0x3e, 0x1c, 0xbd, 0x00, 0xe0, 0x00, 0x02, 0x80, 0x3e, 0x00,
- 0x46, 0x16, 0x4a, 0x10, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54, 0xba, 0x13,
- 0xbb, 0x00, 0x00, 0x4e, 0x01, 0x01, 0x01, 0xea, 0x02, 0x48, 0x02, 0xfa, 0x08, 0x12, 0x30, 0xe4,
- 0x3c, 0x56, 0x4e, 0x01, 0x5d, 0xf0, 0x7a, 0x01, 0x88, 0x0d, 0x8e, 0x10, 0xb6, 0x00, 0xc4, 0x08,
- 0x00, 0x80, 0x04, 0x12, 0x05, 0xfc, 0x24, 0x01, 0x28, 0x01, 0x32, 0x00, 0x3c, 0x01, 0x40, 0x00,
- 0x4b, 0xe4, 0x4b, 0xf4, 0x4c, 0x1c, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x78, 0x01,
- 0x7c, 0x01, 0xbb, 0x55, 0x00, 0x01, 0x02, 0xee, 0x03, 0x58, 0x03, 0xf7, 0x03, 0xfa, 0x04, 0x80,
- 0x08, 0x44, 0x09, 0xf0, 0x10, 0x44, 0x1b, 0x80, 0x20, 0x01, 0x38, 0x1c, 0x4e, 0x1c, 0x5b, 0xf0,
- 0x80, 0x00, 0x8a, 0x15, 0x98, 0x10, 0xaa, 0x00, 0xbd, 0x56, 0xbe, 0x00, 0xc0, 0x00, 0x00, 0x4c,
- 0x00, 0xdc, 0x02, 0x4a, 0x04, 0xfc, 0x05, 0xf0, 0x05, 0xf8, 0x06, 0x13, 0x06, 0xf7, 0x08, 0x13,
- 0x0c, 0x00, 0x0e, 0x47, 0x0e, 0xf7, 0x0f, 0x00, 0x1c, 0x0c, 0x20, 0x00, 0x2a, 0x01, 0x32, 0x1c,
- 0x36, 0x00, 0x42, 0x54, 0x44, 0x0b, 0x44, 0x55, 0x45, 0x5a, 0x59, 0xf0, 0x5c, 0xf0, 0x62, 0x0a,
- 0x69, 0x08, 0x78, 0x13, 0x83, 0x59, 0x8e, 0x18, 0x9a, 0x10, 0x9a, 0x18, 0xb8, 0xf0, 0xd6, 0x0e,
- 0xea, 0x15, 0xf0, 0x00, 0x04, 0x10, 0x04, 0xea, 0x04, 0xf6, 0x05, 0x00, 0x06, 0x00, 0x06, 0x12,
- 0x0a, 0x10, 0x0a, 0x12, 0x0b, 0xf0, 0x0c, 0x10, 0x0c, 0xf0, 0x12, 0x10, 0x19, 0x00, 0x19, 0xe4,
- 0x2a, 0x12, 0x30, 0x1c, 0x33, 0x00, 0x34, 0x00, 0x36, 0x15, 0x38, 0x44, 0x3a, 0x15, 0x40, 0x5c,
- 0x4a, 0xe4, 0x62, 0x1a, 0x68, 0x08, 0x68, 0x54, 0x7a, 0x17, 0x83, 0x55, 0x83, 0x5a, 0x91, 0x44,
- 0xa2, 0x10, 0xa4, 0x00, 0xb0, 0x57, 0xb5, 0x00, 0xba, 0x00, 0xcc, 0x0e, 0xce, 0x45, 0xd0, 0x00,
- 0xe1, 0x00, 0xe5, 0x55, 0xe7, 0x00, 0x00, 0x54, 0x01, 0x48, 0x01, 0x58, 0x02, 0x10, 0x02, 0xe6,
- 0x03, 0xa1, 0x04, 0x13, 0x05, 0xe6, 0x06, 0x83, 0x06, 0xf0, 0x07, 0x00, 0x0a, 0x00, 0x0a, 0xf0,
- 0x0c, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x04, 0x10, 0x10, 0x12, 0x1c, 0x19, 0x81, 0x1a, 0x10,
- 0x1c, 0x00, 0x1c, 0x12, 0x1c, 0x13, 0x1d, 0xf7, 0x1e, 0x13, 0x20, 0x1c, 0x20, 0xe7, 0x22, 0x01,
- 0x26, 0x01, 0x30, 0xe7, 0x38, 0x12, 0x3a, 0x55, 0x3f, 0x00, 0x41, 0x58, 0x43, 0x48, 0x46, 0x1c,
- 0x4e, 0xe4, 0x5a, 0x13, 0x68, 0x13, 0x72, 0x14, 0x76, 0x02, 0x77, 0x57, 0x78, 0x03, 0x89, 0x48,
- 0x8a, 0x13, 0x98, 0x80, 0x99, 0x00, 0x9b, 0x00, 0x9c, 0x32, 0xfe, 0x9c, 0xf0, 0x27, 0x02, 0xfe,
- 0xa6, 0x0d, 0xff, 0x10, 0x00, 0x00, 0xfe, 0xc6, 0x01, 0xfe, 0x18, 0x1a, 0x00, 0xfe, 0xc4, 0x01,
- 0xfe, 0x84, 0x01, 0xff, 0x03, 0x00, 0x00, 0x30, 0xfe, 0x01, 0x05, 0xff, 0x40, 0x00, 0x00, 0x0d,
- 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x10, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00,
- 0xff, 0x10, 0xff, 0xff, 0xff, 0x11, 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21,
- 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xfe, 0xc4, 0x01, 0x38, 0x86, 0x0b, 0x01, 0xfe, 0x96, 0x0f, 0xfe,
- 0x04, 0xf7, 0xfe, 0xc4, 0x01, 0x86, 0x0b, 0x1c, 0x38, 0xfe, 0x3d, 0xf0, 0xfe, 0xfc, 0x01, 0xfe,
- 0x20, 0xf0, 0xdb, 0x04, 0x5e, 0x59, 0x02, 0xfe, 0xc2, 0x0d, 0x01, 0xfe, 0x22, 0x0e, 0xfe, 0xe9,
- 0x12, 0x02, 0xfe, 0x08, 0x03, 0xfe, 0x28, 0x1c, 0x04, 0xfe, 0xa6, 0x00, 0xfe, 0xdd, 0x12, 0x46,
- 0x12, 0xfe, 0xa6, 0x00, 0xcd, 0xfe, 0x48, 0xf0, 0xfe, 0x80, 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0x9a,
- 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xb8, 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x4a, 0x02, 0xfe, 0x47, 0xf0,
- 0xfe, 0x50, 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x3e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x42, 0x02, 0xfe,
- 0x45, 0xf0, 0xfe, 0x46, 0x02, 0x09, 0x0b, 0xa2, 0x09, 0x06, 0x12, 0xc1, 0x02, 0x27, 0xfe, 0x00,
- 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02, 0x1c, 0xfe, 0xed, 0x10, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10,
- 0x01, 0xfe, 0xee, 0x17, 0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc, 0xfe, 0xa8, 0x00, 0x0f, 0x7d, 0x01,
- 0xc5, 0x02, 0x27, 0x17, 0x5d, 0x4b, 0xc3, 0x01, 0xab, 0x0f, 0x7d, 0x01, 0x9f, 0xfe, 0xbd, 0x10,
- 0x0f, 0x7d, 0x01, 0x9f, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe, 0x58, 0x1c, 0x09, 0x06, 0x12,
- 0xc1, 0x38, 0x19, 0x27, 0xfe, 0x3d, 0xf0, 0xfe, 0xfc, 0x01, 0x28, 0xfe, 0x8e, 0x02, 0xfe, 0x5a,
- 0x1c, 0xdd, 0xfe, 0x14, 0x1c, 0x17, 0xfe, 0x30, 0x00, 0x4b, 0xc3, 0x01, 0xfe, 0xfc, 0x0f, 0x09,
- 0x06, 0x12, 0xc1, 0x02, 0xfe, 0xc6, 0x01, 0x2a, 0x2d, 0x05, 0x10, 0x30, 0xfe, 0x69, 0x10, 0x09,
- 0x06, 0x12, 0xc1, 0xfe, 0x04, 0xec, 0x2d, 0x07, 0x2d, 0x09, 0x3c, 0x1c, 0x01, 0x40, 0x81, 0xfe,
- 0x05, 0xf6, 0xfe, 0xa8, 0x00, 0x01, 0xfe, 0x20, 0x17, 0x0a, 0x4f, 0x8d, 0x3a, 0x11, 0x48, 0x1c,
- 0xd3, 0x07, 0x1e, 0x09, 0x51, 0x01, 0xa0, 0x02, 0x27, 0x0f, 0x3d, 0x01, 0x15, 0x05, 0x10, 0xda,
- 0x07, 0x1e, 0x09, 0x51, 0x01, 0x79, 0xfe, 0x28, 0x10, 0x0f, 0xc7, 0x01, 0x15, 0xed, 0x0f, 0x7e,
- 0x01, 0x15, 0xfe, 0x49, 0x54, 0x77, 0xfe, 0x16, 0x03, 0x07, 0x1e, 0x09, 0x51, 0x01, 0xa0, 0x02,
- 0x27, 0x38, 0x81, 0xfe, 0x02, 0xe8, 0x33, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xf5, 0xfe, 0x07,
- 0x4b, 0xfe, 0x20, 0xf0, 0xdb, 0xfe, 0x40, 0x1c, 0x19, 0xf6, 0xfe, 0x26, 0xf0, 0xfe, 0x74, 0x03,
- 0xfe, 0xa0, 0xf0, 0xfe, 0x62, 0x03, 0xfe, 0x11, 0xf0, 0xdb, 0xfe, 0x0e, 0x10, 0xfe, 0x9f, 0xf0,
- 0xfe, 0x82, 0x03, 0xef, 0x13, 0xfe, 0x11, 0x00, 0x02, 0x54, 0x38, 0xfe, 0x48, 0x1c, 0xef, 0x19,
- 0xf6, 0x35, 0xf6, 0xfe, 0x82, 0xf0, 0xfe, 0x88, 0x03, 0x24, 0x2a, 0xc4, 0x70, 0x16, 0xc4, 0x0f,
- 0x7e, 0x01, 0x15, 0x70, 0x7f, 0x07, 0x1e, 0x09, 0x51, 0x01, 0x40, 0x11, 0x3d, 0x07, 0x3d, 0x09,
- 0xa1, 0x01, 0xa0, 0xfc, 0x11, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xce, 0x03, 0x19, 0x32, 0x1f, 0xfe,
- 0xde, 0x03, 0x01, 0x41, 0xd4, 0xfe, 0xee, 0x03, 0x71, 0x8c, 0xd7, 0xfe, 0xae, 0x06, 0x02, 0x25,
- 0x04, 0x7d, 0x2c, 0x1a, 0xfe, 0x20, 0x05, 0x17, 0x88, 0x01, 0x2e, 0x01, 0x9b, 0x01, 0x9d, 0x35,
- 0xfe, 0x60, 0x02, 0x02, 0xf4, 0xef, 0x38, 0x86, 0x18, 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xf5,
- 0xfe, 0x48, 0x1c, 0x8f, 0x01, 0xf2, 0xb1, 0xfe, 0x96, 0xf0, 0xfe, 0x28, 0x04, 0x2f, 0xfe, 0x2c,
- 0x04, 0x35, 0x27, 0x0f, 0x3d, 0x01, 0x15, 0x05, 0x10, 0x1a, 0xfe, 0x0c, 0x05, 0x4c, 0x97, 0xa3,
- 0x33, 0x84, 0x74, 0x19, 0x32, 0x1f, 0x25, 0x04, 0x7d, 0x2c, 0xfe, 0x10, 0x12, 0x17, 0x88, 0x01,
- 0x2e, 0x35, 0xfe, 0x60, 0x02, 0x02, 0xf4, 0x21, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x5e,
- 0x12, 0x0a, 0x08, 0x06, 0xfe, 0x56, 0x12, 0x23, 0x29, 0x98, 0x01, 0x0c, 0x84, 0x74, 0x1f, 0xfe,
- 0xdc, 0x04, 0x23, 0x29, 0x98, 0x01, 0x0c, 0x1f, 0x25, 0x23, 0x29, 0xba, 0xfe, 0x4c, 0x44, 0xfe,
- 0x32, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x07, 0xfe, 0x93, 0x00, 0xfe, 0x4c, 0x54, 0x77, 0xfe, 0x0c,
- 0x05, 0x81, 0xa3, 0x33, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x48, 0x13, 0x3e, 0x05, 0xfe,
- 0xcc, 0x00, 0xfe, 0x40, 0x13, 0x0a, 0x08, 0x06, 0xea, 0xfe, 0x06, 0x10, 0x23, 0x29, 0xba, 0x0a,
- 0x08, 0x39, 0xe1, 0x17, 0xa6, 0x0a, 0x08, 0x06, 0x59, 0x17, 0xfe, 0x0d, 0x00, 0x01, 0x2e, 0x35,
- 0xfe, 0x66, 0x0d, 0x02, 0x25, 0x3b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90, 0xb7, 0x03, 0x17,
- 0xa6, 0x01, 0x2e, 0x35, 0x27, 0x19, 0x27, 0x02, 0xfe, 0x14, 0x05, 0xfe, 0x42, 0x5b, 0x86, 0x18,
- 0xfe, 0x46, 0x59, 0xfe, 0xbf, 0x57, 0xf5, 0x17, 0x78, 0xfe, 0x07, 0x80, 0xfe, 0x31, 0x44, 0x0a,
- 0x08, 0x0b, 0x99, 0xfe, 0x20, 0x80, 0x05, 0x18, 0xfe, 0x70, 0x12, 0x73, 0x08, 0x06, 0xfe, 0x60,
- 0x13, 0x04, 0xfe, 0xa2, 0x00, 0x2c, 0x1a, 0xfe, 0xac, 0x05, 0xfe, 0x31, 0xe4, 0x5f, 0x73, 0x08,
- 0x0b, 0xfe, 0x4a, 0x13, 0x04, 0xfe, 0xa0, 0x00, 0x2c, 0xfe, 0x42, 0x12, 0x62, 0x2f, 0xfe, 0x6c,
- 0x05, 0x19, 0x32, 0xf7, 0x01, 0x0c, 0x26, 0xfe, 0xc4, 0x05, 0x11, 0xfe, 0xe3, 0x00, 0x24, 0x73,
- 0xfe, 0x4a, 0xf0, 0xfe, 0x96, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0x90, 0x05, 0xab, 0x20, 0xfe, 0x21,
- 0x00, 0xa8, 0x20, 0xfe, 0x22, 0x00, 0xa2, 0x20, 0x8d, 0xfe, 0x09, 0x48, 0x01, 0x0c, 0x26, 0xfe,
- 0xc4, 0x05, 0xfe, 0xe2, 0x08, 0x73, 0x08, 0xe0, 0x59, 0x01, 0x99, 0x20, 0x06, 0x16, 0xe8, 0x4b,
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+ 0x05, 0x06, 0x87, 0x20, 0x5e, 0xce, 0xb6, 0x03, 0x17, 0xfe, 0x09, 0x00, 0x01, 0x3b, 0x2f, 0xfe,
+ 0x34, 0x1a, 0x04, 0x76, 0xb7, 0x03, 0x1b, 0xfe, 0x54, 0x1a, 0xfe, 0x14, 0xf0, 0x0c, 0x2f, 0xfe,
+ 0x48, 0x1a, 0x1b, 0xfe, 0x54, 0x1a, 0xfe, 0x82, 0xf0, 0xfe, 0x4c, 0x1a, 0x03, 0xff, 0x15, 0x00,
+ 0x00,
+};
STATIC unsigned short _adv_asc38C0800_size =
- sizeof(_adv_asc38C0800_buf); /* 0x14AA */
-STATIC unsigned long _adv_asc38C0800_chksum =
- 0x05297A65UL; /* Expanded checksum. */
+ sizeof(_adv_asc38C0800_buf); /* 0x14F1 */
+STATIC ADV_DCNT _adv_asc38C0800_chksum =
+ 0x053503A5; /* Expanded checksum. */
/* a_init.c */
/*
*/
STATIC ADVEEP_3550_CONFIG
Default_3550_EEPROM_Config ASC_INITDATA = {
- ADV_EEPROM_BIOS_ENABLE, /* cfg_msw */
- 0x0000, /* cfg_lsw */
+ ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
+ 0x0000, /* cfg_msw */
0xFFFF, /* disc_enable */
0xFFFF, /* wdtr_able */
0xFFFF, /* sdtr_able */
STATIC ADVEEP_38C0800_CONFIG
Default_38C0800_EEPROM_Config ASC_INITDATA = {
- ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_msw */
- 0x0000, /* 01 cfg_lsw */
+ ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
+ 0x0000, /* 01 cfg_msw */
0xFFFF, /* 02 disc_enable */
0xFFFF, /* 03 wdtr_able */
0x4444, /* 04 sdtr_speed1 */
/*
* PCI Command Register
+ *
+ * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
+ * I/O Space Control, Memory Space Control and Bus Master Control bits.
*/
if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
asc_dvc->cfg->chip_version =
AdvGetChipVersion(iop_base, asc_dvc->bus_type);
- ASC_DBG2(1, "iopb_chip_id_1: %x %x\n",
+ ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: %x %x\n",
(ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
(ushort) ADV_CHIP_ID_BYTE);
- ASC_DBG2(1, "iopw_chip_id_0: %x %x\n",
+ ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: %x %x\n",
(ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
(ushort) ADV_CHIP_ID_WORD);
{
AdvPortAddr iop_base;
ushort warn_code;
- ulong sum;
+ ADV_DCNT sum;
int begin_addr;
int end_addr;
ushort code_sum;
int j;
int adv_asc3550_expanded_size;
ADV_CARR_T *carrp;
- ulong contig_len;
- long buf_size;
- ulong carr_paddr;
+ ADV_DCNT contig_len;
+ ADV_SDCNT buf_size;
+ ADV_PADDR carr_paddr;
int i;
ushort scsi_cfg1;
uchar tid;
bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
major = (bios_version >> 12) & 0xF;
minor = (bios_version >> 8) & 0xF;
- if (major <= 3 || (major == 3 && minor == 1))
+ if (major < 3 || (major == 3 && minor == 1))
{
/* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
AdvReadWordLram(iop_base, 0x120, wdtr_able);
{
for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
{
- AdvWriteWordAutoIncLram(iop_base,
- *((ushort *) (&_adv_asc3550_buf[i + 2])));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc3550_buf[i + 3] << 8) |
+ _adv_asc3550_buf[i + 2]));
word++;
}
- i += 3;
+ i += 3;
} else if (_adv_asc3550_buf[i] == 0xfe)
{
- AdvWriteWordAutoIncLram(iop_base,
- *((ushort *) (&_adv_asc3550_buf[i + 1])));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc3550_buf[i + 2] << 8) |
+ _adv_asc3550_buf[i + 1]));
i += 2;
word++;
} else
{
- AdvWriteWordAutoIncLram(iop_base,
- *((ushort *) &_adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
+ _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
word++;
}
}
* queuing will be set in AdvInquiryHandling() based on what a
* device reports it is capable of in Inquiry byte 7.
*
- * If SCSI Bus Resets haev been disabled, then directly set
+ * If SCSI Bus Resets have been disabled, then directly set
* SDTR and WDTR from the EEPROM configuration. This will allow
* the BIOS and warm boot to work without a SCSI bus hang on
* the Inquiry caused by host and target mismatched DTR values.
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
- FLTR_11_TO_20NS | scsi_cfg1);
+ FLTR_DISABLE | scsi_cfg1);
/*
* Set MEM_CFG Microcode Default Value
*
* Driver must have already allocated memory and set 'carrier_buf'.
*/
- ADV_ASSERT(asc_dvc->carrier_buf != NULL);
+ ASC_ASSERT(asc_dvc->carrier_buf != NULL);
carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
asc_dvc->carr_freelist = NULL;
* Get physical address of the carrier 'carrp'.
*/
contig_len = sizeof(ADV_CARR_T);
- carr_paddr = DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
- (long *) &contig_len, ADV_IS_CARRIER_FLAG);
+ carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
+ (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
buf_size -= sizeof(ADV_CARR_T);
}
carrp->carr_pa = carr_paddr;
- carrp->carr_va = (ulong) carrp;
+ carrp->carr_va = ADV_VADDR_TO_U32(carrp);
/*
* Insert the carrier at the beginning of the freelist.
*/
- carrp->next_vpa = (ulong) asc_dvc->carr_freelist;
+ carrp->next_vpa = ADV_VADDR_TO_U32(asc_dvc->carr_freelist);
asc_dvc->carr_freelist = carrp;
carrp++;
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
- asc_dvc->carr_freelist = (ADV_CARR_T *) asc_dvc->icq_sp->next_vpa;
+ asc_dvc->carr_freelist =
+ (ADV_CARR_T *) ADV_U32_TO_VADDR(asc_dvc->icq_sp->next_vpa);
/*
* The first command issued will be placed in the stopper carrier.
/*
* Set RISC ICQ physical address start value.
*/
- AdvWriteDWordLram(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
+ AdvWriteDWordLram(iop_base, ASC_MC_ICQ,
+ cpu_to_le32(asc_dvc->icq_sp->carr_pa));
/*
* Set-up the RISC->Host Initiator Response Queue (IRQ).
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
- asc_dvc->carr_freelist = (ADV_CARR_T *) asc_dvc->irq_sp->next_vpa;
+ asc_dvc->carr_freelist =
+ (ADV_CARR_T *) ADV_U32_TO_VADDR(asc_dvc->irq_sp->next_vpa);
/*
* The first command completed by the RISC will be placed in
/*
* Set RISC IRQ physical address start value.
*/
- AdvWriteDWordLram(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
+ AdvWriteDWordLram(iop_base, ASC_MC_IRQ,
+ cpu_to_le32(asc_dvc->irq_sp->carr_pa));
asc_dvc->carr_pending_cnt = 0;
AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
{
AdvPortAddr iop_base;
ushort warn_code;
- ulong sum;
+ ADV_DCNT sum;
int begin_addr;
int end_addr;
ushort code_sum;
int j;
int adv_asc38C0800_expanded_size;
ADV_CARR_T *carrp;
- ulong contig_len;
- long buf_size;
- ulong carr_paddr;
+ ADV_DCNT contig_len;
+ ADV_SDCNT buf_size;
+ ADV_PADDR carr_paddr;
int i;
ushort scsi_cfg1;
uchar byte;
{
for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
{
- AdvWriteWordAutoIncLram(iop_base,
- *((ushort *) (&_adv_asc38C0800_buf[i + 2])));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc38C0800_buf[i + 3] << 8) |
+ _adv_asc38C0800_buf[i + 2]));
word++;
}
- i += 3;
+ i += 3;
} else if (_adv_asc38C0800_buf[i] == 0xfe)
{
- AdvWriteWordAutoIncLram(iop_base,
- *((ushort *) (&_adv_asc38C0800_buf[i + 1])));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc38C0800_buf[i + 2] << 8) |
+ _adv_asc38C0800_buf[i + 1]));
i += 2;
word++;
} else
{
- AdvWriteWordAutoIncLram(iop_base, *((ushort *)
- &_adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
+ AdvWriteWordAutoIncLram(iop_base, (((ushort)
+ _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
+ _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
word++;
}
}
{
sum += AdvReadWordAutoIncLram(iop_base);
}
+ ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
+
+ ASC_DBG2(1,
+ "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
+ (ulong) sum, (ulong) _adv_asc38C0800_chksum);
if (sum != _adv_asc38C0800_chksum)
{
*
* Driver must have already allocated memory and set 'carrier_buf'.
*/
-
- ADV_ASSERT(asc_dvc->carrier_buf != NULL);
+ ASC_ASSERT(asc_dvc->carrier_buf != NULL);
carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
asc_dvc->carr_freelist = NULL;
* Get physical address for the carrier 'carrp'.
*/
contig_len = sizeof(ADV_CARR_T);
- carr_paddr = DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
- (long *) &contig_len, ADV_IS_CARRIER_FLAG);
+ carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
+ (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
buf_size -= sizeof(ADV_CARR_T);
}
carrp->carr_pa = carr_paddr;
- carrp->carr_va = (ulong) carrp;
+ carrp->carr_va = ADV_VADDR_TO_U32(carrp);
/*
* Insert the carrier at the beginning of the freelist.
*/
- carrp->next_vpa = (ulong) asc_dvc->carr_freelist;
+ carrp->next_vpa = ADV_VADDR_TO_U32(asc_dvc->carr_freelist);
asc_dvc->carr_freelist = carrp;
carrp++;
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
- asc_dvc->carr_freelist = (ADV_CARR_T *) asc_dvc->icq_sp->next_vpa;
+ asc_dvc->carr_freelist =
+ (ADV_CARR_T *) ADV_U32_TO_VADDR(asc_dvc->icq_sp->next_vpa);
/*
* The first command issued will be placed in the stopper carrier.
/*
* Set RISC ICQ physical address start value.
*/
- AdvWriteDWordLram(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
+ AdvWriteDWordLram(iop_base, ASC_MC_ICQ,
+ cpu_to_le32(asc_dvc->icq_sp->carr_pa));
/*
* Set-up the RISC->Host Initiator Response Queue (IRQ).
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
- asc_dvc->carr_freelist = (ADV_CARR_T *) asc_dvc->irq_sp->next_vpa;
+ asc_dvc->carr_freelist =
+ (ADV_CARR_T *) ADV_U32_TO_VADDR(asc_dvc->irq_sp->next_vpa);
/*
* The first command completed by the RISC will be placed in
/*
* Set RISC IRQ physical address start value.
*/
- AdvWriteDWordLram(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
+ AdvWriteDWordLram(iop_base, ASC_MC_IRQ,
+ cpu_to_le32(asc_dvc->irq_sp->carr_pa));
asc_dvc->carr_pending_cnt = 0;
AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
*/
ASC_INITFUNC(
STATIC int,
-AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
+AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
)
{
- AdvPortAddr iop_base;
- ushort warn_code;
- ADVEEP_38C0800_CONFIG eep_config;
- int i;
- uchar tid, termination;
- ushort sdtr_speed = 0;
+ AdvPortAddr iop_base;
+ ushort warn_code;
+ ADVEEP_3550_CONFIG eep_config;
+ int i;
iop_base = asc_dvc->iop_base;
* Read the board's EEPROM configuration.
*
* Set default values if a bad checksum is found.
+ *
+ * XXX - Don't handle big-endian access to EEPROM yet.
*/
- if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
+ if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
{
warn_code |= ASC_WARN_EEPROM_CHKSUM;
/*
* Set EEPROM default values.
*/
- for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
+ for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
{
*((uchar *) &eep_config + i) =
- *((uchar *) &Default_38C0800_EEPROM_Config + i);
+ *((uchar *) &Default_3550_EEPROM_Config + i);
}
/*
eep_config.serial_number_word1 =
AdvReadEEPWord(iop_base, ASC_EEP_DVC_CFG_END - 3);
- AdvSet38C0800EEPConfig(iop_base, &eep_config);
+ AdvSet3550EEPConfig(iop_base, &eep_config);
}
/*
- * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
+ * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
* EEPROM configuration that was read.
*
* This is the mapping of EEPROM fields to Adv Library fields.
*/
asc_dvc->wdtr_able = eep_config.wdtr_able;
- asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
- asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
- asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
- asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
+ asc_dvc->sdtr_able = eep_config.sdtr_able;
+ asc_dvc->ultra_able = eep_config.ultra_able;
asc_dvc->tagqng_able = eep_config.tagqng_able;
asc_dvc->cfg->disc_enable = eep_config.disc_enable;
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
- /*
- * For every Target ID if any of its 'sdtr_speed[1234]' bits
- * are set, then set an 'sdtr_able' bit for it.
- */
- asc_dvc->sdtr_able = 0;
- for (tid = 0; tid <= ADV_MAX_TID; tid++)
- {
- if (tid == 0)
- {
- sdtr_speed = asc_dvc->sdtr_speed1;
- } else if (tid == 4)
- {
- sdtr_speed = asc_dvc->sdtr_speed2;
- } else if (tid == 8)
- {
- sdtr_speed = asc_dvc->sdtr_speed3;
- } else if (tid == 12)
- {
- sdtr_speed = asc_dvc->sdtr_speed4;
- }
- if (sdtr_speed & ADV_MAX_TID)
- {
- asc_dvc->sdtr_able |= (1 << tid);
- }
- sdtr_speed >>= 4;
- }
-
/*
* Set the host maximum queuing (max. 253, min. 16) and the per device
* maximum queuing (max. 63, min. 4).
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
+
/*
* If the EEPROM 'termination' field is set to automatic (0), then set
* the ADV_DVC_CFG 'termination' field to automatic also.
* value check that a legal value is set and set the ADV_DVC_CFG
* 'termination' field appropriately.
*/
- if (eep_config.termination_se == 0)
- {
- termination = 0; /* auto termination for SE */
- } else
- {
- /* Enable manual control with low off / high off. */
- if (eep_config.termination_se == 1)
- {
- termination = 0;
-
- /* Enable manual control with low off / high on. */
- } else if (eep_config.termination_se == 2)
- {
- termination = TERM_SE_HI;
-
- /* Enable manual control with low on / high on. */
- } else if (eep_config.termination_se == 3)
- {
- termination = TERM_SE;
- } else
- {
- /*
- * The EEPROM 'termination_se' field contains a bad value.
- * Use automatic termination instead.
- */
- termination = 0;
- warn_code |= ASC_WARN_EEPROM_TERMINATION;
- }
- }
-
- if (eep_config.termination_lvd == 0)
+ if (eep_config.termination == 0)
{
- asc_dvc->cfg->termination = termination; /* auto termination for LVD */
+ asc_dvc->cfg->termination = 0; /* auto termination */
} else
{
/* Enable manual control with low off / high off. */
- if (eep_config.termination_lvd == 1)
+ if (eep_config.termination == 1)
{
- asc_dvc->cfg->termination = termination;
+ asc_dvc->cfg->termination = TERM_CTL_SEL;
/* Enable manual control with low off / high on. */
- } else if (eep_config.termination_lvd == 2)
+ } else if (eep_config.termination == 2)
{
- asc_dvc->cfg->termination = termination | TERM_LVD_HI;
+ asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
/* Enable manual control with low on / high on. */
- } else if (eep_config.termination_lvd == 3)
+ } else if (eep_config.termination == 3)
{
- asc_dvc->cfg->termination =
- termination | TERM_LVD;
+ asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
} else
{
/*
- * The EEPROM 'termination_lvd' field contains a bad value.
- * Use automatic termination instead.
+ * The EEPROM 'termination' field contains a bad value. Use
+ * automatic termination instead.
*/
- asc_dvc->cfg->termination = termination;
+ asc_dvc->cfg->termination = 0;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
*/
ASC_INITFUNC(
STATIC int,
-AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
+AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
)
{
- AdvPortAddr iop_base;
- ushort warn_code;
- ADVEEP_3550_CONFIG eep_config;
- int i;
+ AdvPortAddr iop_base;
+ ushort warn_code;
+ ADVEEP_38C0800_CONFIG eep_config;
+ int i;
+ uchar tid, termination;
+ ushort sdtr_speed = 0;
iop_base = asc_dvc->iop_base;
* Read the board's EEPROM configuration.
*
* Set default values if a bad checksum is found.
+ *
+ * XXX - Don't handle big-endian access to EEPROM yet.
*/
- if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
+ if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
{
warn_code |= ASC_WARN_EEPROM_CHKSUM;
/*
* Set EEPROM default values.
*/
- for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
+ for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
{
*((uchar *) &eep_config + i) =
- *((uchar *) &Default_3550_EEPROM_Config + i);
+ *((uchar *) &Default_38C0800_EEPROM_Config + i);
}
/*
eep_config.serial_number_word1 =
AdvReadEEPWord(iop_base, ASC_EEP_DVC_CFG_END - 3);
- AdvSet3550EEPConfig(iop_base, &eep_config);
+ AdvSet38C0800EEPConfig(iop_base, &eep_config);
}
/*
- * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
+ * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
* EEPROM configuration that was read.
*
* This is the mapping of EEPROM fields to Adv Library fields.
*/
asc_dvc->wdtr_able = eep_config.wdtr_able;
- asc_dvc->sdtr_able = eep_config.sdtr_able;
- asc_dvc->ultra_able = eep_config.ultra_able;
+ asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
+ asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
+ asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
+ asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
asc_dvc->tagqng_able = eep_config.tagqng_able;
asc_dvc->cfg->disc_enable = eep_config.disc_enable;
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
+ /*
+ * For every Target ID if any of its 'sdtr_speed[1234]' bits
+ * are set, then set an 'sdtr_able' bit for it.
+ */
+ asc_dvc->sdtr_able = 0;
+ for (tid = 0; tid <= ADV_MAX_TID; tid++)
+ {
+ if (tid == 0)
+ {
+ sdtr_speed = asc_dvc->sdtr_speed1;
+ } else if (tid == 4)
+ {
+ sdtr_speed = asc_dvc->sdtr_speed2;
+ } else if (tid == 8)
+ {
+ sdtr_speed = asc_dvc->sdtr_speed3;
+ } else if (tid == 12)
+ {
+ sdtr_speed = asc_dvc->sdtr_speed4;
+ }
+ if (sdtr_speed & ADV_MAX_TID)
+ {
+ asc_dvc->sdtr_able |= (1 << tid);
+ }
+ sdtr_speed >>= 4;
+ }
+
/*
* Set the host maximum queuing (max. 253, min. 16) and the per device
* maximum queuing (max. 63, min. 4).
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
-
/*
* If the EEPROM 'termination' field is set to automatic (0), then set
* the ADV_DVC_CFG 'termination' field to automatic also.
* value check that a legal value is set and set the ADV_DVC_CFG
* 'termination' field appropriately.
*/
- if (eep_config.termination == 0)
+ if (eep_config.termination_se == 0)
{
- asc_dvc->cfg->termination = 0; /* auto termination */
+ termination = 0; /* auto termination for SE */
} else
{
/* Enable manual control with low off / high off. */
- if (eep_config.termination == 1)
+ if (eep_config.termination_se == 1)
{
- asc_dvc->cfg->termination = TERM_CTL_SEL;
+ termination = 0;
/* Enable manual control with low off / high on. */
- } else if (eep_config.termination == 2)
+ } else if (eep_config.termination_se == 2)
{
- asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
+ termination = TERM_SE_HI;
/* Enable manual control with low on / high on. */
- } else if (eep_config.termination == 3)
+ } else if (eep_config.termination_se == 3)
{
- asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
+ termination = TERM_SE;
} else
{
/*
- * The EEPROM 'termination' field contains a bad value. Use
- * automatic termination instead.
+ * The EEPROM 'termination_se' field contains a bad value.
+ * Use automatic termination instead.
*/
- asc_dvc->cfg->termination = 0;
+ termination = 0;
+ warn_code |= ASC_WARN_EEPROM_TERMINATION;
+ }
+ }
+
+ if (eep_config.termination_lvd == 0)
+ {
+ asc_dvc->cfg->termination = termination; /* auto termination for LVD */
+ } else
+ {
+ /* Enable manual control with low off / high off. */
+ if (eep_config.termination_lvd == 1)
+ {
+ asc_dvc->cfg->termination = termination;
+
+ /* Enable manual control with low off / high on. */
+ } else if (eep_config.termination_lvd == 2)
+ {
+ asc_dvc->cfg->termination = termination | TERM_LVD_HI;
+
+ /* Enable manual control with low on / high on. */
+ } else if (eep_config.termination_lvd == 3)
+ {
+ asc_dvc->cfg->termination =
+ termination | TERM_LVD;
+ } else
+ {
+ /*
+ * The EEPROM 'termination_lvd' field contains a bad value.
+ * Use automatic termination instead.
+ */
+ asc_dvc->cfg->termination = termination;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
*/
ASC_INITFUNC(
STATIC ushort,
-AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
- ADVEEP_38C0800_CONFIG *cfg_buf)
+AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
)
{
ushort wval, chksum;
return chksum;
}
-
/*
* Read EEPROM configuration into the specified buffer.
*
*/
ASC_INITFUNC(
STATIC ushort,
-AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
+AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
+ ADVEEP_38C0800_CONFIG *cfg_buf)
)
{
ushort wval, chksum;
return chksum;
}
+
/*
* Read the EEPROM from specified location
*/
}
if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
{
- ADV_ASSERT(0);
+ ASC_ASSERT(0);
}
return;
}
* If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
* set to SCSI_MAX_RETRY.
*
+ * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
+ * for DMA addresses or math operations are byte swapped to little-endian
+ * order.
+ *
* Return:
* ADV_SUCCESS(1) - The request was successfully queued.
* ADV_BUSY(0) - Resource unavailable; Retry again after pending
{
int last_int_level;
AdvPortAddr iop_base;
- long req_size;
- ulong req_paddr;
+ ADV_DCNT req_size;
+ ADV_PADDR req_paddr;
ADV_CARR_T *new_carrp;
- ADV_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
+ ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
/*
* The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
{
return ADV_BUSY;
}
- asc_dvc->carr_freelist = (ADV_CARR_T *) new_carrp->next_vpa;
+ asc_dvc->carr_freelist =
+ (ADV_CARR_T *) ADV_U32_TO_VADDR(new_carrp->next_vpa);
asc_dvc->carr_pending_cnt++;
/*
scsiq->a_flag &= ~ADV_SCSIQ_DONE;
req_size = sizeof(ADV_SCSI_REQ_Q);
- req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
- (long *) &req_size, ADV_IS_SCSIQ_FLAG);
+ req_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
+ (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG));
- ADV_ASSERT(ADV_DWALIGN(req_paddr) == req_paddr);
- ADV_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
+ ASC_ASSERT(ADV_DWALIGN(req_paddr) == req_paddr);
+ ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
- /* Save virtual and physical address of ADV_SCSI_REQ_Q and Carrier. */
- scsiq->scsiq_ptr = (ADV_SCSI_REQ_Q *) scsiq;
+ /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
+ scsiq->scsiq_ptr = ADV_VADDR_TO_U32(scsiq);
scsiq->scsiq_rptr = req_paddr;
- /* XXX - Could have the RISC set these values. */
- scsiq->carr_va = (ulong) asc_dvc->icq_sp;
+ scsiq->carr_va = ADV_VADDR_TO_U32(asc_dvc->icq_sp);
+ /*
+ * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
+ * order during initialization.
+ */
scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
/*
* the microcode. The newly allocated stopper will become the new
* stopper.
*/
- asc_dvc->icq_sp->areq_vpa = (ulong) req_paddr;
+ asc_dvc->icq_sp->areq_vpa = req_paddr;
/*
* Set the 'next_vpa' pointer for the old stopper to be the
return status;
}
- DvcSleepMilliSecond((ulong) asc_dvc->scsi_reset_wait * 1000);
+ DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
return status;
}
uchar int_stat;
ushort target_bit;
ADV_CARR_T *free_carrp;
- ulong irq_next_vpa;
+ ADV_VADDR irq_next_vpa;
int flags;
ADV_SCSI_REQ_Q *scsiq;
/*
* Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
* The RISC will have set 'areq_vpa' to a virtual address.
+ *
+ * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
+ * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
+ * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
+ * in AdvExeScsiQueue().
*/
- scsiq = (ADV_SCSI_REQ_Q *) asc_dvc->irq_sp->areq_vpa;
+ scsiq = (ADV_SCSI_REQ_Q *) ADV_U32_TO_VADDR(asc_dvc->irq_sp->areq_vpa);
/*
* Advance the stopper pointer to the next carrier
* stopper carrier.
*/
free_carrp = asc_dvc->irq_sp;
- asc_dvc->irq_sp = ASC_GET_CARRP(irq_next_vpa);
+ asc_dvc->irq_sp = (ADV_CARR_T *)
+ ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
- free_carrp->next_vpa = (ulong) asc_dvc->carr_freelist;
- asc_dvc->carr_freelist = (ADV_CARR_T *) free_carrp;
+ free_carrp->next_vpa = ADV_VADDR_TO_U32(asc_dvc->carr_freelist);
+ asc_dvc->carr_freelist = free_carrp;
asc_dvc->carr_pending_cnt--;
-
- ADV_ASSERT(scsiq != NULL);
+ ASC_ASSERT(scsiq != NULL);
target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
/*
*/
scsiq->cntl = 0;
+#if __BIG_ENDIAN
/*
- * Check Condition handling
+ * After the request completes the only field in the ASC_SCSI_REQ_Q
+ * structure needs to be byte swapped from little endian order to
+ * big endian order is the residual data count.
*/
- if ((scsiq->done_status == QD_WITH_ERROR) &&
- (scsiq->scsi_status == SS_CHK_CONDITION)
- )
- {
- }
+ scsiqp->data_cnt = le32_to_cpu(scsiqp->data_cnt);
+#endif /* __BIG_ENDIAN */
+
/*
* If the command that completed was a SCSI INQUIRY and
* LUN 0 was sent the command, then process the INQUIRY
* command information for the device.
*/
- else if (scsiq->done_status == QD_NO_ERROR &&
- scsiq->cdb[0] == SCSICMD_Inquiry &&
- scsiq->target_lun == 0)
+ if (scsiq->done_status == QD_NO_ERROR &&
+ scsiq->cdb[0] == SCSICMD_Inquiry &&
+ scsiq->target_lun == 0)
{
AdvInquiryHandling(asc_dvc, scsiq);
}
STATIC int
AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
ushort idle_cmd,
- ulong idle_cmd_parameter)
+ ADV_DCNT idle_cmd_parameter)
{
int last_int_level;
int result;
- ulong i, j;
+ ADV_DCNT i, j;
AdvPortAddr iop_base;
last_int_level = DvcEnterCritical();
}
}
- ADV_ASSERT(0); /* The idle command should never timeout. */
+ ASC_ASSERT(0); /* The idle command should never timeout. */
DvcLeaveCritical(last_int_level);
return ADV_ERROR;
}
/* controller information */
size = sprintf(buffer+len,"\nDisk Array Controller Information:\n");
len += size; pos = begin + len;
-#if LINUX_VERSION_CODE >= 0x020000
strcpy(hrec, ha->binfo.type_string);
-#else
- sprintf(hrec, "%s (Bus %d)", ha->binfo.type_string, busnum);
-#endif
size = sprintf(buffer+len,
" Number: \t%d \tName: \t%s\n",
hanum, hrec);
for (i = 0; i < GDTH_MAXCMDS; ++i) {
scp = ha->cmd_tab[i].cmnd;
-#if LINUX_VERSION_CODE >= 0x020000
if (!SPECIAL_SCP(scp) && scp->target == (unchar)id &&
scp->channel == (unchar)busnum)
-#else
- if (!SPECIAL_SCP(scp) && scp->target == (unchar)id &&
- NUMDATA(scp->host)->busnum == (unchar)busnum)
-#endif
{
scp->SCp.have_data_in = 0;
GDTH_UNLOCK_HA(ha, flags);
GDTH_LOCK_HA(ha, flags);
for (scp = ha->req_first; scp; scp = (Scsi_Cmnd *)scp->SCp.ptr) {
-#if LINUX_VERSION_CODE >= 0x020000
if (scp->target == (unchar)id &&
scp->channel == (unchar)busnum)
-#else
- if (scp->target == (unchar)id &&
- NUMDATA(scp->host)->busnum == (unchar)busnum)
-#endif
{
TRACE2(("gdth_stop_timeout(): update_timeout()\n"));
scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
GDTH_LOCK_HA(ha, flags);
for (scp = ha->req_first; scp; scp = (Scsi_Cmnd *)scp->SCp.ptr) {
-#if LINUX_VERSION_CODE >= 0x020000
if (scp->target == (unchar)id &&
scp->channel == (unchar)busnum)
-#else
- if (scp->target == (unchar)id &&
- NUMDATA(scp->host)->busnum == (unchar)busnum)
-#endif
{
TRACE2(("gdth_start_timeout(): update_timeout()\n"));
gdth_update_timeout(hanum, scp, scp->SCp.buffers_residual);
open (OUTPUT, ">$output") || die "$0 : can't open $output for writing\n";
open (OUTPUTU, ">$outputu") || die "$0 : can't open $outputu for writing\n";
+print OUTPUT "/* DO NOT EDIT - Generated automatically by ".$0." */\n";
print OUTPUT "static u32 ".$prefix."SCRIPT[] = {\n";
$instructions = 0;
for ($i = 0; $i < $#code; ) {
* lock up.
*/
-#define BLIST_NOLUN 0x01
-#define BLIST_FORCELUN 0x02
-#define BLIST_BORKEN 0x04
-#define BLIST_KEY 0x08
-#define BLIST_SINGLELUN 0x10
-#define BLIST_NOTQ 0x20
-#define BLIST_SPARSELUN 0x40
-#define BLIST_MAX5LUN 0x80
+#define BLIST_NOLUN 0x001
+#define BLIST_FORCELUN 0x002
+#define BLIST_BORKEN 0x004
+#define BLIST_KEY 0x008
+#define BLIST_SINGLELUN 0x010
+#define BLIST_NOTQ 0x020
+#define BLIST_SPARSELUN 0x040
+#define BLIST_MAX5LUN 0x080
+#define BLIST_ISDISK 0x100
+#define BLIST_ISROM 0x200
+#define BLIST_GHOST 0x400
+
+
/*
* Data declarations.
extern void scsi_old_done(Scsi_Cmnd * SCpnt);
extern void scsi_old_times_out(Scsi_Cmnd * SCpnt);
-#define SCSI_BLOCK(DEVICE, HOST) \
- ((HOST->block && host_active && HOST != host_active) \
- || ((HOST)->can_queue && HOST->host_busy >= HOST->can_queue) \
- || ((HOST)->host_blocked) \
- || ((DEVICE) != NULL && (DEVICE)->device_blocked) )
+#define SCSI_BLOCK(DEVICE, HOST) \
+ ((HOST->block && host_active && HOST != host_active) \
+ || ((HOST)->can_queue && HOST->host_busy >= HOST->can_queue) \
+ || ((HOST)->host_blocked) \
+ || ((DEVICE) != NULL && (DEVICE)->device_blocked) )
{"CANON", "IPUBJD", "*", BLIST_SPARSELUN},
{"nCipher", "Fastness Crypto", "*", BLIST_FORCELUN},
{"NEC", "PD-1 ODX654P", "*", BLIST_FORCELUN | BLIST_SINGLELUN},
- {"MATSHITA", "PD", "*", BLIST_FORCELUN | BLIST_SINGLELUN},
+ {"MATSHITA", "PD-1", "*", BLIST_FORCELUN | BLIST_SINGLELUN},
{"iomega", "jaz 1GB", "J.86", BLIST_NOTQ | BLIST_NOLUN},
+ {"CREATIVE","DVD-RAM RAM","*", BLIST_GHOST},
+ {"MATSHITA","PD-2 LF-D100","*", BLIST_GHOST},
+ {"HITACHI", "GF-1050","*", BLIST_GHOST}, /* Hitachi SCSI DVD-RAM */
+ {"TOSHIBA","CDROM","*", BLIST_ISROM},
/*
* Must be at end of list...
SCpnt->request.rq_status = RQ_SCSI_BUSY;
spin_lock_irqsave(&io_request_lock, flags);
scsi_do_cmd (SCpnt, (void *) cmnd,
- buffer, bufflen, done, timeout, retries);
+ buffer, bufflen, done, timeout, retries);
spin_unlock_irqrestore(&io_request_lock, flags);
down (&sem);
SCpnt->request.sem = NULL;
struct Scsi_Device_Template *sdtpnt;
Scsi_Device *SDtail, *SDpnt = *SDpnt2;
int bflags, type = -1;
+ static int ghost_channel=-1, ghost_dev=-1;
+ int org_lun = lun;
SDpnt->host = shpnt;
SDpnt->id = dev;
SDpnt->channel = channel;
SDpnt->online = TRUE;
+
+ if ((channel == ghost_channel) && (dev == ghost_dev) && (lun == 1)) {
+ SDpnt->lun = 0;
+ } else {
+ ghost_channel = ghost_dev = -1;
+ }
+
+
/* Some low level driver could use device->type (DB) */
SDpnt->type = -1;
SCpnt->channel = SDpnt->channel;
scsi_wait_cmd (SCpnt, (void *) scsi_cmd,
- (void *) NULL,
- 0, scan_scsis_done, SCSI_TIMEOUT + 4 * HZ, 5);
+ (void *) NULL,
+ 0, scan_scsis_done, SCSI_TIMEOUT + 4 * HZ, 5);
SCSI_LOG_SCAN_BUS(3, printk("scsi: scan_scsis_single id %d lun %d. Return code 0x%08x\n",
dev, lun, SCpnt->result));
SCpnt->cmd_len = 0;
scsi_wait_cmd (SCpnt, (void *) scsi_cmd,
- (void *) scsi_result,
- 256, scan_scsis_done, SCSI_TIMEOUT, 3);
+ (void *) scsi_result,
+ 256, scan_scsis_done, SCSI_TIMEOUT, 3);
SCSI_LOG_SCAN_BUS(3, printk("scsi: INQUIRY %s with code 0x%x\n",
SCpnt->result ? "failed" : "successful", SCpnt->result));
if ((scsi_result[0] >> 5) == 3) {
return 0; /* assume no peripheral if any sort of error */
}
+
/*
- * It would seem some TOSHIBA CDROM gets things wrong
+ * Get any flags for this device.
+ */
+ bflags = get_device_flags (scsi_result);
+
+
+ /* The Toshiba ROM was "gender-changed" here as an inline hack.
+ This is now much more generic.
+ This is a mess: What we really want is to leave the scsi_result
+ alone, and just change the SDpnt structure. And the SDpnt is what
+ we want print_inquiry to print. -- REW
*/
- if (!strncmp(scsi_result + 8, "TOSHIBA", 7) &&
- !strncmp(scsi_result + 16, "CD-ROM", 6) &&
- scsi_result[0] == TYPE_DISK) {
+ if (bflags & BLIST_ISDISK) {
+ scsi_result[0] = TYPE_DISK;
+ scsi_result[1] |= 0x80; /* removable */
+ }
+
+ if (bflags & BLIST_ISROM) {
scsi_result[0] = TYPE_ROM;
- scsi_result[1] |= 0x80; /* removable */
+ scsi_result[1] |= 0x80; /* removable */
}
+
+ if (bflags & BLIST_GHOST) {
+ if ((ghost_channel == channel) && (ghost_dev == dev) && (org_lun == 1)) {
+ lun=1;
+ } else {
+ ghost_channel = channel;
+ ghost_dev = dev;
+ scsi_result[0] = TYPE_MOD;
+ scsi_result[1] |= 0x80; /* removable */
+ }
+ }
+
+
memcpy(SDpnt->vendor, scsi_result + 8, 8);
memcpy(SDpnt->model, scsi_result + 16, 16);
memcpy(SDpnt->rev, scsi_result + 32, 4);
*/
SDpnt->disconnect = 0;
- /*
- * Get any flags for this device.
- */
- bflags = get_device_flags(scsi_result);
/*
* Set the tagged_queue flag for SCSI-II devices that purport to support
scsi_cmd[5] = 0;
SCpnt->cmd_len = 0;
scsi_wait_cmd (SCpnt, (void *) scsi_cmd,
- (void *) scsi_result, 0x2a,
- scan_scsis_done, SCSI_TIMEOUT, 3);
+ (void *) scsi_result, 0x2a,
+ scan_scsis_done, SCSI_TIMEOUT, 3);
}
/*
* Detach the command from the device. It was just a temporary to be used while
*max_dev_lun = 5;
return 1;
}
+
+ /*
+ * If this device is Ghosted, scan upto two luns. (It physically only
+ * has one). -- REW
+ */
+ if (bflags & BLIST_GHOST) {
+ *max_dev_lun = 2;
+ return 1;
+ }
+
+
/*
* We assume the device can't handle lun!=0 if: - it reports scsi-0 (ANSI
* SCSI Revision 0) (old drives like MAXTOR XT-3280) or - it reports scsi-1
instance->max_id = np->maxwide ? 16 : 8;
instance->max_lun = MAX_LUN;
#ifndef NCR_IOMAPPED
- instance->base = np->reg;
+ instance->base = (unsigned long)np->reg;
#endif
instance->irq = np->irq;
instance->unique_id = np->base_io;
#include <linux/version.h>
#include <linux/init.h>
#include <asm/irq.h>
-
-#if LINUX_VERSION_CODE >= 0x010300
#include <linux/blk.h>
-#else
-#include "../block/blk.h"
-#endif
#include "scsi.h"
#include "hosts.h"
-#if LINUX_VERSION_CODE >= 0x010300
int wd33c93_reset(Scsi_Cmnd *SCpnt, unsigned int reset_flags)
-#else
-int wd33c93_reset(Scsi_Cmnd *SCpnt)
-#endif
{
struct Scsi_Host *instance;
struct WD33C93_hostdata *hostdata;
int wd33c93_queuecommand (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
void wd33c93_intr (struct Scsi_Host *instance);
int wd33c93_proc_info(char *, char **, off_t, int, int, int);
-
-#if LINUX_VERSION_CODE >= 0x010300
int wd33c93_reset (Scsi_Cmnd *, unsigned int);
-#else
-int wd33c93_reset (Scsi_Cmnd *);
-#endif
#endif /* WD33C93_H */
switch (dev & 0x0f) {
case SND_DEV_STATUS:
ret = sndstat_file_read(file, buf, count, ppos);
+ break;
#ifdef CONFIG_AUDIO
case SND_DEV_DSP:
return -1;
}
- interface = &dev->actconfig->interface[ifnum];
+ interface = dev->actconfig->interface + ifnum;
if (usb_interface_claimed(interface))
return -1;
for (ifnum = 0; ifnum < dev->actconfig->bNumInterfaces; ifnum++) {
/* if this interface hasn't already been claimed */
- if (!usb_interface_claimed(dev->actconfig->interface)) {
+ if (!usb_interface_claimed(dev->actconfig->interface + ifnum)) {
if (usb_find_interface_driver(dev, ifnum))
rejected++;
}
* support up to 1024x768.
*
*/
+#include <linux/tty.h>
#include <linux/fb.h>
int fbmon_valid_timings(u_int pixclock, u_int htotal, u_int vtotal,
int fbmon_dpms(const struct fb_info *fb_info)
{
- return fb_info->monspecs->dpms;
+ return fb_info->monspecs.dpms;
}
static void tgafb_set_disp(const void *fb_par, struct display *disp,
struct fb_info_gen *info)
{
- disp->screen_base = ioremap(fb_info.tga_fb_base);
+ disp->screen_base = ioremap(fb_info.tga_fb_base, 0);
switch (fb_info.tga_type) {
#ifdef FBCON_HAS_CFB8
case 0: /* 8-plane */
unregister_binfmt(&aout_format);
}
-module_init(init_aout_binfmt)
-module_exit(exit_aout_binfmt)
+EXPORT_NO_SYMBOLS;
+
+module_init(init_aout_binfmt);
+module_exit(exit_aout_binfmt);
+
* 1997-08-09 removed extension stripping, locking cleanup
*/
-#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
EXPORT_NO_SYMBOLS;
-module_init(init_misc_binfmt)
-module_exit(exit_misc_binfmt)
+module_init(init_misc_binfmt);
+module_exit(exit_misc_binfmt);
NULL /* d_iput */
};
+#if 0 /* dead code */
#ifdef NFS_PARANOIA
/*
* Display all dentries holding the specified inode.
unhashed);
}
}
-#endif
+#endif /* NFS_PARANOIA */
+#endif /* 0 */
static struct dentry *nfs_lookup(struct inode *dir, struct dentry * dentry)
{
*
* Copyright (C) 1995, 1996 Olaf Kirch <okir@monad.swb.de>
* Portions Copyright (C) 1999 G. Allen Morris III <gam3@acm.org>
- * Extensive cleanup by Neil Brown <neilb@cse.unsw.edu.au> Southern-Spring 1999
+ * Extensive rewrite by Neil Brown <neilb@cse.unsw.edu.au> Southern-Spring 1999
*/
#include <linux/sched.h>
}
/*
- * Read a directory and return the name of the specified entry.
+ * Read a directory and return the name of the specified entry. i_sem is already down().
*/
static int get_ino_name(struct dentry *dentry, struct qstr *name, unsigned long ino)
{
buffer.sequence = 0;
while (1) {
int old_seq = buffer.sequence;
- down(&dir->i_sem);
error = file.f_op->readdir(&file, &buffer, filldir_one);
- up(&dir->i_sem);
if (error < 0)
break;
/* this should be provided by each filesystem in an nfsd_operations interface as
* iget isn't really the right interface
*/
-static inline struct dentry *nfsd_iget(struct super_block *sb, unsigned long ino, __u32 generation)
+static struct dentry *nfsd_iget(struct super_block *sb, unsigned long ino, __u32 generation)
{
/* iget isn't really right if the inode is currently unallocated!!
* it is well connected. But nobody returns different dentrys do they?
*/
pdentry = child->d_inode->i_op->lookup(child->d_inode, tdentry);
+ d_drop(tdentry); /* we never want ".." hashed */
if (!pdentry) {
/* I don't want to return a ".." dentry.
* I would prefer to return an unconnected "IS_ROOT" dentry,
if (pdentry == NULL)
pdentry = ERR_PTR(-ENOMEM);
}
- dput(tdentry); /* it was never rehashed, it will be discarded */
+ dput(tdentry); /* it is not hashed, it will be discarded */
return pdentry;
}
+static struct dentry *splice(struct dentry *child, struct dentry *parent)
+{
+ int err = 0;
+ struct qstr qs;
+ char namebuf[256];
+ struct list_head *lp;
+ struct dentry *tmp;
+ /* child is an IS_ROOT (anonymous) dentry, but it is hypothesised that
+ * it should be a child of parent.
+ * We see if we can find a name and, if we can - splice it in.
+ * We hold the i_sem on the parent the whole time to try to follow locking protocols.
+ */
+ qs.name = namebuf;
+ down(&parent->d_inode->i_sem);
+
+ /* Now, things might have changed while we waited.
+ * Possibly a friendly filesystem found child and spliced it in in response
+ * to a lookup (though nobody does this yet). In this case, just succeed.
+ */
+ if (child->d_parent == parent) goto out;
+ /* Possibly a new dentry has been made for this child->d_inode in parent by
+ * a lookup. In this case return that dentry. caller must notice and act accordingly
+ */
+ for (lp = child->d_inode->i_dentry.next; lp != &child->d_inode->i_dentry ; lp=lp->next) {
+ tmp = list_entry(lp,struct dentry, d_alias);
+ if (tmp->d_parent == parent) {
+ child = dget(tmp);
+ goto out;
+ }
+ }
+ /* well, if we can find a name for child in parent, it should be safe to splice it in */
+ err = get_ino_name(parent, &qs, child->d_inode->i_ino);
+ if (err)
+ goto out;
+ tmp = d_lookup(parent, &qs);
+ if (tmp) {
+ /* Now that IS odd. I wonder what it means... */
+ err = -EEXIST;
+ printk("nfsd-fh: found a name that I didn't expect: %s/%s\n", parent->d_name.name, qs.name);
+ dput(tmp);
+ goto out;
+ }
+ err = d_splice(child, parent, &qs);
+ dprintk("nfsd_fh: found name %s for ino %ld\n", child->d_name.name, child->d_inode->i_ino);
+ out:
+ up(&parent->d_inode->i_sem);
+ if (err)
+ return ERR_PTR(err);
+ else
+ return child;
+}
+
/*
* This is the basic lookup mechanism for turning an NFS file handle
* into a dentry.
find_fh_dentry(struct super_block *sb, struct knfs_fh *fh, int needpath)
{
struct dentry *dentry, *result = NULL;
- struct qstr qs;
- char namebuf[256];
+ struct dentry *tmp;
int found =0;
u32 err;
+ /* This semaphore is needed to make sure that only one unconnected (free)
+ * dcache path ever exists, as otherwise two partial paths might get
+ * joined together, which would be very confusing.
+ * If there is ever an unconnected non-root directory, then this lock
+ * must be held. This could sensibly be per-filesystem.
+ */
+ static DECLARE_MUTEX(free_path_sem);
- qs.name = namebuf;
+ nfsdstats.fh_lookup++;
/*
* Attempt to find the inode.
*/
+ retry:
result = nfsd_iget(sb, fh->fh_ino, fh->fh_generation);
err = PTR_ERR(result);
if (IS_ERR(result))
if (!IS_ROOT(result) || result->d_inode->i_sb->s_root ==result)
return result;
- /* result is now a "root" dentry, which may be adequate as it stands, or else
+ /* result is now an anonymous dentry, which may be adequate as it stands, or else
* will get spliced into the dcache tree */
if (!S_ISDIR(result->d_inode->i_mode) && ! needpath) {
+ nfsdstats.fh_anon++;
return result;
}
* location in the tree.
*/
dprintk("nfs_fh: need to look harder for %d/%d\n",sb->s_dev,fh->fh_ino);
+ down(&free_path_sem);
found = 0;
if (!S_ISDIR(result->d_inode->i_mode)) {
+ nfsdstats.fh_nocache_nondir++;
if (fh->fh_dirino == 0)
goto err_result; /* don't know how to find parent */
else {
}
if (!IS_ROOT(dentry) || dentry->d_inode->i_sb->s_root ==dentry)
found = 1;
- err = get_ino_name(dentry, &qs, result->d_inode->i_ino);
- if (err)
- goto err_dentry;
-
- /* OK, we have the name in parent of inode, lets fill in the dentry */
- err = d_splice(result, dentry, &qs);
- if (err)
+ tmp = splice(result, dentry);
+ err = PTR_ERR(tmp);
+ if (IS_ERR(tmp))
goto err_dentry;
+ if (tmp != result) {
+ /* it is safe to just use tmp instead, but we must discard result first */
+ d_drop(result);
+ dput(result);
+ result = tmp;
+ /* If !found, then this is really wierd, but it shouldn't hurt */
+ }
}
- }
- else
+ } else {
+ nfsdstats.fh_nocache_dir++;
dentry = dget(result);
+ }
while(!found) {
/* LOOP INVARIANT */
- /* haven't found a place in the tree yet, but we do have a path
+ /* haven't found a place in the tree yet, but we do have a free path
* from dentry down to result, and dentry is a directory.
* Have a hold on dentry and result */
struct dentry *pdentry;
if (!IS_ROOT(pdentry) || parent->i_sb->s_root == pdentry)
found = 1;
- err = get_ino_name(pdentry, &qs, dentry->d_inode->i_ino);
- if (err) {
+ tmp = splice(dentry, pdentry);
+ if (tmp != dentry) {
+ /* Something wrong. We need to drop thw whole dentry->result path
+ * whatever it was
+ */
+ struct dentry *d;
+ for (d=result ; d ; d=(d->d_parent == d)?NULL:d->d_parent)
+ d_drop(d);
+ }
+ if (IS_ERR(tmp)) {
+ err = PTR_ERR(tmp);
dput(pdentry);
goto err_dentry;
}
- err = d_splice(dentry, pdentry, &qs);
- dprintk("nfsd_fh: found name %s for ino %ld\n", dentry->d_name.name, dentry->d_inode->i_ino);
+ if (tmp != dentry) {
+ /* we lost a race, try again
+ */
+ dput(tmp);
+ dput(dentry);
+ dput(result); /* this will discard the whole free path, so we can up the semaphore */
+ up(&free_path_sem);
+ goto retry;
+ }
dput(dentry);
dentry = pdentry;
}
dput(dentry);
+ up(&free_path_sem);
return result;
err_dentry:
dput(dentry);
err_result:
dput(result);
+ up(&free_path_sem);
err_out:
if (err == -ESTALE)
nfsdstats.fh_stale++;
if (nfserr)
goto done;
inode = newfhp->fh_dentry->d_inode;
+ if (inode && newfhp->fh_handle.fh_ino == 0)
+ /* inode might have been instantiated while we slept */
+ fh_update(newfhp);
/* Unfudge the mode bits */
if (attr->ia_valid & ATTR_MODE) {
nfsdstats.rchits,
nfsdstats.rcmisses,
nfsdstats.rcnocache,
- nfsdstats.fh_cached,
- nfsdstats.fh_valid,
- nfsdstats.fh_fixup,
+ nfsdstats.fh_stale,
nfsdstats.fh_lookup,
- nfsdstats.fh_stale);
+ nfsdstats.fh_anon,
+ nfsdstats.fh_nocache_dir,
+ nfsdstats.fh_nocache_nondir);
+
/* Assume we haven't hit EOF yet. Will be set by svc_proc_read. */
*eof = 0;
/* Seeks are not allowed on pipes. */
ret = -ESPIPE;
+ read = 0;
if (ppos != &filp->f_pos)
goto out_nolock;
goto out_nolock;
if (PIPE_EMPTY(*inode)) {
+do_more_read:
ret = 0;
if (!PIPE_WRITERS(*inode))
goto out;
goto out;
for (;;) {
+ PIPE_WAITING_READERS(*inode)++;
pipe_wait(inode);
+ PIPE_WAITING_READERS(*inode)--;
ret = -ERESTARTSYS;
if (signal_pending(current))
goto out_nolock;
/* Read what data is available. */
ret = -EFAULT;
- read = 0;
while (count > 0 && (size = PIPE_LEN(*inode))) {
char *pipebuf = PIPE_BASE(*inode) + PIPE_START(*inode);
ssize_t chars = PIPE_MAX_RCHUNK(*inode);
if (!PIPE_LEN(*inode))
PIPE_START(*inode) = 0;
- /* Signal writers there is more room. */
+ if (count && PIPE_WAITING_WRITERS(*inode) && !(filp->f_flags & O_NONBLOCK)) {
+ /*
+ * We know that we are going to sleep: signal
+ * writers synchronously that there is more
+ * room.
+ */
+ wake_up_interruptible_sync(PIPE_WAIT(*inode));
+ if (!PIPE_EMPTY(*inode))
+ BUG();
+ goto do_more_read;
+ }
+ /* Signal writers asynchronously that there is more room. */
wake_up_interruptible(PIPE_WAIT(*inode));
- if (read)
- UPDATE_ATIME(inode);
ret = read;
-
out:
up(PIPE_SEM(*inode));
out_nolock:
+ if (read)
+ ret = read;
return ret;
}
/* Seeks are not allowed on pipes. */
ret = -ESPIPE;
+ written = 0;
if (ppos != &filp->f_pos)
goto out_nolock;
if (down_interruptible(PIPE_SEM(*inode)))
goto out_nolock;
+do_more_write:
/* No readers yields SIGPIPE. */
if (!PIPE_READERS(*inode))
goto sigpipe;
/* If count <= PIPE_BUF, we have to make it atomic. */
free = (count <= PIPE_BUF ? count : 1);
- written = 0;
/* Wait, or check for, available space. */
if (filp->f_flags & O_NONBLOCK) {
goto out;
} else {
while (PIPE_FREE(*inode) < free) {
+ PIPE_WAITING_WRITERS(*inode)++;
pipe_wait(inode);
+ PIPE_WAITING_WRITERS(*inode)--;
ret = -ERESTARTSYS;
if (signal_pending(current))
goto out_nolock;
break;
do {
- /* This should be a synchronous wake-up: don't do idle reschedules! */
- wake_up_interruptible(PIPE_WAIT(*inode));
+ /*
+ * Synchronous wake-up: it knows that this process
+ * is going to give up this CPU, so it doesnt have
+ * to do idle reschedules.
+ */
+ wake_up_interruptible_sync(PIPE_WAIT(*inode));
+ PIPE_WAITING_WRITERS(*inode)++;
pipe_wait(inode);
+ PIPE_WAITING_WRITERS(*inode)--;
if (signal_pending(current))
goto out_nolock;
if (down_interruptible(PIPE_SEM(*inode)))
ret = -EFAULT;
}
- /* Signal readers there is more data. */
+ if (count && PIPE_WAITING_READERS(*inode) &&
+ !(filp->f_flags & O_NONBLOCK)) {
+ wake_up_interruptible_sync(PIPE_WAIT(*inode));
+ goto do_more_write;
+ }
+ /* Signal readers asynchronously that there is more data. */
wake_up_interruptible(PIPE_WAIT(*inode));
- ret = (written ? written : -EAGAIN);
inode->i_ctime = inode->i_mtime = CURRENT_TIME;
mark_inode_dirty(inode);
out:
up(PIPE_SEM(*inode));
out_nolock:
+ if (written)
+ ret = written;
return ret;
sigpipe:
+ if (written)
+ goto out;
up(PIPE_SEM(*inode));
send_sig(SIGPIPE, current, 0);
return -EPIPE;
PIPE_BASE(*inode) = (char *) page;
PIPE_START(*inode) = PIPE_LEN(*inode) = 0;
PIPE_READERS(*inode) = PIPE_WRITERS(*inode) = 1;
+ PIPE_WAITING_READERS(*inode) = PIPE_WAITING_WRITERS(*inode) = 0;
/*
* Mark the inode dirty from the very beginning,
extern int get_exec_domain_list(char *);
extern int get_irq_list(char *);
extern int get_dma_list(char *);
-extern int get_rtc_status (char *);
extern int get_locks_status (char *, char **, off_t, int);
extern int get_swaparea_info (char *);
#ifdef CONFIG_SGI_DS1286
return len;
}
-#ifdef CONFIG_RTC
-static int rtc_read_proc(char *page, char **start, off_t off,
- int count, int *eof, void *data)
-{
- int len = get_rtc_status(page);
- if (len <= off+count) *eof = 1;
- *start = page + off;
- len -= off;
- if (len>count) len = count;
- if (len<0) len = 0;
- return len;
-}
-#endif
-
#ifdef CONFIG_SGI_DS1286
static int ds1286_read_proc(char *page, char **start, off_t off,
int count, int *eof, void *data)
{"dma", dma_read_proc},
{"ioports", ioports_read_proc},
{"cmdline", cmdline_read_proc},
-#ifdef CONFIG_RTC
- {"rtc", rtc_read_proc},
-#endif
#ifdef CONFIG_SGI_DS1286
{"rtc", ds1286_read_proc},
#endif
#define TSUNAMI_IO_BIAS TSUNAMI_IO(0)
#define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0)
+/* The IO address space is larger than 0xffff */
+#define TSUNAMI_IO_SPACE (TSUNAMI_CONF(0) - TSUNAMI_IO(0))
+#define TSUNAMI_MEM_SPACE (_TSUNAMI_IACK_SC(0) - TSUNAMI_MEM(0))
/*
* Data structure for handling TSUNAMI machine checks:
*/
#define do_div(n,base) ({ \
int __res; \
- __res = ((unsigned long) n) % (unsigned) base; \
- n = ((unsigned long) n) / (unsigned) base; \
+ __res = ((unsigned long) (n)) % (unsigned) (base); \
+ (n) = ((unsigned long) (n)) / (unsigned) (base); \
__res; })
#endif
void (*device_interrupt)(unsigned long vector, struct pt_regs *regs);
void (*machine_check)(u64 vector, u64 la, struct pt_regs *regs);
- void (*init_arch)(unsigned long *, unsigned long *);
+ void (*init_arch)(void);
void (*init_irq)(void);
void (*init_pit)(void);
void (*init_pci)(void);
* results in clearer kernel profiles as we see _who_ is
* doing page clearing or copying.
*/
-static inline void clear_page(unsigned long page)
+static inline void clear_page(void * page)
{
unsigned long count = PAGE_SIZE/64;
unsigned long *ptr = (unsigned long *)page;
} while (count);
}
-static inline void copy_page(unsigned long _to, unsigned long _from)
+static inline void copy_page(void * _to, void * _from)
{
unsigned long count = PAGE_SIZE/64;
unsigned long *to = (unsigned long *)_to;
#endif /* STRICT_MM_TYPECHECKS */
+#if 0
#define BUG() __asm__ __volatile__("call_pal 129 # bugchk")
+#else
+/* hack to see the BUG() information in the early boot stage */
+#define BUG() \
+do { \
+ SRM_printf("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ halt(); \
+} while(0)
+#endif
#define PAGE_BUG(page) BUG()
#endif /* !ASSEMBLY */
--- /dev/null
+#ifndef _ALPHA_PGALLOC_H
+#define _ALPHA_PGALLOC_H
+
+#include <linux/config.h>
+
+/* Caches aren't brain-dead on the Alpha. */
+#define flush_cache_all() do { } while (0)
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_range(mm, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_page_to_ram(page) do { } while (0)
+#define flush_icache_range(start, end) do { } while (0)
+
+/*
+ * Use a few helper functions to hide the ugly broken ASN
+ * numbers on early Alphas (ev4 and ev45)
+ */
+
+#ifndef __EXTERN_INLINE
+#define __EXTERN_INLINE extern inline
+#define __MMU_EXTERN_INLINE
+#endif
+
+__EXTERN_INLINE void
+ev4_flush_tlb_current(struct mm_struct *mm)
+{
+ tbiap();
+}
+
+__EXTERN_INLINE void
+ev4_flush_tlb_other(struct mm_struct *mm)
+{
+}
+
+extern void ev5_flush_tlb_current(struct mm_struct *mm);
+
+__EXTERN_INLINE void
+ev5_flush_tlb_other(struct mm_struct *mm)
+{
+ mm->context = 0;
+}
+
+/*
+ * Flush just one page in the current TLB set.
+ * We need to be very careful about the icache here, there
+ * is no way to invalidate a specific icache page..
+ */
+
+__EXTERN_INLINE void
+ev4_flush_tlb_current_page(struct mm_struct * mm,
+ struct vm_area_struct *vma,
+ unsigned long addr)
+{
+ tbi(2 + ((vma->vm_flags & VM_EXEC) != 0), addr);
+}
+
+__EXTERN_INLINE void
+ev5_flush_tlb_current_page(struct mm_struct * mm,
+ struct vm_area_struct *vma,
+ unsigned long addr)
+{
+ if (vma->vm_flags & VM_EXEC)
+ ev5_flush_tlb_current(mm);
+ else
+ tbi(2, addr);
+}
+
+
+#ifdef CONFIG_ALPHA_GENERIC
+# define flush_tlb_current alpha_mv.mv_flush_tlb_current
+# define flush_tlb_other alpha_mv.mv_flush_tlb_other
+# define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page
+#else
+# ifdef CONFIG_ALPHA_EV4
+# define flush_tlb_current ev4_flush_tlb_current
+# define flush_tlb_other ev4_flush_tlb_other
+# define flush_tlb_current_page ev4_flush_tlb_current_page
+# else
+# define flush_tlb_current ev5_flush_tlb_current
+# define flush_tlb_other ev5_flush_tlb_other
+# define flush_tlb_current_page ev5_flush_tlb_current_page
+# endif
+#endif
+
+#ifdef __MMU_EXTERN_INLINE
+#undef __EXTERN_INLINE
+#undef __MMU_EXTERN_INLINE
+#endif
+
+/*
+ * Flush current user mapping.
+ */
+static inline void flush_tlb(void)
+{
+ flush_tlb_current(current->mm);
+}
+
+#ifndef __SMP__
+/*
+ * Flush everything (kernel mapping may also have
+ * changed due to vmalloc/vfree)
+ */
+static inline void flush_tlb_all(void)
+{
+ tbia();
+}
+
+/*
+ * Flush a specified user mapping
+ */
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ if (mm != current->mm)
+ flush_tlb_other(mm);
+ else
+ flush_tlb_current(mm);
+}
+
+/*
+ * Page-granular tlb flush.
+ *
+ * do a tbisd (type = 2) normally, and a tbis (type = 3)
+ * if it is an executable mapping. We want to avoid the
+ * itlb flush, because that potentially also does a
+ * icache flush.
+ */
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long addr)
+{
+ struct mm_struct * mm = vma->vm_mm;
+
+ if (mm != current->mm)
+ flush_tlb_other(mm);
+ else
+ flush_tlb_current_page(mm, vma, addr);
+}
+
+/*
+ * Flush a specified range of user mapping: on the
+ * Alpha we flush the whole user tlb.
+ */
+static inline void flush_tlb_range(struct mm_struct *mm,
+ unsigned long start, unsigned long end)
+{
+ flush_tlb_mm(mm);
+}
+
+#else /* __SMP__ */
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *);
+extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void flush_tlb_range(struct mm_struct *, unsigned long, unsigned long);
+
+#endif /* __SMP__ */
+
+/*
+ * Allocate and free page tables. The xxx_kernel() versions are
+ * used to allocate a kernel page table - this turns on ASN bits
+ * if any.
+ */
+#ifndef __SMP__
+extern struct pgtable_cache_struct {
+ unsigned long *pgd_cache;
+ unsigned long *pte_cache;
+ unsigned long pgtable_cache_sz;
+} quicklists;
+#else
+#include <asm/smp.h>
+#define quicklists cpu_data[smp_processor_id()]
+#endif
+#define pgd_quicklist (quicklists.pgd_cache)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist (quicklists.pte_cache)
+#define pgtable_cache_size (quicklists.pgtable_cache_sz)
+
+extern __inline__ pgd_t *get_pgd_slow(void)
+{
+ pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init;
+
+ if (ret) {
+ init = pgd_offset(&init_mm, 0UL);
+ memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
+ memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+ (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+
+ pgd_val(ret[PTRS_PER_PGD])
+ = pte_val(mk_pte(mem_map + MAP_NR(ret), PAGE_KERNEL));
+ }
+ return ret;
+}
+
+extern __inline__ pgd_t *get_pgd_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = pgd_quicklist) != NULL) {
+ pgd_quicklist = (unsigned long *)(*ret);
+ ret[0] = ret[1];
+ pgtable_cache_size--;
+ } else
+ ret = (unsigned long *)get_pgd_slow();
+ return (pgd_t *)ret;
+}
+
+extern __inline__ void free_pgd_fast(pgd_t *pgd)
+{
+ *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
+ pgd_quicklist = (unsigned long *) pgd;
+ pgtable_cache_size++;
+}
+
+extern __inline__ void free_pgd_slow(pgd_t *pgd)
+{
+ free_page((unsigned long)pgd);
+}
+
+extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long address_premasked);
+
+extern __inline__ pmd_t *get_pmd_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = (unsigned long *)pte_quicklist) != NULL) {
+ pte_quicklist = (unsigned long *)(*ret);
+ ret[0] = ret[1];
+ pgtable_cache_size--;
+ }
+ return (pmd_t *)ret;
+}
+
+extern __inline__ void free_pmd_fast(pmd_t *pmd)
+{
+ *(unsigned long *)pmd = (unsigned long) pte_quicklist;
+ pte_quicklist = (unsigned long *) pmd;
+ pgtable_cache_size++;
+}
+
+extern __inline__ void free_pmd_slow(pmd_t *pmd)
+{
+ free_page((unsigned long)pmd);
+}
+
+extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
+
+extern __inline__ pte_t *get_pte_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = (unsigned long *)pte_quicklist) != NULL) {
+ pte_quicklist = (unsigned long *)(*ret);
+ ret[0] = ret[1];
+ pgtable_cache_size--;
+ }
+ return (pte_t *)ret;
+}
+
+extern __inline__ void free_pte_fast(pte_t *pte)
+{
+ *(unsigned long *)pte = (unsigned long) pte_quicklist;
+ pte_quicklist = (unsigned long *) pte;
+ pgtable_cache_size++;
+}
+
+extern __inline__ void free_pte_slow(pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+
+extern void __bad_pte(pmd_t *pmd);
+extern void __bad_pmd(pgd_t *pgd);
+
+#define pte_free_kernel(pte) free_pte_fast(pte)
+#define pte_free(pte) free_pte_fast(pte)
+#define pmd_free_kernel(pmd) free_pmd_fast(pmd)
+#define pmd_free(pmd) free_pmd_fast(pmd)
+#define pgd_free(pgd) free_pgd_fast(pgd)
+#define pgd_alloc() get_pgd_fast()
+
+extern inline pte_t * pte_alloc(pmd_t *pmd, unsigned long address)
+{
+ address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+ if (pmd_none(*pmd)) {
+ pte_t *page = get_pte_fast();
+
+ if (!page)
+ return get_pte_slow(pmd, address);
+ pmd_set(pmd, page);
+ return page + address;
+ }
+ if (pmd_bad(*pmd)) {
+ __bad_pte(pmd);
+ return NULL;
+ }
+ return (pte_t *) pmd_page(*pmd) + address;
+}
+
+extern inline pmd_t * pmd_alloc(pgd_t *pgd, unsigned long address)
+{
+ address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
+ if (pgd_none(*pgd)) {
+ pmd_t *page = get_pmd_fast();
+
+ if (!page)
+ return get_pmd_slow(pgd, address);
+ pgd_set(pgd, page);
+ return page + address;
+ }
+ if (pgd_bad(*pgd)) {
+ __bad_pmd(pgd);
+ return NULL;
+ }
+ return (pmd_t *) pgd_page(*pgd) + address;
+}
+
+#define pte_alloc_kernel pte_alloc
+#define pmd_alloc_kernel pmd_alloc
+
+extern int do_check_pgt_cache(int, int);
+
+extern inline void set_pgdir(unsigned long address, pgd_t entry)
+{
+ struct task_struct * p;
+ pgd_t *pgd;
+
+ read_lock(&tasklist_lock);
+ for_each_task(p) {
+ if (!p->mm)
+ continue;
+ *pgd_offset(p->mm,address) = entry;
+ }
+ read_unlock(&tasklist_lock);
+ for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+ pgd[(address >> PGDIR_SHIFT) & (PTRS_PER_PAGE - 1)] = entry;
+}
+
+#endif /* _ALPHA_PGALLOC_H */
* in <asm/page.h> (currently 8192).
*/
#include <linux/config.h>
-#include <linux/spinlock.h> /* For the task lock */
-#include <asm/system.h>
+#include <asm/page.h>
#include <asm/processor.h> /* For TASK_SIZE */
-#include <asm/mmu_context.h>
#include <asm/machvec.h>
-
-/* Caches aren't brain-dead on the Alpha. */
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_range(mm, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr) do { } while (0)
-#define flush_page_to_ram(page) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-
-/*
- * Use a few helper functions to hide the ugly broken ASN
- * numbers on early Alphas (ev4 and ev45)
- */
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __MMU_EXTERN_INLINE
-#endif
-
-__EXTERN_INLINE void
-ev4_flush_tlb_current(struct mm_struct *mm)
-{
- tbiap();
-}
-
-__EXTERN_INLINE void
-ev4_flush_tlb_other(struct mm_struct *mm)
-{
-}
-
-extern void ev5_flush_tlb_current(struct mm_struct *mm);
-
-__EXTERN_INLINE void
-ev5_flush_tlb_other(struct mm_struct *mm)
-{
- mm->context = 0;
-}
-
-/*
- * Flush just one page in the current TLB set.
- * We need to be very careful about the icache here, there
- * is no way to invalidate a specific icache page..
- */
-
-__EXTERN_INLINE void
-ev4_flush_tlb_current_page(struct mm_struct * mm,
- struct vm_area_struct *vma,
- unsigned long addr)
-{
- tbi(2 + ((vma->vm_flags & VM_EXEC) != 0), addr);
-}
-
-__EXTERN_INLINE void
-ev5_flush_tlb_current_page(struct mm_struct * mm,
- struct vm_area_struct *vma,
- unsigned long addr)
-{
- if (vma->vm_flags & VM_EXEC)
- ev5_flush_tlb_current(mm);
- else
- tbi(2, addr);
-}
-
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define flush_tlb_current alpha_mv.mv_flush_tlb_current
-# define flush_tlb_other alpha_mv.mv_flush_tlb_other
-# define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page
-#else
-# ifdef CONFIG_ALPHA_EV4
-# define flush_tlb_current ev4_flush_tlb_current
-# define flush_tlb_other ev4_flush_tlb_other
-# define flush_tlb_current_page ev4_flush_tlb_current_page
-# else
-# define flush_tlb_current ev5_flush_tlb_current
-# define flush_tlb_other ev5_flush_tlb_other
-# define flush_tlb_current_page ev5_flush_tlb_current_page
-# endif
-#endif
-
-#ifdef __MMU_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __MMU_EXTERN_INLINE
-#endif
-
-/*
- * Flush current user mapping.
- */
-static inline void flush_tlb(void)
-{
- flush_tlb_current(current->mm);
-}
-
-#ifndef __SMP__
-/*
- * Flush everything (kernel mapping may also have
- * changed due to vmalloc/vfree)
- */
-static inline void flush_tlb_all(void)
-{
- tbia();
-}
-
-/*
- * Flush a specified user mapping
- */
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
- if (mm != current->mm)
- flush_tlb_other(mm);
- else
- flush_tlb_current(mm);
-}
-
-/*
- * Page-granular tlb flush.
- *
- * do a tbisd (type = 2) normally, and a tbis (type = 3)
- * if it is an executable mapping. We want to avoid the
- * itlb flush, because that potentially also does a
- * icache flush.
- */
-static inline void flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr)
-{
- struct mm_struct * mm = vma->vm_mm;
-
- if (mm != current->mm)
- flush_tlb_other(mm);
- else
- flush_tlb_current_page(mm, vma, addr);
-}
-
-/*
- * Flush a specified range of user mapping: on the
- * Alpha we flush the whole user tlb.
- */
-static inline void flush_tlb_range(struct mm_struct *mm,
- unsigned long start, unsigned long end)
-{
- flush_tlb_mm(mm);
-}
-
-#else /* __SMP__ */
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void flush_tlb_range(struct mm_struct *, unsigned long, unsigned long);
-
-#endif /* __SMP__ */
-
/* Certain architectures need to do special things when PTEs
* within a page table are directly modified. Thus, the following
* hook is made available.
#define BAD_PAGETABLE __bad_pagetable()
#define BAD_PAGE __bad_page()
-#define ZERO_PAGE(vaddr) (PAGE_OFFSET+0x30A000)
+#define ZERO_PAGE(vaddr) (mem_map + MAP_NR(ZERO_PGE))
/* number of bits that fit into a memory pointer */
#define BITS_PER_PTR (8*sizeof(unsigned long))
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
-extern inline pte_t mk_pte(unsigned long page, pgprot_t pgprot)
-{ pte_t pte; pte_val(pte) = ((page-PAGE_OFFSET) << (32-PAGE_SHIFT)) | pgprot_val(pgprot); return pte; }
+#define mk_pte(page, pgprot) \
+({ \
+ pte_t pte; \
+ \
+ pte_val(pte) = ((unsigned long)(page - mem_map) << 32) | \
+ pgprot_val(pgprot); \
+ pte; \
+})
extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
{ pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpage) << (32-PAGE_SHIFT)) | pgprot_val(pgprot); return pte; }
extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
{ pgd_val(*pgdp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
-extern inline unsigned long pte_page(pte_t pte)
-{ return PAGE_OFFSET + ((pte_val(pte) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
+#define pte_pagenr(x) ((unsigned long)((pte_val(x) >> 32)))
+#define pte_page(x) (mem_map+pte_pagenr(x))
extern inline unsigned long pmd_page(pmd_t pmd)
{ return PAGE_OFFSET + ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
extern inline int pgd_present(pgd_t pgd) { return pgd_val(pgd) & _PAGE_VALID; }
extern inline void pgd_clear(pgd_t * pgdp) { pgd_val(*pgdp) = 0; }
+#define page_address(page) ((page)->virtual)
+#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
+
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not..
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
/* to find an entry in a page-table-directory. */
-extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
-{
- return mm->pgd + ((address >> PGDIR_SHIFT) & (PTRS_PER_PAGE - 1));
-}
+#define __pgd_offset(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_offset(mm, address) ((mm)->pgd+__pgd_offset(address))
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
}
-/*
- * Allocate and free page tables. The xxx_kernel() versions are
- * used to allocate a kernel page table - this turns on ASN bits
- * if any.
- */
-#ifndef __SMP__
-extern struct pgtable_cache_struct {
- unsigned long *pgd_cache;
- unsigned long *pte_cache;
- unsigned long pgtable_cache_sz;
-} quicklists;
-#else
-#include <asm/smp.h>
-#define quicklists cpu_data[smp_processor_id()]
-#endif
-#define pgd_quicklist (quicklists.pgd_cache)
-#define pmd_quicklist ((unsigned long *)0)
-#define pte_quicklist (quicklists.pte_cache)
-#define pgtable_cache_size (quicklists.pgtable_cache_sz)
-
-extern __inline__ pgd_t *get_pgd_slow(void)
-{
- pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init;
-
- if (ret) {
- init = pgd_offset(&init_mm, 0);
- memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
- memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
- (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-
- pgd_val(ret[PTRS_PER_PGD])
- = pte_val(mk_pte((unsigned long)ret, PAGE_KERNEL));
- }
- return ret;
-}
-
-extern __inline__ pgd_t *get_pgd_fast(void)
-{
- unsigned long *ret;
-
- if((ret = pgd_quicklist) != NULL) {
- pgd_quicklist = (unsigned long *)(*ret);
- ret[0] = ret[1];
- pgtable_cache_size--;
- } else
- ret = (unsigned long *)get_pgd_slow();
- return (pgd_t *)ret;
-}
-
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
-{
- *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
- pgd_quicklist = (unsigned long *) pgd;
- pgtable_cache_size++;
-}
-
-extern __inline__ void free_pgd_slow(pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long address_premasked);
-
-extern __inline__ pmd_t *get_pmd_fast(void)
-{
- unsigned long *ret;
-
- if((ret = (unsigned long *)pte_quicklist) != NULL) {
- pte_quicklist = (unsigned long *)(*ret);
- ret[0] = ret[1];
- pgtable_cache_size--;
- }
- return (pmd_t *)ret;
-}
-
-extern __inline__ void free_pmd_fast(pmd_t *pmd)
-{
- *(unsigned long *)pmd = (unsigned long) pte_quicklist;
- pte_quicklist = (unsigned long *) pmd;
- pgtable_cache_size++;
-}
-
-extern __inline__ void free_pmd_slow(pmd_t *pmd)
-{
- free_page((unsigned long)pmd);
-}
-
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
-
-extern __inline__ pte_t *get_pte_fast(void)
-{
- unsigned long *ret;
-
- if((ret = (unsigned long *)pte_quicklist) != NULL) {
- pte_quicklist = (unsigned long *)(*ret);
- ret[0] = ret[1];
- pgtable_cache_size--;
- }
- return (pte_t *)ret;
-}
-
-extern __inline__ void free_pte_fast(pte_t *pte)
-{
- *(unsigned long *)pte = (unsigned long) pte_quicklist;
- pte_quicklist = (unsigned long *) pte;
- pgtable_cache_size++;
-}
-
-extern __inline__ void free_pte_slow(pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-extern void __bad_pte(pmd_t *pmd);
-extern void __bad_pmd(pgd_t *pgd);
-
-#define pte_free_kernel(pte) free_pte_fast(pte)
-#define pte_free(pte) free_pte_fast(pte)
-#define pmd_free_kernel(pmd) free_pmd_fast(pmd)
-#define pmd_free(pmd) free_pmd_fast(pmd)
-#define pgd_free(pgd) free_pgd_fast(pgd)
-#define pgd_alloc() get_pgd_fast()
-
-extern inline pte_t * pte_alloc(pmd_t *pmd, unsigned long address)
-{
- address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
- if (pmd_none(*pmd)) {
- pte_t *page = get_pte_fast();
-
- if (!page)
- return get_pte_slow(pmd, address);
- pmd_set(pmd, page);
- return page + address;
- }
- if (pmd_bad(*pmd)) {
- __bad_pte(pmd);
- return NULL;
- }
- return (pte_t *) pmd_page(*pmd) + address;
-}
-
-extern inline pmd_t * pmd_alloc(pgd_t *pgd, unsigned long address)
-{
- address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
- if (pgd_none(*pgd)) {
- pmd_t *page = get_pmd_fast();
-
- if (!page)
- return get_pmd_slow(pgd, address);
- pgd_set(pgd, page);
- return page + address;
- }
- if (pgd_bad(*pgd)) {
- __bad_pmd(pgd);
- return NULL;
- }
- return (pmd_t *) pgd_page(*pgd) + address;
-}
-
-#define pte_alloc_kernel pte_alloc
-#define pmd_alloc_kernel pmd_alloc
-
-extern int do_check_pgt_cache(int, int);
-
-extern inline void set_pgdir(unsigned long address, pgd_t entry)
-{
- struct task_struct * p;
- pgd_t *pgd;
-
- read_lock(&tasklist_lock);
- for_each_task(p) {
- if (!p->mm)
- continue;
- *pgd_offset(p->mm,address) = entry;
- }
- read_unlock(&tasklist_lock);
- for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
- pgd[(address >> PGDIR_SHIFT) & (PTRS_PER_PAGE - 1)] = entry;
-}
-
extern pgd_t swapper_pg_dir[1024];
/*
extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
-#define SWP_TYPE(entry) (((entry) >> 32) & 0xff)
-#define SWP_OFFSET(entry) ((entry) >> 40)
-#define SWP_ENTRY(type,offset) pte_val(mk_swap_pte((type),(offset)))
+#define SWP_TYPE(x) (((x).val >> 32) & 0xff)
+#define SWP_OFFSET(x) ((x).val >> 40)
+#define SWP_ENTRY(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
+#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define swp_entry_to_pte(x) ((pte_t) { (x).val })
#define module_map vmalloc
#define module_unmap vfree
#define kern_addr_valid(addr) (1)
#define io_remap_page_range(start, busaddr, size, prot) \
- remap_page_range(start, virt_to_phys(__ioremap(busaddr)), size, prot)
+ remap_page_range(start, virt_to_phys(__ioremap(busaddr), 0), size, prot)
+
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
#endif /* _ALPHA_PGTABLE_H */
((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#define tas(ptr) (xchg((ptr),1))
+/* Very dirty but nevertheless very fun hack ;). I recall the aboot printf()
+ that will in turn use the SRM console to do the debugging of the boot
+ process. As there's no runtime symbol table, the address of printf()
+ is hardwired and is in function of the bootlx binary you have in /boot...
+ 1999 Andrea Arcangeli <andrea@suse.de> */
+#if 0
+#define SRM_printf(args...) ({ int (*__SRM_printf)(const char *fmt, ...) = (int (*)(const char *fmt, ...)) 0x20000aa0; __SRM_printf(args); })
+#else
+#define SRM_printf(args...)
+#endif
+
#endif /* __ASSEMBLY__ */
#endif
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define RS_TABLE_SIZE 16
+
#if defined(CONFIG_ARCH_A5K)
/* UART CLK PORT IRQ FLAGS */
-#define SERIAL_PORT_DFNS \
+
+#define STD_SERIAL_PORT_DEFNS
{ 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \
- { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS3 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS5 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS6 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS7 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS8 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS9 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
+ { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */
-#elif defined(CONFIG_ARCH_ARC)
+#else
- /* UART CLK PORT IRQ FLAGS */
-#define SERIAL_PORT_DFNS \
+#define STD_SERIAL_PORT_DEFNS
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */
+
+#endif
+
+#define EXTRA_SERIAL_PORT_DEFNS \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS3 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
#endif
-#endif
--- /dev/null
+#define acornfb_valid_pixrate(rate) (rate >= 39325 && rate <= 40119)
+
+static inline void
+acornfb_vidc20_find_rates(struct vidc_timing *vidc,
+ struct fb_var_screeninfo *var)
+{
+ u_int bandwidth;
+
+ vidc->control |= VIDC20_CTRL_PIX_CK;
+
+ /* Calculate bandwidth */
+ bandwidth = var->pixclock * 8 / var->bits_per_pixel;
+
+ /* Encode bandwidth as VIDC20 setting */
+ if (bandwidth > 16667*2)
+ vidc->control |= VIDC20_CTRL_FIFO_16;
+ else if (bandwidth > 13333*2)
+ vidc->control |= VIDC20_CTRL_FIFO_20;
+ else if (bandwidth > 11111*2)
+ vidc->control |= VIDC20_CTRL_FIFO_24;
+ else
+ vidc->control |= VIDC20_CTRL_FIFO_28;
+
+ vidc->pll_ctl = 0x2020;
+}
+
+#ifdef CONFIG_CHRONTEL_7003
+#define acornfb_default_control() VIDC20_CTRL_PIX_HCLK
+#else
+#define acornfb_default_control() VIDC20_CTRL_PIX_VCLK
+#endif
+
+#define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/dma.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS 0xd0000000
+
+#define MAX_DMA_CHANNELS 1
+
+#define DMA_S0 0
+
+#endif /* _ASM_ARCH_DMA_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/hardware.h
+ *
+ * Copyright (C) 1996-1999 Russell King.
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * This file contains the hardware definitions of the
+ * CL7500 evaluation board.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/arch/memory.h>
+#include <asm/iomd.h>
+
+/*
+ * What hardware must be present
+ */
+#define HAS_IOMD
+#define HAS_VIDC20
+
+/* Hardware addresses of major areas.
+ * *_START is the physical address
+ * *_SIZE is the size of the region
+ * *_BASE is the virtual address
+ */
+
+#define IO_START 0x03000000 /* I/O */
+#define IO_SIZE 0x01000000
+#define IO_BASE 0xe0000000
+
+#define ISA_START 0x0c000000 /* ISA */
+#define ISA_SIZE 0x00010000
+#define ISA_BASE 0xe1000000
+
+#define FLASH_START 0x01000000 /* XXX */
+#define FLASH_SIZE 0x01000000
+#define FLASH_BASE 0xe2000000
+
+#define LED_START 0x0302B000
+#define LED_SIZE 0x00001000
+#define LED_BASE 0xe3000000
+#define LED_ADDRESS (LED_BASE + 0xa00)
+
+/* Let's define SCREEN_START for CL7500, even though it's a lie. */
+#define SCREEN_START 0x02000000 /* VRAM */
+#define SCREEN2_END 0xe0000000
+#define SCREEN2_BASE 0xd8000000
+#define SCREEN1_END 0xd8000000
+#define SCREEN1_BASE 0xd0000000
+
+#define FLUSH_BASE 0xdf000000
+
+
+#ifndef __ASSEMBLER__
+
+/*
+ * for use with inb/outb
+ */
+#define IO_VIDC_AUDIO_BASE 0x80140000
+#define IO_VIDC_BASE 0x80100000
+#define IO_IOMD_BASE 0x80080000
+#define IOC_BASE 0x80080000
+
+/*
+ * IO definitions
+ */
+#define EXPMASK_BASE ((volatile unsigned char *)0xe0360000)
+#define IOEB_BASE ((volatile unsigned char *)0xe0350050)
+#define PCIO_FLOPPYDMABASE ((volatile unsigned char *)0xe002a000)
+#define PCIO_BASE 0xe0010000
+
+/*
+ * RAM definitions
+ */
+#define GET_MEMORY_END(p) (PAGE_OFFSET + p->u1.s.page_size * \
+ (p->u1.s.pages_in_bank[0] + \
+ p->u1.s.pages_in_bank[1] + \
+ p->u1.s.pages_in_bank[2] + \
+ p->u1.s.pages_in_bank[3]))
+
+#define PARAMS_BASE 0
+
+#define FLUSH_BASE_PHYS 0x00000000 /* ROM */
+
+#else
+
+#define VIDC_SND_BASE 0xe0500000
+#define VIDC_BASE 0xe0400000
+#define IOMD_BASE 0xe0200000
+#define IOC_BASE 0xe0200000
+#define PCIO_FLOPPYDMABASE 0xe002a000
+#define PCIO_BASE 0xe0010000
+
+#endif
+#endif
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/ide.h
+ *
+ * Copyright (c) 1997 Russell King
+ *
+ * Modifications:
+ * 29-07-1998 RMK Major re-work of IDE architecture specific code
+ */
+#include <asm/irq.h>
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static __inline__ void
+ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int irq)
+{
+ ide_ioreg_t reg = (ide_ioreg_t) data_port;
+ int i;
+
+ memset(hw, 0, sizeof(*hw));
+
+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+ hw->io_ports[i] = reg;
+ reg += 1;
+ }
+ hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
+ hw->irq = irq;
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void
+ide_init_default_hwifs(void)
+{
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/io.h
+ * from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *
+ * Modifications:
+ * 06-Dec-1997 RMK Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/*
+ * This architecture does not require any delayed IO, and
+ * has the constant-optimised IO
+ */
+#undef ARCH_IO_DELAY
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses. PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
+ * and are translated to the start of IO. Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x) (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+extern __inline__ void __outb (unsigned int value, unsigned int port)
+{
+ unsigned long temp;
+ __asm__ __volatile__(
+ "tst %2, #0x80000000\n\t"
+ "mov %0, %4\n\t"
+ "addeq %0, %0, %3\n\t"
+ "strb %1, [%0, %2, lsl #2] @ outb"
+ : "=&r" (temp)
+ : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+ : "cc");
+}
+
+extern __inline__ void __outw (unsigned int value, unsigned int port)
+{
+ unsigned long temp;
+ __asm__ __volatile__(
+ "tst %2, #0x80000000\n\t"
+ "mov %0, %4\n\t"
+ "addeq %0, %0, %3\n\t"
+ "str %1, [%0, %2, lsl #2] @ outw"
+ : "=&r" (temp)
+ : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+ : "cc");
+}
+
+extern __inline__ void __outl (unsigned int value, unsigned int port)
+{
+ unsigned long temp;
+ __asm__ __volatile__(
+ "tst %2, #0x80000000\n\t"
+ "mov %0, %4\n\t"
+ "addeq %0, %0, %3\n\t"
+ "str %1, [%0, %2, lsl #2] @ outl"
+ : "=&r" (temp)
+ : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+ : "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
+extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \
+{ \
+ unsigned long temp, value; \
+ __asm__ __volatile__( \
+ "tst %2, #0x80000000\n\t" \
+ "mov %0, %4\n\t" \
+ "addeq %0, %0, %3\n\t" \
+ "ldr" ##instr## " %1, [%0, %2, lsl #2] @ in"###fnsuffix \
+ : "=&r" (temp), "=r" (value) \
+ : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
+ : "cc"); \
+ return (unsigned sz)value; \
+}
+
+extern __inline__ unsigned int __ioaddr (unsigned int port) \
+{ \
+ if (__PORT_PCIO(port)) \
+ return (unsigned int)(PCIO_BASE + (port << 2)); \
+ else \
+ return (unsigned int)(IO_BASE + (port << 2)); \
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr) \
+ DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(long,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port) \
+({ \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "strb %0, [%1, %2] @ outbc" \
+ : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "strb %0, [%1, %2] @ outbc" \
+ : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
+})
+
+#define __inbc(port) \
+({ \
+ unsigned char result; \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "ldrb %0, [%1, %2] @ inbc" \
+ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "ldrb %0, [%1, %2] @ inbc" \
+ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
+ result; \
+})
+
+#define __outwc(value,port) \
+({ \
+ unsigned long v = value; \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "str %0, [%1, %2] @ outwc" \
+ : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "str %0, [%1, %2] @ outwc" \
+ : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
+})
+
+#define __inwc(port) \
+({ \
+ unsigned short result; \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "ldr %0, [%1, %2] @ inwc" \
+ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "ldr %0, [%1, %2] @ inwc" \
+ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
+ result & 0xffff; \
+})
+
+#define __outlc(value,port) \
+({ \
+ unsigned long v = value; \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "str %0, [%1, %2] @ outlc" \
+ : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "str %0, [%1, %2] @ outlc" \
+ : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
+})
+
+#define __inlc(port) \
+({ \
+ unsigned long result; \
+ if (__PORT_PCIO((port))) \
+ __asm__ __volatile__( \
+ "ldr %0, [%1, %2] @ inlc" \
+ : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
+ else \
+ __asm__ __volatile__( \
+ "ldr %0, [%1, %2] @ inlc" \
+ : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
+ result; \
+})
+
+#define __ioaddrc(port) \
+ (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
+
+/*
+ * Translated address IO functions
+ *
+ * IO address has already been translated to a virtual address
+ */
+#define outb_t(v,p) \
+ (*(volatile unsigned char *)(p) = (v))
+
+#define inb_t(p) \
+ (*(volatile unsigned char *)(p))
+
+#define outl_t(v,p) \
+ (*(volatile unsigned long *)(p) = (v))
+
+#define inl_t(p) \
+ (*(volatile unsigned long *)(p))
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-cl7500/irq.h
+ *
+ * Copyright (C) 1996 Russell King
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * Changelog:
+ * 10-10-1996 RMK Brought up to date with arch-sa110eval
+ * 22-08-1998 RMK Restructured IRQ routines
+ * 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
+ */
+#include <asm/iomd.h>
+
+static inline int fixup_irq(unsigned int irq)
+{
+ if (irq == IRQ_ISA) {
+ int isabits = *((volatile unsigned int *)0xe002b700);
+ if (isabits == 0) {
+ printk("Spurious ISA IRQ!\n");
+ return irq;
+ }
+ irq = 40;
+ while (!(isabits & 1)) {
+ irq++;
+ isabits >>= 1;
+ }
+ }
+
+ return irq;
+}
+
+static void cl7500_mask_irq_ack_a(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]\n"
+" strb %1, [%3]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)),
+ "r" (ioaddr(IOMD_IRQCLRA)));
+}
+
+static void cl7500_mask_irq_a(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+}
+
+static void cl7500_unmask_irq_a(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+}
+
+static void cl7500_mask_irq_b(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+}
+
+static void cl7500_unmask_irq_b(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+}
+
+static void cl7500_mask_irq_c(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKC)));
+}
+
+static void cl7500_unmask_irq_c(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKC)));
+}
+
+
+static void cl7500_mask_irq_d(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKD)));
+}
+
+static void cl7500_unmask_irq_d(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKD)));
+}
+
+static void cl7500_mask_irq_dma(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+}
+
+static void cl7500_unmask_irq_dma(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+}
+
+static void cl7500_mask_irq_fiq(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" bic %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+}
+
+static void cl7500_unmask_irq_fiq(unsigned int irq)
+{
+ unsigned int temp;
+
+ __asm__ __volatile__(
+ "ldrb %0, [%2]\n"
+" orr %0, %0, %1\n"
+" strb %0, [%2]"
+ : "=&r" (temp)
+ : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+}
+
+static void no_action(int cpl, void *dev_id, struct pt_regs *regs)
+{
+}
+
+static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL };
+
+static __inline__ void irq_init_irq(void)
+{
+ extern void ecard_disableirq(unsigned int irq);
+ extern void ecard_enableirq(unsigned int irq);
+ int irq;
+
+ outb(0, IOMD_IRQMASKA);
+ outb(0, IOMD_IRQMASKB);
+ outb(0, IOMD_FIQMASK);
+ outb(0, IOMD_DMAMASK);
+
+ for (irq = 0; irq < NR_IRQS; irq++) {
+ switch (irq) {
+ case 0 ... 6:
+ irq_desc[irq].probe_ok = 1;
+ case 7:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_ack_a;
+ irq_desc[irq].mask = cl7500_mask_irq_a;
+ irq_desc[irq].unmask = cl7500_unmask_irq_a;
+ break;
+
+ case 9 ... 15:
+ irq_desc[irq].probe_ok = 1;
+ case 8:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_b;
+ irq_desc[irq].mask = cl7500_mask_irq_b;
+ irq_desc[irq].unmask = cl7500_unmask_irq_b;
+ break;
+
+ case 16 ... 22:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_dma;
+ irq_desc[irq].mask = cl7500_mask_irq_dma;
+ irq_desc[irq].unmask = cl7500_unmask_irq_dma;
+ break;
+
+ case 24 ... 31:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_c;
+ irq_desc[irq].mask = cl7500_mask_irq_c;
+ irq_desc[irq].unmask = cl7500_unmask_irq_c;
+ break;
+
+ case 32 ... 39:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_d;
+ irq_desc[irq].mask = cl7500_mask_irq_d;
+ irq_desc[irq].unmask = cl7500_unmask_irq_d;
+ break;
+
+ case 40 ... 47:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].probe_ok = 1;
+ irq_desc[irq].mask_ack = no_action;
+ irq_desc[irq].mask = no_action;
+ irq_desc[irq].unmask = no_action;
+ break;
+
+ case 64 ... 72:
+ irq_desc[irq].valid = 1;
+ irq_desc[irq].mask_ack = cl7500_mask_irq_fiq;
+ irq_desc[irq].mask = cl7500_mask_irq_fiq;
+ irq_desc[irq].unmask = cl7500_unmask_irq_fiq;
+ break;
+ }
+ }
+
+ setup_arm_irq(IRQ_ISA, &irq_isa);
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/irqs.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+#define IRQ_INT2 0
+#define IRQ_INT1 2
+#define IRQ_VSYNCPULSE 3
+#define IRQ_POWERON 4
+#define IRQ_TIMER0 5
+#define IRQ_TIMER1 6
+#define IRQ_FORCE 7
+#define IRQ_INT8 8
+#define IRQ_ISA 9
+#define IRQ_INT6 10
+#define IRQ_INT5 11
+#define IRQ_INT4 12
+#define IRQ_INT3 13
+#define IRQ_KEYBOARDTX 14
+#define IRQ_KEYBOARDRX 15
+
+#define IRQ_DMA0 16
+#define IRQ_DMA1 17
+#define IRQ_DMA2 18
+#define IRQ_DMA3 19
+#define IRQ_DMAS0 20
+#define IRQ_DMAS1 21
+
+#define IRQ_IOP0 24
+#define IRQ_IOP1 25
+#define IRQ_IOP2 26
+#define IRQ_IOP3 27
+#define IRQ_IOP4 28
+#define IRQ_IOP5 29
+#define IRQ_IOP6 30
+#define IRQ_IOP7 31
+#define IRQ_MOUSERX 32
+#define IRQ_MOUSETX 33
+#define IRQ_ADC 34
+#define IRQ_EVENT1 35
+#define IRQ_EVENT2 36
+
+#define IRQ_ISA_3 40
+#define IRQ_ISA_4 41
+#define IRQ_ISA_5 42
+#define IRQ_ISA_7 43
+#define IRQ_ISA_9 44
+#define IRQ_ISA_10 45
+#define IRQ_ISA_11 46
+#define IRQ_ISA_14 47
+
+#define FIQ_INT9 0
+#define FIQ_INT5 1
+#define FIQ_INT6 4
+#define FIQ_INT8 6
+#define FIQ_FORCE 7
+
+#define IRQ_TIMER IRQ_TIMER0
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/keyboard.h
+ * from linux/include/asm-arm/arch-rpc/keyboard.h
+ *
+ * Keyboard driver definitions for CL7500 architecture
+ *
+ * (C) 1998 Russell King
+ */
+
+#include <asm/irq.h>
+
+#define NR_SCANCODES 128
+
+extern void ps2kbd_leds(unsigned char leds);
+extern void ps2kbd_init_hw(void);
+extern unsigned char ps2kbd_sysrq_xlate[NR_SCANCODES];
+
+#define kbd_setkeycode(sc,kc) (-EINVAL)
+#define kbd_getkeycode(sc) (-EINVAL)
+
+#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
+#define kbd_unexpected_up(kc) (0200)
+#define kbd_leds(leds) ps2kbd_leds(leds)
+#define kbd_init_hw() ps2kbd_init_hw()
+#define kbd_sysrq_xlate ps2kbd_sysrq_xlate
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+
+#define SYSRQ_KEY 13
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/memory.h
+ *
+ * Copyright (c) 1996,1997,1998 Russell King.
+ *
+ * Changelog:
+ * 20-Oct-1996 RMK Created
+ * 31-Dec-1997 RMK Fixed definitions to reduce warnings
+ * 11-Jan-1998 RMK Uninlined to reduce hits on cache
+ * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
+ * 21-Mar-1999 RMK Renamed to memory.h
+ * RMK Added TASK_SIZE and PAGE_OFFSET
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE (0xc0000000UL)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET (0xc0000000UL)
+
+#ifndef __ASSEMBLY__
+extern unsigned long __virt_to_phys(unsigned long vpage);
+extern unsigned long __phys_to_virt(unsigned long ppage);
+#endif
+
+/*
+ * These are exactly the same on the RiscPC as the
+ * physical memory view.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/param.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/processor.h
+ *
+ * Copyright (c) 1996-1999 Russell King.
+ *
+ * Changelog:
+ * 10-Sep-1996 RMK Created
+ * 21-Mar-1999 RMK Added asm/arch/memory.h
+ */
+
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+#include <asm/arch/memory.h>
+
+/*
+ * Bus types
+ */
+#define EISA_bus 0
+#define EISA_bus__is_a_macro /* for versions in ksyms.c */
+#define MCA_bus 0
+#define MCA_bus__is_a_macro /* for versions in ksyms.c */
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/serial.h
+ *
+ * Copyright (c) 1996 Russell King.
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * Changelog:
+ * 15-10-1996 RMK Created
+ * 10-08-1999 PJB Added COM3/COM4 for CL7500
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1843200 / 16)
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+ /* UART CLK PORT IRQ FLAGS */
+#define SERIAL_PORT_DFNS \
+ { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \
+ { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ \
+ { 0, BASE_BAUD, 0x804002e8, 41, STD_COM_FLAGS }, /* ttyS2 */ \
+ { 0, BASE_BAUD, 0x804003e8, 40, STD_COM_FLAGS }, /* ttyS3 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS5 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS6 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS7 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS8 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS9 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/shmparam.h
+ *
+ * Copyright (c) 1999 Nexus Electronics Ltd
+ */
+
+/* The processor-centric definitions are OK. */
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/system.h
+ *
+ * Copyright (c) 1999 Nexus Electronics Ltd.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/iomd.h>
+
+#define arch_reset(mode) { \
+ outb (0, IOMD_ROMCR0); \
+ cli(); \
+ __asm__ __volatile__("msr spsr, r1;" \
+ "mcr p15, 0, %0, c1, c0, 0;" \
+ "movs pc, #0" \
+ : \
+ : "r" (cpu_reset())); \
+ }
+
+/*
+ * We can wait for an interrupt...
+ */
+#define proc_idle() \
+ outb(0, IOMD_SUSMODE)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/time.h
+ *
+ * Copyright (c) 1996 Russell King.
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * Changelog:
+ * 24-Sep-1996 RMK Created
+ * 10-Oct-1996 RMK Brought up to date with arch-sa110eval
+ * 04-Dec-1997 RMK Updated for new arch/arm/time.c
+ * 10-Aug-1999 PJB Converted for CL7500
+ */
+#include <asm/iomd.h>
+
+static long last_rtc_update = 0; /* last time the cmos clock got updated */
+
+extern __inline__ unsigned long gettimeoffset (void)
+{
+ unsigned long offset = 0;
+ unsigned int count1, count2, status1, status2;
+
+ status1 = IOMD_IRQREQA;
+ barrier ();
+ outb(0, IOMD_T0LATCH);
+ barrier ();
+ count1 = inb(IOMD_T0CNTL) | (inb(IOMD_T0CNTH) << 8);
+ barrier ();
+ status2 = inb(IOMD_IRQREQA);
+ barrier ();
+ outb(0, IOMD_T0LATCH);
+ barrier ();
+ count2 = inb(IOMD_T0CNTL) | (inb(IOMD_T0CNTH) << 8);
+
+ if (count2 < count1) {
+ /*
+ * This means that we haven't just had an interrupt
+ * while reading into status2.
+ */
+ if (status2 & (1 << 5))
+ offset = tick;
+ count1 = count2;
+ } else if (count2 > count1) {
+ /*
+ * We have just had another interrupt while reading
+ * status2.
+ */
+ offset += tick;
+ count1 = count2;
+ }
+
+ count1 = LATCH - count1;
+ /*
+ * count1 = number of clock ticks since last interrupt
+ */
+ offset += count1 * tick / LATCH;
+ return offset;
+}
+
+extern __inline__ unsigned long get_rtc_time(void)
+{
+ return mktime(1976, 06, 24, 0, 0, 0);
+}
+
+static int set_rtc_time(unsigned long nowtime)
+{
+ return 0;
+}
+
+static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ do_timer(regs);
+
+ /* If we have an externally synchronized linux clock, then update
+ * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
+ * called as close as possible to 500 ms before the new second starts.
+ */
+ if ((time_status & STA_UNSYNC) == 0 &&
+ xtime.tv_sec > last_rtc_update + 660 &&
+ xtime.tv_usec >= 50000 - (tick >> 1) &&
+ xtime.tv_usec < 50000 + (tick >> 1)) {
+ if (set_rtc_time(xtime.tv_sec) == 0)
+ last_rtc_update = xtime.tv_sec;
+ else
+ last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+ }
+
+ {
+ /* Twinkle the lights. */
+ static int count, bit = 8, dir = 1;
+ if (count-- == 0) {
+ bit += dir;
+ if (bit == 8 || bit == 15) dir = -dir;
+ count = 5;
+ *((volatile unsigned int *)(0xe002ba00)) = 1 << bit;
+ }
+ }
+
+ if (!user_mode(regs))
+ do_profile(instruction_pointer(regs));
+}
+
+static struct irqaction timerirq = {
+ timer_interrupt,
+ 0,
+ 0,
+ "timer",
+ NULL,
+ NULL
+};
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+extern __inline__ void setup_timer(void)
+{
+ outb(LATCH & 255, IOMD_T0LTCHL);
+ outb(LATCH >> 8, IOMD_T0LTCHH);
+ outb(0, IOMD_T0GO);
+
+ xtime.tv_sec = get_rtc_time();
+
+ setup_arm_irq(IRQ_TIMER, &timerirq);
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/timex.h
+ *
+ * CL7500 architecture timex specifications
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+/*
+ * On the ARM7500, the clock ticks at 2MHz.
+ */
+#define CLOCK_TICK_RATE 2000000
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-cl7500/uncompress.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ */
+
+#define BASE 0x03010000
+
+static __inline__ void putc(char c)
+{
+ while (!(*((volatile unsigned int *)(BASE + 0xbf4)) & 0x20));
+ *((volatile unsigned int *)(BASE + 0xbe0)) = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void puts(const char *s)
+{
+ while (*s) {
+ putc(*s);
+ if (*s == '\n')
+ putc('\r');
+ s++;
+ }
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+ int baud = 3686400 / (9600 * 16);
+
+ *((volatile unsigned int *)(BASE + 0xBEC)) = 0x80;
+ *((volatile unsigned int *)(BASE + 0xBE0)) = baud & 0xff;
+ *((volatile unsigned int *)(BASE + 0xBE4)) = (baud & 0xff00) >> 8;
+ *((volatile unsigned int *)(BASE + 0xBEC)) = 3; /* 8 bits */
+ *((volatile unsigned int *)(BASE + 0xBF0)) = 3; /* DTR, RTS */
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define RS_TABLE_SIZE 2
+
/* UART CLK PORT IRQ FLAGS */
-#define SERIAL_PORT_DFNS \
+#define STD_SERIAL_PORT_DEFNS \
{ 0, BASE_BAUD, 0x3F8, 1, STD_COM_FLAGS }, /* ttyS0 */ \
- { 0, BASE_BAUD, 0x2F8, 2, STD_COM_FLAGS }, /* ttyS1 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS3 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS5 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS6 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS7 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS8 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS9 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
+ { 0, BASE_BAUD, 0x2F8, 2, STD_COM_FLAGS } /* ttyS1 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
#endif
#define _SER_IRQ0 IRQ_ISA_UART
#define _SER_IRQ1 IRQ_ISA_UART2
+#define RS_TABLE_SIZE 16
+
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
/* UART CLK PORT IRQ FLAGS */
-#define SERIAL_PORT_DFNS \
+#define STD_SERIAL_PORT_DEFNS \
{ 0, BASE_BAUD, 0x3F8, _SER_IRQ0, STD_COM_FLAGS }, /* ttyS0 */ \
- { 0, BASE_BAUD, 0x2F8, _SER_IRQ1, STD_COM_FLAGS }, /* ttyS1 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS2 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS3 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS4 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS5 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS6 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS7 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS8 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS9 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS10 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS11 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS12 */ \
- { 0, BASE_BAUD, 0 , 0 , STD_COM_FLAGS }, /* ttyS13 */
+ { 0, BASE_BAUD, 0x2F8, _SER_IRQ1, STD_COM_FLAGS }, /* ttyS1 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
#endif
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define RS_TABLE_SIZE 16
+
/* UART CLK PORT IRQ FLAGS */
-#define SERIAL_PORT_DFNS \
+#define STD_SERIAL_PORT_DEFNS \
{ 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
{ 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
- { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
+ { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS } /* ttyS13 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
#endif
/* Standard COM flags */
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define RS_TABLE_SIZE 4
+
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, IRQ_GPIO3, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0x2F8, IRQ_GPIO3, STD_COM_FLAGS }, /* ttyS1 */ \
{ 0, BASE_BAUD, 0x3E8, IRQ_GPIO3, STD_COM_FLAGS }, /* ttyS2 */ \
- { 0, BASE_BAUD, 0x2E8, IRQ_GPIO3, STD_COM4_FLAGS }, /* ttyS3 */
+ { 0, BASE_BAUD, 0x2E8, IRQ_GPIO3, STD_COM4_FLAGS } /* ttyS3 */
--- /dev/null
+#ifndef __ASM_ARM_DIV64
+#define __ASM_ARM_DIV64
+
+/*
+ * unsigned long long division. Yuck Yuck! What is Linux coming to?
+ * This is 100% disgusting
+ */
+#define do_div(n,base) \
+({ \
+ unsigned long __low, __low2, __high, __rem; \
+ __low = (n) & 0xffffffff; \
+ __high = (n) >> 32; \
+ if (__high) { \
+ __rem = __high % (unsigned long)base; \
+ __high = __high / (unsigned long)base; \
+ __low2 = __low >> 16; \
+ __low2 += __rem << 16; \
+ __rem = __low2 % (unsigned long)base; \
+ __low2 = __low2 / (unsigned long)base; \
+ __low = __low & 0xffff; \
+ __low += __rem << 16; \
+ __rem = __low % (unsigned long)base; \
+ __low = __low / (unsigned long)base; \
+ n = __low + (__low2 << 16) + (__high << 32); \
+ } else { \
+ __rem = __low % (unsigned long)base; \
+ n = (__low / (unsigned long)base); \
+ } \
+ __rem; \
+})
+
+#endif
+
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
-#define O_ACCMODE 0003
-#define O_RDONLY 00
-#define O_WRONLY 01
-#define O_RDWR 02
-#define O_CREAT 0100 /* not fcntl */
-#define O_EXCL 0200 /* not fcntl */
-#define O_NOCTTY 0400 /* not fcntl */
-#define O_TRUNC 01000 /* not fcntl */
-#define O_APPEND 02000
-#define O_NONBLOCK 04000
+#define O_ACCMODE 0003
+#define O_RDONLY 00
+#define O_WRONLY 01
+#define O_RDWR 02
+#define O_CREAT 0100 /* not fcntl */
+#define O_EXCL 0200 /* not fcntl */
+#define O_NOCTTY 0400 /* not fcntl */
+#define O_TRUNC 01000 /* not fcntl */
+#define O_APPEND 02000
+#define O_NONBLOCK 04000
#define O_NDELAY O_NONBLOCK
-#define O_SYNC 010000
-#define FASYNC 020000 /* fcntl, for BSD compatibility */
-#define O_DIRECTORY 040000 /* must be a directory */
+#define O_SYNC 010000
+#define FASYNC 020000 /* fcntl, for BSD compatibility */
+#define O_DIRECTORY 040000 /* must be a directory */
#define O_NOFOLLOW 0100000 /* don't follow links */
+#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
+#define O_LARGEFILE 0400000
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get f_flags */
#include <asm/arch/memory.h>
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
-#define MAP_NR(addr) (__pa(addr) >> PAGE_SHIFT)
+#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+#define MAP_NR(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> PAGE_SHIFT)
#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/pgalloc.h
+ */
+#ifndef _ASMARM_PGALLOC_H
+#define _ASMARM_PGALLOC_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/processor.h>
+
+/*
+ * Get the cache handling stuff now.
+ */
+#include <asm/proc/cache.h>
+
+/*
+ * Page table cache stuff
+ */
+#ifndef CONFIG_NO_PGT_CACHE
+
+#ifdef __SMP__
+#error Pgtable caches have to be per-CPU, so that no locking is needed.
+#endif /* __SMP__ */
+
+extern struct pgtable_cache_struct {
+ unsigned long *pgd_cache;
+ unsigned long *pte_cache;
+ unsigned long pgtable_cache_sz;
+} quicklists;
+
+#define pgd_quicklist (quicklists.pgd_cache)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist (quicklists.pte_cache)
+#define pgtable_cache_size (quicklists.pgtable_cache_sz)
+
+/* used for quicklists */
+#define __pgd_next(pgd) (((unsigned long *)pgd)[1])
+#define __pte_next(pte) (((unsigned long *)pte)[0])
+
+extern __inline__ pgd_t *get_pgd_fast(void)
+{
+ unsigned long *ret;
+
+ if ((ret = pgd_quicklist) != NULL) {
+ pgd_quicklist = (unsigned long *)__pgd_next(ret);
+ ret[1] = ret[2];
+ clean_cache_area(ret + 1, 4);
+ pgtable_cache_size--;
+ }
+ return (pgd_t *)ret;
+}
+
+extern __inline__ void free_pgd_fast(pgd_t *pgd)
+{
+ __pgd_next(pgd) = (unsigned long) pgd_quicklist;
+ pgd_quicklist = (unsigned long *) pgd;
+ pgtable_cache_size++;
+}
+
+/* We don't use pmd cache, so this is a dummy routine */
+#define get_pmd_fast() ((pmd_t *)0)
+
+extern __inline__ void free_pmd_fast(pmd_t *pmd)
+{
+}
+
+extern __inline__ pte_t *get_pte_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = pte_quicklist) != NULL) {
+ pte_quicklist = (unsigned long *)__pte_next(ret);
+ ret[0] = ret[1];
+ clean_cache_area(ret, 4);
+ pgtable_cache_size--;
+ }
+ return (pte_t *)ret;
+}
+
+extern __inline__ void free_pte_fast(pte_t *pte)
+{
+ __pte_next(pte) = (unsigned long) pte_quicklist;
+ pte_quicklist = (unsigned long *) pte;
+ pgtable_cache_size++;
+}
+
+#else /* CONFIG_NO_PGT_CACHE */
+
+#define pgd_quicklist ((unsigned long *)0)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist ((unsigned long *)0)
+
+#define get_pgd_fast() ((pgd_t *)0)
+#define get_pmd_fast() ((pmd_t *)0)
+#define get_pte_fast() ((pte_t *)0)
+
+#define free_pgd_fast(pgd) free_pgd_slow(pgd)
+#define free_pmd_fast(pmd) free_pmd_slow(pmd)
+#define free_pte_fast(pte) free_pte_slow(pte)
+
+#endif /* CONFIG_NO_PGT_CACHE */
+
+extern pgd_t *get_pgd_slow(void);
+extern void free_pgd_slow(pgd_t *pgd);
+
+#define free_pmd_slow(pmd) do { } while (0)
+
+extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long addr_preadjusted);
+extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long addr_preadjusted);
+extern void free_pte_slow(pte_t *pte);
+
+/*
+ * Allocate and free page tables. The xxx_kernel() versions are
+ * used to allocate a kernel page table - this turns on ASN bits
+ * if any.
+ */
+#define pte_free_kernel(pte) free_pte_fast(pte)
+#define pte_free(pte) free_pte_fast(pte)
+
+#ifndef pte_alloc_kernel
+extern __inline__ pte_t * pte_alloc_kernel(pmd_t *pmd, unsigned long address)
+{
+ address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+ if (pmd_none(*pmd)) {
+ pte_t *page = (pte_t *) get_pte_fast();
+
+ if (!page)
+ return get_pte_kernel_slow(pmd, address);
+ set_pmd(pmd, mk_kernel_pmd(page));
+ return page + address;
+ }
+ if (pmd_bad(*pmd)) {
+ __handle_bad_pmd_kernel(pmd);
+ return NULL;
+ }
+ return (pte_t *) pmd_page(*pmd) + address;
+}
+#endif
+
+extern __inline__ pte_t *pte_alloc(pmd_t * pmd, unsigned long address)
+{
+ address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+ if (pmd_none(*pmd)) {
+ pte_t *page = (pte_t *) get_pte_fast();
+
+ if (!page)
+ return get_pte_slow(pmd, address);
+ set_pmd(pmd, mk_user_pmd(page));
+ return page + address;
+ }
+ if (pmd_bad(*pmd)) {
+ __handle_bad_pmd(pmd);
+ return NULL;
+ }
+ return (pte_t *) pmd_page(*pmd) + address;
+}
+
+#define pmd_free_kernel pmd_free
+#define pmd_free(pmd) do { } while (0)
+
+#define pmd_alloc_kernel pmd_alloc
+extern __inline__ pmd_t *pmd_alloc(pgd_t *pgd, unsigned long address)
+{
+ return (pmd_t *) pgd;
+}
+
+#define pgd_free(pgd) free_pgd_fast(pgd)
+
+extern __inline__ pgd_t *pgd_alloc(void)
+{
+ pgd_t *pgd;
+
+ pgd = get_pgd_fast();
+ if (!pgd)
+ pgd = get_pgd_slow();
+
+ return pgd;
+}
+
+extern int do_check_pgt_cache(int, int);
+
+extern __inline__ void set_pgdir(unsigned long address, pgd_t entry)
+{
+ struct task_struct * p;
+
+ read_lock(&tasklist_lock);
+ for_each_task(p) {
+ if (!p->mm)
+ continue;
+ *pgd_offset(p->mm,address) = entry;
+ }
+ read_unlock(&tasklist_lock);
+
+#ifndef CONFIG_NO_PGT_CACHE
+ {
+ pgd_t *pgd;
+ for (pgd = (pgd_t *)pgd_quicklist; pgd;
+ pgd = (pgd_t *)__pgd_next(pgd))
+ pgd[address >> PGDIR_SHIFT] = entry;
+ }
+#endif
+}
+
+#endif
/*
* Permanent address of a page.
*/
-#define page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
+#define page_address(page) ({ if (!(page)->virtual) BUG(); (page)->virtual; })
+#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
#define pte_page(x) (mem_map + pte_pagenr(x))
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_present(pgd) (1)
-#define pgd_clear(pgdp)
-
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
return pte;
}
-extern __inline__ pte_t mk_pte(struct page *page, pgprot_t pgprot)
-{
- pte_t pte;
- pte_val(pte) = (PHYS_OFFSET + ((page - mem_map) << PAGE_SHIFT)) | pgprot_val(pgprot);
- return pte;
-}
+#define mk_pte(page,pgprot) \
+({ \
+ pte_t __pte; \
+ pte_val(__pte) = PHYS_OFFSET + \
+ (((page) - mem_map) << PAGE_SHIFT) + \
+ pgprot_val(pgprot); \
+ __pte; \
+})
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_none(pgd) (0)
+#define pgd_bad(pgd) (0)
+#define pgd_present(pgd) (1)
+#define pgd_clear(pgdp)
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
#define __pte_offset(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, addr) ((pte_t *)pmd_page(*(dir)) + __pte_offset(addr))
-/*
- * Get the cache handling stuff now.
- */
-#include <asm/proc/cache.h>
-
-/*
- * Page table cache stuff
- */
-#ifndef CONFIG_NO_PGT_CACHE
-
-#ifdef __SMP__
-#error Pgtable caches have to be per-CPU, so that no locking is needed.
-#endif /* __SMP__ */
-
-extern struct pgtable_cache_struct {
- unsigned long *pgd_cache;
- unsigned long *pte_cache;
- unsigned long pgtable_cache_sz;
-} quicklists;
-
-#define pgd_quicklist (quicklists.pgd_cache)
-#define pmd_quicklist ((unsigned long *)0)
-#define pte_quicklist (quicklists.pte_cache)
-#define pgtable_cache_size (quicklists.pgtable_cache_sz)
-
-/* used for quicklists */
-#define __pgd_next(pgd) (((unsigned long *)pgd)[1])
-#define __pte_next(pte) (((unsigned long *)pte)[0])
-
-extern __inline__ pgd_t *get_pgd_fast(void)
-{
- unsigned long *ret;
-
- if ((ret = pgd_quicklist) != NULL) {
- pgd_quicklist = (unsigned long *)__pgd_next(ret);
- ret[1] = ret[2];
- clean_cache_area(ret + 1, 4);
- pgtable_cache_size--;
- }
- return (pgd_t *)ret;
-}
-
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
-{
- __pgd_next(pgd) = (unsigned long) pgd_quicklist;
- pgd_quicklist = (unsigned long *) pgd;
- pgtable_cache_size++;
-}
-
-/* We don't use pmd cache, so this is a dummy routine */
-#define get_pmd_fast() ((pmd_t *)0)
-
-extern __inline__ void free_pmd_fast(pmd_t *pmd)
-{
-}
-
-extern __inline__ pte_t *get_pte_fast(void)
-{
- unsigned long *ret;
-
- if((ret = pte_quicklist) != NULL) {
- pte_quicklist = (unsigned long *)__pte_next(ret);
- ret[0] = ret[1];
- clean_cache_area(ret, 4);
- pgtable_cache_size--;
- }
- return (pte_t *)ret;
-}
-
-extern __inline__ void free_pte_fast(pte_t *pte)
-{
- __pte_next(pte) = (unsigned long) pte_quicklist;
- pte_quicklist = (unsigned long *) pte;
- pgtable_cache_size++;
-}
-
-#else /* CONFIG_NO_PGT_CACHE */
-
-#define pgd_quicklist ((unsigned long *)0)
-#define pmd_quicklist ((unsigned long *)0)
-#define pte_quicklist ((unsigned long *)0)
-
-#define get_pgd_fast() ((pgd_t *)0)
-#define get_pmd_fast() ((pmd_t *)0)
-#define get_pte_fast() ((pte_t *)0)
-
-#define free_pgd_fast(pgd) free_pgd_slow(pgd)
-#define free_pmd_fast(pmd) free_pmd_slow(pmd)
-#define free_pte_fast(pte) free_pte_slow(pte)
-
-#endif /* CONFIG_NO_PGT_CACHE */
-
-extern pgd_t *get_pgd_slow(void);
-extern void free_pgd_slow(pgd_t *pgd);
-
-#define free_pmd_slow(pmd) do { } while (0)
-
-extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long addr_preadjusted);
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long addr_preadjusted);
-extern void free_pte_slow(pte_t *pte);
-
#include <asm/proc/pgtable.h>
extern __inline__ pte_t pte_modify(pte_t pte, pgprot_t newprot)
return pte;
}
-/*
- * Allocate and free page tables. The xxx_kernel() versions are
- * used to allocate a kernel page table - this turns on ASN bits
- * if any.
- */
-#define pte_free_kernel(pte) free_pte_fast(pte)
-#define pte_free(pte) free_pte_fast(pte)
-
-#ifndef pte_alloc_kernel
-extern __inline__ pte_t * pte_alloc_kernel(pmd_t *pmd, unsigned long address)
-{
- address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
- if (pmd_none(*pmd)) {
- pte_t *page = (pte_t *) get_pte_fast();
-
- if (!page)
- return get_pte_kernel_slow(pmd, address);
- set_pmd(pmd, mk_kernel_pmd(page));
- return page + address;
- }
- if (pmd_bad(*pmd)) {
- __handle_bad_pmd_kernel(pmd);
- return NULL;
- }
- return (pte_t *) pmd_page(*pmd) + address;
-}
-#endif
-
-extern __inline__ pte_t *pte_alloc(pmd_t * pmd, unsigned long address)
-{
- address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
- if (pmd_none(*pmd)) {
- pte_t *page = (pte_t *) get_pte_fast();
-
- if (!page)
- return get_pte_slow(pmd, address);
- set_pmd(pmd, mk_user_pmd(page));
- return page + address;
- }
- if (pmd_bad(*pmd)) {
- __handle_bad_pmd(pmd);
- return NULL;
- }
- return (pte_t *) pmd_page(*pmd) + address;
-}
-
-#define pmd_free_kernel pmd_free
-#define pmd_free(pmd) do { } while (0)
-
-#define pmd_alloc_kernel pmd_alloc
-extern __inline__ pmd_t *pmd_alloc(pgd_t *pgd, unsigned long address)
-{
- return (pmd_t *) pgd;
-}
-
-#define pgd_free(pgd) free_pgd_fast(pgd)
-
-extern __inline__ pgd_t *pgd_alloc(void)
-{
- pgd_t *pgd;
-
- pgd = get_pgd_fast();
- if (!pgd)
- pgd = get_pgd_slow();
-
- return pgd;
-}
-
-extern int do_check_pgt_cache(int, int);
-
-extern __inline__ void set_pgdir(unsigned long address, pgd_t entry)
-{
- struct task_struct * p;
-
- read_lock(&tasklist_lock);
- for_each_task(p) {
- if (!p->mm)
- continue;
- *pgd_offset(p->mm,address) = entry;
- }
- read_unlock(&tasklist_lock);
-
-#ifndef CONFIG_NO_PGT_CACHE
- {
- pgd_t *pgd;
- for (pgd = (pgd_t *)pgd_quicklist; pgd;
- pgd = (pgd_t *)__pgd_next(pgd))
- pgd[address >> PGDIR_SHIFT] = entry;
- }
-#endif
-}
-
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-#define update_mmu_cache(vma,address,pte)
+#define update_mmu_cache(vma,address,pte) do { } while (0)
-/*
+/* Encode and decode a swap entry.
+ *
* We support up to 32GB of swap on 4k machines
*/
-#define SWP_TYPE(entry) (((pte_val(entry)) >> 2) & 0x7f)
-#define SWP_OFFSET(entry) ((pte_val(entry)) >> 9)
-#define SWP_ENTRY(type,offset) __pte((((type) << 2) | ((offset) << 9)))
+#define SWP_TYPE(x) (((x).val >> 2) & 0x7f)
+#define SWP_OFFSET(x) ((x).val >> 9)
+#define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
+#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define swp_entry_to_pte(swp) ((pte_t) { (swp).val })
#define module_map vmalloc
#define module_unmap vfree
-/*
- * We rely on GCC optimising this code away for
- * architectures which it doesn't apply to. Note
- * that `addr' is checked against PAGE_OFFSET and
- * end_mem by the calling code.
- */
-#define __kern_valid_idx(a) (((a) - PAGE_OFFSET) >> 20)
-
-extern __inline__ int __kern_valid_addr(unsigned long addr)
-{
- extern unsigned long *valid_addr_bitmap;
- unsigned int idx = __kern_valid_idx(addr);
-
- return test_bit(idx, valid_addr_bitmap);
-}
-
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define PageSkip(page) (machine_is_riscpc() && test_bit(PG_skip, &(page)->flags))
-#define kern_addr_valid(addr) (!machine_is_riscpc() || __kern_valid_addr(addr))
#define io_remap_page_range remap_page_range
regs->ARM_r0 = stack[0]; /* r0 (argc) */ \
})
+#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
+#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1020])
+
/* Allocation and freeing of basic task resources. */
/*
* NOTE! The task struct and the stack go together
extern unsigned long get_page_8k(int priority);
extern void free_page_8k(unsigned long page);
-#define THREAD_SIZE (8192)
-
#define ll_alloc_task_struct() ((struct task_struct *)get_page_8k(GFP_KERNEL))
#define ll_free_task_struct(p) free_page_8k((unsigned long)(p))
*/
static __inline__ void flush_page_to_ram(struct page *page)
{
- unsigned long virt = page_address(page);
- cpu_flush_ram_page(virt);
+ cpu_flush_ram_page(page_address(page));
}
/*
regs->ARM_r0 = stack[0]; /* r0 (argc) */ \
})
+#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1021])
+#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
+
/* Allocation and freeing of basic task resources. */
/*
* NOTE! The task struct and the stack go together
*/
-#define THREAD_SIZE (PAGE_SIZE * 2)
#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
#define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
#define NR_DEBUGS 5
+#include <asm/atomic.h>
#include <asm/ptrace.h>
#include <asm/arch/memory.h>
#include <asm/arch/processor.h>
};
struct thread_struct {
+ atomic_t refcount;
/* fault info */
unsigned long address;
unsigned long trap_no;
{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
#define INIT_THREAD { \
+ ATOMIC_INIT(1), \
0, \
0, \
0, \
unsigned long get_wchan(struct task_struct *p);
-#ifdef CONFIG_CPU_26
-# define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
-# define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1020])
-#else
-# define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1021])
-# define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
-#endif
+#define THREAD_SIZE (8192)
extern struct task_struct *alloc_task_struct(void);
-extern void free_task_struct(struct task_struct *);
+extern void __free_task_struct(struct task_struct *);
+#define get_task_struct(p) atomic_inc(&(p)->thread.refcount)
+#define put_task_struct(p) free_task_struct(p)
+#define free_task_struct(p) \
+ do { \
+ if (atomic_dec_and_test(&(p)->thread.refcount)) \
+ __free_task_struct((p)); \
+ } while (0)
#define init_task (init_task_union.task)
#define init_stack (init_task_union.stack)
#include <asm/arch/serial.h>
+#define SERIAL_PORT_DFNS \
+ STD_SERIAL_PORT_DEFNS \
+ EXTRA_SERIAL_PORT_DEFNS
+
#endif
--- /dev/null
+#ifndef _PPC_PGALLOC_H
+#define _PPC_PGALLOC_H
+
+
+
+/* We don't use pmd cache, so this is a dummy routine */
+extern __inline__ pmd_t *get_pmd_fast(void)
+{
+ return (pmd_t *)0;
+}
+
+extern __inline__ void free_pmd_fast(pmd_t *pmd)
+{
+}
+
+extern __inline__ void free_pmd_slow(pmd_t *pmd)
+{
+}
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+extern inline void pmd_free(pmd_t * pmd)
+{
+}
+
+extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
+{
+ return (pmd_t *) pgd;
+}
+
+#define pmd_free_kernel pmd_free
+#define pmd_alloc_kernel pmd_alloc
+#define pte_alloc_kernel pte_alloc
+
+extern __inline__ pgd_t *get_pgd_slow(void)
+{
+ pgd_t *ret, *init;
+ /*if ( (ret = (pgd_t *)get_zero_page_fast()) == NULL )*/
+ if ( (ret = (pgd_t *)__get_free_page(GFP_KERNEL)) != NULL )
+ memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
+ if (ret) {
+ init = pgd_offset(&init_mm, 0);
+ memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+ (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+ }
+ return ret;
+}
+
+extern __inline__ pgd_t *get_pgd_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = pgd_quicklist) != NULL) {
+ pgd_quicklist = (unsigned long *)(*ret);
+ ret[0] = ret[1];
+ pgtable_cache_size--;
+ } else
+ ret = (unsigned long *)get_pgd_slow();
+ return (pgd_t *)ret;
+}
+
+extern __inline__ void free_pgd_fast(pgd_t *pgd)
+{
+ *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
+ pgd_quicklist = (unsigned long *) pgd;
+ pgtable_cache_size++;
+}
+
+extern __inline__ void free_pgd_slow(pgd_t *pgd)
+{
+ free_page((unsigned long)pgd);
+}
+
+extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
+
+extern __inline__ pte_t *get_pte_fast(void)
+{
+ unsigned long *ret;
+
+ if((ret = (unsigned long *)pte_quicklist) != NULL) {
+ pte_quicklist = (unsigned long *)(*ret);
+ ret[0] = ret[1];
+ pgtable_cache_size--;
+ }
+ return (pte_t *)ret;
+}
+
+extern __inline__ void free_pte_fast(pte_t *pte)
+{
+ *(unsigned long *)pte = (unsigned long) pte_quicklist;
+ pte_quicklist = (unsigned long *) pte;
+ pgtable_cache_size++;
+}
+
+extern __inline__ void free_pte_slow(pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+#define pte_free_kernel(pte) free_pte_fast(pte)
+#define pte_free(pte) free_pte_fast(pte)
+#define pgd_free(pgd) free_pgd_fast(pgd)
+#define pgd_alloc() get_pgd_fast()
+
+extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
+{
+ address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
+ if (pmd_none(*pmd)) {
+ pte_t * page = (pte_t *) get_pte_fast();
+
+ if (!page)
+ return get_pte_slow(pmd, address);
+ pmd_val(*pmd) = (unsigned long) page;
+ return page + address;
+ }
+ if (pmd_bad(*pmd)) {
+ __bad_pte(pmd);
+ return NULL;
+ }
+ return (pte_t *) pmd_page(*pmd) + address;
+}
+
+extern int do_check_pgt_cache(int, int);
+
+extern __inline__ pte_t *find_pte(struct mm_struct *mm,unsigned long va)
+{
+ pgd_t *dir;
+ pmd_t *pmd;
+ pte_t *pte;
+
+ va &= PAGE_MASK;
+
+ dir = pgd_offset( mm, va );
+ if (dir)
+ {
+ pmd = pmd_offset(dir, va & PAGE_MASK);
+ if (pmd && pmd_present(*pmd))
+ {
+ pte = pte_offset(pmd, va);
+ if (pte && pte_present(*pte))
+ {
+ pte_uncache(*pte);
+ flush_tlb_page(find_vma(mm,va),va);
+ }
+ }
+ }
+ return pte;
+}
+
+#endif /* _PPC_PGALLOC_H */
#define _PPC_PGTABLE_H
#ifndef __ASSEMBLY__
-#include <linux/mm.h>
#include <linux/threads.h>
+#include <linux/sched.h>
+#include <asm/atomic.h>
#include <asm/processor.h> /* For TASK_SIZE */
#include <asm/mmu.h>
#include <asm/page.h>
#ifndef CONFIG_8xx
+struct mm_struct;
+struct vm_area_struct;
extern void local_flush_tlb_all(void);
extern void local_flush_tlb_mm(struct mm_struct *mm);
extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
* Permanent address of a page.
*/
#define page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
+#define __page_address(page) ({ if (PageHighMem(page)) BUG(); PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT); })
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
#define pte_page(x) (mem_map+pte_pagenr(x))
return pte;
}
-extern inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
-{
- pte_t pte;
- pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot);
- return pte;
-}
+#define mk_pte(page,pgprot) \
+({ \
+ pte_t pte; \
+ pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \
+ pte; \
+})
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
/* return a pre-zero'd page from the list, return NULL if none available -- Cort */
extern unsigned long get_zero_page_fast(void);
-extern __inline__ pgd_t *get_pgd_slow(void)
-{
- pgd_t *ret, *init;
- /*if ( (ret = (pgd_t *)get_zero_page_fast()) == NULL )*/
- if ( (ret = (pgd_t *)__get_free_page(GFP_KERNEL)) != NULL )
- memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
- if (ret) {
- init = pgd_offset(&init_mm, 0);
- memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
- (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
- }
- return ret;
-}
-
-extern __inline__ pgd_t *get_pgd_fast(void)
-{
- unsigned long *ret;
-
- if((ret = pgd_quicklist) != NULL) {
- pgd_quicklist = (unsigned long *)(*ret);
- ret[0] = ret[1];
- pgtable_cache_size--;
- } else
- ret = (unsigned long *)get_pgd_slow();
- return (pgd_t *)ret;
-}
-
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
-{
- *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
- pgd_quicklist = (unsigned long *) pgd;
- pgtable_cache_size++;
-}
-
-extern __inline__ void free_pgd_slow(pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
-
-extern __inline__ pte_t *get_pte_fast(void)
-{
- unsigned long *ret;
-
- if((ret = (unsigned long *)pte_quicklist) != NULL) {
- pte_quicklist = (unsigned long *)(*ret);
- ret[0] = ret[1];
- pgtable_cache_size--;
- }
- return (pte_t *)ret;
-}
-
-extern __inline__ void free_pte_fast(pte_t *pte)
-{
- *(unsigned long *)pte = (unsigned long) pte_quicklist;
- pte_quicklist = (unsigned long *) pte;
- pgtable_cache_size++;
-}
-
-extern __inline__ void free_pte_slow(pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-/* We don't use pmd cache, so this is a dummy routine */
-extern __inline__ pmd_t *get_pmd_fast(void)
-{
- return (pmd_t *)0;
-}
-
-extern __inline__ void free_pmd_fast(pmd_t *pmd)
-{
-}
-
-extern __inline__ void free_pmd_slow(pmd_t *pmd)
-{
-}
-
extern void __bad_pte(pmd_t *pmd);
-#define pte_free_kernel(pte) free_pte_fast(pte)
-#define pte_free(pte) free_pte_fast(pte)
-#define pgd_free(pgd) free_pgd_fast(pgd)
-#define pgd_alloc() get_pgd_fast()
-
-extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
-{
- address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
- if (pmd_none(*pmd)) {
- pte_t * page = (pte_t *) get_pte_fast();
-
- if (!page)
- return get_pte_slow(pmd, address);
- pmd_val(*pmd) = (unsigned long) page;
- return page + address;
- }
- if (pmd_bad(*pmd)) {
- __bad_pte(pmd);
- return NULL;
- }
- return (pte_t *) pmd_page(*pmd) + address;
-}
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
-extern inline void pmd_free(pmd_t * pmd)
-{
-}
-
-extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
-{
- return (pmd_t *) pgd;
-}
-
-#define pmd_free_kernel pmd_free
-#define pmd_alloc_kernel pmd_alloc
-#define pte_alloc_kernel pte_alloc
-
-extern int do_check_pgt_cache(int, int);
-
extern inline void set_pgdir(unsigned long address, pgd_t entry)
{
struct task_struct * p;
extern pgd_t swapper_pg_dir[1024];
-extern __inline__ pte_t *find_pte(struct mm_struct *mm,unsigned long va)
-{
- pgd_t *dir;
- pmd_t *pmd;
- pte_t *pte;
-
- va &= PAGE_MASK;
-
- dir = pgd_offset( mm, va );
- if (dir)
- {
- pmd = pmd_offset(dir, va & PAGE_MASK);
- if (pmd && pmd_present(*pmd))
- {
- pte = pte_offset(pmd, va);
- if (pte && pte_present(*pte))
- {
- pte_uncache(*pte);
- flush_tlb_page(find_vma(mm,va),va);
- }
- }
- }
- return pte;
-}
-
/*
* Page tables may have changed. We don't need to do anything here
* as entries are faulted into the hash table by the low-level
typedef int acpi_dstate_t;
+/*
+ * System sleep states
+ */
+enum
+{
+ ACPI_S0, /* working */
+ ACPI_S1, /* sleep */
+ ACPI_S2, /* sleep */
+ ACPI_S3, /* sleep */
+ ACPI_S4, /* non-volatile sleep */
+ ACPI_S5, /* soft-off */
+};
+
+typedef int acpi_sstate_t;
+
struct acpi_dev;
/*
/* strangess to avoid integer overflow */
#define ACPI_uS_TO_TMR_TICKS(val) \
(((val) * (ACPI_TMR_HZ / 10000)) / 100)
+#define ACPI_TMR_TICKS_TO_uS(ticks) \
+ (((ticks) * 100) / (ACPI_TMR_HZ / 10000))
/* CPU cycles -> PM timer cycles, looks somewhat heuristic but
(ticks = 3/11 * CPU_MHz + 2) comes pretty close for my systems
/* FACS flags */
#define ACPI_S4BIOS 0x00000001
+/* processor block offsets */
+#define ACPI_P_CNT 0x00000000
+#define ACPI_P_LVL2 0x00000004
+#define ACPI_P_LVL3 0x00000005
+
+/* C-state latencies (microseconds) */
+#define ACPI_MAX_P_LVL2_LAT 100
+#define ACPI_MAX_P_LVL3_LAT 1000
+#define ACPI_INFINITE_LAT (~0UL)
+
struct acpi_rsdp {
__u32 signature[2];
__u8 checksum;
ACPI_GPE_ENABLE,
ACPI_GPE_LEVEL,
ACPI_EVENT,
- ACPI_P_LVL2,
- ACPI_P_LVL3,
+ ACPI_P_BLK,
ACPI_P_LVL2_LAT,
ACPI_P_LVL3_LAT,
ACPI_S5_SLP_TYP,
};
-#define ACPI_P_LVL_DISABLED 0x80
#define ACPI_SLP_TYP_DISABLED (~0UL)
/*
#define ACPI_PIIX4_S5_MASK (0x0000 << 10)
#define ACPI_PIIX4_PM_TMR 0x0008
#define ACPI_PIIX4_GPE0 0x000c
-#define ACPI_PIIX4_P_CNT 0x0010
-#define ACPI_PIIX4_P_LVL2 0x0014
-#define ACPI_PIIX4_P_LVL3 0x0015
+#define ACPI_PIIX4_P_BLK 0x0010
#define ACPI_PIIX4_PM1_EVT_LEN 0x04
#define ACPI_PIIX4_PM1_CNT_LEN 0x02
#include <asm/pgtable.h>
#include <asm/dma.h>
+#include <asm/cache.h>
#include <linux/init.h>
/*
#ifndef _LINUX_FB_H
#define _LINUX_FB_H
+#include <linux/tty.h>
#include <asm/types.h>
/* Definitions of frame buffers */
#include <linux/types.h>
#include <linux/version.h>
#include <linux/config.h>
-#if LINUX_VERSION_CODE <= KERNEL_VER(1,2,13)
-typedef daddr_t __kernel_daddr_t; /* needed for mtio.h */
-#endif
#include <linux/mtio.h>
#define FT_SECTOR(x) (x+1) /* sector offset into real sector */
extern int request_resource(struct resource *root, struct resource *new);
extern int release_resource(struct resource *new);
+struct pci_dev;
extern int allocate_resource(struct resource *root, struct resource *new,
unsigned long size,
unsigned long min, unsigned long max,
- unsigned long align);
+ unsigned long align, struct pci_dev *);
/* Convenience shorthand with allocation */
#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name))
extern void autoirq_setup(int waittime);
extern int autoirq_report(int waittime);
+extern unsigned long resource_fixup(struct pci_dev *, struct resource *,
+ unsigned long, unsigned long);
+
#endif /* _LINUX_IOPORT_H */
unsigned int rchits; /* repcache hits */
unsigned int rcmisses; /* repcache hits */
unsigned int rcnocache; /* uncached reqs */
- unsigned int fh_cached; /* dentry cached */
- unsigned int fh_valid; /* dentry validated */
- unsigned int fh_fixup; /* dentry fixup validated */
- unsigned int fh_lookup; /* new lookup required */
unsigned int fh_stale; /* FH stale error */
+ unsigned int fh_lookup; /* dentry cached */
+ unsigned int fh_anon; /* anon file dentry returned */
+ unsigned int fh_nocache_dir; /* filehandle not foudn in dcache */
+ unsigned int fh_nocache_nondir; /* filehandle not foudn in dcache */
};
#ifdef __KERNEL__
int (*write_dword)(struct pci_dev *, int where, u32 val);
};
+struct pbus_set_ranges_data
+{
+ int found_vga;
+ unsigned long io_start, io_end;
+ unsigned long mem_start, mem_end;
+};
+
void pcibios_init(void);
void pcibios_fixup_bus(struct pci_bus *);
+void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
int pcibios_enable_device(struct pci_dev *);
char *pcibios_setup (char *str);
#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424
#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d
-#define PCI_VENDOR_ID_SK 0x1148
-#define PCI_DEVICE_ID_SK_FP 0x4000
-#define PCI_DEVICE_ID_SK_TR 0x4200
-#define PCI_DEVICE_ID_SK_GE 0x4300
+#define PCI_VENDOR_ID_SYSKONNECT 0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000
+#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300
#define PCI_VENDOR_ID_VMIC 0x114a
#define PCI_DEVICE_ID_VMIC_VME 0x7587
unsigned int start;
unsigned int readers;
unsigned int writers;
+ unsigned int waiting_readers;
+ unsigned int waiting_writers;
};
/* Differs from PIPE_BUF in that PIPE_SIZE is the length of the actual
#define PIPE_LEN(inode) ((inode).i_size)
#define PIPE_READERS(inode) ((inode).i_pipe->readers)
#define PIPE_WRITERS(inode) ((inode).i_pipe->writers)
+#define PIPE_WAITING_READERS(inode) ((inode).i_pipe->waiting_readers)
+#define PIPE_WAITING_WRITERS(inode) ((inode).i_pipe->waiting_writers)
#define PIPE_EMPTY(inode) (PIPE_LEN(inode) == 0)
#define PIPE_FULL(inode) (PIPE_LEN(inode) == PIPE_SIZE)
#define CURRENT_TIME (xtime.tv_sec)
extern void FASTCALL(__wake_up(wait_queue_head_t *q, unsigned int mode));
+extern void FASTCALL(__wake_up_sync(wait_queue_head_t *q, unsigned int mode));
extern void FASTCALL(sleep_on(wait_queue_head_t *q));
extern long FASTCALL(sleep_on_timeout(wait_queue_head_t *q,
signed long timeout));
extern void FASTCALL(wake_up_process(struct task_struct * tsk));
#define wake_up(x) __wake_up((x),TASK_UNINTERRUPTIBLE | TASK_INTERRUPTIBLE)
+#define wake_up_sync(x) __wake_up_sync((x),TASK_UNINTERRUPTIBLE | TASK_INTERRUPTIBLE)
#define wake_up_interruptible(x) __wake_up((x),TASK_INTERRUPTIBLE)
+#define wake_up_interruptible_sync(x) __wake_up_sync((x),TASK_INTERRUPTIBLE)
extern int in_group_p(gid_t);
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Tue Apr 14 12:41:42 1998
- * Modified at: Tue Oct 19 20:00:03 1999
+ * Modified at: Tue Nov 16 12:54:01 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1999 Dag Brattli, All Rights Reserved.
int irda_device_txqueue_empty(struct net_device *dev);
int irda_device_set_raw_mode(struct net_device* self, int status);
int irda_device_set_dtr_rts(struct net_device *dev, int dtr, int rts);
+int irda_device_change_speed(struct net_device *dev, __u32 speed);
int irda_device_setup(struct net_device *dev);
/* Dongle interface */
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Mon Aug 4 20:40:53 1997
- * Modified at: Thu Oct 7 23:06:36 1999
+ * Modified at: Tue Nov 16 10:00:36 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
hashbin_t *discovery_log;
discovery_t *discovery_cmd;
+ __u32 speed;
+
struct qos_info qos_tx; /* QoS requested by peer */
struct qos_info qos_rx; /* QoS requested by self */
struct qos_info *qos_dev; /* QoS supported by device */
int irlap_generate_rand_time_slot(int S, int s);
void irlap_initiate_connection_state(struct irlap_cb *);
void irlap_flush_all_queues(struct irlap_cb *);
-void irlap_change_speed(struct irlap_cb *self, __u32 speed);
+void irlap_change_speed(struct irlap_cb *self, __u32 speed, int now);
void irlap_wait_min_turn_around(struct irlap_cb *, struct qos_info *);
void irlap_init_qos_capabilities(struct irlap_cb *, struct qos_info *);
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sun Aug 3 13:49:59 1997
- * Modified at: Sat Oct 30 19:54:07 1999
+ * Modified at: Sat Nov 13 23:48:55 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1997, 1998-1999 Dag Brattli <dagb@cs.uit.no>
dongle_t *dongle; /* Dongle driver */
__u32 flags; /* Interface flags */
+ __u32 new_speed;
spinlock_t lock; /* For serializing operations */
void irport_stop(struct irport_cb *self, int iobase);
int irport_probe(int iobase);
+int irport_change_speed(struct irda_task *task);
void __irport_change_speed(struct irport_cb *self, __u32 speed);
void irport_interrupt(int irq, void *dev_id, struct pt_regs *regs);
int irport_hard_xmit(struct sk_buff *skb, struct net_device *dev);
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Tue Dec 9 21:13:12 1997
- * Modified at: Mon Oct 18 23:24:31 1999
+ * Modified at: Fri Nov 5 10:46:51 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1997, 1999 Dag Brattli, All Rights Reserved.
struct qos_info qos; /* QoS capabilities for this device */
dongle_t *dongle; /* Dongle driver */
+ __u32 new_speed;
+
__u32 flags; /* Interface flags */
INFRARED_MODE mode;
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Fri Nov 13 14:37:40 1998
- * Modified at: Mon Oct 18 15:08:53 1999
+ * Modified at: Mon Nov 8 10:00:27 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>
struct qos_info qos; /* QoS capabilities for this device */
__u32 flags; /* Interface flags */
+ __u32 new_speed;
};
static inline void switch_bank(int iobase, int bank)
struct qos_info qos; /* QoS capabilities for this device */
__u32 flags; /* Interface flags */
+ __u32 new_speed;
struct pci_dev *pdev; /*PCI device */
int base; /*IO base */
* Status: Experimental.
* Author: Paul VanderSpek
* Created at: Thu Nov 19 13:55:34 1998
- * Modified at: Fri Oct 15 16:06:46 1999
+ * Modified at: Mon Nov 8 10:00:40 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli, All Rights Reserved.
struct qos_info qos; /* QoS capabilities for this device */
__u32 flags; /* Interface flags */
+ __u32 new_speed;
};
static inline void switch_bank( int iobase, int set)
if(sma==NULL)
return -EINVAL;
+ nsems = sma->sem_nsems;
+
err=-EIDRM;
if (sem_checkid(sma,semid))
goto out_unlock;
if (ipcperms (&sma->sem_perm, (cmd==SETVAL||cmd==SETALL)?S_IWUGO:S_IRUGO))
goto out_unlock;
- nsems = sma->sem_nsems;
switch (cmd) {
case GETALL:
{
EXPORT_SYMBOL(find_vma);
EXPORT_SYMBOL(get_unmapped_area);
EXPORT_SYMBOL(init_mm);
+#ifdef CONFIG_HIGHMEM
+EXPORT_SYMBOL(kmap_high);
+EXPORT_SYMBOL(kunmap_high);
+EXPORT_SYMBOL(highmem_start_page);
+#endif
/* filesystem internal functions */
EXPORT_SYMBOL(in_group_p);
EXPORT_SYMBOL(__bforget);
EXPORT_SYMBOL(ll_rw_block);
EXPORT_SYMBOL(__wait_on_buffer);
+EXPORT_SYMBOL(___wait_on_page);
EXPORT_SYMBOL(add_blkdev_randomness);
EXPORT_SYMBOL(block_read_full_page);
EXPORT_SYMBOL(block_write_full_page);
static int find_resource(struct resource *root, struct resource *new,
unsigned long size,
unsigned long min, unsigned long max,
- unsigned long align)
+ unsigned long align, struct pci_dev * dev)
{
struct resource *this = root->child;
unsigned long start, end;
if (end > max)
end = max;
start = (start + align - 1) & ~(align - 1);
+ start = resource_fixup (dev, new, start, size);
if (start < end && end - start + 1 >= size) {
new->start = start;
new->end = start + size - 1;
int allocate_resource(struct resource *root, struct resource *new,
unsigned long size,
unsigned long min, unsigned long max,
- unsigned long align)
+ unsigned long align, struct pci_dev * dev)
{
int err;
write_lock(&resource_lock);
- err = find_resource(root, new, size, min, max, align);
+ err = find_resource(root, new, size, min, max, align, dev);
if (err >= 0 && __request_resource(root, new))
err = -EBUSY;
write_unlock(&resource_lock);
return goodness(p, cpu, prev->mm) - goodness(prev, cpu, prev->mm);
}
-static void reschedule_idle(struct task_struct * p)
+/*
+ * This is ugly, but reschedule_idle() is very timing-critical.
+ * We enter with the runqueue spinlock held, but we might end
+ * up unlocking it early, so the caller must not unlock the
+ * runqueue, it's always done by reschedule_idle().
+ */
+static inline void reschedule_idle(struct task_struct * p, unsigned long flags)
{
#ifdef __SMP__
int this_cpu = smp_processor_id(), target_cpu;
- struct task_struct *tsk, *target_tsk;
+ struct task_struct *tsk;
int cpu, best_cpu, i;
- unsigned long flags;
-
- spin_lock_irqsave(&runqueue_lock, flags);
/*
* shortcut if the woken up task's last CPU is
* idle now.
*/
best_cpu = p->processor;
- target_tsk = idle_task(best_cpu);
- if (cpu_curr(best_cpu) == target_tsk)
+ tsk = idle_task(best_cpu);
+ if (cpu_curr(best_cpu) == tsk)
goto send_now;
- target_tsk = NULL;
+ /*
+ * The only heuristics - we use the tsk->avg_slice value
+ * to detect 'frequent reschedulers'.
+ *
+ * If both the woken-up process and the preferred CPU is
+ * is a frequent rescheduler, then skip the asynchronous
+ * wakeup, the frequent rescheduler will likely chose this
+ * task during it's next schedule():
+ */
+ tsk = cpu_curr(best_cpu);
+ if ((p->avg_slice < cacheflush_time) &&
+ (tsk->avg_slice < cacheflush_time))
+ goto out_no_target;
+
+ /*
+ * We know that the preferred CPU has a cache-affine current
+ * process, lets try to find a new idle CPU for the woken-up
+ * process:
+ */
for (i = 0; i < smp_num_cpus; i++) {
cpu = cpu_logical_map(i);
tsk = cpu_curr(cpu);
+ /*
+ * We use the first available idle CPU. This creates
+ * a priority list between idle CPUs, but this is not
+ * a problem.
+ */
if (tsk == idle_task(cpu))
- target_tsk = tsk;
+ goto send_now;
}
- if (target_tsk && p->avg_slice > cacheflush_time)
- goto send_now;
-
+ /*
+ * No CPU is idle, but maybe this process has enough priority
+ * to preempt it's preferred CPU. (this is a shortcut):
+ */
tsk = cpu_curr(best_cpu);
if (preemption_goodness(tsk, p, best_cpu) > 0)
- target_tsk = tsk;
+ goto send_now;
/*
- * found any suitable CPU?
+ * We should get here rarely - or in the high CPU contention
+ * case. No CPU is idle and this process is either lowprio or
+ * the preferred CPU is highprio. Maybe some other CPU can/must
+ * be preempted:
*/
- if (!target_tsk)
- goto out_no_target;
+ for (i = 0; i < smp_num_cpus; i++) {
+ cpu = cpu_logical_map(i);
+ tsk = cpu_curr(cpu);
+ if (preemption_goodness(tsk, p, cpu) > 0)
+ goto send_now;
+ }
+
+out_no_target:
+ spin_unlock_irqrestore(&runqueue_lock, flags);
+ return;
send_now:
- target_cpu = target_tsk->processor;
- target_tsk->need_resched = 1;
+ target_cpu = tsk->processor;
+ tsk->need_resched = 1;
spin_unlock_irqrestore(&runqueue_lock, flags);
/*
* the APIC stuff can go outside of the lock because
if (target_cpu != this_cpu)
smp_send_reschedule(target_cpu);
return;
-out_no_target:
- spin_unlock_irqrestore(&runqueue_lock, flags);
- return;
#else /* UP */
int this_cpu = smp_processor_id();
struct task_struct *tsk;
* "current->state = TASK_RUNNING" to mark yourself runnable
* without the overhead of this.
*/
-void wake_up_process(struct task_struct * p)
+inline void wake_up_process(struct task_struct * p)
{
unsigned long flags;
if (task_on_runqueue(p))
goto out;
add_to_runqueue(p);
- spin_unlock_irqrestore(&runqueue_lock, flags);
+ reschedule_idle(p, flags); // spin_unlocks runqueue
- reschedule_idle(p);
return;
out:
spin_unlock_irqrestore(&runqueue_lock, flags);
}
+static inline void wake_up_process_synchronous(struct task_struct * p)
+{
+ unsigned long flags;
+
+ /*
+ * We want the common case fall through straight, thus the goto.
+ */
+ spin_lock_irqsave(&runqueue_lock, flags);
+ p->state = TASK_RUNNING;
+ if (task_on_runqueue(p))
+ goto out;
+ add_to_runqueue(p);
+out:
+ spin_unlock_irqrestore(&runqueue_lock, flags);
+}
+
static void process_timeout(unsigned long __data)
{
struct task_struct * p = (struct task_struct *) __data;
{
#ifdef __SMP__
if ((prev->state == TASK_RUNNING) &&
- (prev != idle_task(smp_processor_id())))
- reschedule_idle(prev);
+ (prev != idle_task(smp_processor_id()))) {
+ unsigned long flags;
+
+ spin_lock_irqsave(&runqueue_lock, flags);
+ reschedule_idle(prev, flags); // spin_unlocks runqueue
+ }
wmb();
prev->has_cpu = 0;
#endif /* __SMP__ */
return;
}
-void __wake_up(wait_queue_head_t *q, unsigned int mode)
+static inline void __wake_up_common(wait_queue_head_t *q, unsigned int mode, const int sync)
{
struct list_head *tmp, *head;
struct task_struct *p;
#if WAITQUEUE_DEBUG
curr->__waker = (long)__builtin_return_address(0);
#endif
- wake_up_process(p);
+ if (sync)
+ wake_up_process_synchronous(p);
+ else
+ wake_up_process(p);
if (state & TASK_EXCLUSIVE)
break;
}
return;
}
+void __wake_up(wait_queue_head_t *q, unsigned int mode)
+{
+ __wake_up_common(q, mode, 0);
+}
+
+void __wake_up_sync(wait_queue_head_t *q, unsigned int mode)
+{
+ __wake_up_common(q, mode, 1);
+}
+
#define SLEEP_ON_VAR \
unsigned long flags; \
wait_queue_t wait; \
struct dentry *dentry = file->f_dentry;
struct inode *inode = dentry->d_inode;
unsigned long limit = current->rlim[RLIMIT_FSIZE].rlim_cur;
- loff_t pos = *ppos;
+ loff_t pos;
struct page *page, **hash, *cached_page;
unsigned long written;
long status;
int err;
- if (pos < 0)
- return -EINVAL;
-
cached_page = NULL;
down(&inode->i_sem);
+
+ pos = *ppos;
+ err = -EINVAL;
+ if (pos < 0)
+ goto out;
+
err = file->f_error;
if (err) {
file->f_error = 0;
totalpages = 0;
for (i = 0; i < MAX_NR_ZONES; i++) {
unsigned long size = zones_size[i];
- if (size & ((1 << MAX_ORDER)-1))
- BUG();
totalpages += size;
}
printk("totalpages: %08x\n", totalpages);
- i = totalpages >> 7;
/*
* Select nr of pages we try to keep free for important stuff
* with a minimum of 10 pages and a maximum of 256 pages, so
zone->free_area[i].map =
(unsigned int *) alloc_bootmem(bitmap_size);
}
- if (zone->size != size)
- BUG();
}
build_zonelists();
}
return;
sk->state = TCP_CLOSE;
- sk->err = reason;
+ sk->err = ECONNRESET;
sk->shutdown |= SEND_SHUTDOWN;
if (!sk->dead) {
sk->state_change(sk);
static int irda_open_tsap(struct irda_sock *self, __u8 tsap_sel, char *name)
{
notify_t notify;
+
+ if (self->tsap) {
+ WARNING(__FUNCTION__ "(), busy!\n");
+ return -EBUSY;
+ }
/* Initialize callbacks to be used by the IrDA stack */
irda_notify_init(¬ify);
¬ify);
if (self->tsap == NULL) {
IRDA_DEBUG( 0, __FUNCTION__ "(), Unable to allocate TSAP!\n");
- return -1;
+ return -ENOMEM;
}
/* Remember which TSAP selector we actually got */
self->stsap_sel = self->tsap->stsap_sel;
* Just move to the listen state
*
*/
-static int irda_listen( struct socket *sock, int backlog)
+static int irda_listen(struct socket *sock, int backlog)
{
struct sock *sk = sock->sk;
+ IRDA_DEBUG(0, __FUNCTION__ "()\n");
+
if (sk->type == SOCK_STREAM && sk->state != TCP_LISTEN) {
sk->max_ack_backlog = backlog;
sk->state = TCP_LISTEN;
__u16 hints = 0;
int err;
+ IRDA_DEBUG(0, __FUNCTION__ "()\n");
+
self = sk->protinfo.irda;
ASSERT(self != NULL, return -1;);
err = irda_open_tsap(self, addr->sir_lsap_sel, addr->sir_name);
if (err < 0)
- return -ENOMEM;
+ return err;
/* Register with LM-IAS */
self->ias_obj = irias_new_object(addr->sir_name, jiffies);
struct irda_sock *self;
int err;
+ IRDA_DEBUG(0, __FUNCTION__ "()\n");
+
self = sk->protinfo.irda;
if (sk->state == TCP_ESTABLISHED && sock->state == SS_CONNECTING) {
return -EPIPE;
}
+ if (sk->state != TCP_ESTABLISHED)
+ return -ENOTCONN;
+
self = sk->protinfo.irda;
ASSERT(self != NULL, return -1;);
msg->msg_namelen = 0;
- /* Lock the socket to prevent queue disordering
- * while sleeps in memcpy_tomsg
- */
-/* down(&self->readsem); */
-
do {
int chunk;
struct sk_buff *skb;
*/
if (sk->err) {
- /* up(&self->readsem); */
return sock_error(sk);
}
if (sk->shutdown & RCV_SHUTDOWN)
break;
- /* up(&self->readsem); */
-
if (noblock)
return -EAGAIN;
irda_data_wait(sk);
if (signal_pending(current))
return -ERESTARTSYS;
- /* down(&self->readsem); */
continue;
}
- /* Never glue messages from different writers */
-/* if (check_creds && */
-/* memcmp(UNIXCREDS(skb), &scm->creds, sizeof(scm->creds)) != 0) */
-/* { */
-/* skb_queue_head(&sk->receive_queue, skb); */
-/* break; */
-/* } */
-
chunk = min(skb->len, size);
if (memcpy_toiovec(msg->msg_iov, skb->data, chunk)) {
skb_queue_head(&sk->receive_queue, skb);
copied += chunk;
size -= chunk;
- /* Copy credentials */
-/* scm->creds = *UNIXCREDS(skb); */
-/* check_creds = 1; */
-
/* Mark read part of skb as used */
if (!(flags & MSG_PEEK)) {
skb_pull(skb, chunk);
-/* if (UNIXCB(skb).fp) */
-/* unix_detach_fds(scm, skb); */
-
/* put the skb back if we didn't use it up.. */
if (skb->len) {
IRDA_DEBUG(1, __FUNCTION__ "(), back on q!\n");
break;
}
- kfree_skb(skb);
-
-/* if (scm->fp) */
-/* break; */
+ kfree_skb(skb);
} else {
IRDA_DEBUG(0, __FUNCTION__ "() questionable!?\n");
- /* It is questionable, see note in unix_dgram_recvmsg. */
-/* if (UNIXCB(skb).fp) */
-/* scm->fp = scm_fp_dup(UNIXCB(skb).fp); */
/* put message back and return */
skb_queue_head(&sk->receive_queue, skb);
}
}
- /* up(&self->readsem); */
-
return copied;
}
*
*
*/
-static int irda_shutdown( struct socket *sk, int how)
+static int irda_shutdown(struct socket *sock, int how)
{
+ struct irda_sock *self;
+ struct sock *sk = sock->sk;
+
IRDA_DEBUG( 0, __FUNCTION__ "()\n");
- /* FIXME - generate DM and RNR states */
- return -EOPNOTSUPP;
+ self = sk->protinfo.irda;
+ ASSERT(self != NULL, return -1;);
+
+ sk->state = TCP_CLOSE;
+ sk->shutdown |= SEND_SHUTDOWN;
+ sk->state_change(sk);
+
+ if (self->iriap)
+ iriap_close(self->iriap);
+
+ if (self->tsap) {
+ irttp_disconnect_request(self->tsap, NULL, P_NORMAL);
+ irttp_close_tsap(self->tsap);
+ self->tsap = NULL;
+ }
+
+ return 0;
}
/*
switch (optname) {
case IRLMP_IAS_SET:
IRDA_DEBUG(0, __FUNCTION__ "(), sorry not impl. yet!\n");
- return 0;
+ return -ENOPROTOOPT;
case IRTTP_MAX_SDU_SIZE:
IRDA_DEBUG(2, __FUNCTION__ "(), setting max_sdu_size = %d\n", opt);
self->max_sdu_size_rx = opt;
break;
case IRTTP_MAX_SDU_SIZE:
val = self->max_data_size;
- IRDA_DEBUG(2, __FUNCTION__ "(), getting max_sdu_size = %d\n", val);
len = sizeof(int);
if (put_user(len, optlen))
return -EFAULT;
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sat Oct 9 09:22:27 1999
- * Modified at: Mon Oct 18 22:40:10 1999
+ * Modified at: Tue Nov 16 12:54:13 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1999 Dag Brattli, All Rights Reserved.
return ret;
}
+int irda_device_change_speed(struct net_device *dev, __u32 speed)
+{
+ struct if_irda_req req;
+ int ret;
+
+ IRDA_DEBUG(0, __FUNCTION__ "()\n");
+
+ if (!dev->do_ioctl) {
+ ERROR(__FUNCTION__ "(), do_ioctl not impl. by "
+ "device driver\n");
+ return -1;
+ }
+
+ req.ifr_baudrate = speed;
+
+ ret = dev->do_ioctl(dev, (struct ifreq *) &req, SIOCSBANDWIDTH);
+
+ return ret;
+}
+
/*
* Function irda_device_is_receiving (dev)
*
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Thu Aug 21 00:02:07 1997
- * Modified at: Sun Oct 31 22:10:45 1999
+ * Modified at: Fri Nov 5 20:25:42 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
* Register some default services for IrLMP
*/
hints = irlmp_service_to_hint(S_COMPUTER);
- hints |= irlmp_service_to_hint(S_PNP);
+ /*hints |= irlmp_service_to_hint(S_PNP);*/
service_handle = irlmp_register_service(hints);
/*
if (self->mode == IAS_CLIENT) {
IRDA_DEBUG(4, __FUNCTION__ "(), disconnect as client\n");
+
+ iriap_do_client_event(self, IAP_LM_DISCONNECT_INDICATION,
+ NULL);
/*
* Inform service user that the request failed by sending
- * it a NULL value.
+ * it a NULL value. Warning, the client might close us, so
+ * remember no to use self anymore after calling confirm
*/
if (self->confirm)
self->confirm(IAS_DISCONNECT, 0, NULL, self->priv);
-
-
- iriap_do_client_event(self, IAP_LM_DISCONNECT_INDICATION,
- NULL);
- /* Close instance only if client */
- /* iriap_close(self); */
-
} else {
IRDA_DEBUG(4, __FUNCTION__ "(), disconnect as server\n");
iriap_do_server_event(self, IAP_LM_DISCONNECT_INDICATION,
/* Finished, close connection! */
iriap_disconnect_request(self);
+ /* Warning, the client might close us, so remember no to use self
+ * anymore after calling confirm
+ */
if (self->confirm)
self->confirm(IAS_SUCCESS, obj_id, value, self->priv);
}
WARNING(__FUNCTION__ "(), No such class!\n");
/* Finished, close connection! */
iriap_disconnect_request(self);
-
+
+ /*
+ * Warning, the client might close us, so remember
+ * no to use self anymore after calling confirm
+ */
if (self->confirm)
self->confirm(IAS_CLASS_UNKNOWN, 0, NULL,
self->priv);
/* Finished, close connection! */
iriap_disconnect_request(self);
+ /*
+ * Warning, the client might close us, so remember
+ * no to use self anymore after calling confirm
+ */
if (self->confirm)
self->confirm(IAS_CLASS_UNKNOWN, 0, NULL,
self->priv);
break;
- }
-
- /* iriap_close(self); */
+ }
break;
default:
IRDA_DEBUG(0, __FUNCTION__ "(), Unknown op-code: %02x\n",
* Status: Stable
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Mon Aug 4 20:40:53 1997
- * Modified at: Fri Oct 8 23:17:36 1999
+ * Modified at: Tue Nov 16 10:01:06 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli, All Rights Reserved.
* Change the speed of the IrDA port
*
*/
-void irlap_change_speed(struct irlap_cb *self, __u32 speed)
+void irlap_change_speed(struct irlap_cb *self, __u32 speed, int now)
{
- IRDA_DEBUG(4, __FUNCTION__ "(), setting speed to %d\n", speed);
+ IRDA_DEBUG(0, __FUNCTION__ "(), setting speed to %d\n", speed);
ASSERT(self != NULL, return;);
ASSERT(self->magic == LAP_MAGIC, return;);
- /* Must use the same speed in both directions */
- self->qos_rx.baud_rate.value = speed;
- self->qos_tx.baud_rate.value = speed;
+ self->speed = speed;
+
+ /* Change speed now, or just piggyback speed on frames */
+ if (now)
+ irda_device_change_speed(self->netdev, speed);
}
#ifdef CONFIG_IRDA_COMPRESSION
* you get when you do a little bit flicking :-)
*/
IRDA_DEBUG(4, __FUNCTION__ "(), comp bits 0x%02x\n",
- self->qos_rx.compression.bits);
+ self->qos_rx.compression.bits);
mask = 0x80; /* Start with testing MSB */
for (i=0;i<8;i++) {
IRDA_DEBUG(4, __FUNCTION__ "(), testing bit %d\n", 8-i);
if (self->qos_rx.compression.bits & mask) {
- IRDA_DEBUG(4, __FUNCTION__ "(), bit %d is set by defalt\n",
- 8-i);
+ IRDA_DEBUG(4, __FUNCTION__
+ "(), bit %d is set by defalt\n", 8-i);
comp = hashbin_find(irlap_compressors,
- compression[ msb_index(mask)],
- NULL);
+ compression[msb_index(mask)],
+ NULL);
if (!comp) {
/* Protocol not supported, so clear the bit */
IRDA_DEBUG(4, __FUNCTION__ "(), Compression "
ASSERT(self != NULL, return;);
ASSERT(self->magic == LAP_MAGIC, return;);
- irlap_change_speed(self, 9600);
+ irlap_change_speed(self, 9600, TRUE);
/* Default value in NDM */
self->bofs_count = 11;
ASSERT(self != NULL, return;);
ASSERT(self->magic == LAP_MAGIC, return;);
- irlap_change_speed(self, qos->baud_rate.value);
+ irlap_change_speed(self, qos->baud_rate.value, FALSE);
self->window_size = qos->window_size.value;
self->window = qos->window_size.value;
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sat Aug 16 00:59:29 1997
- * Modified at: Sun Oct 10 11:14:22 1999
+ * Modified at: Tue Nov 16 12:33:41 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
irlap_connect_indication(self, skb);
} else {
- IRDA_DEBUG(0, __FUNCTION__ "(), SNRM frame does not contain"
- " and I field!\n");
+ IRDA_DEBUG(0, __FUNCTION__
+ "(), SNRM frame does not contain"
+ " and I field!\n");
dev_kfree_skb(skb);
}
break;
irlap_qos_negotiate(self, skb);
- irlap_initiate_connection_state( self);
+ irlap_initiate_connection_state(self);
- /*
- * We are allowed to send two frames!
+#if 0
+ /*
+ * We are allowed to send two frames, but this may increase
+ * the connect latency, so lets not do it for now.
*/
irlap_send_ua_response_frame(self, &self->qos_rx);
- irlap_send_ua_response_frame(self, &self->qos_rx);
-
+#endif
+
+ /*
+ * Applying the parameters now will make sure we change speed
+ * after we have sent the next frame
+ */
irlap_apply_connection_parameters(self, &self->qos_tx);
+ /*
+ * Sending this frame will force a speed change after it has
+ * been sent
+ */
+ irlap_send_ua_response_frame(self, &self->qos_rx);
+
/*
* The WD-timer could be set to the duration of the P-timer
* for this case, but it is recommended to use twice the
* value (note 3 IrLAP p. 60).
*/
irlap_start_wd_timer(self, self->wd_timeout);
- irlap_next_state( self, LAP_NRM_S);
+ irlap_next_state(self, LAP_NRM_S);
break;
case RECV_DISCOVERY_XID_CMD:
- IRDA_DEBUG( 3, __FUNCTION__ "(), event RECV_DISCOVER_XID_CMD!\n");
- irlap_next_state( self, LAP_NDM);
+ IRDA_DEBUG(3, __FUNCTION__ "(), event RECV_DISCOVER_XID_CMD!\n");
+ irlap_next_state(self, LAP_NDM);
break;
case DISCONNECT_REQUEST:
- irlap_send_dm_frame( self);
+ irlap_send_dm_frame(self);
irlap_next_state( self, LAP_CONN);
break;
default:
- IRDA_DEBUG(1, __FUNCTION__ "(), Unknown event %d, %s\n", event,
- irlap_event[event]);
-
+ IRDA_DEBUG(1, __FUNCTION__ "(), Unknown event %d, %s\n", event,
+ irlap_event[event]);
+
if (skb)
dev_kfree_skb(skb);
irlap_apply_connection_parameters(self, &self->qos_tx);
self->retry_count = 0;
- /* This frame will just be sent at the old speed */
- /* irlap_send_rr_frame( self, CMD_FRAME); */
+ /* This frame will actually force the speed change */
+ irlap_send_rr_frame(self, CMD_FRAME);
irlap_start_final_timer(self, self->final_timeout/2);
irlap_next_state(self, LAP_NRM_P);
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Tue Aug 19 10:27:26 1997
- * Modified at: Sat Oct 9 09:42:11 1999
+ * Modified at: Fri Nov 5 09:45:58 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
*/
cb->magic = LAP_MAGIC;
cb->mtt = self->mtt_required;
- cb->speed = self->qos_tx.baud_rate.value;
+ cb->speed = self->speed;
/* Reset */
self->mtt_required = 0;
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Mon Dec 15 13:55:39 1997
- * Modified at: Sun Oct 31 20:31:01 1999
+ * Modified at: Sun Nov 14 08:57:52 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1997, 1999 Dag Brattli, All Rights Reserved.
* Status: Experimental.
* Author: Thomas Davis, <ratbert@radiks.net>
* Created at: Sat Feb 21 21:33:24 1998
- * Modified at: Fri Oct 8 09:26:46 1999
+ * Modified at: Sun Nov 14 08:54:54 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999, Dag Brattli <dagb@cs.uit.no>
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Mon Jun 7 10:25:11 1999
- * Modified at: Tue Oct 5 11:52:54 1999
+ * Modified at: Fri Nov 5 08:20:38 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1999 Dag Brattli, All Rights Reserved.
/* Find expected data type for this parameter identifier (pi)*/
type = pi_minor_info->type;
- IRDA_DEBUG(3, __FUNCTION__ "(), pi=[%d,%d], type=%d\n",
- pi_major, pi_minor, type);
-
/* Check if handler has been implemented */
if (!pi_minor_info->func) {
MESSAGE(__FUNCTION__"(), no handler for pi=%#x\n", pi);
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Tue Sep 9 00:00:26 1997
- * Modified at: Tue Oct 5 11:50:41 1999
+ * Modified at: Tue Nov 16 09:50:19 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
IRDA_DEBUG(2, "Final BAUD_RATE: 0x%04x\n", final);
self->qos_tx.baud_rate.bits = final;
- self->qos_rx.baud_rate.bits = final;
+ self->qos_rx.baud_rate.bits = final;
}
return 0;
projects / history.git / commitdiff