if (unlikely(skb == NULL))
BUG();
- pci_unmap_single(tp->pdev, ri->mapping,
+ pci_unmap_single(tp->pdev,
+ pci_unmap_addr(ri, mapping),
(skb->len - skb->data_len),
PCI_DMA_TODEVICE);
BUG();
pci_unmap_page(tp->pdev,
- ri->mapping,
+ pci_unmap_addr(ri, mapping),
skb_shinfo(skb)->frags[i].size,
PCI_DMA_TODEVICE);
PCI_DMA_FROMDEVICE);
map->skb = skb;
- map->mapping = mapping;
+ pci_unmap_addr_set(map, mapping, mapping);
if (src_map != NULL)
src_map->skb = NULL;
};
dest_map->skb = src_map->skb;
- dest_map->mapping = src_map->mapping;
+ pci_unmap_addr_set(dest_map, mapping,
+ pci_unmap_addr(src_map, mapping));
dest_desc->addr_hi = src_desc->addr_hi;
dest_desc->addr_lo = src_desc->addr_lo;
if (rxp->skb == NULL)
continue;
- pci_unmap_single(tp->pdev, rxp->mapping,
+ pci_unmap_single(tp->pdev,
+ pci_unmap_addr(rxp, mapping),
RX_PKT_BUF_SZ - tp->rx_offset,
PCI_DMA_FROMDEVICE);
dev_kfree_skb(rxp->skb);
if (rxp->skb == NULL)
continue;
- pci_unmap_single(tp->pdev, rxp->mapping,
+ pci_unmap_single(tp->pdev,
+ pci_unmap_addr(rxp, mapping),
RX_MINI_PKT_BUF_SZ - tp->rx_offset,
PCI_DMA_FROMDEVICE);
dev_kfree_skb(rxp->skb);
if (rxp->skb == NULL)
continue;
- pci_unmap_single(tp->pdev, rxp->mapping,
+ pci_unmap_single(tp->pdev,
+ pci_unmap_addr(rxp, mapping),
RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
PCI_DMA_FROMDEVICE);
dev_kfree_skb(rxp->skb);
continue;
}
- pci_unmap_single(tp->pdev, txp->mapping,
+ pci_unmap_single(tp->pdev,
+ pci_unmap_addr(txp, mapping),
(skb->len - skb->data_len),
PCI_DMA_TODEVICE);
txp->skb = NULL;
for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
- pci_unmap_page(tp->pdev, txp->mapping,
+ pci_unmap_page(tp->pdev,
+ pci_unmap_addr(txp, mapping),
skb_shinfo(skb)->frags[j].size,
PCI_DMA_TODEVICE);
i++;
pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
&cacheline_sz_reg);
- tp->pci_cacheline_sz = (cacheline_sz_reg >> 24) & 0xff;
- tp->pci_lat_timer = (cacheline_sz_reg >> 16) & 0xff;
- tp->pci_hdr_type = (cacheline_sz_reg >> 8) & 0xff;
- tp->pci_bist = (cacheline_sz_reg >> 0) & 0xff;
+ tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
+ tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
+ tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
+ tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
+
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
+ tp->pci_lat_timer < 64) {
+ tp->pci_lat_timer = 64;
+
+ cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
+ cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
+ cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
+ cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
+
+ pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
+ cacheline_sz_reg);
+ }
pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
&pci_state_reg);
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
+ return 0;
+
ret = 0;
while (1) {
u32 *p, i;