static char *serial_name = "CPM UART driver";
static char *serial_version = "0.03";
-static DECLARE_TASK_QUEUE(tq_serial);
-
static struct tty_driver serial_driver, callout_driver;
static int serial_refcount;
int serial_console_setup(struct console *co, char *options);
int magic;
int flags;
- struct serial_state *state;
+ struct serial_state *state;
/* struct serial_struct *state; */
/* struct async_struct *state; */
int blocked_open; /* # of blocked opens */
long session; /* Session of opening process */
long pgrp; /* pgrp of opening process */
- struct tq_struct tqueue;
- struct tq_struct tqueue_hangup;
+ struct work_struct tqueue;
+ struct work_struct tqueue_hangup;
wait_queue_head_t open_wait;
wait_queue_head_t close_wait;
-/* struct wait_queue *open_wait; */
-/* struct wait_queue *close_wait;i */
/* CPM Buffer Descriptor pointers.
#elif defined(CONFIG_CONSOLE_115200)
#define CONSOLE_BAUDRATE 115200
#else
- #warn "console baud rate undefined"
+ #warning "console baud rate undefined"
#define CONSOLE_BAUDRATE 9600
#endif
* -----------------------------------------------------------------------
*/
-/*
- * This routine is used by the interrupt handler to schedule
- * processing in the software interrupt portion of the driver.
- */
-static _INLINE_ void rs_sched_event(ser_info_t *info,
- int event)
-{
- info->event |= 1 << event;
- queue_task(&info->tqueue, &tq_serial);
- mark_bh(SERIAL_BH);
-}
-
static _INLINE_ void receive_chars(ser_info_t *info)
{
struct tty_struct *tty = info->tty;
info->rx_cur = (QUICC_BD *)bdp;
- queue_task(&tty->flip.tqueue, &tq_timer);
+ schedule_work(&tty->flip.work);
}
static _INLINE_ void receive_break(ser_info_t *info)
*(tty->flip.char_buf_ptr++) = 0;
tty->flip.count++;
- queue_task(&tty->flip.tqueue, &tq_timer);
+ schedule_work(&tty->flip.work);
}
static _INLINE_ void transmit_chars(ser_info_t *info)
if ((info->flags & TX_WAKEUP) ||
(info->tty->flags & (1 << TTY_DO_WRITE_WAKEUP))) {
- rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
+ schedule_work(&info->tqueue);
}
#ifdef SERIAL_DEBUG_INTR
* -------------------------------------------------------------------
*/
-/*
- * This routine is used to handle the "bottom half" processing for the
- * serial driver, known also the "software interrupt" processing.
- * This processing is done at the kernel interrupt level, after the
- * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
- * is where time-consuming activities which can not be done in the
- * interrupt driver proper are done; the interrupt driver schedules
- * them using rs_sched_event(), and they get done here.
- */
-static void do_serial_bh(void)
-{
- run_task_queue(&tq_serial);
-}
static void do_softint(void *private_)
{
}
-
-
/*
* This routine is called from the scheduler tqueue when the interrupt
* routine has signalled that a hangup has occurred. The path of
tty_hangup(tty);
}
-/*static void rs_360_timer(void)
-{
- printk("rs_360_timer\n");
-}*/
-
static int startup(ser_info_t *info)
{
*/
char_time = 1;
if (timeout)
- char_time = min(char_time, timeout);
+ char_time = min(char_time, (unsigned long)timeout);
#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
printk("jiff=%lu...", jiffies);
ser_info_t *info;
int retval, line;
- line = MINOR(tty->device) - tty->driver.minor_start;
+ line = minor(tty->device) - tty->driver.minor_start;
if ((line < 0) || (line >= NR_PORTS))
return -ENODEV;
retval = get_async_struct(line, &info);
volatile struct uart_pram *sup;
/* volatile immap_t *immap; */
- init_bh(SERIAL_BH, do_serial_bh);
-
show_serial_version();
/* Initialize the tty_driver structure */
/* info = kmalloc(sizeof(ser_info_t), GFP_KERNEL); */
info = &quicc_ser_info[i];
if (info) {
- /* __clear_user(info,sizeof(ser_info_t)); */
memset (info, 0, sizeof(ser_info_t));
- init_waitqueue_head(&info->open_wait);
- init_waitqueue_head(&info->close_wait);
info->magic = SERIAL_MAGIC;
- info->flags = state->flags;
- info->tqueue.routine = do_softint;
- info->tqueue.data = info;
- info->tqueue_hangup.routine = do_serial_hangup;
- info->tqueue_hangup.data = info;
info->line = i;
+ info->flags = state->flags;
+ INIT_WORK(&info->tqueue, do_softint, info);
+ INIT_WORK(&info->tqueue_hangup, do_serial_hangup, info);
+ init_waitqueue_head(&info->open_wait);
+ init_waitqueue_head(&info->close_wait);
info->state = state;
state->info = (struct async_struct *)info;
*(uint *)_periph_base = sipex_mode_bits;
/* printk ("sipex bits = 0x%08x\n", sipex_mode_bits); */
#endif
-
- scp = &pquicc->scc_regs[idx];
- sup = &pquicc->pram[info->state->port].scc.pscc.u;
- sup->rbase = dp_addr;
- }
- else {
- sp = &cp->smc_regs[idx];
- up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
- up->rbase = dp_addr;
}
dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * TX_NUM_FIFO);
bdp->status = (BD_SC_WRAP | BD_SC_INTRPT);
if (info->state->smc_scc_num & NUM_IS_SCC) {
+ scp = &pquicc->scc_regs[idx];
+ sup = &pquicc->pram[info->state->port].scc.pscc.u;
+ sup->rbase = dp_addr;
sup->tbase = dp_addr;
/* Set up the uart parameters in the
/* Configure SMCs Tx/Rx instead of port B
* parallel I/O.
*/
+ up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
+ up->rbase = dp_addr;
iobits = 0xc0 << (idx * 4);
cp->pip_pbpar |= iobits;
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
+ sp = &cp->smc_regs[idx];
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
/* Disable all interrupts and clear all pending
int serial_console_setup( struct console *co, char *options)
{
struct serial_state *ser;
- uint mem_addr, dp_addr, bidx, idx, iobits;
- int i;
+ uint mem_addr, dp_addr, bidx, idx, iobits;
ushort chan;
QUICC_BD *bdp;
volatile QUICC *cp;
idx = PORT_NUM(ser->smc_scc_num);
if (ser->smc_scc_num & NUM_IS_SCC) {
- scp = &cp->scc_regs[idx];
- /* sup = (scc_uart_t *)&cp->cp_dparam[ser->port]; */
- sup = &pquicc->pram[ser->port].scc.pscc.u;
/* TODO: need to set up SCC pin assignment etc. here */
}
else {
- sp = &cp->smc_regs[idx];
- /* up = (smc_uart_t *)&cp->cp_dparam[ser->port]; */
- up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
-
iobits = 0xc0 << (idx * 4);
cp->pip_pbpar |= iobits;
cp->pip_pbdir &= ~iobits;
/* Set up the uart parameters in the parameter ram.
*/
if (ser->smc_scc_num & NUM_IS_SCC) {
+ scp = &cp->scc_regs[idx];
+ /* sup = (scc_uart_t *)&cp->cp_dparam[ser->port]; */
+ sup = &pquicc->pram[ser->port].scc.pscc.u;
sup->rbase = dp_addr;
sup->tbase = dp_addr + sizeof(QUICC_BD);
}
else {
+ /* up = (smc_uart_t *)&cp->cp_dparam[ser->port]; */
+ up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
+
up->rbase = dp_addr; /* Base of receive buffer desc. */
up->tbase = dp_addr+sizeof(QUICC_BD); /* Base of xmt buffer desc. */
up->rfcr = SMC_EB;
*/
chan = smc_chan_map[idx];
cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
- printk("");
while (cp->cp_cr & CPM_CR_FLG);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
+ sp = &cp->smc_regs[idx];
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
/* And finally, enable Rx and Tx.