#define MD_4232 5
#define MD_C930 6
#define MD_IWAVE 7
-#define MD_4235 8 /* Crystal Audio CS4235 */
+#define MD_4235 8 /* Crystal Audio CS4235 */
+#define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
/* Mixer parameters */
int recmask;
static int nr_ad1848_devs = 0;
int deskpro_xl = 0;
+int deskpro_m = 0;
#ifdef CONFIG_SOUND_SPRO
int soundpro = 1;
#else
#endif
-static int ad_format_mask[9 /*devc->model */ ] =
+static int ad_format_mask[10 /*devc->model */ ] =
{
0,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
- AFMT_U8 | AFMT_S16_LE /* CS4235 */
+ AFMT_U8 | AFMT_S16_LE /* CS4235 */,
+ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/
};
static ad1848_info adev_info[MAX_AUDIO_DEV];
static struct {
unsigned char flags;
#define CAP_F_TIMER 0x01
-} capabilities [9 /*devc->model */ ] = {
+} capabilities [10 /*devc->model */ ] = {
{0}
,{0} /* MD_1848 */
,{CAP_F_TIMER} /* MD_4231 */
,{CAP_F_TIMER} /* MD_4232 */
,{0} /* MD_C930 */
,{CAP_F_TIMER} /* MD_IWAVE */
- ,{0} /* MD_4235 */
+ ,{0} /* MD_4235 */
+ ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
};
static int ad1848_open(int dev, int mode);
while (timeout > 0 && (ad_read(devc, 11) & 0x20))
timeout--;
if (ad_read(devc, 11) & 0x20)
- if (devc->model != MD_1845)
+ if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
}
case MD_4231:
case MD_4231A:
case MD_1845:
+ case MD_1845_SSCAPE:
devc->supported_devices = MODE2_MIXER_DEVICES;
break;
if (arg <= 0)
return portc->speed;
- if (devc->model == MD_1845) /* AD1845 has different timer than others */
+ if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
{
if (arg < 4000)
arg = 4000;
ad_enter_MCE(devc); /* Enables changes to the format select reg */
- if (devc->model == MD_1845) /* Use alternate speed select registers */
+ if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
{
fs &= 0xf0; /* Mask off the rate select bits */
ad_enter_MCE(devc); /* Enables changes to the format select reg */
- if (devc->model == MD_1845) /* Use alternate speed select registers */
+ if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
{
fs &= 0xf0; /* Mask off the rate select bits */
while (timeout < 10000 && inb(devc->base) == 0x80)
timeout++;
- if (devc->model != MD_1848 && devc->model != MD_1845)
+ if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
{
/*
* CS4231 compatible devices don't have separate sampling rate selection
if (devc->model > MD_1848)
{
- ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
+ if (devc->model == MD_1845_SSCAPE)
+ ad_write(devc, 12, ad_read(devc, 12) | 0x50);
+ else
+ ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
if (devc->model == MD_IWAVE)
ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
- for (i = 16; i < 32; i++)
- ad_write(devc, i, init_values[i]);
+ if (devc-> model != MD_1845_SSCAPE)
+ for (i = 16; i < 32; i++)
+ ad_write(devc, i, init_values[i]);
if (devc->model == MD_IWAVE)
ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
else
ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
- if (devc->model == MD_1845)
+ if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
if (devc->model == MD_IWAVE)
int interwave = 0;
int ad1847_flag = 0;
int cs4248_flag = 0;
+ int sscape_flag = 0;
int i;
interwave = 1;
*ad_flags = 0;
}
+
+ if (*ad_flags == 0x87654321)
+ {
+ sscape_flag = 1;
+ *ad_flags = 0;
+ }
+
if (*ad_flags == 0x12345677)
{
cs4248_flag = 1;
devc->chip_name = "AD1847";
+ if (sscape_flag == 1)
+ devc->model = MD_1845_SSCAPE;
+
return 1;
}
switch (cmd)
{
case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
- if (devc->model != MD_1845)
+ if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
return -EINVAL;
ad_enter_MCE(devc);
ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
}
}
+/*
+ * Experimental initialization sequence for the integrated sound system
+ * of the Compaq Deskpro M.
+ */
+
+static int init_deskpro_m(struct address_info *hw_config)
+{
+ unsigned char tmp;
+
+ if ((tmp = inb(0xc44)) == 0xff)
+ {
+ DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
+ return 0;
+ }
+
+ outb(0x10, 0xc44);
+ outb(0x40, 0xc45);
+ outb(0x00, 0xc46);
+ outb(0xe8, 0xc47);
+ outb(0x14, 0xc44);
+ outb(0x40, 0xc45);
+ outb(0x00, 0xc46);
+ outb(0xe8, 0xc47);
+ outb(0x10, 0xc44);
+
+ return 1;
+}
+
/*
* Experimental initialization sequence for the integrated sound system
* of Compaq Deskpro XL.
return 0;
}
+ if (deskpro_m) /* Compaq Deskpro M */
+ {
+ if (!init_deskpro_m(hw_config))
+ return 0;
+ }
+
/*
* Check if the IO port returns valid signature. The original MS Sound
* system returns 0x04 while some cards (AudioTrix Pro for example)
* the timer divider.
*/
- if (devc->model == MD_1845)
+ if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
xtal_nsecs = 10050;
else if (ad_read(devc, 8) & 0x01)
xtal_nsecs = 9920;
MODULE_PARM(dma2, "i"); /* Second DMA channel */
MODULE_PARM(type, "i"); /* Card type */
MODULE_PARM(deskpro_xl, "i"); /* Special magic for Deskpro XL boxen */
+MODULE_PARM(deskpro_m, "i"); /* Special magic for Deskpro M box */
MODULE_PARM(soundpro, "i"); /* More special magic for SoundPro chips */
int io = -1;
*
* Low level driver for Ensoniq SoundScape
*/
-
/*
* Copyright (C) by Hannu Savolainen 1993-1997
*
* Version 2 (June 1991). See the "COPYING" file distributed with this software
* for more info.
*/
-
+
/*
- * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
+ * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
+ * Sergey Smitienko : ensoniq p'n'p support
*/
#include <linux/config.h>
#include "sound_config.h"
#include "soundmodule.h"
+#include "sound_firmware.h"
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/fcntl.h>
+#include <linux/ctype.h>
+#include <linux/stddef.h>
+#include <linux/kmod.h>
+#ifdef __KERNEL__
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/segment.h>
+#include <linux/wait.h>
+#include <linux/malloc.h>
+#include <linux/ioport.h>
+#endif /* __KERNEL__ */
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+
#ifdef CONFIG_SSCAPE
#define CMD_GET_BOARD_TYPE 0x82
#define CMD_SET_CONTROL 0x88 /* Old firmware only */
#define CMD_GET_CONTROL 0x89 /* Old firmware only */
-#define CTL_MASTER_VOL 0
-#define CTL_MIC_MODE 2
-#define CTL_SYNTH_VOL 4
-#define CTL_WAVE_VOL 7
+#define CTL_MASTER_VOL 0
+#define CTL_MIC_MODE 2
+#define CTL_SYNTH_VOL 4
+#define CTL_WAVE_VOL 7
#define CMD_SET_EXTMIDI 0x8a
#define CMD_GET_EXTMIDI 0x8b
#define CMD_SET_MT32 0x8c
#define CMD_ACK 0x80
+#define IC_ODIE 1
+#define IC_OPUS 2
+
typedef struct sscape_info
{
int base, irq, dma;
+
+ int codec, codec_irq; /* required to setup pnp cards*/
+ int codec_type;
+ int ic_type;
+ char* raw_buf;
+ unsigned long raw_buf_phys;
+ int buffsize; /* -------------------------- */
+
int ok; /* Properly detected */
int failed;
int dma_allocated;
restore_flags(flags);
}
+static unsigned char sscape_pnp_read_codec(sscape_info* devc, unsigned char reg)
+{
+ unsigned char res;
+ unsigned long flags;
+
+ save_flags(flags);
+ cli();
+ outb( reg, devc -> codec);
+ res = inb (devc -> codec + 1);
+ restore_flags(flags);
+ return res;
+
+}
+
+static void sscape_pnp_write_codec(sscape_info* devc, unsigned char reg, unsigned char data)
+{
+ unsigned long flags;
+
+ save_flags(flags);
+ cli();
+ outb( reg, devc -> codec);
+ outb( data, devc -> codec + 1);
+ restore_flags(flags);
+}
+
static void host_open(struct sscape_info *devc)
{
outb((0x00), PORT(HOST_CTRL)); /* Put the board to the host mode */
return data;
}
+static int host_command1(struct sscape_info *devc, int cmd)
+{
+ unsigned char buf[10];
+ buf[0] = (unsigned char) (cmd & 0xff);
+ return host_write(devc, buf, 1);
+}
+
static int host_command2(struct sscape_info *devc, int cmd, int parm1)
{
};
static int sscape_detected = 0;
+static int sscape_is_pnp = 0;
void attach_sscape(struct address_info *hw_config)
{
*/
#define SSCAPE_REGS { \
/* I0 */ 0x00, \
- 0xf0, /* Note! Ignored. Set always to 0xf0 */ \
- 0x20, /* Note! Ignored. Set always to 0x20 */ \
- 0x20, /* Note! Ignored. Set always to 0x20 */ \
- 0xf5, /* Ignored */ \
- 0x10, \
- 0x00, \
- 0x2e, /* I7 MEM config A. Likely to vary between models */ \
- 0x00, /* I8 MEM config B. Likely to vary between models */ \
+/* I1 */ 0xf0, /* Note! Ignored. Set always to 0xf0 */ \
+/* I2 */ 0x20, /* Note! Ignored. Set always to 0x20 */ \
+/* I3 */ 0x20, /* Note! Ignored. Set always to 0x20 */ \
+/* I4 */ 0xf5, /* Ignored */ \
+/* I5 */ 0x10, \
+/* I6 */ 0x00, \
+/* I7 */ 0x2e, /* I7 MEM config A. Likely to vary between models */ \
+/* I8 */ 0x00, /* I8 MEM config B. Likely to vary between models */ \
/* I9 */ 0x40 /* Ignored */ \
}
#endif
printk(KERN_ERR "Invalid IRQ%d\n", hw_config->irq);
return;
}
- save_flags(flags);
- cli();
-
- for (i = 1; i < 10; i++)
- {
+
+ if (sscape_is_pnp == 0) {
+
+ save_flags(flags);
+ cli();
+ for (i = 1; i < 10; i++)
+ {
switch (i)
{
case 1: /* Host interrupt enable */
default:
sscape_write(devc, i, regs[i]);
}
+ }
+ restore_flags(flags);
}
- restore_flags(flags);
-
#ifdef SSCAPE_DEBUG2
/*
* Temporary debugging aid. Print contents of the registers after
return 1;
}
+static int sscape_read_host_ctrl(sscape_info* devc)
+{
+ return host_read(devc);
+}
+
+static void sscape_write_host_ctrl2(sscape_info *devc, int a, int b)
+{
+ host_command2(devc, a, b);
+}
+
+static int sscape_alloc_dma(sscape_info *devc)
+{
+ char *start_addr, *end_addr;
+ int i, dma_pagesize;
+ int sz, size;
+
+ if (devc->raw_buf != NULL) return 0; /* Already done */
+ dma_pagesize = (devc->dma < 4) ? (64 * 1024) : (128 * 1024);
+ devc->raw_buf = NULL;
+ devc->buffsize = 8192*4;
+ if (devc->buffsize > dma_pagesize) devc->buffsize = dma_pagesize;
+ start_addr = NULL;
+ /*
+ * Now loop until we get a free buffer. Try to get smaller buffer if
+ * it fails. Don't accept smaller than 8k buffer for performance
+ * reasons.
+ */
+ while (start_addr == NULL && devc->buffsize > PAGE_SIZE) {
+ for (sz = 0, size = PAGE_SIZE; size < devc->buffsize; sz++, size <<= 1);
+ devc->buffsize = PAGE_SIZE * (1 << sz);
+ start_addr = (char *) __get_free_pages(GFP_ATOMIC|GFP_DMA, sz);
+ if (start_addr == NULL) devc->buffsize /= 2;
+ }
+
+ if (start_addr == NULL) {
+ printk(KERN_ERR "sscape pnp init error: Couldn't allocate DMA buffer\n");
+ return 0;
+ } else {
+ /* make some checks */
+ end_addr = start_addr + devc->buffsize - 1;
+ /* now check if it fits into the same dma-pagesize */
+
+ if (((long) start_addr & ~(dma_pagesize - 1)) != ((long) end_addr & ~(dma_pagesize - 1))
+ || end_addr >= (char *) (MAX_DMA_ADDRESS)) {
+ printk(KERN_ERR "sscape pnp: Got invalid address 0x%lx for %db DMA-buffer\n", (long) start_addr, devc->buffsize);
+ return 0;
+ }
+ }
+ devc->raw_buf = start_addr;
+ devc->raw_buf_phys = virt_to_bus(start_addr);
+
+ for (i = MAP_NR(start_addr); i <= MAP_NR(end_addr); i++)
+ set_bit(PG_reserved, &mem_map[i].flags);;
+ return 1;
+}
+
+static void sscape_free_dma(sscape_info *devc)
+{
+ int sz, size, i;
+ unsigned long start_addr, end_addr;
+
+ if (devc->raw_buf == NULL) return;
+ for (sz = 0, size = PAGE_SIZE; size < devc->buffsize; sz++, size <<= 1);
+ start_addr = (unsigned long) devc->raw_buf;
+ end_addr = start_addr + devc->buffsize;
+
+ for (i = MAP_NR(start_addr); i <= MAP_NR(end_addr); i++)
+ clear_bit(PG_reserved, &mem_map[i].flags);;
+
+ free_pages((unsigned long) devc->raw_buf, sz);
+ devc->raw_buf = NULL;
+}
+
+/* Intel version !!!!!!!!! */
+
+static int sscape_start_dma(int chan, unsigned long physaddr, int count, int dma_mode)
+{
+ unsigned long flags;
+
+ flags = claim_dma_lock();
+ disable_dma(chan);
+ clear_dma_ff(chan);
+ set_dma_mode(chan, dma_mode);
+ set_dma_addr(chan, physaddr);
+ set_dma_count(chan, count);
+ enable_dma(chan);
+ release_dma_lock(flags);
+ return 0;
+}
+
+static void sscape_pnp_start_dma(sscape_info* devc, int arg )\r
+{
+ int reg;
+ if (arg == 0) reg = 2;
+ else reg = 3;
+
+ sscape_write(devc, reg, sscape_read( devc, reg) | 0x01);
+ sscape_write(devc, reg, sscape_read( devc, reg) & 0xFE);
+}
+
+static int sscape_pnp_wait_dma (sscape_info* devc, int arg )
+{
+ int reg;
+ unsigned long i;
+ unsigned char d;
+
+ if (arg == 0) reg = 2;
+ else reg = 3;
+
+ sleep ( 1 );
+ i = 0;
+ do {
+ d = sscape_read(devc, reg) & 1;
+ if ( d == 1) break;
+ i++;
+ } while (i < 500000);
+ d = sscape_read(devc, reg) & 1;
+ return d;
+}
+
+static int sscape_pnp_alloc_dma(sscape_info* devc)
+{
+ /* printk(KERN_INFO "sscape: requesting dma\n"); */
+ if (request_dma(devc -> dma, "sscape")) return 0;
+ /* printk(KERN_INFO "sscape: dma channel allocated\n"); */
+ if (!sscape_alloc_dma(devc)) {
+ free_dma(devc -> dma);
+ return 0;
+ };
+ return 1;
+}
+
+static void sscape_pnp_free_dma(sscape_info* devc)
+{
+ sscape_free_dma( devc);
+ free_dma(devc -> dma );
+ /* printk(KERN_INFO "sscape: dma released\n"); */
+}
+
+static int sscape_pnp_upload_file(sscape_info* devc, char* fn)
+{
+ int done = 0;
+ int timeout_val;
+ char* data,*dt;
+ int len,l;
+ unsigned long flags;
+
+ sscape_write( devc, 9, sscape_read(devc, 9 ) & 0x3F );
+ sscape_write( devc, 2, (devc -> dma << 4) | 0x80 );
+ sscape_write( devc, 3, 0x20 );
+ sscape_write( devc, 9, sscape_read( devc, 9 ) | 0x80 );
+
+ len = mod_firmware_load(fn, &data);
+ if (len == 0) {
+ printk(KERN_ERR "sscape: file not found: %s\n", fn);
+ return 0;
+ }
+ dt = data;
+ save_flags(flags);
+ cli();
+ while ( len > 0 ) {
+ if (len > devc -> buffsize) l = devc->buffsize;
+ else l = len;
+ len -= l;
+ memcpy(devc->raw_buf, dt, l); dt += l;
+ sscape_start_dma(devc->dma, devc->raw_buf_phys, l, 0x48);
+ sscape_pnp_start_dma ( devc, 0 );
+ if (sscape_pnp_wait_dma ( devc, 0 ) == 0) return 0;
+ }
+
+ restore_flags(flags);
+ vfree(data);
+
+ outb(0, devc -> base + 2);\r
+ outb(0, devc -> base);\r
+
+ sscape_write ( devc, 9, sscape_read( devc, 9 ) | 0x40);
+
+ timeout_val = 5 * HZ;
+ while (!done && timeout_val-- > 0)
+ {
+ unsigned char x;
+ sleep(1);
+ x = inb( devc -> base + 3);
+ if (x == 0xff || x == 0xfe) /* OBP startup acknowledge */
+ {
+ //printk(KERN_ERR "Soundscape: Acknowledge = %x\n", x);
+ done = 1;
+ }
+ }
+ timeout_val = 5 * HZ;
+ done = 0;
+ while (!done && timeout_val-- > 0)
+ {
+ unsigned char x;
+ sleep(1);
+ x = inb( devc -> base + 3);
+ if (x == 0xfe) /* OBP startup acknowledge */
+ {
+ //printk(KERN_ERR "Soundscape: Acknowledge = %x\n", x);
+ done = 1;
+ }
+ }
+
+ if ( !done ) printk(KERN_ERR "soundscape: OBP Initialization failed.\n");
+
+ sscape_write( devc, 2, devc->ic_type == IC_ODIE ? 0x70 : 0x40);
+ sscape_write( devc, 3, (devc -> dma << 4) + 0x80);
+ return 1;
+}
+
+static void sscape_pnp_init_hw(sscape_info* devc)
+{
+ unsigned char midi_irq = 0, sb_irq = 0;
+ unsigned i;
+ static char code_file_name[23] = "/sndscape/sndscape.cox";
+
+ int sscape_sb_enable = 0;
+ int sscape_joystic_enable = 0x7f;
+ int sscape_mic_enable = 0;
+ int sscape_ext_midi = 0;
+
+ if ( !sscape_pnp_alloc_dma(devc) ) {
+ printk(KERN_ERR "sscape: faild to allocate dma\n");
+ return;
+ }
+
+ for (i = 0; i < 4; i++) {
+ if ( devc -> irq == valid_interrupts[i] )
+ midi_irq = i;
+ if ( devc -> codec_irq == valid_interrupts[i] )
+ sb_irq = i;
+ }
+
+ sscape_write( devc, 5, 0x50);
+ sscape_write( devc, 7, 0x2e);
+ sscape_write( devc, 8, 0x00);
+
+ sscape_write( devc, 2, devc->ic_type == IC_ODIE ? 0x70 : 0x40);
+ sscape_write( devc, 3, ( devc -> dma << 4) | 0x80);
+
+ if ( sscape_sb_enable )
+ sscape_write (devc, 4, 0xF0 | (sb_irq << 2) | midi_irq);
+ else
+ sscape_write (devc, 4, 0xF0 | (midi_irq<<2) | midi_irq);
+
+ i = 0x10; //sscape_read(devc, 9) & (devc->ic_type == IC_ODIE ? 0xf0 : 0xc0);
+ if ( sscape_sb_enable )
+ i |= devc->ic_type == IC_ODIE ? 0x05 : 0x07;
+ if (sscape_joystic_enable) i |= 8;
+
+ sscape_write (devc, 9, i);
+ sscape_write (devc, 6, 0x80);
+ sscape_write (devc, 1, 0x80);
+
+ if (devc -> codec_type == 2) {
+ sscape_pnp_write_codec( devc, 0x0C, 0x50);
+ sscape_pnp_write_codec( devc, 0x10, sscape_pnp_read_codec( devc, 0x10) & 0x3F);
+ sscape_pnp_write_codec( devc, 0x11, sscape_pnp_read_codec( devc, 0x11) | 0xC0);
+ sscape_pnp_write_codec( devc, 29, 0x20);
+ }
+
+ if (sscape_pnp_upload_file(devc, "/sndscape/scope.cod") == 0 ) {
+ printk(KERN_ERR "sscape: faild to upload file /sndscape/scope.cod\n");
+ sscape_pnp_free_dma(devc);
+ return;
+ }
+
+ i = sscape_read_host_ctrl( devc );
+
+ if ( (i & 0x0F) > 7 ) {
+ printk(KERN_ERR "sscape: scope.cod faild\n");
+ sscape_pnp_free_dma(devc);
+ return;
+ }
+ if ( i & 0x10 ) sscape_write( devc, 7, 0x2F);
+ code_file_name[21] = (char) ( i & 0x0F) + 0x30;
+ if (sscape_pnp_upload_file( devc, code_file_name) == 0) {
+ printk(KERN_ERR "sscape: faild to upload file %s\n", code_file_name);
+ sscape_pnp_free_dma(devc);
+ return;
+ }
+
+ if (devc->ic_type != IC_ODIE) {
+ sscape_pnp_write_codec( devc, 10, (sscape_pnp_read_codec(devc, 10) & 0x7f) |
+ ( sscape_mic_enable == 0 ? 0x00 : 0x80) );
+ }
+ sscape_write_host_ctrl2( devc, 0x84, 0x32 );
+ sscape_write_host_ctrl2( devc, 0x86, 0x32 );
+ sscape_write_host_ctrl2( devc, 0x8A, sscape_ext_midi);
+
+ sscape_pnp_write_codec ( devc, 6, 0x3f ); //WAV_VOL
+ sscape_pnp_write_codec ( devc, 7, 0x3f ); //WAV_VOL
+ sscape_pnp_write_codec ( devc, 2, 0x1F ); //WD_CDXVOLL
+ sscape_pnp_write_codec ( devc, 3, 0x1F ); //WD_CDXVOLR
+
+ if (devc -> codec_type == 1) {
+ sscape_pnp_write_codec ( devc, 4, 0x1F );
+ sscape_pnp_write_codec ( devc, 5, 0x1F );
+ sscape_write_host_ctrl2( devc, 0x88, sscape_mic_enable);
+ } else {
+ int t;
+ sscape_pnp_write_codec ( devc, 0x10, 0x1F << 1);
+ sscape_pnp_write_codec ( devc, 0x11, 0xC0 | (0x1F << 1));
+
+ t = sscape_pnp_read_codec( devc, 0x00) & 0xDF;
+ if ( (sscape_mic_enable == 0)) t |= 0;
+ else t |= 0x20;
+ sscape_pnp_write_codec ( devc, 0x00, t);
+ t = sscape_pnp_read_codec( devc, 0x01) & 0xDF;
+ if ( (sscape_mic_enable == 0) ) t |= 0;
+ else t |= 0x20;
+ sscape_pnp_write_codec ( devc, 0x01, t);
+ sscape_pnp_write_codec ( devc, 0x40 | 29 , 0x20);
+ outb(0, devc -> codec);
+ }
+ if (devc -> ic_type == IC_OPUS ) {
+ int i = sscape_read( devc, 9 );
+ sscape_write( devc, 9, i | 3 );
+ sscape_write( devc, 3, 0x40);
+
+ if (check_region(0x228, 1)) {
+ outb(0, 0x228);
+ release_region(0x228,1);
+ }
+ sscape_write( devc, 3, (devc -> dma << 4) | 0x80);
+ sscape_write( devc, 9, i );
+ }
+
+ host_close ( devc );
+ sscape_pnp_free_dma(devc);
+}
+
+static int detect_sscape_pnp(sscape_info* devc)
+{
+ long i, irq_bits = 0xff;
+ unsigned int d;
+
+ DDB(printk("Entered detect_sscape_pnp(%x)\n", devc->base));
+
+ if (check_region(devc->base, 8)) {
+ printk(KERN_ERR "detect_sscape_pnp: port %x is not free\n", devc->base);
+ return 0;
+ }
+
+ if (check_region(devc->codec, 2)) {
+ printk(KERN_ERR "detect_sscape_pnp: port %x is not free\n", devc->codec);
+ return 0;
+ }
+
+ if ( (inb( devc -> base + 2) & 0x78) != 0) return 0;
+
+ d = inb ( devc -> base + 4) & 0xF0;
+ if ( (d & 0x80) != 0) return 0;
+
+ if (d == 0) {
+ devc->codec_type = 1;
+ devc->ic_type = IC_ODIE;
+ }
+ else if ( (d & 0x60) != 0) {
+ devc->codec_type = 2;
+ devc->ic_type = IC_OPUS;
+ }
+ else if ( (d & 0x40) != 0) {
+ devc->codec_type = 2;
+ devc->ic_type = IC_ODIE;
+ }
+ else return 0;
+
+ sscape_is_pnp = 1;
+
+ outb(0xFA, devc -> base+4);
+ if ((inb( devc -> base+4) & 0x9F) != 0x0A)
+ return 0;
+ outb(0xFE, devc -> base+4);
+ if ( (inb(devc -> base+4) & 0x9F) != 0x0E)
+ return 0;
+ if ( (inb(devc -> base+5) & 0x9F) != 0x0E)
+ return 0;
+
+ if (devc->codec_type == 2) {
+ if (devc -> codec != devc -> base + 8)
+ printk("soundscape warning: incorrect codec port specified\n");
+ devc -> codec = devc -> base + 8;
+ d = 0x10 | (sscape_read(devc, 9) & 0xCF);
+ sscape_write(devc, 9, d);
+ sscape_write(devc, 6, 0x80);
+ } else {
+ //todo: check codec is not base + 8
+ }
+
+ d = (sscape_read(devc, 9) & 0x3F) | 0xC0;
+ sscape_write(devc, 9, d);
+
+ for (i = 0; i < 550000; i++)
+ if ( !(inb(devc -> codec) & 0x80) ) break;
+
+ d = inb(devc -> codec);
+ if (d & 0x80)
+ return 0;
+ if ( inb(devc -> codec + 2) == 0xFF)
+ return 0;
+
+ sscape_write(devc, 9, sscape_read(devc, 9) & 0x3F );
+
+ d = inb(devc -> codec) & 0x80;
+ if ( d == 0) {
+ printk(KERN_INFO "soundscape: hardware detected\n");
+ valid_interrupts = valid_interrupts_new;
+ } else {
+ printk(KERN_INFO "soundscape: board looks like media fx\n");
+ valid_interrupts = valid_interrupts_old;
+ old_hardware = 1;
+ }
+
+ sscape_write( devc, 9, 0xC0 | (sscape_read(devc, 9) & 0x3F) );
+
+ for (i = 0; i < 550000; i++)
+ if ( !(inb(devc -> codec) & 0x80))
+ break;
+
+ sscape_pnp_init_hw(devc);
+
+ for (i = 0; i < sizeof(valid_interrupts); i++)
+ {
+ if (devc->codec_irq == valid_interrupts[i]) {
+ irq_bits = i;
+ break;
+ }
+ }
+ sscape_write(devc, GA_INTENA_REG, 0x00);
+ sscape_write(devc, GA_DMACFG_REG, 0x50);
+ sscape_write(devc, GA_DMAA_REG, 0x70);
+ sscape_write(devc, GA_DMAB_REG, 0x20);
+ sscape_write(devc, GA_INTCFG_REG, 0xf0);
+ sscape_write(devc, GA_CDCFG_REG, 0x89 | (devc->dma << 4) | (irq_bits << 1));
+
+ sscape_pnp_write_codec( devc, 0, sscape_pnp_read_codec( devc, 0) | 0x20);
+ sscape_pnp_write_codec( devc, 0, sscape_pnp_read_codec( devc, 1) | 0x20);
+
+ release_region(devc->codec, 2);
+ release_region(devc->base, 8);
+
+ return 1;
+}
+
int probe_sscape(struct address_info *hw_config)
{
#endif
devc->failed = 1;
- if (!detect_ga(devc))
- return 0;
+ if (!detect_ga(devc)) {
+ if (detect_sscape_pnp(devc)) {
+ sscape_detected = hw_config->io_base;
+ return 1;
+ }
+ else return 0;
+ }
if (old_hardware) /* Check that it's really an old Spea/Reveal card. */
{
{
int i, irq_bits = 0xff;
int ad_flags = 0;
-
+
if (devc->failed)
{
- printk(KERN_ERR "soundscape: Card not detected\n");
- return 0;
+ printk(KERN_ERR "soundscape: Card not detected\n");
+ return 0;
}
if (devc->ok == 0)
{
printk(KERN_ERR "soundscape: Invalid MSS IRQ%d\n", hw_config->irq);
return 0;
}
- if (old_hardware)
- ad_flags = 0x12345677; /* Tell that we may have a CS4248 chip (Spea-V7 Media FX) */
- return ad1848_detect(hw_config->io_base, &ad_flags, hw_config->osp);
+
+ if (!sscape_is_pnp) {
+ if (old_hardware)
+ ad_flags = 0x12345677; /* Tell that we may have a CS4248 chip (Spea-V7 Media FX) */
+ return ad1848_detect(hw_config->io_base, &ad_flags, hw_config->osp);
+ }
+ else {
+ if (old_hardware)
+ ad_flags = 0x12345677; /* Tell that we may have a CS4248 chip (Spea-V7 Media FX) */
+ else
+ ad_flags = 0x87654321; /* Tell that we have a soundscape pnp with 1845 chip */
+ return ad1848_detect(hw_config->io_base, &ad_flags, hw_config->osp);
+ }
}
void attach_ss_ms_sound(struct address_info *hw_config)
int i, irq_bits = 0xff;
- hw_config->dma = devc->dma; /* Share the DMA with the ODIE/OPUS chip */
-
- /*
- * Setup the DMA polarity.
- */
-
- sscape_write(devc, GA_DMACFG_REG, 0x50);
-
- /*
- * Take the gate-array off of the DMA channel.
- */
-
- sscape_write(devc, GA_DMAB_REG, 0x20);
-
- /*
- * Init the AD1848 (CD-ROM) config reg.
- */
-
- for (i = 0; i < sizeof(valid_interrupts); i++)
- {
- if (hw_config->irq == valid_interrupts[i])
- {
- irq_bits = i;
- break;
- }
- }
- sscape_write(devc, GA_CDCFG_REG, 0x89 | (hw_config->dma << 4) | (irq_bits << 1));
-
- if (hw_config->irq == devc->irq)
- printk(KERN_WARNING "soundscape: Warning! The WSS mode can't share IRQ with MIDI\n");
-
- hw_config->slots[0] = ad1848_init("SoundScape", hw_config->io_base,
- hw_config->irq,
- hw_config->dma,
- hw_config->dma,
- 0,
- devc->osp);
-
+
+ if (!sscape_is_pnp) /*pnp is already setup*/
+ {
+ /*
+ * Setup the DMA polarity.
+ */
+ sscape_write(devc, GA_DMACFG_REG, 0x50);
+
+ /*
+ * Take the gate-array off of the DMA channel.
+ */
+ sscape_write(devc, GA_DMAB_REG, 0x20);
+
+ /*
+ * Init the AD1848 (CD-ROM) config reg.
+ */
+ for (i = 0; i < sizeof(valid_interrupts); i++)
+ {
+ if (hw_config->irq == valid_interrupts[i])
+ {
+ irq_bits = i;
+ break;
+ }
+ }
+ sscape_write(devc, GA_CDCFG_REG, 0x89 | (hw_config->dma << 4) | (irq_bits << 1));
+ }
+
+ if (hw_config->irq == devc->irq)
+ printk(KERN_WARNING "soundscape: Warning! The WSS mode can't share IRQ with MIDI\n");
+
+ if (! sscape_is_pnp )
+ hw_config->slots[0] = ad1848_init("SoundScape", hw_config->io_base,
+ hw_config->irq,
+ hw_config->dma,
+ hw_config->dma,
+ 0,
+ devc->osp);
+
+ else
+ hw_config->slots[0] = ad1848_init("SoundScape PNP", hw_config->io_base,
+ hw_config->irq,
+ hw_config->dma,
+ hw_config->dma,
+ 0,
+ devc->osp);
+
if (hw_config->slots[0] != -1) /* The AD1848 driver installed itself */
{
audio_devs[hw_config->slots[0]]->coproc = &sscape_coproc_operations;
/* Set proper routings here (what are they) */
AD1848_REROUTE(SOUND_MIXER_LINE1, SOUND_MIXER_LINE);
}
+
#ifdef SSCAPE_DEBUG5
/*
* Temporary debugging aid. Print contents of the registers
printk(KERN_ERR "CONFIG_MPU_IRQ must be specified if CONFIG_MPU_IO is set.\n");
return -EINVAL;
}
+
+ devc->codec = io;
+ devc->codec_irq = irq;
+ devc->codec_type = 0;
+ devc->ic_type = 0;
+ devc->raw_buf = NULL;
+
config.irq = irq;
config.dma = dma;
config.io_base = io;
* 23-Jul-1999: Fixed small fragment security exposure opened on 15-May-1998.
* John McDonald <jm@dataprotect.com>
* Thomas Lopatic <tl@dataprotect.com>
- * 21-Oct-1999: Use bh, not interrupt locking. --RR
- * Applied count fix by Emanuele Caratti <wiz@iol.it>
*/
/*
*
- * The original Linux port was done Alan Cox, with changes/fixes from
+ * The origina Linux port was done Alan Cox, with changes/fixes from
* Pauline Middlelink, Jos Vos, Thomas Quinot, Wouter Gadeyne, Juan
* Jose Ciarlante, Bernd Eckenfels, Keith Owens and others.
*
static struct sock *ipfwsk;
#endif
-/* Don't call SLOT_NUMBER when you have a write lock. */
#ifdef __SMP__
#define SLOT_NUMBER() (cpu_number_map[smp_processor_id()]*2 + !in_interrupt())
#else
__FILE__, __LINE__, SLOT_NUMBER()); \
} while (0)
-#define FWC_NOINT() \
-do { \
- if (in_interrupt()) \
- printk("Rusty, you promised! %s %u\n", __FILE__, __LINE__); \
-} while(0)
#else
#define FWC_DEBUG_LOCK(d) do { } while(0)
#define FWC_DEBUG_UNLOCK(d) do { } while(0)
#define FWC_DONT_HAVE_LOCK(d) do { } while(0)
#define FWC_HAVE_LOCK(d) do { } while(0)
-#define FWC_NOINT() do { } while(0)
#endif /*DEBUG_IP_FIRWALL_LOCKING*/
-/* We never to a write lock in bh, so we only need write_lock_bh */
#define FWC_READ_LOCK(l) do { FWC_DEBUG_LOCK(fwc_rlocks); read_lock(l); } while (0)
-/* Debug after lock obtained, (in_interrupt() will be true there), so
- SLOT_NUMBER consistent. */
-#define FWC_WRITE_LOCK(l) do { FWC_NOINT(); write_lock_bh(l); FWC_DEBUG_LOCK(fwc_wlocks); } while (0)
+#define FWC_WRITE_LOCK(l) do { FWC_DEBUG_LOCK(fwc_wlocks); write_lock(l); } while (0)
+#define FWC_READ_LOCK_IRQ(l,f) do { FWC_DEBUG_LOCK(fwc_rlocks); read_lock_irqsave(l,f); } while (0)
+#define FWC_WRITE_LOCK_IRQ(l,f) do { FWC_DEBUG_LOCK(fwc_wlocks); write_lock_irqsave(l,f); } while (0)
#define FWC_READ_UNLOCK(l) do { FWC_DEBUG_UNLOCK(fwc_rlocks); read_unlock(l); } while (0)
-#define FWC_WRITE_UNLOCK(l) do { FWC_DEBUG_UNLOCK(fwc_wlocks); write_unlock_bh(l); } while (0)
+#define FWC_WRITE_UNLOCK(l) do { FWC_DEBUG_UNLOCK(fwc_wlocks); write_unlock(l); } while (0)
+#define FWC_READ_UNLOCK_IRQ(l,f) do { FWC_DEBUG_UNLOCK(fwc_rlocks); read_unlock_irqrestore(l,f); } while (0)
+#define FWC_WRITE_UNLOCK_IRQ(l,f) do { FWC_DEBUG_UNLOCK(fwc_wlocks); write_unlock_irqrestore(l,f); } while (0)
struct ip_chain;
{
struct ip_chain *prevchain; /* Pointer to referencing chain */
struct ip_fwkernel *prevrule; /* Pointer to referencing rule */
- unsigned int count;
struct ip_counters counters;
};
else FWC_HAVE_LOCK(fwc_rlocks);
f = chain->chain;
- count = 0;
do {
+ count = 0;
for (; f; f = f->next) {
count++;
if (ip_rule_match(f,rif,ip,
else {
f->branch->reent[slot].prevchain
= chain;
- f->branch->reent[slot].count = count;
f->branch->reent[slot].prevrule
= f->next;
chain = f->branch;
f = chain->chain;
- count = 0;
}
}
else if (f->simplebranch == FW_SKIP)
if (chain->reent[slot].prevchain) {
struct ip_chain *tmp = chain;
f = chain->reent[slot].prevrule;
- count = chain->reent[slot].count;
chain = chain->reent[slot].prevchain;
tmp->reent[slot].prevchain = NULL;
}
{
int ret;
struct ip_chain *chain;
+ unsigned long flags;
- FWC_WRITE_LOCK(&ip_fw_lock);
+ FWC_WRITE_LOCK_IRQ(&ip_fw_lock, flags);
switch (cmd) {
case IP_FW_FLUSH:
struct iphdr *ip;
/* Don't need write lock. */
- FWC_WRITE_UNLOCK(&ip_fw_lock);
+ FWC_WRITE_UNLOCK_IRQ(&ip_fw_lock, flags);
if (len != sizeof(struct ip_fwtest) || !check_label(m))
return EINVAL;
ret = EINVAL;
}
- FWC_WRITE_UNLOCK(&ip_fw_lock);
+ FWC_WRITE_UNLOCK_IRQ(&ip_fw_lock, flags);
return ret;
}
{
struct ip_chain *i;
struct ip_fwkernel *j = ip_fw_chains->chain;
+ unsigned long flags;
int len = 0;
int last_len = 0;
off_t upto = 0;
duprintf("ip_fw_chains is 0x%0lX\n", (unsigned long int)ip_fw_chains);
/* Need a write lock to lock out ``readers'' which update counters. */
- FWC_WRITE_LOCK(&ip_fw_lock);
+ FWC_WRITE_LOCK_IRQ(&ip_fw_lock, flags);
for (i = ip_fw_chains; i; i = i->next) {
for (j = i->chain; j; j = j->next) {
}
}
outside:
- FWC_WRITE_UNLOCK(&ip_fw_lock);
+ FWC_WRITE_UNLOCK_IRQ(&ip_fw_lock, flags);
buffer[len] = '\0';
duprintf("ip_chain_procinfo: Length = %i (of %i). Offset = %li.\n",
struct ip_chain *i;
int len = 0,last_len = 0;
off_t pos = 0,begin = 0;
+ unsigned long flags;
/* Need a write lock to lock out ``readers'' which update counters. */
- FWC_WRITE_LOCK(&ip_fw_lock);
+ FWC_WRITE_LOCK_IRQ(&ip_fw_lock, flags);
for (i = ip_fw_chains; i; i = i->next)
{
last_len = len;
}
- FWC_WRITE_UNLOCK(&ip_fw_lock);
+ FWC_WRITE_UNLOCK_IRQ(&ip_fw_lock, flags);
*start = buffer+(offset-begin);
len-=(offset-begin);
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