June 12, 2001
-Status of peripherals in -rmk tree
-----------------------------------
+Status of peripherals in -rmk tree (updated 14/10/2001)
+-------------------------------------------------------
Assabet:
Serial ports:
- Radio: TX, RX, CTS, DSR, DCD, RI
- COM: TX, RX, CTS, DSR, DCD, RTS, DTR, PM
- I2C: TX, RX
- L3: No
+ Radio: TX, RX, CTS, DSR, DCD, RI
+ PM: Not tested.
+ COM: TX, RX, CTS, DSR, DCD, RTS, DTR, PM
+ PM: Not tested.
+ I2C: Implemented, not fully tested.
+ L3: Fully tested, pass.
+ PM: Not tested.
Video:
- LCD: PM
- Video out: Not fully
- Touchscreen: No
+ LCD: Fully tested. PM
+ (LCD doesn't like being blanked with
+ neponset connected)
+ Video out: Not fully
Audio:
- Codec: No
- POTS: No
+ UDA1341:
+ Playback: Fully tested, pass.
+ Record: Implemented, not tested.
+ PM: Not tested.
+
+ UCB1200:
+ Audio play: Implemented, not heavily tested.
+ Audio rec: Implemented, not heavily tested.
+ Telco audio play: Implemented, not heavily tested.
+ Telco audio rec: Implemented, not heavily tested.
+ POTS control: No
+ Touchscreen: Yes
+ PM: Not tested.
Other:
- PCMCIA: Yes
- USB: No
+ PCMCIA:
+ LPE: Fully tested, pass.
+ USB: No
+ IRDA:
+ SIR: Fully tested, pass.
+ FIR: Fully tested, pass.
+ PM: Not tested.
Neponset:
Serial ports:
COM1,2: TX, RX, CTS, DSR, DCD, RTS, DTR
+ PM: Not tested.
+ USB: Implemented, not heavily tested.
+ PCMCIA: Implemented, not heavily tested.
+ PM: Not tested.
+ CF: Implemented, not heavily tested.
+ PM: Not tested.
More stuff can be found in the -np (Nicolas Pitre's) tree.
r: relaxed, case insensitive
n: normal, default setting, currently case insensitive
-nocase -- Returning with having the 8.3 format alias kept in
- the disk. Default, return lowercase letter.
+shortname=lower|win95|winnt|mixed
+ -- Shortname display/create setting.
+ lower: convert to lowercase for display,
+ emulate the Windows 95 rule for create.
+ win95: emulate the Windows 95 rule for display/create.
+ winnt: emulate the Windows NT rule for display/create.
+ mixed: emulate the Windows NT rule for display,
+ emulate the Windows 95 rule for create.
+ Default setting is `lower'.
<bool>: 0,1,yes,no,true,false
Disclaimer
----------
-THIS DRIVER IS A DEVELOPMENT RELEASE FOR A DEVELOPMENT KERNEL. DO NOT
-USE IN A PRODUCTION ENVIRONMENT.
-
DO NOT CONTACT DONALD BECKER FOR SUPPORT OF THIS DRIVER, his driver is
completely different and maintained independently of the 8139too code base.
Tested Adapters
---------------
AOpen ALN-325C
+AT-2500TX 10/100 PCI Fast Ethernet Network Adapter Card
KTI KF-230TX
KTI KF-230TX/2
Lantech FastNet TX
L: linux-hams@vger.kernel.org
S: Maintained
-8139TOO ETHERNET DRIVER
+8139CP 10/100 FAST ETHERNET DRIVER
+P: Jeff Garzik
+M: jgarzik@mandrakesoft.com
+S: Maintained
+
+8139TOO 10/100 FAST ETHERNET DRIVER
P: Jeff Garzik
M: jgarzik@mandrakesoft.com
W: http://sourceforge.net/projects/gkernel/
L: Linux-Kernel@vger.kernel.org
S: Maintained
+i386 SETUP CODE / CPU ERRATA WORKAROUNDS
+P: Dave Jones
+M: davej@suse.de
+P: H. Peter Anvin
+M: hpa@zytor.com
+S: Maintained
+
i810 TCO TIMER WATCHDOG
P: Nils Faerber
M: nils@kernelconcepts.de
VERSION = 2
PATCHLEVEL = 4
SUBLEVEL = 14
-EXTRAVERSION =-pre1
+EXTRAVERSION =-pre2
KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
return ret;
}
+
+/* Get an address range which is currently unmapped. Similar to the
+ generic version except that we know how to honor ADDR_LIMIT_32BIT. */
+
+static unsigned long
+arch_get_unmapped_area_1(unsigned long addr, unsigned long len,
+ unsigned long limit)
+{
+ struct vm_area_struct *vma = find_vma(current->mm, addr);
+
+ while (1) {
+ /* At this point: (!vma || addr < vma->vm_end). */
+ if (limit - len < addr)
+ return -ENOMEM;
+ if (!vma || addr + len <= vma->vm_start)
+ return addr;
+ addr = vma->vm_end;
+ vma = vma->vm_next;
+ }
+}
+
+unsigned long
+arch_get_unmapped_area(struct file *filp, unsigned long addr,
+ unsigned long len, unsigned long pgoff,
+ unsigned long flags)
+{
+ unsigned long limit;
+
+ /* "32 bit" actually means 31 bit, since pointers sign extend. */
+ if (current->personality & ADDR_LIMIT_32BIT)
+ limit = 0x80000000;
+ else
+ limit = TASK_SIZE;
+
+ if (len > limit)
+ return -ENOMEM;
+
+ /* First, see if the given suggestion fits. */
+ if (addr) {
+ struct vm_area_struct *vma;
+
+ addr = PAGE_ALIGN(addr);
+ vma = find_vma(current->mm, addr);
+ if (limit - len >= addr &&
+ (!vma || addr + len <= vma->vm_start))
+ return addr;
+ }
+
+ /* Next, try allocating at TASK_UNMAPPED_BASE. */
+ addr = arch_get_unmapped_area_1 (PAGE_ALIGN(TASK_UNMAPPED_BASE),
+ len, limit);
+ if (addr != -ENOMEM)
+ return addr;
+
+ /* Finally, try allocating in low memory. */
+ addr = arch_get_unmapped_area_1 (PAGE_SIZE, len, limit);
+
+ return addr;
+}
CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \
Co-EBSA285 CONFIG_ARCH_CO285 \
EBSA-110 CONFIG_ARCH_EBSA110 \
+ Epxa10db CONFIG_ARCH_CAMELOT \
FootBridge CONFIG_ARCH_FOOTBRIDGE \
Integrator CONFIG_ARCH_INTEGRATOR \
LinkUp-L7200 CONFIG_ARCH_L7200 \
dep_bool ' Brutus' CONFIG_SA1100_BRUTUS $CONFIG_ARCH_SA1100
dep_bool ' CerfBoard' CONFIG_SA1100_CERF $CONFIG_ARCH_SA1100
if [ "$CONFIG_SA1100_CERF" = "y" ]; then
- bool ' 32MB Cerf support' CONFIG_SA1100_CERF_32MB
+ choice 'Cerf RAM available' \
+ "8MB CONFIG_SA1100_CERF_8MB \
+ 16MB CONFIG_SA1100_CERF_16MB \
+ 32MB CONFIG_SA1100_CERF_32MB \
+ 64MB CONFIG_SA1100_CERF_64MB" CerfRam
+ choice 'Cerf Flash available' \
+ "8MB CONFIG_SA1100_CERF_FLASH_8MB \
+ 16MB CONFIG_SA1100_CERF_FLASH_16MB \
+ 32MB CONFIG_SA1100_CERF_FLASH_32MB" CerfFlash
+ bool 'Cerf w/CPLD support (CerfPDA)' CONFIG_SA1100_CERF_CPLD
fi
dep_bool ' Compaq iPAQ H3600' CONFIG_SA1100_H3600 $CONFIG_ARCH_SA1100
#dep_bool ' Empeg' CONFIG_SA1100_EMPEG $CONFIG_ARCH_SA1100
"$CONFIG_ARCH_TBOX" = "y" -o "$CONFIG_ARCH_SHARK" = "y" -o \
"$CONFIG_ARCH_NEXUSPCI" = "y" -o "$CONFIG_ARCH_CLPS711X" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" -o "$CONFIG_ARCH_SA1100" = "y" -o \
- "$CONFIG_ARCH_L7200" = "y" -o "$CONFIG_ARCH_ANAKIN" = "y" ]; then
+ "$CONFIG_ARCH_L7200" = "y" -o "$CONFIG_ARCH_ANAKIN" = "y" -o \
+ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
define_bool CONFIG_CPU_32v4 y
else
define_bool CONFIG_CPU_32v4 n
"$CONFIG_ARCH_CATS" = "y" -o \
"$CONFIG_ARCH_P720T" = "y" -o \
"$CONFIG_ARCH_CDB89712" = "y" -o \
+ "$CONFIG_ARCH_CAMELOT" = "y" -o \
"$CONFIG_ARCH_ANAKIN" = "y" ]; then
string 'Default kernel command string' CONFIG_CMDLINE ""
fi
bool 'Verbose kernel error messages' CONFIG_DEBUG_ERRORS
bool 'Verbose user fault messages' CONFIG_DEBUG_USER
bool 'Include debugging information in kernel binary' CONFIG_DEBUG_INFO
+bool 'Debug memory allocations' CONFIG_DEBUG_SLAB
bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
+bool 'Spinlock debugging' CONFIG_DEBUG_SPINLOCK
dep_bool 'Disable pgtable cache' CONFIG_NO_PGT_CACHE $CONFIG_CPU_26
# These options are only for real kernel hackers who want to get their hands dirty.
dep_bool 'Kernel low-level debugging functions' CONFIG_DEBUG_LL $CONFIG_EXPERIMENTAL
--- /dev/null
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+CONFIG_SA1100_ADSBITSY=y
+CONFIG_SA1111=y
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+CONFIG_DISCONTIGMEM=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="ip=off"
+# CONFIG_PFS168_CMDLINE is not set
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=y
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_KEYBDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+CONFIG_UCB1200=y
+CONFIG_TOUCHSCREEN_UCB1200=y
+CONFIG_AUDIO_UCB1200=y
+CONFIG_ADC_UCB1200=y
+# CONFIG_TOUCHSCREEN_BITSY is not set
+# CONFIG_PROFILER is not set
+# CONFIG_PFS168_SPI is not set
+# CONFIG_PFS168_DTMF is not set
+# CONFIG_PFS168_MISC is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_JOYSTICK is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_SA1100_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_SA1100=y
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_E1355 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+CONFIG_FBCON_FONTWIDTH8_ONLY=y
+CONFIG_FBCON_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+CONFIG_USB_OHCI_NOPCI=y
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_KBD is not set
+CONFIG_USB_MOUSE=y
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_DABUSB is not set
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_NET1080 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
#
# Code maturity level options
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_L7200 is not set
#
CONFIG_SA1100_ASSABET=y
# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_EXTENEX1 is not set
# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
# CONFIG_SA1100_ITSY is not set
#
# CLPS711X/EP721X Implementations
#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
# CONFIG_CPU_ARM1020 is not set
# CONFIG_CPU_SA110 is not set
CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
CONFIG_DISCONTIGMEM=y
-# CONFIG_CPU_BIG_ENDIAN is not set
#
# General setup
#
# CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
# CONFIG_ISA_DMA is not set
CONFIG_CPU_FREQ=y
CONFIG_HOTPLUG=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_FASTFPE is not set
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_PM=y
-# CONFIG_APM is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE=""
-# CONFIG_PFS168_CMDLINE is not set
CONFIG_LEDS=y
CONFIG_LEDS_TIMER=y
CONFIG_LEDS_CPU=y
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_I4 is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_JEDEC is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_SUN_UFLASH is not set
# CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_TQM8XXL is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_NETSC520 is not set
-# CONFIG_MTD_SBC_GXX is not set
-# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
CONFIG_MTD_SA1100=y
-CONFIG_MTD_SA1100_REDBOOT_PARTITIONS=y
-# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
# CONFIG_MTD_DC21285 is not set
# CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_DBOX2 is not set
-# CONFIG_MTD_CSTM_MIPS_IXX is not set
-# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SOLUTIONENGINE is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
-# CONFIG_MTD_OCELOT is not set
-# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_PCI is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_LART is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
#
# Block devices
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
# CONFIG_BLK_DEV_DAC960 is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
+# CONFIG_ARM_AM79C961A is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_WINBOND_FIR is not set
# CONFIG_TOSHIBA_FIR is not set
# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
CONFIG_SA1100_FIR=m
#
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
# Input core support
#
# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
#
# Character devices
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_SERIAL_21285 is not set
-# CONFIG_SERIAL_21285_OLD is not set
-# CONFIG_SERIAL_21285_CONSOLE is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
# CONFIG_SERIAL_AMBA is not set
# CONFIG_SERIAL_AMBA_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X is not set
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
CONFIG_SA1100_DEFAULT_BAUDRATE=38400
CONFIG_SERIAL_8250=m
# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=32
-CONFIG_UCB1200=y
-CONFIG_TOUCHSCREEN_UCB1200=y
-# CONFIG_AUDIO_UCB1200 is not set
-CONFIG_ADC_UCB1200=y
-# CONFIG_TOUCHSCREEN_BITSY is not set
-# CONFIG_PROFILER is not set
-# CONFIG_PFS168_SPI is not set
-# CONFIG_PFS168_DTMF is not set
-# CONFIG_PFS168_MISC is not set
#
# I2C support
#
# CONFIG_I2C is not set
+#
+# L3 serial bus support
+#
+CONFIG_L3=y
+CONFIG_L3_ALGOBIT=y
+CONFIG_L3_BIT_SA1100_GPIO=y
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+CONFIG_BIT_SA1100_GPIO=y
+
#
# Mice
#
#
# Joysticks
#
-# CONFIG_JOYSTICK is not set
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
#
# Input core support is needed for joysticks
#
# PCMCIA character devices
#
+CONFIG_PCMCIA_SERIAL_CS=m
+# CONFIG_MWAVE is not set
#
# Multimedia devices
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
-CONFIG_JFFS_FS_VERBOSE=0
+# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_CRAMFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
# CONFIG_MINIX_FS is not set
-# CONFIG_VXFS_FS is not set
+# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# Network File Systems
#
# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_ROOT_NFS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
#
# Partition Types
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
# CONFIG_FB_CLPS711X is not set
-# CONFIG_FB_CYBER2000 is not set
CONFIG_FB_SA1100=y
-# CONFIG_FB_ANAKIN is not set
-# CONFIG_FB_E1355 is not set
+# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FBCON_ADVANCED is not set
CONFIG_FBCON_CFB2=y
# Sound
#
CONFIG_SOUND=y
-CONFIG_SOUND_ASSABET_UDA1341=y
-# CONFIG_SOUND_BITSY_UDA1341 is not set
-# CONFIG_SOUND_SA1111_UDA1341 is not set
-# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=y
+CONFIG_SOUND_UDA1341=y
+CONFIG_SOUND_ASSABET_UDA1341=y
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_TVMIXER is not set
+#
+# Multimedia Capabilities Port drivers
+#
+CONFIG_MCP=y
+CONFIG_MCP_SA1100=y
+CONFIG_MCP_UCB1200=y
+CONFIG_MCP_UCB1200_AUDIO=m
+CONFIG_MCP_UCB1200_TS=y
+
#
# USB support
#
# CONFIG_USB is not set
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
#
# Bluetooth support
#
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_SLAB is not set
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_NO_PGT_CACHE is not set
# CONFIG_DEBUG_LL is not set
# CONFIG_DEBUG_DC21285_PORT is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-#
-CONFIG_ARM=y
-# CONFIG_EISA is not set
-# CONFIG_SBUS is not set
-# CONFIG_MCA is not set
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-# CONFIG_OBSOLETE is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_KMOD is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_ANAKIN is not set
-# CONFIG_ARCH_ARCA5K is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_RPC is not set
-CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_SHARK is not set
-
-#
-# Archimedes/A5000 Implementations
-#
-
-#
-# Archimedes/A5000 Implementations (select only ONE)
-#
-# CONFIG_ARCH_ARC is not set
-# CONFIG_ARCH_A5K is not set
-
-#
-# Footbridge Implementations
-#
-# CONFIG_ARCH_CATS is not set
-# CONFIG_ARCH_PERSONAL_SERVER is not set
-# CONFIG_ARCH_EBSA285_ADDIN is not set
-# CONFIG_ARCH_EBSA285_HOST is not set
-# CONFIG_ARCH_NETWINDER is not set
-
-#
-# SA11x0 Implementations
-#
-# CONFIG_SA1100_ASSABET is not set
-# CONFIG_ASSABET_NEPONSET is not set
-# CONFIG_SA1100_BRUTUS is not set
-# CONFIG_SA1100_CERF is not set
-CONFIG_SA1100_BITSY=y
-# CONFIG_SA1100_EXTENEX1 is not set
-# CONFIG_SA1100_FLEXANET is not set
-# CONFIG_SA1100_FREEBIRD is not set
-# CONFIG_SA1100_GRAPHICSCLIENT is not set
-# CONFIG_SA1100_JORNADA720 is not set
-# CONFIG_SA1100_HUW_WEBPANEL is not set
-# CONFIG_SA1100_ITSY is not set
-# CONFIG_SA1100_LART is not set
-# CONFIG_SA1100_NANOENGINE is not set
-# CONFIG_SA1100_OMNIMETER is not set
-# CONFIG_SA1100_PANGOLIN is not set
-# CONFIG_SA1100_PLEB is not set
-# CONFIG_SA1100_SHERMAN is not set
-# CONFIG_SA1100_SIMPAD is not set
-# CONFIG_SA1100_PFS168 is not set
-# CONFIG_SA1100_VICTOR is not set
-# CONFIG_SA1100_XP860 is not set
-# CONFIG_SA1100_YOPY is not set
-CONFIG_SA1100_USB=m
-CONFIG_SA1100_USB_NETLINK=m
-# CONFIG_SA1100_USB_CHAR is not set
-
-#
-# CLPS711X/EP721X Implementations
-#
-# CONFIG_ARCH_P720T is not set
-# CONFIG_ARCH_ACORN is not set
-# CONFIG_FOOTBRIDGE is not set
-# CONFIG_FOOTBRIDGE_HOST is not set
-# CONFIG_FOOTBRIDGE_ADDIN is not set
-CONFIG_CPU_32=y
-# CONFIG_CPU_26 is not set
-
-#
-# Processor Type
-#
-# CONFIG_CPU_32v3 is not set
-CONFIG_CPU_32v4=y
-# CONFIG_CPU_ARM610 is not set
-# CONFIG_CPU_ARM710 is not set
-# CONFIG_CPU_ARM720T is not set
-# CONFIG_CPU_ARM920T is not set
-# CONFIG_CPU_ARM1020 is not set
-# CONFIG_CPU_SA110 is not set
-CONFIG_CPU_SA1100=y
-CONFIG_DISCONTIGMEM=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-
-#
-# General setup
-#
-# CONFIG_PCI is not set
-# CONFIG_ISA is not set
-# CONFIG_ISA_DMA is not set
-CONFIG_CPU_FREQ=y
-CONFIG_HOTPLUG=y
-
-#
-# PCMCIA/CardBus support
-#
-CONFIG_PCMCIA=y
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-# CONFIG_PCMCIA_CLPS6700 is not set
-CONFIG_PCMCIA_SA1100=y
-CONFIG_NET=y
-CONFIG_SYSVIPC=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_FASTFPE is not set
-CONFIG_KCORE_ELF=y
-# CONFIG_KCORE_AOUT is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_PM=y
-CONFIG_APM=m
-# CONFIG_ARTHUR is not set
-CONFIG_CMDLINE=""
-# CONFIG_PFS168_CMDLINE is not set
-# CONFIG_LEDS is not set
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BOOTLDR_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_JEDEC is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_SUN_UFLASH is not set
-# CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_TQM8XXL is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_NETSC520 is not set
-# CONFIG_MTD_SBC_GXX is not set
-# CONFIG_MTD_ELAN_104NC is not set
-# CONFIG_MTD_SA1100 is not set
-# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
-# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
-# CONFIG_MTD_DC21285 is not set
-# CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_DBOX2 is not set
-# CONFIG_MTD_CSTM_MIPS_IXX is not set
-# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SOLUTIONENGINE is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
-# CONFIG_MTD_OCELOT is not set
-# CONFIG_MTD_L440GX is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_LART is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Plug and Play configuration
-#
-# CONFIG_PNP is not set
-# CONFIG_ISAPNP is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_XD is not set
-# CONFIG_PARIDE is not set
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-# CONFIG_BLK_DEV_MD is not set
-# CONFIG_MD_LINEAR is not set
-# CONFIG_MD_RAID0 is not set
-# CONFIG_MD_RAID1 is not set
-# CONFIG_MD_RAID5 is not set
-# CONFIG_BLK_DEV_LVM is not set
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_FILTER is not set
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_INET_ECN is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_IPV6 is not set
-# CONFIG_KHTTPD is not set
-# CONFIG_ATM is not set
-
-#
-#
-#
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_DECNET is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_LLC is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_FASTROUTE is not set
-# CONFIG_NET_HW_FLOWCONTROL is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-# CONFIG_MYRI_SBUS is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PLIP is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPPOE is not set
-# CONFIG_SLIP is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-# CONFIG_NET_FC is not set
-# CONFIG_RCPCI is not set
-# CONFIG_SHAPER is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-
-#
-# PCMCIA network device support
-#
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=y
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_ARCNET_COM20020_CS is not set
-# CONFIG_PCMCIA_IBMTR is not set
-# CONFIG_NET_PCMCIA_RADIO is not set
-
-#
-# Amateur Radio support
-#
-# CONFIG_HAMRADIO is not set
-
-#
-# IrDA (infrared) support
-#
-# CONFIG_IRDA is not set
-
-#
-# ATA/IDE/MFM/RLL support
-#
-CONFIG_IDE=m
-
-#
-# IDE, ATA and ATAPI Block devices
-#
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_HD_IDE is not set
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
-# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
-# CONFIG_BLK_DEV_IDEDISK_IBM is not set
-# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
-# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
-# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
-# CONFIG_BLK_DEV_IDEDISK_WD is not set
-# CONFIG_BLK_DEV_COMMERIAL is not set
-# CONFIG_BLK_DEV_TIVO is not set
-# CONFIG_BLK_DEV_IDECS is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_CMD640 is not set
-# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
-# CONFIG_BLK_DEV_ISAPNP is not set
-# CONFIG_IDE_CHIPSETS is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_DMA_NONPCI is not set
-# CONFIG_BLK_DEV_IDE_MODES is not set
-
-#
-# SCSI support
-#
-# CONFIG_SCSI is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-# CONFIG_I2O_BLOCK is not set
-# CONFIG_I2O_LAN is not set
-# CONFIG_I2O_SCSI is not set
-# CONFIG_I2O_PROC is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input core support
-#
-# CONFIG_INPUT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_VT_CONSOLE is not set
-CONFIG_SERIAL=m
-# CONFIG_SERIAL_EXTENDED is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_SERIAL_21285 is not set
-# CONFIG_SERIAL_21285_OLD is not set
-# CONFIG_SERIAL_21285_CONSOLE is not set
-# CONFIG_SERIAL_AMBA is not set
-# CONFIG_SERIAL_AMBA_CONSOLE is not set
-# CONFIG_SERIAL_CLPS711X is not set
-# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_SA1100_DEFAULT_BAUDRATE=38400
-CONFIG_SERIAL_8250=m
-# CONFIG_SERIAL_8250_CONSOLE is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=32
-# CONFIG_UCB1200 is not set
-# CONFIG_TOUCHSCREEN_UCB1200 is not set
-# CONFIG_AUDIO_UCB1200 is not set
-# CONFIG_ADC_UCB1200 is not set
-CONFIG_TOUCHSCREEN_BITSY=y
-CONFIG_PROFILER=m
-# CONFIG_PFS168_SPI is not set
-# CONFIG_PFS168_DTMF is not set
-# CONFIG_PFS168_MISC is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Mice
-#
-# CONFIG_BUSMOUSE is not set
-CONFIG_MOUSE=m
-# CONFIG_PSMOUSE is not set
-# CONFIG_82C710_MOUSE is not set
-# CONFIG_PC110_PAD is not set
-
-#
-# Joysticks
-#
-# CONFIG_JOYSTICK is not set
-
-#
-# Input core support is needed for joysticks
-#
-# CONFIG_QIC02_TAPE is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-CONFIG_SA1100_RTC=m
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_FTAPE is not set
-# CONFIG_AGP is not set
-# CONFIG_DRM is not set
-
-#
-# PCMCIA character devices
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# File systems
-#
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_ADFS_FS is not set
-# CONFIG_ADFS_FS_RW is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_BFS_FS is not set
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-# CONFIG_UMSDOS_FS is not set
-CONFIG_VFAT_FS=m
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
-CONFIG_JFFS_FS_VERBOSE=2
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_CRAMFS=m
-# CONFIG_TMPFS is not set
-CONFIG_RAMFS=y
-# CONFIG_ISO9660_FS is not set
-# CONFIG_JOLIET is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_NTFS_FS is not set
-# CONFIG_NTFS_RW is not set
-# CONFIG_HPFS_FS is not set
-CONFIG_PROC_FS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
-CONFIG_DEVPTS_FS=y
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_QNX4FS_RW is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_EXT2_FS=y
-# CONFIG_SYSV_FS is not set
-# CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_UFS_FS_WRITE is not set
-
-#
-# Network File Systems
-#
-# CONFIG_CODA_FS is not set
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_ROOT_NFS is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-CONFIG_SUNRPC=y
-CONFIG_LOCKD=y
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_NCPFS_PACKET_SIGNING is not set
-# CONFIG_NCPFS_IOCTL_LOCKING is not set
-# CONFIG_NCPFS_STRONG is not set
-# CONFIG_NCPFS_NFS_NS is not set
-# CONFIG_NCPFS_OS2_NS is not set
-# CONFIG_NCPFS_SMALLDOS is not set
-# CONFIG_NCPFS_NLS is not set
-# CONFIG_NCPFS_EXTRAS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_SMB_NLS=y
-CONFIG_NLS=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Console drivers
-#
-CONFIG_PC_KEYMAP=y
-# CONFIG_VGA_CONSOLE is not set
-
-#
-# Frame-buffer support
-#
-CONFIG_FB=y
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FB_ACORN is not set
-# CONFIG_FB_CLPS711X is not set
-# CONFIG_FB_CYBER2000 is not set
-CONFIG_FB_SA1100=y
-# CONFIG_FB_ANAKIN is not set
-# CONFIG_FB_E1355 is not set
-# CONFIG_FB_VIRTUAL is not set
-CONFIG_FBCON_ADVANCED=y
-# CONFIG_FBCON_MFB is not set
-# CONFIG_FBCON_CFB2 is not set
-# CONFIG_FBCON_CFB4 is not set
-# CONFIG_FBCON_CFB8 is not set
-CONFIG_FBCON_CFB16=y
-# CONFIG_FBCON_CFB24 is not set
-# CONFIG_FBCON_CFB32 is not set
-# CONFIG_FBCON_AFB is not set
-# CONFIG_FBCON_ILBM is not set
-# CONFIG_FBCON_IPLAN2P2 is not set
-# CONFIG_FBCON_IPLAN2P4 is not set
-# CONFIG_FBCON_IPLAN2P8 is not set
-# CONFIG_FBCON_MAC is not set
-# CONFIG_FBCON_VGA_PLANES is not set
-# CONFIG_FBCON_VGA is not set
-# CONFIG_FBCON_HGA is not set
-CONFIG_FBCON_FONTWIDTH8_ONLY=y
-CONFIG_FBCON_FONTS=y
-CONFIG_FONT_8x8=y
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-# CONFIG_SOUND_ASSABET_UDA1341 is not set
-CONFIG_SOUND_BITSY_UDA1341=m
-# CONFIG_SOUND_SA1111_UDA1341 is not set
-# CONFIG_SOUND_SA1100SSP is not set
-# CONFIG_SOUND_CMPCI is not set
-# CONFIG_SOUND_EMU10K1 is not set
-# CONFIG_SOUND_FUSION is not set
-# CONFIG_SOUND_CS4281 is not set
-# CONFIG_SOUND_ES1370 is not set
-# CONFIG_SOUND_ES1371 is not set
-# CONFIG_SOUND_ESSSOLO1 is not set
-# CONFIG_SOUND_MAESTRO is not set
-# CONFIG_SOUND_MAESTRO3 is not set
-# CONFIG_SOUND_ICH is not set
-# CONFIG_SOUND_SONICVIBES is not set
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_VIA82CXXX is not set
-# CONFIG_MIDI_VIA82CXXX is not set
-# CONFIG_SOUND_OSS is not set
-# CONFIG_SOUND_TVMIXER is not set
-
-#
-# USB support
-#
-# CONFIG_USB is not set
-
-#
-# Bluetooth support
-#
-# CONFIG_BLUEZ is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_NO_FRAME_POINTER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_INFO is not set
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_NO_PGT_CACHE is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_DEBUG_DC21285_PORT is not set
-# CONFIG_DEBUG_CLPS711X_UART2 is not set
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-#
-CONFIG_ARM=y
-# CONFIG_SBUS is not set
-CONFIG_UID16=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-# CONFIG_OBSOLETE is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_KMOD is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_ARCA5K is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_RPC is not set
-CONFIG_ARCH_SA1100=y
-
-#
-# SA11x0 Implementations
-#
-# CONFIG_SA1100_ASSABET is not set
-# CONFIG_SA1100_BRUTUS is not set
-CONFIG_SA1100_CERF=y
-CONFIG_SA1100_CERF_32MB=y
-# CONFIG_SA1100_BITSY is not set
-# CONFIG_SA1100_LART is not set
-# CONFIG_SA1100_THINCLIENT is not set
-# CONFIG_SA1100_GRAPHICSCLIENT is not set
-# CONFIG_SA1100_NANOENGINE is not set
-# CONFIG_SA1100_VICTOR is not set
-# CONFIG_SA1100_XP860 is not set
-# CONFIG_ANGELBOOT is not set
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
-# CONFIG_ARCH_ACORN is not set
-# CONFIG_FOOTBRIDGE is not set
-# CONFIG_FOOTBRIDGE_HOST is not set
-# CONFIG_FOOTBRIDGE_ADDIN is not set
-CONFIG_CPU_32=y
-# CONFIG_CPU_26 is not set
-CONFIG_CPU_32v4=y
-CONFIG_CPU_SA1100=y
-CONFIG_DISCONTIGMEM=y
-# CONFIG_PCI is not set
-# CONFIG_ISA is not set
-# CONFIG_ISA_DMA is not set
-CONFIG_PC_KEYMAP=y
-
-#
-# General setup
-#
-# CONFIG_SA1100_CERF_CMDLINE is not set
-CONFIG_HOTPLUG=y
-
-#
-# PCMCIA/CardBus support
-#
-CONFIG_PCMCIA=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_SA1100_PCMCIA=y
-CONFIG_VIRTUAL_BUS=y
-CONFIG_NET=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SYSCTL=y
-CONFIG_NWFPE=y
-CONFIG_KCORE_ELF=y
-# CONFIG_KCORE_AOUT is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_PM is not set
-# CONFIG_ARTHUR is not set
-CONFIG_CMDLINE="console=ttyS0,38400"
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_LEDS_CPU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Plug and Play configuration
-#
-# CONFIG_PNP is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_LVM is not set
-# CONFIG_BLK_DEV_MD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_BLK_DEV_FLASH=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_FILTER is not set
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_IP_ROUTER is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_ALIAS is not set
-# CONFIG_INET_ECN is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_IPV6 is not set
-# CONFIG_KHTTPD is not set
-# CONFIG_ATM is not set
-
-#
-#
-#
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_DECNET is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_LLC is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_FASTROUTE is not set
-# CONFIG_NET_HW_FLOWCONTROL is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_CERF_CS8900A=y
-# CONFIG_ARM_AM79C961A is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_LANCE is not set
-# CONFIG_NET_VENDOR_SMC is not set
-# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
-# CONFIG_NET_ISA is not set
-# CONFIG_NET_PCI is not set
-# CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_YELLOWFIN is not set
-# CONFIG_ACENIC is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-# CONFIG_NET_FC is not set
-# CONFIG_RCPCI is not set
-# CONFIG_SHAPER is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-
-#
-# PCMCIA network device support
-#
-# CONFIG_NET_PCMCIA is not set
-
-#
-# Amateur Radio support
-#
-# CONFIG_HAMRADIO is not set
-
-#
-# IrDA (infrared) support
-#
-# CONFIG_IRDA is not set
-
-#
-# ATA/IDE/MFM/RLL support
-#
-CONFIG_IDE=y
-
-#
-# IDE, ATA and ATAPI Block devices
-#
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_HD_IDE is not set
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
-# CONFIG_BLK_DEV_COMMERIAL is not set
-CONFIG_BLK_DEV_IDECS=y
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_CMD640 is not set
-# CONFIG_IDE_CHIPSETS is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_DMA_NONPCI is not set
-# CONFIG_BLK_DEV_IDE_MODES is not set
-
-#
-# SCSI support
-#
-# CONFIG_SCSI is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_VT_CONSOLE is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_TOUCHSCREEN_UCB1200=y
-# CONFIG_TOUCHSCREEN_BITSY is not set
-# CONFIG_SERIAL is not set
-# CONFIG_SERIAL_EXTENDED is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=32
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Mice
-#
-# CONFIG_BUSMOUSE is not set
-# CONFIG_MOUSE is not set
-
-#
-# Joysticks
-#
-# CONFIG_JOYSTICK is not set
-# CONFIG_QIC02_TAPE is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-
-#
-# Video For Linux
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_FTAPE is not set
-# CONFIG_AGP is not set
-# CONFIG_DRM is not set
-# CONFIG_PCMCIA_SERIAL is not set
-
-#
-# File systems
-#
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_FAT_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS_VERBOSE=0
-# CONFIG_CRAMFS is not set
-# CONFIG_RAMFS is not set
-# CONFIG_ISO9660_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_NTFS_FS is not set
-# CONFIG_HPFS_FS is not set
-CONFIG_PROC_FS=y
-# CONFIG_DEVFS_FS is not set
-CONFIG_DEVPTS_FS=y
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_EXT2_FS=y
-# CONFIG_SYSV_FS is not set
-# CONFIG_UDF_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-# CONFIG_CODA_FS is not set
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_ROOT_NFS is not set
-# CONFIG_NFSD is not set
-CONFIG_SUNRPC=y
-CONFIG_LOCKD=y
-# CONFIG_SMB_FS is not set
-# CONFIG_NCP_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
-
-#
-# Console drivers
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
-
-#
-# Frame-buffer support
-#
-CONFIG_FB=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FB_SA1100=y
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FBCON_ADVANCED is not set
-CONFIG_FBCON_CFB2=y
-CONFIG_FBCON_CFB4=y
-CONFIG_FBCON_CFB8=y
-CONFIG_FBCON_CFB16=y
-# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
-# CONFIG_FBCON_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB is not set
-
-#
-# Kernel hacking
-#
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_DEBUG_LL is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+CONFIG_SA1100_CERF=y
+# CONFIG_SA1100_CERF_8MB is not set
+# CONFIG_SA1100_CERF_16MB is not set
+CONFIG_SA1100_CERF_32MB=y
+# CONFIG_SA1100_CERF_64MB is not set
+# CONFIG_SA1100_CERF_FLASH_8MB is not set
+CONFIG_SA1100_CERF_FLASH_16MB=y
+# CONFIG_SA1100_CERF_FLASH_32MB is not set
+# CONFIG_SA1100_CERF_CPLD is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_USB=y
+CONFIG_SA1100_USB_NETLINK=y
+CONFIG_SA1100_USB_CHAR=y
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySA0 root=1f03 rw"
+# CONFIG_PFS168_CMDLINE is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_SUN_UFLASH is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
+# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
+# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_OCTAGON is not set
+# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_EL1 is not set
+# CONFIG_EL2 is not set
+# CONFIG_ELPLUS is not set
+# CONFIG_EL16 is not set
+# CONFIG_ELMC is not set
+# CONFIG_ELMC_II is not set
+CONFIG_CERF_CS8900A=y
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=9600
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+# CONFIG_UCB1200 is not set
+# CONFIG_TOUCHSCREEN_UCB1200 is not set
+# CONFIG_AUDIO_UCB1200 is not set
+# CONFIG_ADC_UCB1200 is not set
+# CONFIG_TOUCHSCREEN_H3600 is not set
+# CONFIG_PROFILER is not set
+# CONFIG_PFS168_SPI is not set
+# CONFIG_PFS168_DTMF is not set
+# CONFIG_PFS168_MISC is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_BIT_SA1100_UCB1200 is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+
+#
+# L3 driver support
+#
+# CONFIG_L3_DRV_UDA1341 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_UMSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_FREEVXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+CONFIG_ROMFS_FS=y
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# Miscellaneous USB drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+CONFIG_SA1100_CERF=y
+# CONFIG_SA1100_CERF_8MB is not set
+# CONFIG_SA1100_CERF_16MB is not set
+# CONFIG_SA1100_CERF_32MB is not set
+CONFIG_SA1100_CERF_64MB=y
+# CONFIG_SA1100_CERF_FLASH_8MB is not set
+# CONFIG_SA1100_CERF_FLASH_16MB is not set
+CONFIG_SA1100_CERF_FLASH_32MB=y
+CONFIG_SA1100_CERF_CPLD=y
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_USB=y
+CONFIG_SA1100_USB_NETLINK=y
+CONFIG_SA1100_USB_CHAR=y
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySA0 cpufreq_max=221200 root=1f03 rw"
+# CONFIG_PFS168_CMDLINE is not set
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+# CONFIG_MTD_CFI_B2 is not set
+CONFIG_MTD_CFI_B4=y
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_SUN_UFLASH is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
+# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
+# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_OCTAGON is not set
+# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_EL1 is not set
+# CONFIG_EL2 is not set
+# CONFIG_ELPLUS is not set
+# CONFIG_EL16 is not set
+# CONFIG_ELMC is not set
+# CONFIG_ELMC_II is not set
+CONFIG_CERF_CS8900A=y
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+CONFIG_NET_RADIO=y
+CONFIG_STRIP=m
+CONFIG_WAVELAN=m
+CONFIG_ARLAN=m
+CONFIG_AIRONET4500=m
+CONFIG_AIRONET4500_NONCS=m
+# CONFIG_AIRONET4500_PNP is not set
+# CONFIG_AIRONET4500_PCI is not set
+# CONFIG_AIRONET4500_ISA is not set
+# CONFIG_AIRONET4500_I365 is not set
+CONFIG_AIRONET4500_PROC=m
+
+#
+# Wireless Pcmcia cards support
+#
+CONFIG_PCMCIA_HERMES=m
+CONFIG_AIRO_CS=m
+CONFIG_NET_WIRELESS=y
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=m
+CONFIG_PCMCIA_3C574=m
+CONFIG_PCMCIA_FMVJ18X=m
+CONFIG_PCMCIA_PCNET=m
+CONFIG_PCMCIA_NMCLAN=m
+CONFIG_PCMCIA_SMC91C92=m
+CONFIG_PCMCIA_XIRC2PS=m
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+CONFIG_NET_PCMCIA_RADIO=y
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_PCMCIA_NETWAVE=m
+CONFIG_PCMCIA_WAVELAN=m
+CONFIG_AIRONET4500_CS=m
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+CONFIG_UCB1200=y
+CONFIG_TOUCHSCREEN_UCB1200=y
+CONFIG_CERF_TS_MANUAL=y
+CONFIG_CERF_TS_MAXX="924"
+CONFIG_CERF_TS_MAXY="920"
+CONFIG_CERF_TS_MINX="57"
+CONFIG_CERF_TS_MINY="52"
+CONFIG_CERF_TS_RESX="240"
+CONFIG_CERF_TS_RESY="320"
+# CONFIG_AUDIO_UCB1200 is not set
+# CONFIG_ADC_UCB1200 is not set
+# CONFIG_TOUCHSCREEN_H3600 is not set
+# CONFIG_PROFILER is not set
+# CONFIG_PFS168_SPI is not set
+# CONFIG_PFS168_DTMF is not set
+# CONFIG_PFS168_MISC is not set
+CONFIG_SA1100_CERF_KEYPAD=y
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_BIT_SA1100_UCB1200 is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+
+#
+# L3 driver support
+#
+# CONFIG_L3_DRV_UDA1341 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_UMSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_FREEVXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+CONFIG_ROMFS_FS=y
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_SA1100=y
+CONFIG_CERF_LCD_38_A=y
+# CONFIG_CERF_LCD_57_A is not set
+# CONFIG_CERF_LCD_72_A is not set
+CONFIG_SA1100_CERF_LCD_BACKLIGHT=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+CONFIG_SOUND_CERF_UDA1341=y
+# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
+# CONFIG_SOUND_TVMIXER is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# Miscellaneous USB drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
+#
+# Bluetooth support
+#
+CONFIG_BLUEZ=y
+CONFIG_BLUEZ_L2CAP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BLUEZ_HCIUSB is not set
+CONFIG_BLUEZ_HCIUART=y
+# CONFIG_BLUEZ_HCIVHCI is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+CONFIG_SA1100_CERF=y
+# CONFIG_SA1100_CERF_8MB is not set
+# CONFIG_SA1100_CERF_16MB is not set
+CONFIG_SA1100_CERF_32MB=y
+# CONFIG_SA1100_CERF_64MB is not set
+# CONFIG_SA1100_CERF_FLASH_8MB is not set
+CONFIG_SA1100_CERF_FLASH_16MB=y
+# CONFIG_SA1100_CERF_FLASH_32MB is not set
+# CONFIG_SA1100_CERF_CPLD is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_USB=y
+CONFIG_SA1100_USB_NETLINK=y
+CONFIG_SA1100_USB_CHAR=y
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySA0 root=1f03 rw"
+# CONFIG_PFS168_CMDLINE is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_SUN_UFLASH is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
+# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
+# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_OCTAGON is not set
+# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_EL1 is not set
+# CONFIG_EL2 is not set
+# CONFIG_ELPLUS is not set
+# CONFIG_EL16 is not set
+# CONFIG_ELMC is not set
+# CONFIG_ELMC_II is not set
+CONFIG_CERF_CS8900A=y
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=y
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+CONFIG_UCB1200=y
+CONFIG_TOUCHSCREEN_UCB1200=y
+# CONFIG_CERF_TS_MANUAL is not set
+CONFIG_AUDIO_UCB1200=y
+# CONFIG_ADC_UCB1200 is not set
+# CONFIG_TOUCHSCREEN_H3600 is not set
+# CONFIG_PROFILER is not set
+# CONFIG_PFS168_SPI is not set
+# CONFIG_PFS168_DTMF is not set
+# CONFIG_PFS168_MISC is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_BIT_SA1100_UCB1200 is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+
+#
+# L3 driver support
+#
+# CONFIG_L3_DRV_UDA1341 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_UMSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_FREEVXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+CONFIG_ROMFS_FS=y
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_SA1100=y
+# CONFIG_CERF_LCD_38_A is not set
+CONFIG_CERF_LCD_57_A=y
+# CONFIG_CERF_LCD_72_A is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# Miscellaneous USB drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
--- /dev/null
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_CLPS711X=y
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Footbridge Implementations
+#
+
+#
+# SA11x0 Implementations
+#
+
+#
+# CLPS711X/EP721X Implementations
+#
+CONFIG_ARCH_EDB7211=y
+CONFIG_EP7211_BOOT_MODE=y
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_ACORN is not set
+CONFIG_ARCH_EP7211=y
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+CONFIG_CPU_ARM720T=y
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+# CONFIG_CPU_SA1100 is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_ANGELBOOT is not set
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_NWFPE=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_NET_SB1000 is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_SERIAL_CLPS711X=y
+CONFIG_SERIAL_CLPS711X_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_JOYSTICK is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+CONFIG_MINIX_FS=y
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_SYSV_FS_WRITE is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_LL=y
--- /dev/null
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+CONFIG_ARCH_CAMELOT=y
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+CONFIG_CPU_ARM922T=y
+CONFIG_CPU_ARM92X_CPU_IDLE=y
+CONFIG_CPU_ARM92X_I_CACHE_ON=y
+CONFIG_CPU_ARM92X_D_CACHE_ON=y
+# CONFIG_CPU_ARM92X_WRITETHROUGH is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+# CONFIG_CPU_SA1100 is not set
+# CONFIG_ARM_THUMB is not set
+# CONFIG_DISCONTIGMEM is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyUA0,38400 root=/dev/mtdblock0 rw"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_BOOTLDR_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_SUN_UFLASH is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
+# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+CONFIG_MTD_EPXA10DB=y
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
+# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_OCTAGON is not set
+# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+# CONFIG_MTD_SA1100 is not set
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_ETHER00=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+CONFIG_SERIAL_UART00=y
+CONFIG_SERIAL_UART00_CONSOLE=y
+# CONFIG_SERIAL_SA1100 is not set
+# CONFIG_SERIAL_SA1100_CONSOLE is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_L3_DRV_UDA1341 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_FREEVXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+CONFIG_ROMFS_FS=y
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_DABUSB is not set
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
# CONFIG_SBUS is not set
# CONFIG_MCA is not set
CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
#
# Code maturity level options
#
# System Type
#
+# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_ARCA5K is not set
# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_SHARK is not set
#
# Archimedes/A5000 Implementations
# CONFIG_SA1100_CERF is not set
# CONFIG_SA1100_BITSY is not set
# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
CONFIG_SA1100_GRAPHICSCLIENT=y
+# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
# CONFIG_SA1100_LART is not set
-# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
# CONFIG_SA1100_VICTOR is not set
# CONFIG_SA1100_XP860 is not set
# CONFIG_SA1100_YOPY is not set
-# CONFIG_SA1100_PFS168 is not set
-CONFIG_SA1100_USB=m
-CONFIG_SA1100_USB_NETLINK=m
-CONFIG_SA1100_USB_CHAR=m
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
#
# CLPS711X/EP721X Implementations
# CONFIG_CPU_SA110 is not set
CONFIG_CPU_SA1100=y
CONFIG_DISCONTIGMEM=y
+# CONFIG_CPU_BIG_ENDIAN is not set
#
# General setup
#
-
-#
-# Please ensure that you have read the help on the next option
-#
-# CONFIG_ANGELBOOT is not set
# CONFIG_PCI is not set
# CONFIG_ISA is not set
# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
CONFIG_HOTPLUG=y
#
# CONFIG_I82365 is not set
# CONFIG_TCIC is not set
# CONFIG_PCMCIA_CLPS6700 is not set
-CONFIG_PCMCIA_SA1100=m
+CONFIG_PCMCIA_SA1100=y
CONFIG_NET=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PM is not set
+# CONFIG_APM is not set
# CONFIG_ARTHUR is not set
-CONFIG_CMDLINE="root=nfs"
+CONFIG_CMDLINE="ip=off"
# CONFIG_PFS168_CMDLINE is not set
-# CONFIG_LEDS is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UCB1200 is not set
#
# Parallel port support
#
# Memory Technology Devices (MTD)
#
-CONFIG_MTD=m
+CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
#
-# Disk-On-Chip Device Drivers
+# User Modules And Translation Layers
#
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
#
-# RAM/ROM Device Drivers
+# RAM/ROM/Flash chip drivers
#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_JEDEC is not set
#
-# Linearly Mapped Flash Device Drivers
+# Mapping drivers for chip access
#
-CONFIG_MTD_CFI=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_INTELEXT=m
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
-# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=800000
+CONFIG_MTD_PHYSMAP_LEN=1000000
+CONFIG_MTD_PHYSMAP_BUSWIDTH=4
+# CONFIG_MTD_SUN_UFLASH is not set
# CONFIG_MTD_NORA is not set
# CONFIG_MTD_PNC2000 is not set
# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_SBC_MEDIAGX is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
# CONFIG_MTD_ELAN_104NC is not set
-CONFIG_MTD_SA1100=m
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
+# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
# CONFIG_MTD_DC21285 is not set
# CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_CSTM_CFI_JEDEC is not set
-# CONFIG_MTD_JEDEC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
# CONFIG_MTD_MIXMEM is not set
# CONFIG_MTD_OCTAGON is not set
# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
#
-# NAND Flash Device Drivers
+# Self-contained MTD device drivers
#
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_NAND_SPIA is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
#
-# User Modules And Translation Layers
+# Disk-On-Chip Device Drivers
#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_MTD_BLOCK_RO is not set
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
#
# Plug and Play configuration
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
CONFIG_NET_VENDOR_SMC=y
# CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
# CONFIG_ULTRA is not set
# CONFIG_ULTRA32 is not set
CONFIG_SMC9194=y
# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_MYRI_SBUS is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=m
+CONFIG_PCMCIA_PCNET=y
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_PCMCIA_XIRC2PS is not set
#
# ATA/IDE/MFM/RLL support
#
-CONFIG_IDE=m
+CONFIG_IDE=y
#
# IDE, ATA and ATAPI Block devices
#
-CONFIG_BLK_DEV_IDE=m
+CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
-CONFIG_BLK_DEV_IDEDISK=m
+CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
# CONFIG_BLK_DEV_IDEDISK_WD is not set
# CONFIG_BLK_DEV_COMMERIAL is not set
# CONFIG_BLK_DEV_TIVO is not set
-CONFIG_BLK_DEV_IDECS=m
+CONFIG_BLK_DEV_IDECS=y
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_SA1100_DEFAULT_BAUDRATE=9600
-# CONFIG_TOUCHSCREEN_UCB1200 is not set
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+CONFIG_UCB1200=y
+CONFIG_TOUCHSCREEN_UCB1200=y
+CONFIG_AUDIO_UCB1200=y
+CONFIG_ADC_UCB1200=y
# CONFIG_TOUCHSCREEN_BITSY is not set
# CONFIG_PROFILER is not set
# CONFIG_PFS168_SPI is not set
# CONFIG_PFS168_DTMF is not set
# CONFIG_PFS168_MISC is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=32
#
# I2C support
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
-# CONFIG_PCMCIA_SERIAL is not set
+
+#
+# PCMCIA character devices
+#
#
# Multimedia devices
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
-CONFIG_VFAT_FS=m
+CONFIG_VFAT_FS=y
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
+CONFIG_JFFS_FS=y
CONFIG_JFFS_FS_VERBOSE=0
-CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_CRAMFS is not set
-CONFIG_RAMFS=m
+CONFIG_CRAMFS=y
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
-# CONFIG_SYSV_FS_WRITE is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
#
CONFIG_PC_KEYMAP=y
# CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
#
# Frame-buffer support
# CONFIG_FB_CLPS711X is not set
# CONFIG_FB_CYBER2000 is not set
CONFIG_FB_SA1100=y
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_E1355 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FBCON_ADVANCED is not set
CONFIG_FBCON_CFB2=y
#
# CONFIG_USB is not set
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
#
# Kernel hacking
#
--- /dev/null
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_GRAPHICSMASTER=y
+# CONFIG_SA1100_ADSBITSY is not set
+CONFIG_SA1111=y
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+CONFIG_DISCONTIGMEM=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="ip=off"
+# CONFIG_PFS168_CMDLINE is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=800000
+CONFIG_MTD_PHYSMAP_LEN=1000000
+CONFIG_MTD_PHYSMAP_BUSWIDTH=4
+# CONFIG_MTD_SUN_UFLASH is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
+# CONFIG_MTD_ELAN_104NC is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
+# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
+# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_OCTAGON is not set
+# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+CONFIG_NET_VENDOR_SMC=y
+# CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
+# CONFIG_ULTRA is not set
+# CONFIG_ULTRA32 is not set
+CONFIG_SMC9194=y
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=y
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_KEYBDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+CONFIG_UCB1200=y
+CONFIG_TOUCHSCREEN_UCB1200=y
+CONFIG_AUDIO_UCB1200=y
+CONFIG_ADC_UCB1200=y
+# CONFIG_TOUCHSCREEN_BITSY is not set
+# CONFIG_PROFILER is not set
+# CONFIG_PFS168_SPI is not set
+# CONFIG_PFS168_DTMF is not set
+# CONFIG_PFS168_MISC is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_JOYSTICK is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_SA1100_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRAMFS=y
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_SA1100=y
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_E1355 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+CONFIG_FBCON_FONTWIDTH8_ONLY=y
+CONFIG_FBCON_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+CONFIG_USB_OHCI_NOPCI=y
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_KBD is not set
+CONFIG_USB_MOUSE=y
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_DABUSB is not set
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_NET1080 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
# Automatically generated make config: don't edit
#
CONFIG_ARM=y
+# CONFIG_EISA is not set
# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
#
# Code maturity level options
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+# CONFIG_KMOD is not set
#
# System Type
#
+# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_ARCA5K is not set
# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
#
# Archimedes/A5000 Implementations
#
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
#
# Footbridge Implementations
#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
#
# SA11x0 Implementations
#
# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
-CONFIG_SA1100_BITSY=y
-# CONFIG_SA1100_LART is not set
+CONFIG_SA1100_H3600=y
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
# CONFIG_SA1100_NANOENGINE is not set
-# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
# CONFIG_SA1100_XP860 is not set
-# CONFIG_SA1100_PANGOLIN is not set
-# CONFIG_ANGELBOOT is not set
+# CONFIG_SA1100_YOPY is not set
CONFIG_SA1100_USB=m
-CONFIG_SA1100_FREQUENCY_SCALE=y
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
+CONFIG_SA1100_USB_NETLINK=m
+# CONFIG_SA1100_USB_CHAR is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
#
# Processor Type
#
+# CONFIG_CPU_32v3 is not set
CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
CONFIG_DISCONTIGMEM=y
#
# General setup
#
# CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
# CONFIG_ISA_DMA is not set
-CONFIG_PC_KEYMAP=y
+CONFIG_CPU_FREQ=y
CONFIG_HOTPLUG=y
#
# PCMCIA/CardBus support
#
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_DEBUG=y
-PCMCIA_DEBUG=1
-CONFIG_SA1100_PCMCIA=y
-CONFIG_VIRTUAL_BUS=y
+CONFIG_PCMCIA=y
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
CONFIG_NET=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
-CONFIG_NWFPE=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
CONFIG_KCORE_ELF=y
# CONFIG_KCORE_AOUT is not set
-CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_PM=y
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE=""
# CONFIG_LEDS is not set
-# CONFIG_ALIGNMENT_TRAP is not set
+CONFIG_ALIGNMENT_TRAP=y
#
# Parallel port support
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_BOOTLDR_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
#
-# MTD drivers for mapped chips
+# User Modules And Translation Layers
#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-# CONFIG_MTD_JEDEC is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+# CONFIG_MTD_CFI_B2 is not set
+CONFIG_MTD_CFI_B4=y
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
#
-# Drivers for chip mappings
+# Mapping drivers for chip access
#
-# CONFIG_MTD_MIXMEM is not set
+# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_NORA is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_PCI is not set
#
-# User modules and translation layers for MTD devices
+# Self-contained MTD device drivers
#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
#
# Plug and Play configuration
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
#
# Block devices
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
# CONFIG_BLK_DEV_DAC960 is not set
CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_LVM is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_BLK_DEV_FLASH=y
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
#
# Networking options
#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_NETLINK=y
-CONFIG_RTNETLINK=y
-CONFIG_NETLINK_DEV=y
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
+# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_IPV6 is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-# CONFIG_ETHERTAP is not set
-# CONFIG_NET_SB1000 is not set
#
# Ethernet (10 or 100Mbit)
#
# Ethernet (1000 Mbit)
#
-# CONFIG_YELLOWFIN is not set
# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
CONFIG_PPP=m
# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=m
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=m
+CONFIG_PCMCIA_PCNET=y
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_PCMCIA_XIRC2PS is not set
# CONFIG_ARCNET_COM20020_CS is not set
# CONFIG_PCMCIA_IBMTR is not set
-CONFIG_NET_PCMCIA_RADIO=y
-# CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_PCMCIA_NETWAVE is not set
-# CONFIG_PCMCIA_WAVELAN is not set
-# CONFIG_AIRONET4500_CS is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
#
# Amateur Radio support
#
# IrDA (infrared) support
#
-# CONFIG_IRDA is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+# CONFIG_IRDA_OPTIONS is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_NSC_FIR is not set
+# CONFIG_WINBOND_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
+CONFIG_SA1100_FIR=m
#
# ATA/IDE/MFM/RLL support
# CONFIG_BLK_DEV_IDEDISK_WD is not set
# CONFIG_BLK_DEV_COMMERIAL is not set
# CONFIG_BLK_DEV_TIVO is not set
-CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECS is not set
CONFIG_BLK_DEV_IDECD=m
-CONFIG_BLK_DEV_IDETAPE=m
-CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_BLK_DEV_IDESCSI is not set
#
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
# Input core support
#
# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
#
# Character devices
#
CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_SERIAL is not set
+# CONFIG_VT_CONSOLE is not set
+CONFIG_SERIAL=m
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_SA1100_DEFAULT_BAUDRATE=115200
-# CONFIG_TOUCHSCREEN_UCB1200 is not set
-CONFIG_TOUCHSCREEN_BITSY=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+CONFIG_SERIAL_8250=m
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=32
#
# CONFIG_I2C is not set
+#
+# L3 serial bus support
+#
+CONFIG_L3=y
+CONFIG_L3_ALGOBIT=y
+CONFIG_L3_BIT_SA1100_GPIO=y
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+CONFIG_BIT_SA1100_GPIO=y
+
#
# Mice
#
# CONFIG_BUSMOUSE is not set
-# CONFIG_MOUSE is not set
+CONFIG_MOUSE=m
+# CONFIG_PSMOUSE is not set
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
#
# Joysticks
#
-# CONFIG_JOYSTICK is not set
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
#
# Input core support is needed for joysticks
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=m
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
-# CONFIG_PCMCIA_SERIAL is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_PCMCIA_SERIAL_CS is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
#
# File systems
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
# CONFIG_UMSDOS_FS is not set
CONFIG_VFAT_FS=m
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
-CONFIG_JFFS_FS_VERBOSE=2
-CONFIG_CRAMFS=y
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRAMFS=m
+# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
# CONFIG_MINIX_FS is not set
+# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
-# CONFIG_SYSV_FS_WRITE is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# Network File Systems
#
# CONFIG_CODA_FS is not set
-CONFIG_NFS_FS=m
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_ROOT_NFS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V3 is not set
-CONFIG_SUNRPC=m
-CONFIG_LOCKD=m
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_REMOTE=""
+# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
-# CONFIG_NCPFS_MOUNT_SUBDIR is not set
-# CONFIG_NCPFS_NDS_DOMAINS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+CONFIG_ZLIB_FS_INFLATE=m
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
+CONFIG_SMB_NLS=y
CONFIG_NLS=y
#
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Console drivers
#
+CONFIG_PC_KEYMAP=y
# CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
#
# Frame-buffer support
#
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
CONFIG_FB_SA1100=y
+# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FBCON_ADVANCED is not set
-CONFIG_FBCON_CFB2=y
-CONFIG_FBCON_CFB4=y
-CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
CONFIG_FBCON_CFB16=y
-# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
-# CONFIG_FBCON_FONTS is not set
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+CONFIG_FBCON_FONTWIDTH8_ONLY=y
+CONFIG_FBCON_FONTS=y
CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
#
# Sound
#
-CONFIG_SOUND=m
-CONFIG_SOUND_UDA1341=m
-# CONFIG_SOUND_SA1100_SSP is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_ES1371 is not set
# CONFIG_SOUND_ESSSOLO1 is not set
# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=y
+CONFIG_SOUND_UDA1341=y
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+CONFIG_SOUND_H3600_UDA1341=y
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_TVMIXER is not set
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
#
# USB support
#
# CONFIG_USB is not set
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
#
# Kernel hacking
#
-CONFIG_FRAME_POINTER=y
+# CONFIG_NO_FRAME_POINTER is not set
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_INFO is not set
-# CONFIG_MAGIC_SYSRQ is not set
-CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
#
# CONFIG_SA1100_ASSABET is not set
# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_EXTENEX1 is not set
# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
# CONFIG_SA1100_ITSY is not set
#
# CLPS711X/EP721X Implementations
#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_FASTFPE is not set
CONFIG_KCORE_ELF=y
CONFIG_PM=y
CONFIG_APM=m
# CONFIG_ARTHUR is not set
-CONFIG_CMDLINE="console=ttySA0,9600"
+CONFIG_CMDLINE="console=ttySA0,9600 root=/dev/ram"
# CONFIG_PFS168_CMDLINE is not set
CONFIG_LEDS=y
# CONFIG_LEDS_TIMER is not set
#
# Memory Technology Devices (MTD)
#
-CONFIG_MTD=m
+CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_DEBUG_VERBOSE=1
-# CONFIG_MTD_PARTITIONS is not set
+CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_BOOTLDR_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
#
# RAM/ROM/Flash chip drivers
#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_B1 is not set
-# CONFIG_MTD_CFI_B2 is not set
-CONFIG_MTD_CFI_B4=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-CONFIG_MTD_CFI_INTELEXT=m
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_AMDSTD is not set
# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_NETSC520 is not set
# CONFIG_MTD_SBC_GXX is not set
# CONFIG_MTD_ELAN_104NC is not set
-# CONFIG_MTD_SA1100 is not set
-# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
-# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
-# CONFIG_MTD_DC21285 is not set
-# CONFIG_MTD_IQ80310 is not set
# CONFIG_MTD_DBOX2 is not set
# CONFIG_MTD_CSTM_MIPS_IXX is not set
# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_SOLUTIONENGINE is not set
# CONFIG_MTD_MIXMEM is not set
# CONFIG_MTD_OCTAGON is not set
# CONFIG_MTD_VMAX is not set
# CONFIG_MTD_OCELOT is not set
# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+# CONFIG_MTD_SA1100 is not set
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_LART is not set
+CONFIG_MTD_LART=y
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
#
# Block devices
# CONFIG_ATM is not set
#
-#
+#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_WINBOND_FIR is not set
# CONFIG_TOSHIBA_FIR is not set
# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
CONFIG_SA1100_FIR=m
#
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
# Input core support
#
# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
#
# Character devices
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_SERIAL_21285 is not set
-# CONFIG_SERIAL_21285_OLD is not set
-# CONFIG_SERIAL_21285_CONSOLE is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
# CONFIG_SERIAL_AMBA is not set
# CONFIG_SERIAL_AMBA_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X is not set
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
CONFIG_SA1100_DEFAULT_BAUDRATE=9600
# CONFIG_SERIAL_8250 is not set
# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_TOUCHSCREEN_UCB1200=m
CONFIG_AUDIO_UCB1200=m
CONFIG_ADC_UCB1200=m
-# CONFIG_TOUCHSCREEN_BITSY is not set
+# CONFIG_TOUCHSCREEN_H3600 is not set
CONFIG_PROFILER=m
# CONFIG_PFS168_SPI is not set
# CONFIG_PFS168_DTMF is not set
#
# CONFIG_I2C is not set
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+
+#
+# L3 driver support
+#
+# CONFIG_L3_DRV_UDA1341 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
#
# Mice
#
#
# Joysticks
#
-# CONFIG_JOYSTICK is not set
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
#
# Input core support is needed for joysticks
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
# CONFIG_AUTOFS4_FS is not set
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
-CONFIG_JFFS_FS_VERBOSE=1
+# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=1
CONFIG_CRAMFS=m
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
# CONFIG_MINIX_FS is not set
-# CONFIG_VXFS_FS is not set
+# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# Network File Systems
#
# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
# CONFIG_ROOT_NFS is not set
# Sound
#
CONFIG_SOUND=m
-# CONFIG_SOUND_ASSABET_UDA1341 is not set
-# CONFIG_SOUND_BITSY_UDA1341 is not set
-# CONFIG_SOUND_SA1111_UDA1341 is not set
-CONFIG_SOUND_SA1100SSP=m
+# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+CONFIG_SOUND_SA1100SSP=m
# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_TVMIXER is not set
#
#
# CONFIG_USB is not set
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# Miscellaneous USB drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
#
# Bluetooth support
#
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
#
# Code maturity level options
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_L7200 is not set
#
CONFIG_SA1100_ASSABET=y
CONFIG_ASSABET_NEPONSET=y
+# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_EXTENEX1 is not set
# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
# CONFIG_SA1100_ITSY is not set
# CONFIG_SA1100_XP860 is not set
# CONFIG_SA1100_YOPY is not set
CONFIG_SA1111=y
+CONFIG_FORCE_MAX_ZONEORDER=9
CONFIG_SA1100_USB=m
CONFIG_SA1100_USB_NETLINK=m
CONFIG_SA1100_USB_CHAR=m
#
# CLPS711X/EP721X Implementations
#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
# CONFIG_CPU_ARM1020 is not set
# CONFIG_CPU_SA110 is not set
CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
CONFIG_DISCONTIGMEM=y
-# CONFIG_CPU_BIG_ENDIAN is not set
#
# General setup
#
# CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
# CONFIG_ISA_DMA is not set
-# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_FREQ=y
CONFIG_HOTPLUG=y
#
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_FASTFPE is not set
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PM is not set
-# CONFIG_APM is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE=""
-# CONFIG_PFS168_CMDLINE is not set
CONFIG_LEDS=y
CONFIG_LEDS_TIMER=y
CONFIG_LEDS_CPU=y
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_INTELEXT=m
# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
# CONFIG_MTD_JEDEC is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_SUN_UFLASH is not set
# CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_TQM8XXL is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_NETSC520 is not set
-# CONFIG_MTD_SBC_GXX is not set
-# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
CONFIG_MTD_SA1100=m
-# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
-# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
# CONFIG_MTD_DC21285 is not set
# CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_DBOX2 is not set
-# CONFIG_MTD_CSTM_MIPS_IXX is not set
-# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SOLUTIONENGINE is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
-# CONFIG_MTD_OCELOT is not set
-# CONFIG_MTD_L440GX is not set
+# CONFIG_MTD_PCI is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_LART is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
#
# Block devices
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
# CONFIG_BLK_DEV_DAC960 is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
+# CONFIG_ARM_AM79C961A is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_ULTRA32 is not set
CONFIG_SMC9194=y
# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_SERIAL_21285 is not set
-# CONFIG_SERIAL_21285_OLD is not set
-# CONFIG_SERIAL_21285_CONSOLE is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
# CONFIG_SERIAL_AMBA is not set
# CONFIG_SERIAL_AMBA_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X is not set
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
CONFIG_SA1100_DEFAULT_BAUDRATE=9600
CONFIG_SERIAL_8250=m
# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=32
-CONFIG_UCB1200=y
-CONFIG_TOUCHSCREEN_UCB1200=y
-# CONFIG_AUDIO_UCB1200 is not set
-# CONFIG_ADC_UCB1200 is not set
-# CONFIG_TOUCHSCREEN_BITSY is not set
-# CONFIG_PROFILER is not set
-# CONFIG_PFS168_SPI is not set
-# CONFIG_PFS168_DTMF is not set
-# CONFIG_PFS168_MISC is not set
#
# I2C support
#
# CONFIG_I2C is not set
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
#
# Mice
#
#
# Joysticks
#
-# CONFIG_JOYSTICK is not set
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
#
-# Input core support is needed for joysticks
+# Joysticks
#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
# CONFIG_QIC02_TAPE is not set
#
#
# PCMCIA character devices
#
+CONFIG_PCMCIA_SERIAL_CS=m
+# CONFIG_MWAVE is not set
#
# Multimedia devices
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=m
-CONFIG_JFFS_FS_VERBOSE=0
+# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_CRAMFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
# CONFIG_MINIX_FS is not set
-# CONFIG_VXFS_FS is not set
+# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# Network File Systems
#
# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_ROOT_NFS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
#
# Partition Types
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
# CONFIG_FB_CLPS711X is not set
-# CONFIG_FB_CYBER2000 is not set
CONFIG_FB_SA1100=y
-# CONFIG_FB_ANAKIN is not set
-# CONFIG_FB_E1355 is not set
+# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FBCON_ADVANCED is not set
CONFIG_FBCON_CFB2=y
# Sound
#
CONFIG_SOUND=y
-CONFIG_SOUND_ASSABET_UDA1341=m
-# CONFIG_SOUND_BITSY_UDA1341 is not set
-CONFIG_SOUND_SA1111_UDA1341=m
-# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=y
+# CONFIG_SOUND_UDA1341 is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_TVMIXER is not set
+#
+# Multimedia Capabilities Port drivers
+#
+CONFIG_MCP=y
+CONFIG_MCP_SA1100=y
+CONFIG_MCP_UCB1200=y
+CONFIG_MCP_UCB1200_AUDIO=m
+CONFIG_MCP_UCB1200_TS=y
+
#
# USB support
#
#
# CONFIG_USB_DEVICEFS is not set
# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_LONG_TIMEOUT is not set
+# CONFIG_USB_LARGE_CONFIG is not set
#
# USB Controllers
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
CONFIG_USB_OHCI=y
-CONFIG_USB_OHCI_NOPCI=y
+CONFIG_USB_OHCI_SA1111=y
#
# USB Device Class drivers
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# USB Human Interface Devices (HID)
#
CONFIG_USB_HID=y
+# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_WACOM is not set
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
#
# USB Multimedia devices
#
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
#
# USB Network adaptors
#
-# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
-# CONFIG_USB_NET1080 is not set
+# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
-
-#
-# USB misc drivers
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
#
# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
#
# Bluetooth support
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_SLAB is not set
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_NO_PGT_CACHE is not set
# CONFIG_DEBUG_LL is not set
# CONFIG_DEBUG_DC21285_PORT is not set
#
-# Automatically generated make config: don't edit
+# Automatically generated by make menuconfig: don't edit
#
CONFIG_ARM=y
# CONFIG_EISA is not set
# CONFIG_SBUS is not set
# CONFIG_MCA is not set
CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
#
# Code maturity level options
#
# System Type
#
+# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_ARCA5K is not set
# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_RPC is not set
CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_SHARK is not set
#
# Archimedes/A5000 Implementations
#
-
-#
-# Archimedes/A5000 Implementations (select only ONE)
-#
# CONFIG_ARCH_ARC is not set
# CONFIG_ARCH_A5K is not set
# CONFIG_SA1100_CERF is not set
# CONFIG_SA1100_BITSY is not set
# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
# CONFIG_SA1100_LART is not set
# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
CONFIG_SA1100_PANGOLIN=y
+CONFIG_SA1100_PANGOLIN_PCMCIA_IDE=y
# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
# CONFIG_SA1100_PFS168 is not set
# CONFIG_SA1100_VICTOR is not set
# CONFIG_SA1100_XP860 is not set
# CONFIG_SA1100_USB is not set
# CONFIG_SA1100_USB_NETLINK is not set
# CONFIG_SA1100_USB_CHAR is not set
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
#
# CLPS711X/EP721X Implementations
# CONFIG_FOOTBRIDGE_ADDIN is not set
CONFIG_CPU_32=y
# CONFIG_CPU_26 is not set
-
-#
-# Processor Type
-#
# CONFIG_CPU_32v3 is not set
CONFIG_CPU_32v4=y
# CONFIG_CPU_ARM610 is not set
# CONFIG_CPU_SA110 is not set
CONFIG_CPU_SA1100=y
CONFIG_DISCONTIGMEM=y
+# CONFIG_CPU_BIG_ENDIAN is not set
#
# General setup
#
-
-#
-# Please ensure that you have read the help on the next option
-#
-# CONFIG_ANGELBOOT is not set
# CONFIG_PCI is not set
# CONFIG_ISA is not set
# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
CONFIG_HOTPLUG=y
#
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_FASTFPE is not set
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FPE_FASTFPE=y
CONFIG_KCORE_ELF=y
# CONFIG_KCORE_AOUT is not set
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PM is not set
+# CONFIG_APM is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE="keepinitrd"
# CONFIG_PFS168_CMDLINE is not set
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UCB1200 is not set
#
# Parallel port support
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
-
-#
-# RAM/ROM Device Drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_MTDRAM is not set
-
-#
-# Linearly Mapped Flash Device Drivers
+# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+# CONFIG_MTD_CFI_B2 is not set
+CONFIG_MTD_CFI_B4=y
+# CONFIG_MTD_CFI_I1 is not set
+# CONFIG_MTD_CFI_I2 is not set
+CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_AMDSTD is not set
# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_SUN_UFLASH is not set
# CONFIG_MTD_NORA is not set
# CONFIG_MTD_PNC2000 is not set
# CONFIG_MTD_RPXLITE is not set
+# CONFIG_MTD_TQM8XXL is not set
# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_SBC_MEDIAGX is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_SBC_GXX is not set
# CONFIG_MTD_ELAN_104NC is not set
CONFIG_MTD_SA1100=y
+# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set
+# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set
# CONFIG_MTD_DC21285 is not set
# CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_CSTM_CFI_JEDEC is not set
-# CONFIG_MTD_JEDEC is not set
+# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SOLUTIONENGINE is not set
# CONFIG_MTD_MIXMEM is not set
# CONFIG_MTD_OCTAGON is not set
# CONFIG_MTD_VMAX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_L440GX is not set
#
-# NAND Flash Device Drivers
+# Self-contained MTD device drivers
#
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_NAND_SPIA is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_LART is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
#
-# User Modules And Translation Layers
+# NAND Flash Device Drivers
#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+# CONFIG_MTD_NAND is not set
#
# Plug and Play configuration
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
-
-#
-#
-#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_DECNET is not set
# ARCnet devices
#
# CONFIG_ARCNET is not set
-CONFIG_DUMMY=y
+# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
-# CONFIG_NET_VENDOR_SMC is not set
+CONFIG_NET_VENDOR_SMC=y
+# CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
+# CONFIG_ULTRA is not set
+# CONFIG_ULTRA32 is not set
+CONFIG_SMC9194=y
# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_MYRI_SBUS is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_PCMCIA_XIRC2PS is not set
# CONFIG_ARCNET_COM20020_CS is not set
# CONFIG_PCMCIA_IBMTR is not set
-# CONFIG_NET_PCMCIA_RADIO is not set
-CONFIG_PCMCIA_NETCARD=y
+CONFIG_NET_PCMCIA_RADIO=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_PCMCIA_NETWAVE is not set
+# CONFIG_PCMCIA_WAVELAN is not set
+# CONFIG_AIRONET4500_CS is not set
+CONFIG_PCMCIA_WVLAN=y
#
# Amateur Radio support
#
# ATA/IDE/MFM/RLL support
#
-CONFIG_IDE=y
+CONFIG_IDE=m
#
# IDE, ATA and ATAPI Block devices
#
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
+CONFIG_BLK_DEV_IDE=m
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
-CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_BLK_DEV_IDEDISK=m
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
# CONFIG_BLK_DEV_IDEDISK_WD is not set
# CONFIG_BLK_DEV_COMMERIAL is not set
# CONFIG_BLK_DEV_TIVO is not set
-CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_PANGOLIN is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_BLK_DEV_IDESCSI is not set
-
-#
-# IDE chipset support/bugfixes
-#
# CONFIG_BLK_DEV_CMD640 is not set
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
# CONFIG_BLK_DEV_ISAPNP is not set
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
CONFIG_SA1100_DEFAULT_BAUDRATE=115200
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+# CONFIG_UCB1200 is not set
# CONFIG_TOUCHSCREEN_UCB1200 is not set
+# CONFIG_AUDIO_UCB1200 is not set
+# CONFIG_ADC_UCB1200 is not set
# CONFIG_TOUCHSCREEN_BITSY is not set
CONFIG_PROFILER=y
# CONFIG_PFS168_SPI is not set
# CONFIG_PFS168_DTMF is not set
# CONFIG_PFS168_MISC is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=32
#
# I2C support
# Joysticks
#
# CONFIG_JOYSTICK is not set
-
-#
-# Input core support is needed for joysticks
-#
# CONFIG_QIC02_TAPE is not set
#
#
# PCMCIA character devices
#
-# CONFIG_PCMCIA_SERIAL_CS is not set
#
# Multimedia devices
CONFIG_JFFS_FS_VERBOSE=0
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
+# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
-# CONFIG_SYSV_FS_WRITE is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
#
CONFIG_PC_KEYMAP=y
# CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
#
# Frame-buffer support
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_SA1100 is not set
CONFIG_FB_MQ200=y
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_E1355 is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_FBCON_ADVANCED=y
# CONFIG_FBCON_MFB is not set
-# CONFIG_FBCON_CFB2 is not set
-# CONFIG_FBCON_CFB4 is not set
-# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
CONFIG_FBCON_CFB16=y
# CONFIG_FBCON_CFB24 is not set
# CONFIG_FBCON_CFB32 is not set
# Sound
#
CONFIG_SOUND=y
-CONFIG_SOUND_UDA1341=y
-# CONFIG_SOUND_SA1100_SSP is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+CONFIG_SOUND_PANGOLIN_UDA1341=y
+# CONFIG_SOUND_BITSY_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
# CONFIG_SOUND_OSS is not set
# CONFIG_SOUND_TVMIXER is not set
#
# CONFIG_USB is not set
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
#
# Kernel hacking
#
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
#
# Code maturity level options
#
# CONFIG_SA1100_ASSABET is not set
# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
# CONFIG_SA1100_BRUTUS is not set
# CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3600 is not set
# CONFIG_SA1100_EXTENEX1 is not set
# CONFIG_SA1100_FLEXANET is not set
# CONFIG_SA1100_FREEBIRD is not set
# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
# CONFIG_SA1100_JORNADA720 is not set
# CONFIG_SA1100_HUW_WEBPANEL is not set
# CONFIG_SA1100_ITSY is not set
# CONFIG_SA1100_PANGOLIN is not set
# CONFIG_SA1100_PLEB is not set
# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
# CONFIG_SA1100_PFS168 is not set
# CONFIG_SA1100_VICTOR is not set
# CONFIG_SA1100_XP860 is not set
#
# CLPS711X/EP721X Implementations
#
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
# CONFIG_ARCH_ACORN is not set
# CONFIG_FOOTBRIDGE is not set
# CONFIG_FOOTBRIDGE_HOST is not set
# CONFIG_CPU_ARM1020 is not set
CONFIG_CPU_SA110=y
# CONFIG_CPU_SA1100 is not set
+# CONFIG_ARM_THUMB is not set
# CONFIG_DISCONTIGMEM is not set
#
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
# CONFIG_FPE_NWFPE is not set
CONFIG_FPE_FASTFPE=y
CONFIG_KCORE_ELF=y
#
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y
+CONFIG_PARPORT_PC_CML1=y
+# CONFIG_PARPORT_SERIAL is not set
# CONFIG_PARPORT_PC_FIFO is not set
# CONFIG_PARPORT_PC_SUPERIO is not set
# CONFIG_PARPORT_ARC is not set
# CONFIG_PARPORT_AMIGA is not set
# CONFIG_PARPORT_MFC3 is not set
# CONFIG_PARPORT_ATARI is not set
+# CONFIG_PARPORT_GSC is not set
# CONFIG_PARPORT_SUNBPP is not set
# CONFIG_PARPORT_OTHER is not set
# CONFIG_PARPORT_1284 is not set
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
#
# Block devices
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
# CONFIG_BLK_DEV_LVM is not set
#
# CONFIG_APRICOT is not set
CONFIG_CS89x0=y
# CONFIG_TULIP is not set
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_DEBUG is not set
#
-# IEEE 1394 (FireWire) support
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set
# Input core support
#
# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
#
# Character devices
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_SERIAL_21285 is not set
-# CONFIG_SERIAL_21285_OLD is not set
-# CONFIG_SERIAL_21285_CONSOLE is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
# CONFIG_SERIAL_AMBA is not set
# CONFIG_SERIAL_AMBA_CONSOLE is not set
# CONFIG_SERIAL_CLPS711X is not set
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
# CONFIG_SERIAL_SA1100 is not set
# CONFIG_SERIAL_SA1100_CONSOLE is not set
# CONFIG_SERIAL_8250 is not set
# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
CONFIG_PRINTER=m
#
# CONFIG_I2C is not set
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
#
# Mice
#
#
# Joysticks
#
-# CONFIG_JOYSTICK is not set
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
#
# Input core support is needed for joysticks
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
#
# Multimedia devices
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_UMSDOS_FS is not set
# CONFIG_RAMFS is not set
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
# CONFIG_MINIX_FS is not set
-# CONFIG_VXFS_FS is not set
+# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
# Network File Systems
#
# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_ROOT_NFS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
#
# Partition Types
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_CLGEN is not set
# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
# CONFIG_FB_CLPS711X is not set
-CONFIG_FB_CYBER2000=y
# CONFIG_FB_SA1100 is not set
-# CONFIG_FB_ANAKIN is not set
-# CONFIG_FB_E1355 is not set
+CONFIG_FB_CYBER2000=y
# CONFIG_FB_MATROX is not set
# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_3DFX is not set
# CONFIG_FB_SIS is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FBCON_ADVANCED is not set
CONFIG_FBCON_CFB8=y
# Sound
#
CONFIG_SOUND=m
+# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_WAVEARTIST is not set
# CONFIG_SOUND_TVMIXER is not set
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
#
# USB support
#
# CONFIG_USB is not set
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PLUSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# Miscellaneous USB drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ID75 is not set
+
#
# Bluetooth support
#
no-irq-arch := $(CONFIG_ARCH_INTEGRATOR) $(CONFIG_ARCH_CLPS711X) \
$(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \
- $(CONFIG_ARCH_SA1100)
+ $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT)
ifneq ($(findstring y,$(no-irq-arch)),y)
obj-y += irq-arch.o
bne 1001b
.endm
+#elif defined(CONFIG_ARCH_CAMELOT)
+
+#include <asm/arch/excalibur.h>
+#define UART00_TYPE
+#include <asm/arch/uart00.h>
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldr \rx, =EXC_UART00_BASE @ physical base address
+ orrne \rx, \rx, #0xff000000 @ virtual base
+ orrne \rx, \rx, #0x00f00000
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_TD(0)]
+ .endm
+
+ .macro waituart,rd,rx
+1001: ldr \rd, [\rx, #UART_TSR(0)]
+ and \rd, \rd, #UART_TSR_TX_LEVEL_MSK
+ cmp \rd, #15
+ beq 1001b
+ .endm
+
+ .macro busyuart,rd,rx
+1001: ldr \rd, [\rx, #UART_TSR(0)]
+ ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK
+ bne 1001b
+ .endm
+
#else
#error Unknown architecture
#endif
#include <linux/config.h>
#include "entry-header.S"
+
#ifdef IOC_BASE
/* IOC / IOMD based hardware */
#include <asm/hardware/iomd.h>
.macro irq_prio_table
.endm
+
+#elif defined (CONFIG_ARCH_CAMELOT)
+#include <asm/arch/platform.h>
+#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
+#include <asm/arch/int_ctrl00.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+ ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
+ ldr \irqnr,[\irqstat]
+ cmp \irqnr,#0
+ subne \irqnr,\irqnr,#1
+
+
+ .endm
+
+ .macro irq_prio_table
+ .endm
#elif defined(CONFIG_ARCH_ANAKIN)
1: moveq r0, #-2
LOADREGS(eqfd, sp!, {r4 - r8, pc})
-2: stmfd sp!, {pc} @ calculate offset of PC in STMIA instruction
+2: stmfd sp!, {pc} @ calculate offset of PC in STMIA instruction
ldr r0, [sp], #4
adr r1, 2b - 4
sub offset, r0, r1
-3: tst frame, mask @ Check for address exceptions...
+3: tst frame, mask @ Check for address exceptions...
bne 1b
- ldmda frame, {r0, r1, r2, r3} @ fp, sp, lr, pc
+1001: ldmda frame, {r0, r1, r2, r3} @ fp, sp, lr, pc
mov next, r0
- sub save, r3, offset @ Correct PC for prefetching
+ sub save, r3, offset @ Correct PC for prefetching
bic save, save, mask
adr r0, .Lfe
mov r1, save
bic r2, r2, mask
- bl SYMBOL_NAME(printk)
+ bl SYMBOL_NAME(printk) @ print pc and link register
sub r0, frame, #16
- ldr r1, [save, #4]
+1002: ldr r1, [save, #4] @ get instruction at function+4
mov r3, r1, lsr #10
ldr r2, .Ldsi+4
teq r3, r2 @ Check for stmia sp!, {args}
addeq save, save, #4 @ next instruction
bleq .Ldumpstm
- ldr r1, [save, #4] @ Get 'stmia sp!, {rlist, fp, ip, lr, pc}' instruction
+1003: ldr r1, [save, #4] @ Get 'stmia sp!, {rlist, fp, ip, lr, pc}' instruction
mov r3, r1, lsr #10
ldr r2, .Ldsi
teq r3, r2
bne 3b
LOADREGS(fd, sp!, {r4 - r8, pc})
+/*
+ * Fixup for LDMDB
+ */
+ .section .fixup,"ax"
+ .align 0
+1004: ldr r0, =.Lbad
+ mov r1, frame
+ bl SYMBOL_NAME(printk)
+ LOADREGS(fd, sp!, {r4 - r8, pc})
+ .ltorg
+ .previous
+
+ .section __ex_table,"a"
+ .align 3
+ .long 1001b, 1004b
+ .long 1002b, 1004b
+ .long 1003b, 1004b
+ .previous
#define instr r4
#define reg r5
.Lfe: .asciz "Function entered at [<%p>] from [<%p>]\n"
.Lfp: .asciz " r%d = %08X%c"
.Lcr: .asciz "\n"
+.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
.align
.Ldsi: .word 0x00e92dd8 >> 2
.word 0x00e92d00 >> 2
mov r1, lr
b SYMBOL_NAME(printk)
-/* Purpose: read a block of data from a hardware register to memory.
- * Proto : void insw(int from_port, void *to, int len_in_words);
- * Notes : increment to, 'to' must be 16-bit aligned
- */
-
-ENTRY(insw)
- addr r0
- teq r2, #0
- bne __raw_readsw
- RETINSTR(mov, pc, lr)
-
-ENTRY(insb)
- addr r0
- teq r2, #0
- bne __raw_readsb
- RETINSTR(mov, pc, lr)
-
-@ Purpose: write a block of data from memory to a hardware register.
-@ Proto : outsw(int to_reg, void *from, int len_in_words);
-@ Notes : increments from
-
-ENTRY(outsw)
- addr r0
- teq r2, #0
- bne __raw_writesw
- RETINSTR(mov, pc, lr)
-
-ENTRY(outsb)
- addr r0
- teq r2, #0
- bne __raw_writesb
- RETINSTR(mov, pc, lr)
-
@ Purpose: write a memc register
@ Proto : void memc_write(int register, int value);
@ Returns: nothing
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET := epxa10db.o
+
+# Object file lists.
+
+obj-y := arch.o irq.o mm.o time.o
+obj-m :=
+obj-n :=
+obj- :=
+
+export-objs :=
+
+
+include $(TOPDIR)/Rules.make
--- /dev/null
+/*
+ * linux/arch/arm/mach-epxa10db/arch.c
+ *
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+
+extern void epxa10db_map_io(void);
+extern void epxa10db_init_irq(void);
+
+
+static void __init
+epxa10db_fixup(struct machine_desc *desc, struct param_struct *params,
+ char **cmdline, struct meminfo *mi)
+{
+
+ mi->nr_banks = 1;
+ mi->bank[0].start = 0;
+ mi->bank[0].size = (32*1024*1024);
+ mi->bank[0].node = 0;
+
+/*
+ ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
+ setup_ramdisk( 1, 0, 0, 8192 );
+ setup_initrd(0xc0200000, 6*1024*1024);
+*/
+}
+
+MACHINE_START(CAMELOT, "Altera Epxa10db")
+ MAINTAINER("Altera Corporation")
+ BOOT_MEM(0x00000000, 0x7fffc000, 0xffffc000)
+ FIXUP(epxa10db_fixup)
+ MAPIO(epxa10db_map_io)
+ INITIRQ(epxa10db_init_irq)
+
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-epxa10db/dma.c
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/sched.h>
+#include <linux/malloc.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+
+#include <asm/mach/dma.h>
+
+void __init arch_dma_init(dma_t *dma)
+{
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-epxa10db/irq.c
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/platform.h>
+#include <asm/arch/int_ctrl00.h>
+
+
+static void mask_irq(unsigned int irq)
+{
+ __raw_writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+}
+
+static void unmask_irq(unsigned int irq)
+{
+ __raw_writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+}
+
+void __init epxa10db_init_irq(void)
+{
+ unsigned int i;
+
+ /*
+ * This bit sets up the interrupt controller using
+ * the 6 PLD interrupts mode (the default) each
+ * irqs is assigned a priority which is the same
+ * as its interrupt number. This scheme is used because
+ * its easy, but you may want to change it depending
+ * on the contents of your PLD
+ */
+
+ __raw_writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+ for (i = 0; i < NR_IRQS; i++){
+ __raw_writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
+ }
+
+
+ for (i = 0; i < NR_IRQS; i++) {
+
+ irq_desc[i].valid = 1;
+ irq_desc[i].probe_ok = 1;
+ irq_desc[i].mask_ack = mask_irq;
+ irq_desc[i].mask = mask_irq;
+ irq_desc[i].unmask = unmask_irq;
+ }
+
+ /* Disable all interrupt */
+ __raw_writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
+
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-epxa10db/mm.c
+ *
+ * MM routines for Altera'a Epxa10db board
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+
+/* Page table mapping for I/O region */
+
+static struct map_desc epxa10db_io_desc[] __initdata = {
+ { IO_ADDRESS(EXC_REGISTERS_BASE), EXC_REGISTERS_BASE, SZ_16K , DOMAIN_IO, 0, 1},
+{IO_ADDRESS(EXC_PLD_BLOCK0_BASE), EXC_PLD_BLOCK0_BASE, SZ_16K , DOMAIN_IO, 0, 1},
+{IO_ADDRESS(EXC_PLD_BLOCK1_BASE), EXC_PLD_BLOCK1_BASE, SZ_16K , DOMAIN_IO, 0, 1},
+{IO_ADDRESS(EXC_PLD_BLOCK2_BASE), EXC_PLD_BLOCK2_BASE, SZ_16K , DOMAIN_IO, 0, 1},
+{IO_ADDRESS(EXC_PLD_BLOCK3_BASE), EXC_PLD_BLOCK3_BASE, SZ_16K , DOMAIN_IO, 0, 1},
+{ FLASH_VADDR(EXC_EBI_BLOCK0_BASE), EXC_EBI_BLOCK0_BASE, SZ_16M , DOMAIN_IO, 0, 1},
+ LAST_DESC
+};
+
+void __init epxa10db_map_io(void)
+{
+ iotable_init(epxa10db_io_desc);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-epxa10db/time.c
+ *
+ * Copyright (C) 2000 Deep Blue Solutions
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+
+
+
+extern int (*set_rtc)(void);
+
+static int epxa10db_set_rtc(void)
+{
+ return 1;
+}
+
+static int epxa10db_rtc_init(void)
+{
+ set_rtc = epxa10db_set_rtc;
+
+ return 0;
+}
+
+__initcall(epxa10db_rtc_init);
obj-n :=
obj- :=
-export-objs := assabet.o h3600.o freebird.o huw_webpanel.o yopy.o \
- generic.o hwtimer.o irq.o usb_ctl.o usb_recv.o usb_send.o \
- dma-sa1100.o dma-sa1111.o pcipool.o sa1111-pcibuf.o
+export-objs := assabet.o dma-sa1100.o dma-sa1111.o freebird.o generic.o \
+ h3600.o huw_webpanel.o irq.o pcipool.o sa1111-pcibuf.o \
+ yopy.o
+
+# These aren't present yet, and prevents a plain -ac kernel building.
+# hwtimer.o usb_ctl.o usb_recv.o usb_send.o
# Common support (must be linked before board specific support)
obj-y += generic.o irq.o dma-sa1100.o
# We link the CPU support next, so that RAM timings can be tuned.
ifeq ($(CONFIG_CPU_FREQ),y)
obj-$(CONFIG_SA1100_ASSABET) += cpu-sa1110.o
+obj-$(CONFIG_SA1100_CERF) += cpu-sa1110.o
obj-$(CONFIG_SA1100_LART) += cpu-sa1100.o
endif
# LEDs support
leds-y := leds.o
+leds-$(CONFIG_SA1100_ADSBITSY) += leds-adsbitsy.o
leds-$(CONFIG_SA1100_ASSABET) += leds-assabet.o
leds-$(CONFIG_SA1100_BRUTUS) += leds-brutus.o
leds-$(CONFIG_SA1100_CERF) += leds-cerf.o
leds-$(CONFIG_SA1100_FLEXANET) += leds-flexanet.o
leds-$(CONFIG_SA1100_GRAPHICSCLIENT) += leds-graphicsclient.o
+leds-$(CONFIG_SA1100_GRAPHICSMASTER) += leds-graphicsmaster.o
leds-$(CONFIG_SA1100_LART) += leds-lart.o
leds-$(CONFIG_SA1100_PFS168) += leds-pfs168.o
-leds-$(CONFIG_SA1100_GRAPHICSMASTER) += leds-graphicsmaster.o
+leds-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o
obj-$(CONFIG_LEDS) += $(leds-y)
+# Miscelaneous functions
+obj-$(CONFIG_PM) += pm.o sleep.o
+
include $(TOPDIR)/Rules.make
#include <linux/tty.h>
#include <linux/module.h>
#include <linux/errno.h>
+#include <linux/serial_core.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
-#include <linux/serial_core.h>
+#include <asm/arch/assabet.h>
#include "generic.h"
-unsigned long BCR_value = BCR_DB1110;
-unsigned long SCR_value = SCR_INIT;
+unsigned long BCR_value = ASSABET_BCR_DB1110;
+unsigned long SCR_value = ASSABET_SCR_INIT;
EXPORT_SYMBOL(BCR_value);
EXPORT_SYMBOL(SCR_value);
* This must precede any driver calls to BCR_set()
* or BCR_clear().
*/
- BCR = BCR_value = BCR_DB1111;
+ ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
NCR_0 = 0;
#ifndef CONFIG_ASSABET_NEPONSET
*/
static void __init map_sa1100_gpio_regs( void )
{
- unsigned long phys = _GPLR & PMD_MASK;
+ unsigned long phys = __PREG(GPLR) & PMD_MASK;
unsigned long virt = io_p2v(phys);
int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
pmd_t pmd;
{
if (port->mapbase == _Ser1UTCR0) {
if (state)
- BCR_clear(BCR_RS232EN);
+ ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
else
- BCR_set(BCR_RS232EN);
+ ASSABET_BCR_set(ASSABET_BCR_RS232EN);
}
}
/*
* Note! this can be called from IRQ context.
- * FIXME: You _need_ to handle BCR carefully, which doesn't
+ * FIXME: You _need_ to handle ASSABET_BCR carefully, which doesn't
* happen at the moment. Suggest putting interrupt save/restore
- * in BCR_set/clear.
+ * in ASSABET_BCR_set/clear.
*
* NB: Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
* and UART3 (radio module). We only handle them for UART1 here.
u_int set = 0, clear = 0;
if (mctrl & TIOCM_RTS)
- set |= BCR_COM_RTS;
+ set |= ASSABET_BCR_COM_RTS;
else
- clear |= BCR_COM_RTS;
+ clear |= ASSABET_BCR_COM_RTS;
if (mctrl & TIOCM_DTR)
- set |= BCR_COM_DTR;
+ set |= ASSABET_BCR_COM_DTR;
else
- clear |= BCR_COM_DTR;
+ clear |= ASSABET_BCR_COM_DTR;
- BCR_clear(clear);
- BCR_set(set);
+ ASSABET_BCR_clear(clear);
+ ASSABET_BCR_set(set);
}
}
static int assabet_get_mctrl(struct uart_port *port)
{
u_int ret = 0;
- u_int bsr = BSR;
+ u_int bsr = ASSABET_BSR;
/* need 2 reads to read current value */
- bsr = BSR;
+ bsr = ASSABET_BSR;
if (port->mapbase == _Ser1UTCR0) {
- if (bsr & BSR_COM_DCD)
+ if (bsr & ASSABET_BSR_COM_DCD)
ret |= TIOCM_CD;
- if (bsr & BSR_COM_CTS)
+ if (bsr & ASSABET_BSR_COM_CTS)
ret |= TIOCM_CTS;
- if (bsr & BSR_COM_DSR)
+ if (bsr & ASSABET_BSR_COM_DSR)
ret |= TIOCM_DSR;
} else if (port->mapbase == _Ser3UTCR0) {
- if (bsr & BSR_RAD_DCD)
+ if (bsr & ASSABET_BSR_RAD_DCD)
ret |= TIOCM_CD;
- if (bsr & BSR_RAD_CTS)
+ if (bsr & ASSABET_BSR_RAD_CTS)
ret |= TIOCM_CTS;
- if (bsr & BSR_RAD_DSR)
+ if (bsr & ASSABET_BSR_RAD_DSR)
ret |= TIOCM_DSR;
- if (bsr & BSR_RAD_RI)
+ if (bsr & ASSABET_BSR_RAD_RI)
ret |= TIOCM_RI;
} else {
ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
*/
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
+
+ /*
+ * Set up registers for sleep mode.
+ */
+ PWER = PWER_GPIO0;
+ PGSR = 0;
+ PCFR = 0;
+
+ /*
+ * Clear all possible wakeup reasons.
+ */
+ RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
}
#include "generic.h"
+static void __init cerf_init_irq (void)
+{
+ sa1100_init_irq();
+
+ /* Need to register these as rising edge interrupts
+ * For standard 16550 serial driver support
+ * Basically - I copied it from pfs168.c :)
+ */
+#ifdef CONFIG_SA1100_CERF_CPLD
+ set_GPIO_IRQ_edge(GPIO_GPIO(3), GPIO_RISING_EDGE); /* PDA Full serial port */
+ set_GPIO_IRQ_edge(GPIO_GPIO(2), GPIO_RISING_EDGE); /* PDA Bluetooth */
+ GPDR &= ~(GPIO_GPIO(3)); /* Set the direction of serial port GPIO pin to in */
+ GPDR &= ~(GPIO_GPIO(2)); /* Set the direction of bluetooth GPIO pin to in */
+#endif /* CONFIG_SA1100_CERF_CPLD */
+}
+
static void __init
fixup_cerf(struct machine_desc *desc, struct param_struct *params,
char **cmdline, struct meminfo *mi)
{
-#ifdef CONFIG_SA1100_CERF_32MB
- // 32MB RAM
+#if defined(CONFIG_SA1100_CERF_64MB)
+ // 64MB RAM
+ SET_BANK( 0, 0xc0000000, 64*1024*1024 );
+ mi->nr_banks = 1;
+#elif defined(CONFIG_SA1100_CERF_32MB) // 32MB RAM
SET_BANK( 0, 0xc0000000, 32*1024*1024 );
mi->nr_banks = 1;
-#else
- // 16Meg Ram.
+#elif defined(CONFIG_SA1100_CERF_16MB) // 16Meg Ram.
SET_BANK( 0, 0xc0000000, 8*1024*1024 );
- SET_BANK( 1, 0xc8000000, 8*1024*1024 ); // comment this out for 8MB Cerfs
+ SET_BANK( 1, 0xc8000000, 8*1024*1024 );
mi->nr_banks = 2;
+#elif defined(CONFIG_SA1100_CERF_8MB)
+ // 8Meg Ram.
+ SET_BANK( 0, 0xc0000000, 8*1024*1024 );
+ mi->nr_banks = 1;
+#else
+ #error "Undefined memory size for Cerfboard."
#endif
- ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
- setup_ramdisk(1, 0, 0, 8192);
- // Save 2Meg for RAMDisk
- setup_initrd(0xc0500000, 3*1024*1024);
+// ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
+// setup_ramdisk(1, 0, 0, 8192);
+// // Save 2Meg for RAMDisk
+// setup_initrd(0xc0500000, 3*1024*1024);
}
static struct map_desc cerf_io_desc[] __initdata = {
- /* virtual physical length domain r w c b */
- { 0xe8000000, 0x00000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
- { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Crystal Chip */
+ /* virtual physical length domain r w c b */
+ { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
+ { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Crystal Ethernet Chip */
+#ifdef CONFIG_SA1100_CERF_CPLD
+ { 0xf1000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CPLD Chip */
+ { 0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CerfPDA Bluetooth */
+ { 0xf3000000, 0x18000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CerfPDA Serial */
+#endif
LAST_DESC
};
sa1100_map_io();
iotable_init(cerf_io_desc);
- sa1100_register_uart(0, 3);
+ sa1100_register_uart(0, 3);
+#ifdef CONFIG_SA1100_CERF_IRDA_ENABLED
sa1100_register_uart(1, 1);
+#else
+ sa1100_register_uart(1, 2);
+ sa1100_register_uart(2, 1);
+#endif
}
-MACHINE_START(CERF, "Intrinsyc CerfBoard")
- MAINTAINER("Pieter Truter")
+MACHINE_START(CERF, "Intrinsyc's Cerf Family of Products")
+ MAINTAINER("support@intrinsyc.com")
BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
FIXUP(fixup_cerf)
MAPIO(cerf_map_io)
- INITIRQ(sa1100_init_irq)
+ INITIRQ(cerf_init_irq)
MACHINE_END
int channel;
for (channel = 0; channel < SA1100_DMA_CHANNELS; channel++) {
dma_chan[channel].regs =
- (dma_regs_t *) io_p2v(_DDAR(channel));
+ (dma_regs_t *) &DDAR(channel);
dma_chan[channel].irq = IRQ_DMA0 + channel;
}
return 0;
#include <asm/io.h>
#include <asm/dma.h>
-
// #define DEBUG
#ifdef DEBUG
#define DPRINTK( s, arg... ) printk( "dma<%s>: " s, dma->device_id , ##arg )
* SDRAM bank 1 on Neponset). The default configuration selects
* Assabet, so any address in bank 1 is necessarily invalid.
*/
- if((machine_is_assabet() || machine_is_pfs168()) && addr >= _DRAMBnk1)
+ if((machine_is_assabet() || machine_is_pfs168()) && addr >= 0xc8000000)
return -1;
/* The bug only applies to buffers located more than one megabyte
return -1;
break;
default:
- printk(KERN_ERR "%s(): invalid SMCR DRAC value 0%o\n",
+ printk(KERN_ERR "%s(): invalid SMCR DRAC value 0%lo\n",
__FUNCTION__, FExtr(SBI_SMCR, SMCR_DRAC));
return -1;
}
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
+
+ /* Set up sleep mode registers */
+ PWER = 0x1;
+ PGSR = 0x0;
+ PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS;
}
MACHINE_START(FREEBIRD, "Freebird-HPC-1.1")
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
+#include <linux/serial_core.h>
#include <asm/arch/irq.h>
LAST_DESC
};
+static struct gc_uart_ctrl_data_t gc_uart_ctrl_data[] = {
+ { GPIO_GC_UART0_CTS, 0, NULL,NULL },
+ { GPIO_GC_UART1_CTS, 0, NULL,NULL },
+ { GPIO_GC_UART2_CTS, 0, NULL,NULL }
+};
+
+static void
+graphicsclient_cts_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct gc_uart_ctrl_data_t * uart_data = (struct gc_uart_ctrl_data_t *)dev_id;
+ int cts = !(GPLR & uart_data->cts_gpio);
+
+ /* NOTE: I supose that we will no get any interrupt
+ if the GPIO is not changed, so maybe
+ the cts_prev_state can be removed ... */
+ if (cts != uart_data->cts_prev_state) {
+ uart_data->cts_prev_state = cts;
+
+ uart_handle_cts_change(uart_data->info, cts);
+ }
+}
+
+static int
+graphicsclient_register_cts_intr(int gpio, int irq,
+ struct gc_uart_ctrl_data_t *uart_data)
+{
+ int ret = 0;
+
+ set_GPIO_IRQ_edge(gpio, GPIO_BOTH_EDGES);
+
+ ret = request_irq(irq, graphicsclient_cts_intr,
+ 0, "GC RS232 CTS", uart_data);
+ if (ret) {
+ printk(KERN_ERR "uart_open: failed to register CTS irq (%d)\n",
+ ret);
+ free_irq(irq, uart_data);
+ }
+
+ return ret;
+}
+
+static int
+graphicsclient_uart_open(struct uart_port *port, struct uart_info *info)
+{
+ int ret = 0;
+
+ if (port->mapbase == _Ser1UTCR0) {
+ Ser1SDCR0 |= SDCR0_UART;
+ /* Set RTS Output */
+ GPDR |= GPIO_GC_UART0_RTS;
+ GPSR = GPIO_GC_UART0_RTS;
+
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GC_UART0_CTS;
+
+ gc_uart_ctrl_data[0].cts_prev_state = 0;
+ gc_uart_ctrl_data[0].info = info;
+ gc_uart_ctrl_data[0].port = port;
+
+ /* register uart0 CTS irq */
+ ret = graphicsclient_register_cts_intr(GPIO_GC_UART0_CTS,
+ IRQ_GC_UART0_CTS,
+ &gc_uart_ctrl_data[0]);
+ } else if (port->mapbase == _Ser2UTCR0) {
+ Ser2UTCR4 = Ser2HSCR0 = 0;
+ /* Set RTS Output */
+ GPDR |= GPIO_GC_UART1_RTS;
+ GPSR = GPIO_GC_UART1_RTS;
+
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GC_UART1_RTS;
+
+ gc_uart_ctrl_data[1].cts_prev_state = 0;
+ gc_uart_ctrl_data[1].info = info;
+ gc_uart_ctrl_data[1].port = port;
+
+ /* register uart1 CTS irq */
+ ret = graphicsclient_register_cts_intr(GPIO_GC_UART1_CTS,
+ IRQ_GC_UART1_CTS,
+ &gc_uart_ctrl_data[1]);
+ } else if (port->mapbase == _Ser3UTCR0) {
+ /* Set RTS Output */
+ GPDR |= GPIO_GC_UART2_RTS;
+ GPSR = GPIO_GC_UART2_RTS;
+
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GC_UART2_RTS;
+
+ gc_uart_ctrl_data[2].cts_prev_state = 0;
+ gc_uart_ctrl_data[2].info = info;
+ gc_uart_ctrl_data[2].port = port;
+
+ /* register uart2 CTS irq */
+ ret = graphicsclient_register_cts_intr(GPIO_GC_UART2_CTS,
+ IRQ_GC_UART2_CTS,
+ &gc_uart_ctrl_data[2]);
+ }
+ return ret;
+}
+
+static int
+graphicsclient_uart_close(struct uart_port *port, struct uart_info *info)
+{
+ if (port->mapbase == _Ser1UTCR0) {
+ free_irq(IRQ_GC_UART0_CTS, &gc_uart_ctrl_data[0]);
+ } else if (port->mapbase == _Ser2UTCR0) {
+ free_irq(IRQ_GC_UART1_CTS, &gc_uart_ctrl_data[1]);
+ } else if (port->mapbase == _Ser3UTCR0) {
+ free_irq(IRQ_GC_UART2_CTS, &gc_uart_ctrl_data[2]);
+ }
+
+ return 0;
+}
+
+static int graphicsclient_get_mctrl(struct uart_port *port)
+{
+ int result = TIOCM_CD | TIOCM_DSR;
+
+ if (port->mapbase == _Ser1UTCR0) {
+ if (!(GPLR & GPIO_GC_UART0_CTS))
+ result |= TIOCM_CTS;
+ } else if (port->mapbase == _Ser2UTCR0) {
+ if (!(GPLR & GPIO_GC_UART1_CTS))
+ result |= TIOCM_CTS;
+ } else if (port->mapbase == _Ser3UTCR0) {
+ if (!(GPLR & GPIO_GC_UART2_CTS))
+ result |= TIOCM_CTS;
+ } else {
+ result = TIOCM_CTS;
+ }
+
+ return result;
+}
+
+static void graphicsclient_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+ if (port->mapbase == _Ser1UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GC_UART0_RTS;
+ else
+ GPSR = GPIO_GC_UART0_RTS;
+ } else if (port->mapbase == _Ser2UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GC_UART1_RTS;
+ else
+ GPSR = GPIO_GC_UART1_RTS;
+ } else if (port->mapbase == _Ser3UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GC_UART2_RTS;
+ else
+ GPSR = GPIO_GC_UART2_RTS;
+ }
+}
+
+static void
+graphicsclient_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+ if (!state) {
+ /* make serial ports work ... */
+ Ser2UTCR4 = 0;
+ Ser2HSCR0 = 0;
+ Ser1SDCR0 |= SDCR0_UART;
+ }
+}
+
+static struct sa1100_port_fns graphicsclient_port_fns __initdata = {
+ open: graphicsclient_uart_open,
+ close: graphicsclient_uart_close,
+ get_mctrl: graphicsclient_get_mctrl,
+ set_mctrl: graphicsclient_set_mctrl,
+ pm: graphicsclient_uart_pm,
+};
+
static void __init graphicsclient_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsclient_io_desc);
+ sa1100_register_uart_fns(&graphicsclient_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
LAST_DESC
};
+static int graphicsmaster_uart_open(struct uart_port *port, struct uart_info *info)
+{
+ int ret = 0;
+
+ if (port->mapbase == _Ser1UTCR0) {
+ Ser1SDCR0 |= SDCR0_UART;
+ /* Set RTS Output */
+ GPSR = GPIO_GPIO15;
+ GPDR |= GPIO_GPIO15;
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GPIO14;
+ }
+ else if (port->mapbase == _Ser2UTCR0) {
+ Ser2UTCR4 = Ser2HSCR0 = 0;
+ /* Set RTS Output */
+ GPSR = GPIO_GPIO17;
+ GPDR |= GPIO_GPIO17;
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GPIO16;
+ }
+ else if (port->mapbase == _Ser3UTCR0) {
+ /* Set RTS Output */
+ GPSR = GPIO_GPIO19;
+ GPDR |= GPIO_GPIO19;
+ /* Set CTS Input */
+ GPDR &= ~GPIO_GPIO18;
+ }
+ return ret;
+}
+
+static int graphicsmaster_get_mctrl(struct uart_port *port)
+{
+ int result = TIOCM_CD | TIOCM_DSR;
+
+ if (port->mapbase == _Ser1UTCR0) {
+ if (!(GPLR & GPIO_GPIO14))
+ result |= TIOCM_CTS;
+ } else if (port->mapbase == _Ser2UTCR0) {
+ if (!(GPLR & GPIO_GPIO16))
+ result |= TIOCM_CTS;
+ } else if (port->mapbase == _Ser3UTCR0) {
+ if (!(GPLR & GPIO_GPIO17))
+ result |= TIOCM_CTS;
+ } else {
+ result = TIOCM_CTS;
+ }
+
+ return result;
+}
+
+static void graphicsmaster_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+ if (port->mapbase == _Ser1UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GPIO15;
+ else
+ GPSR = GPIO_GPIO15;
+ } else if (port->mapbase == _Ser2UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GPIO17;
+ else
+ GPSR = GPIO_GPIO17;
+ } else if (port->mapbase == _Ser3UTCR0) {
+ if (mctrl & TIOCM_RTS)
+ GPCR = GPIO_GPIO19;
+ else
+ GPSR = GPIO_GPIO19;
+ }
+}
+
+static void
+graphicsmaster_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+ if (!state) {
+ /* make serial ports work ... */
+ Ser2UTCR4 = 0;
+ Ser2HSCR0 = 0;
+ Ser1SDCR0 |= SDCR0_UART;
+ }
+}
+
+static struct sa1100_port_fns graphicsmaster_port_fns __initdata = {
+ open: graphicsmaster_uart_open,
+ get_mctrl: graphicsmaster_get_mctrl,
+ set_mctrl: graphicsmaster_set_mctrl,
+ pm: graphicsmaster_uart_pm,
+};
+
static void __init graphicsmaster_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsmaster_io_desc);
+ sa1100_register_uart_fns(&graphicsmaster_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
static int h3600_egpio = EGPIO_H3600_RS232_ON;
+void init_h3600_egpio(void)
+{
+#ifdef CONFIG_IPAQ_H3100
+ int h3100_controls = (GPIO_H3100_BT_ON
+ | GPIO_H3100_QMUTE
+ | GPIO_H3100_LCD_3V_ON
+ | GPIO_H3100_AUD_ON
+ | GPIO_H3100_AUD_PWR_ON
+ | GPIO_H3100_IR_ON
+ | GPIO_H3100_IR_FSEL);
+ GPDR |= h3100_controls;
+ GPCR = h3100_controls;
+ GAFR = GPIO_SSP_CLK;
+#endif
+}
+
void clr_h3600_egpio(unsigned long x)
{
+#ifdef CONFIG_IPAQ_H3100
+ unsigned long gpcr = 0;
+ if (x&EGPIO_H3600_QMUTE)
+ gpcr |= GPIO_H3100_QMUTE;
+ if (x&EGPIO_H3600_LCD_ON)
+ gpcr |= GPIO_H3100_LCD_3V_ON;
+ if (x&EGPIO_H3600_AUD_AMP_ON)
+ gpcr |= GPIO_H3100_AUD_ON;
+ if (x&EGPIO_H3600_AUD_PWR_ON)
+ gpcr |= GPIO_H3100_AUD_PWR_ON;
+ if (x&EGPIO_H3600_IR_ON)
+ gpcr |= GPIO_H3100_IR_ON;
+ if (x&EGPIO_H3600_IR_FSEL)
+ gpcr |= GPIO_H3100_IR_FSEL;
+ GPCR = gpcr;
+#endif
h3600_egpio &= ~x;
H3600_EGPIO = h3600_egpio;
}
void set_h3600_egpio(unsigned long x)
{
+#ifdef CONFIG_IPAQ_H3100
+ unsigned long gpsr = 0;
+ if (x&EGPIO_H3600_QMUTE)
+ gpsr |= GPIO_H3100_QMUTE;
+ if (x&EGPIO_H3600_LCD_ON)
+ gpsr |= GPIO_H3100_LCD_3V_ON;
+ if (x&EGPIO_H3600_AUD_AMP_ON)
+ gpsr |= GPIO_H3100_AUD_ON;
+ if (x&EGPIO_H3600_AUD_PWR_ON)
+ gpsr |= GPIO_H3100_AUD_PWR_ON;
+ if (x&EGPIO_H3600_IR_ON)
+ gpsr |= GPIO_H3100_IR_ON;
+ if (x&EGPIO_H3600_IR_FSEL)
+ gpsr |= GPIO_H3100_IR_FSEL;
+ GPSR = gpsr;
+#endif
h3600_egpio |= x;
H3600_EGPIO = h3600_egpio;
}
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
{ 0xf0000000, 0x49000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */
- { 0xf1000000, 0x10000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 2 */
- { 0xf3000000, 0x40000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 4 */
+ { 0xf1000000, 0x10000000, 0x02800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 2 */
+ { 0xf3800000, 0x40000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 4 */
LAST_DESC
};
sa1100_register_uart_fns(&h3600_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1); /* isn't this one driven elsewhere? */
- sa1100_register_uart(2, 2);
+ init_h3600_egpio();
/*
* Default GPIO settings.
*/
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+
+ /* Configure suspend conditions */
+ PGSR = 0;
+ PWER = 0x1 | (1 << 31);
+ PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS;
}
MACHINE_START(H3600, "Compaq iPAQ")
--- /dev/null
+/*
+ * linux/arch/arm/mach-sa1100/leds-adsbitsy.c
+ *
+ * ADS Bitsy LED
+ * 7/25/01 Woojung Huh
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED 1
+#define LED_STATE_CLAIMED 2
+
+static unsigned int led_state;
+static unsigned int hw_led_state;
+
+#define LED_TIMER GPIO_GPIO20 /* green heartbeat */
+
+#define LED_MASK (LED_TIMER)
+
+void adsbitsy_leds_event(led_event_t evt)
+{
+ unsigned long flags;
+
+ save_flags_cli(flags);
+
+ switch (evt) {
+ case led_start:
+ hw_led_state = 0; /* gc leds are positive logic */
+ led_state = LED_STATE_ENABLED;
+ break;
+
+ case led_stop:
+ led_state &= ~LED_STATE_ENABLED;
+ break;
+
+ case led_claim:
+ led_state |= LED_STATE_CLAIMED;
+ hw_led_state = LED_MASK;
+ break;
+
+ case led_release:
+ led_state &= ~LED_STATE_CLAIMED;
+ hw_led_state = LED_MASK;
+ break;
+
+#ifdef CONFIG_LEDS_TIMER
+ case led_timer:
+ if (!(led_state & LED_STATE_CLAIMED))
+ hw_led_state ^= LED_TIMER;
+ break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+ case led_idle_start:
+ break;
+
+ case led_idle_end:
+ break;
+#endif
+
+ case led_green_on:
+ break;
+
+ case led_green_off:
+ break;
+
+ case led_amber_on:
+ break;
+
+ case led_amber_off:
+ break;
+
+ case led_red_on:
+ break;
+
+ case led_red_off:
+ break;
+
+ default:
+ break;
+ }
+
+ if (led_state & LED_STATE_ENABLED) {
+ GPSR = hw_led_state;
+ GPCR = hw_led_state ^ LED_MASK;
+ }
+
+ restore_flags(flags);
+}
#include <asm/hardware.h>
#include <asm/leds.h>
#include <asm/system.h>
+#include <asm/arch/assabet.h>
#include "leds.h"
static unsigned int led_state;
static unsigned int hw_led_state;
-#define BCR_LED_MASK (BCR_LED_GREEN | BCR_LED_RED)
+#define ASSABET_BCR_LED_MASK (ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED)
void assabet_leds_event(led_event_t evt)
{
switch (evt) {
case led_start:
- hw_led_state = BCR_LED_RED | BCR_LED_GREEN;
+ hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
led_state = LED_STATE_ENABLED;
break;
case led_claim:
led_state |= LED_STATE_CLAIMED;
- hw_led_state = BCR_LED_RED | BCR_LED_GREEN;
+ hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
break;
case led_release:
led_state &= ~LED_STATE_CLAIMED;
- hw_led_state = BCR_LED_RED | BCR_LED_GREEN;
+ hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
break;
#ifdef CONFIG_LEDS_TIMER
case led_timer:
if (!(led_state & LED_STATE_CLAIMED))
- hw_led_state ^= BCR_LED_GREEN;
+ hw_led_state ^= ASSABET_BCR_LED_GREEN;
break;
#endif
#ifdef CONFIG_LEDS_CPU
case led_idle_start:
if (!(led_state & LED_STATE_CLAIMED))
- hw_led_state |= BCR_LED_RED;
+ hw_led_state |= ASSABET_BCR_LED_RED;
break;
case led_idle_end:
if (!(led_state & LED_STATE_CLAIMED))
- hw_led_state &= ~BCR_LED_RED;
+ hw_led_state &= ~ASSABET_BCR_LED_RED;
break;
#endif
case led_green_on:
if (led_state & LED_STATE_CLAIMED)
- hw_led_state &= ~BCR_LED_GREEN;
+ hw_led_state &= ~ASSABET_BCR_LED_GREEN;
break;
case led_green_off:
if (led_state & LED_STATE_CLAIMED)
- hw_led_state |= BCR_LED_GREEN;
+ hw_led_state |= ASSABET_BCR_LED_GREEN;
break;
case led_amber_on:
case led_red_on:
if (led_state & LED_STATE_CLAIMED)
- hw_led_state &= ~BCR_LED_RED;
+ hw_led_state &= ~ASSABET_BCR_LED_RED;
break;
case led_red_off:
if (led_state & LED_STATE_CLAIMED)
- hw_led_state |= BCR_LED_RED;
+ hw_led_state |= ASSABET_BCR_LED_RED;
break;
default:
}
if (led_state & LED_STATE_ENABLED)
- BCR = BCR_value = (BCR_value & ~BCR_LED_MASK) | hw_led_state;
+ ASSABET_BCR = BCR_value = (BCR_value & ~ASSABET_BCR_LED_MASK) |
+ hw_led_state;
local_irq_restore(flags);
}
static unsigned int led_state;
static unsigned int hw_led_state;
+#ifdef CONFIG_SA1100_CERF_CPLD
+
+#define LED_D0 GPIO_GPIO(0)
+#define LED_D1 GPIO_GPIO(0)
+#define LED_D2 GPIO_GPIO(0)
+#define LED_D3 GPIO_GPIO(0)
+#define LED_MASK (LED_D0|LED_D1|LED_D2|LED_D3)
+
+#else
+
#define LED_D0 GPIO_GPIO(0)
#define LED_D1 GPIO_GPIO(1)
#define LED_D2 GPIO_GPIO(2)
#define LED_D3 GPIO_GPIO(3)
#define LED_MASK (LED_D0|LED_D1|LED_D2|LED_D3)
+#endif
+
void cerf_leds_event(led_event_t evt)
{
unsigned long flags;
#define LED_GREEN (1)
#define LED_MASK (1)
+extern void set_cs3_bit(int value);
+extern void clear_cs3_bit(int value);
+
void simpad_leds_event(led_event_t evt)
{
unsigned long flags;
//local_irq_save(flags);
- switch (evt)
+ switch (evt)
{
case led_start:
hw_led_state = LED_GREEN;
}
if (led_state & LED_STATE_ENABLED)
- cs3_shadow |= LED2_ON;
-
+ set_cs3_bit(LED2_ON);
+ else
+ clear_cs3_bit(LED2_ON);
//local_irq_restore(flags);
}
leds_event = pfs168_leds_event;
if (machine_is_graphicsmaster())
leds_event = graphicsmaster_leds_event;
+ if (machine_is_adsbitsy())
+ leds_event = adsbitsy_leds_event;
leds_event(led_start);
return 0;
extern void lart_leds_event(led_event_t evt);
extern void pfs168_leds_event(led_event_t evt);
extern void graphicsmaster_leds_event(led_event_t evt);
+extern void adsbitsy_leds_event(led_event_t evt);
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
+#include <linux/serial_core.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/irq.h>
#include <asm/mach/serial_sa1100.h>
-#include <linux/serial_core.h>
+#include <asm/arch/assabet.h>
#include "sa1111.h"
irq = NEPONSET_USAR_IRQ;
irq_desc[irq].valid = 1;
irq_desc[irq].probe_ok = 1;
- set_GPIO_IRQ_edge( GPIO_NEP_IRQ, GPIO_RISING_EDGE );
- setup_arm_irq( IRQ_GPIO_NEP_IRQ, &neponset_irq );
+ set_GPIO_IRQ_edge(ASSABET_GPIO_NEP_IRQ, GPIO_RISING_EDGE);
+ setup_arm_irq(ASSABET_IRQ_GPIO_NEP_IRQ, &neponset_irq);
}
static int __init neponset_init(void)
--- /dev/null
+/*
+ * SA1100 Power Management Routines
+ *
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ *
+ * History:
+ *
+ * 2001-02-06: Cliff Brake Initial code
+ *
+ * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
+ * Chester Kuo <chester@linux.org.tw>
+ * Save more value for the resume function! Support
+ * Bitsy/Assabet/Freebird board
+ *
+ * 2001-08-29: Nicolas Pitre <nico@cam.org>
+ * Cleaned up, pushed platform dependent stuff
+ * in the platform specific files.
+ */
+
+/*
+ * Debug macros
+ */
+#define DEBUG 1
+#ifdef DEBUG
+# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+# define DPRINTK(fmt, args...)
+#endif
+
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+#include <linux/acpi.h>
+
+#include <asm/hardware.h>
+#include <asm/memory.h>
+#include <asm/system.h>
+
+#include "sleep.h"
+
+extern void sa1100_cpu_suspend(void);
+extern void sa1100_cpu_resume(void);
+
+extern unsigned long *sleep_save; /* virtual address */
+extern unsigned long sleep_save_p; /* physical address */
+
+#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
+#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
+
+int pm_do_suspend(void)
+{
+ int retval;
+
+ /* set up pointer to sleep parameters */
+ sleep_save = kmalloc (SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC);
+ if (!sleep_save)
+ return -ENOMEM;
+ sleep_save_p = virt_to_phys(sleep_save);
+
+ retval = pm_send_all(PM_SUSPEND, (void *)2);
+ if (retval) {
+ kfree(sleep_save);
+ return retval;
+ }
+
+ cli();
+
+ /* preserve current time */
+ RCNR = xtime.tv_sec;
+
+ /* save vital registers */
+ SAVE(OSCR);
+ SAVE(OSMR0);
+ SAVE(OSMR1);
+ SAVE(OSMR2);
+ SAVE(OSMR3);
+ SAVE(OIER);
+
+ SAVE(GPDR);
+ SAVE(GRER);
+ SAVE(GFER);
+ SAVE(GAFR);
+
+ SAVE(PPDR);
+ SAVE(PPSR);
+ SAVE(PPAR);
+ SAVE(PSDR);
+
+ SAVE(Ser1SDCR0);
+
+ SAVE(ICMR);
+
+ /* ... maybe a global variable initialized by arch code to set this? */
+ GRER = PWER;
+ GFER = 0;
+ GEDR = GEDR;
+
+ /* Clear previous reset status */
+ RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
+
+ /* set resume return address */
+ PSPR = virt_to_phys(sa1100_cpu_resume);
+
+ /* go zzz */
+ sa1100_cpu_suspend();
+
+ /* ensure not to come back here if it wasn't intended */
+ PSPR = 0;
+
+ DPRINTK("*** made it back from resume\n");
+
+ /* restore registers */
+ RESTORE(GPDR);
+ RESTORE(GRER);
+ RESTORE(GFER);
+ RESTORE(GAFR);
+
+ /* clear any edge detect bit */
+ GEDR = GEDR;
+
+ RESTORE(PPDR);
+ RESTORE(PPSR);
+ RESTORE(PPAR);
+ RESTORE(PSDR);
+
+ RESTORE(Ser1SDCR0);
+
+ PSSR = PSSR_PH;
+
+ RESTORE(OSMR0);
+ RESTORE(OSMR1);
+ RESTORE(OSMR2);
+ RESTORE(OSMR3);
+ RESTORE(OSCR);
+ RESTORE(OIER);
+
+ ICLR = 0;
+ ICCR = 1;
+ RESTORE(ICMR);
+
+ /* restore current time */
+ xtime.tv_sec = RCNR;
+
+ sti();
+
+ kfree (sleep_save);
+
+ retval = pm_send_all(PM_RESUME, (void *)0);
+ if (retval)
+ return retval;
+
+ return 0;
+}
+
+
+static struct ctl_table pm_table[] =
+{
+ {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&pm_do_suspend},
+ {0}
+};
+
+static struct ctl_table pm_dir_table[] =
+{
+ {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
+ {0}
+};
+
+/*
+ * Initialize power interface
+ */
+static int __init pm_init(void)
+{
+ register_sysctl_table(pm_dir_table, 1);
+ return 0;
+}
+
+__initcall(pm_init);
+
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
+#include <linux/proc_fs.h>
+#include <linux/string.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
+#include <linux/serial_core.h>
#include "generic.h"
-void init_simpad_cs3()
+long cs3_shadow;
+
+static int __init simpad_init(void)
+{
+ PSPR = 0xc0008000;
+ GPDR &= ~GPIO_GPIO0;
+ cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
+ ENABLE_5V | RESET_SIMCARD);
+ *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
+ return 0;
+}
+
+__initcall(simpad_init);
+
+long get_cs3_shadow()
{
- cs3_shadow =(DISPLAY_ON | RS232_ON | PCMCIA_BUFF_DIS | RESET_SIMCARD);
- printk("\nCall CS3 init:%x\n",cs3_shadow);
- *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
- cs3_shadow =(DISPLAY_ON| RS232_ON |RESET_SIMCARD);
+ return cs3_shadow;
}
-void PCMCIA_setbit(int value)
+void set_cs3_bit(int value)
{
- cs3_shadow |= value;
+ cs3_shadow |= value;
+ *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
}
-void PCMCIA_clearbit(int value)
+void clear_cs3_bit(int value)
{
- cs3_shadow &= ~value;
+ cs3_shadow &= ~value;
+ *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
}
static void __init
fixup_simpad(struct machine_desc *desc, struct param_struct *params,
char **cmdline, struct meminfo *mi)
{
-#ifdef CONFIG_SA1100_SIMPAD_64MB
+#ifdef CONFIG_SA1100_SIMPAD_DRAM_64MB /* DRAM */
SET_BANK( 0, 0xc0000000, 64*1024*1024 );
#else
SET_BANK( 0, 0xc0000000, 32*1024*1024 );
mi->nr_banks = 1;
ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
setup_ramdisk( 1, 0, 0, 8192 );
- setup_initrd( __phys_to_virt(0xc0800000), 8*1024*1024 );
+ setup_initrd( __phys_to_virt(0xc0800000), 4*1024*1024 );
}
static struct map_desc simpad_io_desc[] __initdata = {
- /* virtual physical length domain r w c b */
- { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0, neccessary for mtd */
- { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */
+ /* virtual physical length domain r w c b */
+ { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 },
+ { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */
{ 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
LAST_DESC
};
+
+static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+ if (port->mapbase == (u_int)&Ser1UTCR0) {
+ if (state)
+ clear_cs3_bit(RS232_ON);
+ else
+ set_cs3_bit(RS232_ON);
+ }
+}
+
+static struct sa1100_port_fns simpad_port_fns __initdata = {
+ pm: simpad_uart_pm,
+};
+
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc);
+#ifndef CONFIG_SERIAL_SA1100_OLD
+ //It is only possible to register 3 UART in serial_sa1100.c
sa1100_register_uart(0, 3);
- sa1100_register_uart(1, 1);
+ sa1100_register_uart(1, 1);
+#endif
+}
+
+#ifdef CONFIG_PROC_FS
+
+static char* name[]={
+ "VCC_5V_EN",
+ "VCC_3V_EN",
+ "EN1",
+ "EN0",
+ "DISPLAY_ON",
+ "PCMCIA_BUFF_DIS",
+ "MQ_RESET",
+ "PCMCIA_RESET",
+ "DECT_POWER_ON",
+ "IRDA_SD",
+ "RS232_ON",
+ "SD_MEDIAQ",
+ "LED2_ON",
+ "IRDA_MODE",
+ "ENABLE_5V",
+ "RESET_SIMCARD"
+};
+
+static int proc_cs3_read(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ char *p = page;
+ int len, i;
+
+ p += sprintf(p, "Chipselect3 : %x\n", cs3_shadow);
+ for (i = 0; i <= 15; i++) {
+ if(cs3_shadow & (1<<i)) {
+ p += sprintf(p, "%s\t: TRUE \n",name[i]);
+ } else
+ p += sprintf(p, "%s\t: FALSE \n",name[i]);
+ }
+ len = (p - page) - off;
+ if (len < 0)
+ len = 0;
+
+ *eof = (len <= count) ? 1 : 0;
+ *start = page + off;
+
+ return len;
}
+
+
+static struct proc_dir_entry *proc_cs3;
+
+static int __init cs3_init(void)
+{
+ proc_cs3 = create_proc_entry("cs3", 0, 0);
+ if (proc_cs3)
+ proc_cs3->read_proc = proc_cs3_read;
+ return 0;
+}
+
+static int __exit cs3_exit(void)
+{
+ if (proc_cs3)
+ remove_proc_entry( "cs3", 0);
+ return 0;
+}
+__initcall(cs3_init);
+#endif // CONFIG_PROC_FS
MACHINE_START(SIMPAD, "Simpad")
MAINTAINER("Juergen Messerer")
--- /dev/null
+/*
+ * SA11x0 Assembler Sleep/WakeUp Management Routines
+ *
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ *
+ * History:
+ *
+ * 2001-02-06: Cliff Brake Initial code
+ *
+ * 2001-08-29: Nicolas Pitre Simplified.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/hardware.h>
+#include "sleep.h"
+
+/*
+ * sa1100_cpu_suspend()
+ *
+ * Causes sa11x0 to enter sleep state
+ *
+ */
+
+ .text
+
+ENTRY(sleep_save) .word 0 @ virtual address of parameter array
+ENTRY(sleep_save_p) .word 0 @ physical address of parameter array
+
+ENTRY(sa1100_cpu_suspend)
+
+ @ save registers on stack
+ stmfd sp!, {r4 - r12, lr}
+
+ @ load virtual address for sleep_save array
+ ldr r4, sleep_save
+
+ @ save stack pointer
+ str sp, [r4, #(SLEEP_SAVE_SP*4)]
+
+ @ save coprocessor registers
+ mrc p15, 0, r1, c1, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R1*4)]
+ mrc p15, 0, r1, c2, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R2*4)]
+ mrc p15, 0, r1, c3, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R3*4)]
+ mrc p15, 0, r1, c5, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R5*4)]
+ mrc p15, 0, r1, c6, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R6*4)]
+ mrc p15, 0, r1, c13, c0, 0
+ str r1, [r4, #(SLEEP_SAVE_CP15_R13*4)]
+
+ @ clean data cache and invalidate WB
+ bl cpu_sa1100_cache_clean_invalidate_all
+
+ @ disable clock switching
+ mcr p15, 0, r1, c15, c2, 2
+
+ @ Adjust memory timing before lowering CPU clock
+ @ Clock speed adjustment without changing memory timing makes
+ @ CPU hang in some cases
+ ldr r0, =MDREFR
+ ldr r1, [r0]
+ orr r1, r1, #MDREFR_K1DB2
+ str r1, [r0]
+
+ @ delay 90us and set CPU PLL to lowest speed
+ @ fixes resume problem on high speed SA1110
+ mov r0, #90
+ bl SYMBOL_NAME(udelay)
+ ldr r0, =PPCR
+ mov r1, #0
+ str r1, [r0]
+ mov r0, #90
+ bl SYMBOL_NAME(udelay)
+
+
+/* setup up register contents for jump to page containing SA1110 SDRAM controller bug fix suspend code
+ *
+ * r0 points to MSC0 register
+ * r1 points to MSC1 register
+ * r2 points to MSC2 register
+ * r3 is MSC0 value
+ * r4 is MSC1 value
+ * r5 is MSC2 value
+ * r6 points to MDREFR register
+ * r7 is first MDREFR value
+ * r8 is second MDREFR value
+ * r9 is pointer to MDCNFG register
+ * r10 is MDCNFG value
+ * r11 is third MDREFR value
+ * r12 is pointer to PMCR register
+ * r13 is PMCR value (1)
+ *
+ */
+
+ ldr r0, =MSC0
+ ldr r1, =MSC1
+ ldr r2, =MSC2
+
+ ldr r3, [r0]
+ bic r3, r3, #FMsk(MSC_RT)
+ bic r3, r3, #FMsk(MSC_RT)<<16
+
+ ldr r4, [r1]
+ bic r4, r4, #FMsk(MSC_RT)
+ bic r4, r4, #FMsk(MSC_RT)<<16
+
+ ldr r5, [r2]
+ bic r5, r5, #FMsk(MSC_RT)
+ bic r5, r5, #FMsk(MSC_RT)<<16
+
+ ldr r6, =MDREFR
+
+ ldr r7, [r6]
+ bic r7, r7, #0x0000FF00
+ bic r7, r7, #0x000000F0
+ orr r8, r7, #MDREFR_SLFRSH
+
+ ldr r9, =MDCNFG
+ ldr r10, [r9]
+ bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
+ bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
+
+ bic r11, r8, #MDREFR_SLFRSH
+ bic r11, r11, #MDREFR_E1PIN
+
+ ldr r12, =PMCR
+
+ mov r13, #PMCR_SF
+
+ b sa1110_sdram_controller_fix
+
+ .align 5
+sa1110_sdram_controller_fix:
+
+ @ Step 1 clear RT field of all MSCx registers
+ str r3, [r0]
+ str r4, [r1]
+ str r5, [r2]
+
+ @ Step 2 clear DRI field in MDREFR
+ str r7, [r6]
+
+ @ Step 3 set SLFRSH bit in MDREFR
+ str r8, [r6]
+
+ @ Step 4 clear DE bis in MDCNFG
+ str r10, [r9]
+
+ @ Step 5 clear DRAM refresh control register
+ str r11, [r6]
+
+ @ Wow, now the hardware suspend request pins can be used, that makes them functional for
+ @ about 7 ns out of the entire time that the CPU is running!
+
+ @ Step 6 set force sleep bit in PMCR
+
+ str r13, [r12]
+
+20: b 20b @ loop waiting for sleep
+
+/*
+ * cpu_sa1100_resume()
+ *
+ * entry point from bootloader into kernel during resume
+ *
+ */
+
+ .align 5
+ENTRY(sa1100_cpu_resume)
+
+ @ set SVC, irqs off
+ mov r0, #I_BIT | MODE_SVC
+ msr cpsr_c, r0
+
+ @ load physical address of sleep_save
+ ldr r4, sleep_save_p
+
+ @ restore cp15_r3, domain id
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R3*4)]
+ mcr p15, 0, r1, c3, c0 ,0
+
+ @ restore cp15_r2, translation table base address
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R2*4)]
+ mcr p15, 0, r1, c2, c0 ,0
+
+ mov r1, #0
+ mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
+ mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
+
+ @ get saved cp15 r1 (control register)
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R1*4)]
+
+ @ get address to jump to after turning on MMU
+ ldr r2, =resume_after_mmu
+
+ cmp r2, #0
+
+ b resume_turn_on_mmu
+
+ .align 5
+resume_turn_on_mmu:
+
+ @ turn on mmu
+ mcr p15, 0, r1, c1, c0 ,0
+
+ @ jump to resume_after_mmu
+ mov pc, r2
+ nop
+ nop
+
+ .align 5
+resume_after_mmu:
+
+ @ load virtual address for sleep_save array
+ ldr r4, sleep_save
+
+ @ restore the rest of CPU state
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R13*4)]
+ mcr p15, 0, r1, c13, c0, 0
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R5*4)]
+ mcr p15, 0, r1, c5, c0 ,0
+ ldr r1, [r4, #(SLEEP_SAVE_CP15_R6*4)]
+ mcr p15, 0, r1, c6, c0 ,0
+
+ @ restore stack pointer
+ ldr sp, [r4, #(SLEEP_SAVE_SP*4)]
+
+ @ return to caller
+ ldmfd sp!, {r4 - r12, pc}
+
+
--- /dev/null
+/*
+ * Offsets for register values preserved in RAM while in sleep mode
+ */
+
+#define SLEEP_SAVE_OSCR 0
+#define SLEEP_SAVE_OSMR0 1
+#define SLEEP_SAVE_OSMR1 2
+#define SLEEP_SAVE_OSMR2 3
+#define SLEEP_SAVE_OSMR3 4
+#define SLEEP_SAVE_OIER 5
+#define SLEEP_SAVE_GPDR 6
+#define SLEEP_SAVE_GRER 7
+#define SLEEP_SAVE_GFER 8
+#define SLEEP_SAVE_GAFR 9
+#define SLEEP_SAVE_PPDR 10
+#define SLEEP_SAVE_PPSR 11
+#define SLEEP_SAVE_PPAR 12
+#define SLEEP_SAVE_PSDR 13
+#define SLEEP_SAVE_Ser1SDCR0 14
+#define SLEEP_SAVE_ICMR 15
+#define SLEEP_SAVE_SP 16
+#define SLEEP_SAVE_CP15_R1 17
+#define SLEEP_SAVE_CP15_R2 18
+#define SLEEP_SAVE_CP15_R3 19
+#define SLEEP_SAVE_CP15_R5 20
+#define SLEEP_SAVE_CP15_R6 21
+#define SLEEP_SAVE_CP15_R13 22
+
+#define SLEEP_SAVE_SIZE 23
+
/*
* linux/arch/arm/mach-shark/dma.c
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* arch/arm/kernel/dma-ebsa285.c
/*
* arch/arm/kernel/leds-shark.c
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* arch/arm/kernel/leds-footbridge.c
/*
* linux/arch/arm/mach-shark/mm.c
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* Oops, we didn't handle the instruction.
*/
printk(KERN_ERR "Alignment trap: not handling instruction "
- "%08lx at [<%08lx>]", instr, instrptr);
+ "%08lx at [<%08lx>]\n", instr, instrptr);
ai_skipped += 1;
return 1;
sbc r1, r1, r1 @ r1 = C - 1
and r3, r3, #255
mov pc, lr
-
+
/*
* cpu_arm920_check_bugs()
*/
mov r2, #1
cpu_arm920_cache_clean_invalidate_all_r2:
mov ip, #0
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
/*
* end: Area end address
* flags: nonzero for I cache as well
*/
- .align 5
+ .align 5
ENTRY(cpu_arm920_cache_clean_invalidate_range)
bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM
+ bic r1, r1, #DCACHELINESIZE - 1 @ && added by DHM
sub r3, r1, r0
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm920_cache_clean_invalidate_all_r2
-1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
+1: teq r2, #0
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
+ mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
+ add r0, r0, #DCACHELINESIZE
+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
+ mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
+ add r0, r0, #DCACHELINESIZE
+#else
+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
+ mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
+ mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
+#endif
cmp r0, r1
blt 1b
- teq r2, #0
- movne r0, #0
- mcrne p15, 0, r0, c7, c5, 0 @ invalidate I cache
+
+ mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/*
.align 5
ENTRY(cpu_arm920_flush_ram_page)
mov r1, #PAGESIZE
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
+ add r0, r0, #DCACHELINESIZE
+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
+ add r0, r0, #DCACHELINESIZE
+#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
+#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
*/
.align 5
ENTRY(cpu_arm920_dcache_invalidate_range)
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1
- bic r0, r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1
mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
+#endif @ clean D entry
+ bic r0, r0, #DCACHELINESIZE - 1
+ bic r1, r1, #DCACHELINESIZE - 1
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
cmp r0, r1
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_range)
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
mov r2, #0
bgt cpu_arm920_cache_clean_invalidate_all_r2
+ bic r1, r1, #DCACHELINESIZE -1
+ add r1, r1, #DCACHELINESIZE
+
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
- mcr p15, 0, r0, c7, c10, 1 @ clean D entry
- add r0, r0, #DCACHELINESIZE
- subs r1, r1, #2 * DCACHELINESIZE
+ subs r1, r1, #DCACHELINESIZE
bpl 1b
+#endif
mcr p15, 0, r2, c7, c10, 4 @ drain WB
mov pc, lr
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_page)
-#ifndef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_entry)
-#ifndef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
*
* invalidate a range of virtual addresses from the Icache
*
+ * This is a little misleading, it is not intended to clean out
+ * the i-cache but to make sure that any data written to the
+ * range is made consistant. This means that when we execute code
+ * in that region, everything works as we expect.
+ *
+ * This generally means writing back data in the Dcache and
+ * write buffer and flushing the Icache over that region
+ *
* start: virtual start address
* end: virtual end address
+ *
+ * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to
+ * loop twice, once for i-cache, once for d-cache)
*/
.align 5
ENTRY(cpu_arm920_icache_invalidate_range)
-1: mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
- add r0, r0, #DCACHELINESIZE
- cmp r0, r1
- blo 1b
+ bic r0, r0, #ICACHELINESIZE - 1 @ Safety check
+ sub r1, r1, r0
+ cmp r1, #MAX_AREA_SIZE
+ bgt cpu_arm920_cache_clean_invalidate_all_r2
+
+ bic r1, r1, #ICACHELINESIZE - 1
+ add r1, r1, #ICACHELINESIZE
+
+1: mcr p15, 0, r0, c7, c5, 1 @ Clean I entry
+ mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
+ add r0, r0, #ICACHELINESIZE
+ subs r1, r1, #ICACHELINESIZE
+ bne 1b
+
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov pc, lr
+
ENTRY(cpu_arm920_icache_invalidate_page)
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mov pc, lr
-
/* ================================== TLB ================================= */
/*
ENTRY(cpu_arm920_tlb_invalidate_range)
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
+
+ mov r3, #PAGESIZE
+ sub r3, r3, #1
+ bic r0, r0, r3
+ bic r1, r1, r3
+
1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
add r0, r0, #PAGESIZE
.align 5
ENTRY(cpu_arm920_set_pgd)
mov ip, #0
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
*/
.align 5
ENTRY(cpu_arm920_set_pmd)
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
- eor r3, r1, #0x0a @ C & small page?
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+ eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
#endif
cpu_manu_name:
- .asciz "ARM/VLSI"
+ .asciz "ARM/CIRRUS"
ENTRY(cpu_arm920_name)
- .ascii "Arm920"
+ .ascii "Arm920T"
#if defined(CONFIG_CPU_ARM920_CPU_IDLE)
.ascii "s"
#endif
#endif
#if defined(CONFIG_CPU_ARM920_D_CACHE_ON)
.ascii "d"
-#if defined(CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH)
+#if defined(CONFIG_CPU_ARM920_WRITETHROUGH)
.ascii "(wt)"
#else
.ascii "(wb)"
bic r0, r0, #DCACHELINESIZE - 1
sub r3, r1, r0
cmp r3, #MAX_AREA_SIZE
- bgt cpu_sa110_cache_clean_invalidate_all_r2
+ bhi cpu_sa110_cache_clean_invalidate_all_r2
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
cmp r0, r1
- blt 1b
+ blo 1b
teq r2, #0
movne r0, #0
mcrne p15, 0, r0, c7, c5, 0 @ invalidate I cache
ENTRY(cpu_sa1100_cache_clean_invalidate_range)
sub r3, r1, r0
cmp r3, #MAX_AREA_SIZE
- bgt cpu_sa1100_cache_clean_invalidate_all_r2
+ bhi cpu_sa1100_cache_clean_invalidate_all_r2
b 1b
/*
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
cmp r0, r1
- blt 1b
+ blo 1b
mov pc, lr
/*
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
mov r2, #0
- bgt cpu_sa110_cache_clean_invalidate_all_r2
+ bhi cpu_sa110_cache_clean_invalidate_all_r2
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
mov r2, #0
- bgt cpu_sa1100_cache_clean_invalidate_all_r2
+ bhi cpu_sa1100_cache_clean_invalidate_all_r2
b 1b
/*
.align 5
ENTRY(cpu_sa110_icache_invalidate_range)
ENTRY(cpu_sa1100_icache_invalidate_range)
+ bic r0, r0, #DCACHELINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
add r0, r0, #DCACHELINESIZE
cmp r0, r1
.align 5
ENTRY(cpu_sa110_tlb_invalidate_range)
ENTRY(cpu_sa1100_tlb_invalidate_range)
+ bic r0, r0, #0x0ff
+ bic r0, r0, #0xf00
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
add r0, r0, #PAGESIZE
cmp r0, r1
- blt 1b
+ blo 1b
mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
mov pc, lr
# To add an entry into this database, please see Documentation/arm/README,
# or contact rmk@arm.linux.org.uk
#
-# Last update: Fri Oct 5 18:40:53 2001
+# Last update: Mon Oct 22 09:49:06 2001
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
gator SA1100_GATOR GATOR 103
granite ARCH_GRANITE GRANITE 104
consus SA1100_CONSUS CONSUS 105
-agilent_aaed2000 ARCH_AAEC2000_AAED2000 AAEC2000_AAED2000 106
+aaed2000 ARCH_AAED2000 AAED2000 106
cdb89712 ARCH_CDB89712 CDB89712 107
graphicsmaster SA1100_GRAPHICSMASTER GRAPHICSMASTER 108
adsbitsy SA1100_ADSBITSY ADSBITSY 109
bluestem SA1100_BLUESTEM BLUESTEM 120
xingu8 ARCH_XINGU8 XINGU8 121
bushstb ARCH_BUSHSTB BUSHSTB 122
+epsilon1 SA1100_EPSILON1 EPSILON1 123
+balloon SA1100_BALLOON BALLOON 124
+puppy ARCH_PUPPY PUPPY 125
#
CONFIG_PCMCIA=y
CONFIG_CARDBUS=y
+# CONFIG_I82092 is not set
# CONFIG_I82365 is not set
# CONFIG_TCIC is not set
CONFIG_SYSVIPC=y
)
UNEXPECTED_IO_APIC();
+ printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
(reg_01.version != 0x10) && /* oldest IO-APICs */
ack_APIC_irq();
if (!(v & (1 << (i & 0x1f)))) {
+#ifdef APIC_LOCKUP_DEBUG
+ struct irq_pin_list *entry;
+#endif
+
#ifdef APIC_MISMATCH_DEBUG
atomic_inc(&irq_mis_count);
#endif
spin_lock(&ioapic_lock);
__mask_and_edge_IO_APIC_irq(irq);
#ifdef APIC_LOCKUP_DEBUG
- for (;;) {
- struct irq_pin_list *entry = irq_2_pin + irq;
+ for (entry = irq_2_pin + irq;;) {
unsigned int reg;
if (entry->pin == -1)
if (!local_irq_count(smp_processor_id())) {
do {
barrier();
+ cpu_relax();
} while (irq_desc[irq].status & IRQ_INPROGRESS);
}
}
#ifdef CONFIG_SMP
/* Wait to make sure it's not being used on another CPU */
- while (desc->status & IRQ_INPROGRESS)
+ while (desc->status & IRQ_INPROGRESS) {
barrier();
+ cpu_relax();
+ }
#endif
kfree(action);
return;
unsigned long config, dummy;
struct pci_dev *dev = NULL;
- /* ServerWorks LE chipsets have problems with write-combining
- Don't allow it and leave room for other chipsets to be tagged */
-
- if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
- switch(dev->vendor) {
- case PCI_VENDOR_ID_SERVERWORKS:
- switch (dev->device) {
- case PCI_DEVICE_ID_SERVERWORKS_LE:
+ /* ServerWorks LE chipsets have problems with write-combining
+ Don't allow it and leave room for other chipsets to be tagged */
+
+ if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
+ if ((dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
+ (dev->device == PCI_DEVICE_ID_SERVERWORKS_LE)) {
+ printk (KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
return 0;
- break;
- default:
- break;
- }
- break;
- default:
- break;
+ }
}
- }
-
switch ( mtrr_if )
{
#define SIO_PM_GP_EN 0x80
-static void
-visws_get_board_type_and_rev(void)
+static void __init visws_get_board_type_and_rev(void)
{
int raw;
}
}
-void __init add_memory_region(unsigned long long start,
+static void __init add_memory_region(unsigned long long start,
unsigned long long size, int type)
{
int x = e820.nr_map;
*/
#define LOWMEMSIZE() (0x9f000)
-void __init setup_memory_region(void)
+static void __init setup_memory_region(void)
{
char *who = "BIOS-e820";
} /* setup_memory_region */
-static inline void parse_mem_cmdline (char ** cmdline_p)
+static void __init parse_mem_cmdline (char ** cmdline_p)
{
char c = ' ', *to = command_line, *from = COMMAND_LINE;
int len = 0;
/*
* Read Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
*/
-static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
+static void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
unsigned char ccr2, ccr3;
unsigned long flags;
-
+
/* we test for DEVID by checking whether CCR3 is writable */
local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3);
* Actually since bugs.h doesnt even reference this perhaps someone should
* fix the documentation ???
*/
-unsigned char Cx86_dir0_msb __initdata = 0;
+static unsigned char Cx86_dir0_msb __initdata = 0;
static char Cx86_model[][9] __initdata = {
"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
static void __init check_cx686_slop(struct cpuinfo_x86 *c)
{
unsigned long flags;
-
+
if (Cx86_dir0_msb == 3) {
unsigned char ccr3, ccr5;
return;
}
+#ifdef CONFIG_X86_OOSTORE
+
+static u32 __init power2(u32 x)
+{
+ u32 s=1;
+ while(s<=x)
+ s<<=1;
+ return s>>=1;
+}
+
+/*
+ * Set up an actual MCR
+ */
+
+static void __init winchip_mcr_insert(int reg, u32 base, u32 size, int key)
+{
+ u32 lo, hi;
+
+ hi = base & ~0xFFF;
+ lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
+ lo &= ~0xFFF; /* Remove the ctrl value bits */
+ lo |= key; /* Attribute we wish to set */
+ wrmsr(reg+MSR_IDT_MCR0, lo, hi);
+ mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
+}
+
+/*
+ * Figure what we can cover with MCR's
+ *
+ * Shortcut: We know you can't put 4Gig of RAM on a winchip
+ */
+
+static u32 __init ramtop(void) /* 16388 */
+{
+ int i;
+ u32 top = 0;
+ u32 clip = 0xFFFFFFFFUL;
+
+ for (i = 0; i < e820.nr_map; i++) {
+ unsigned long start, end;
+
+ if (e820.map[i].addr > 0xFFFFFFFFUL)
+ continue;
+ /*
+ * Don't MCR over reserved space. Ignore the ISA hole
+ * we frob around that catastrophy already
+ */
+
+ if (e820.map[i].type == E820_RESERVED)
+ {
+ if(e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
+ clip = e820.map[i].addr;
+ continue;
+ }
+ start = e820.map[i].addr;
+ end = e820.map[i].addr + e820.map[i].size;
+ if (start >= end)
+ continue;
+ if (end > top)
+ top = end;
+ }
+ /* Everything below 'top' should be RAM except for the ISA hole.
+ Because of the limited MCR's we want to map NV/ACPI into our
+ MCR range for gunk in RAM
+
+ Clip might cause us to MCR insufficient RAM but that is an
+ acceptable failure mode and should only bite obscure boxes with
+ a VESA hole at 15Mb
+
+ The second case Clip sometimes kicks in is when the EBDA is marked
+ as reserved. Again we fail safe with reasonable results
+ */
+
+ if(top>clip)
+ top=clip;
+
+ return top;
+}
+
+/*
+ * Compute a set of MCR's to give maximum coverage
+ */
+
+static int __init winchip_mcr_compute(int nr, int key)
+{
+ u32 mem = ramtop();
+ u32 root = power2(mem);
+ u32 base = root;
+ u32 top = root;
+ u32 floor = 0;
+ int ct = 0;
+
+ while(ct<nr)
+ {
+ u32 fspace = 0;
+
+ /*
+ * Find the largest block we will fill going upwards
+ */
+
+ u32 high = power2(mem-top);
+
+ /*
+ * Find the largest block we will fill going downwards
+ */
+
+ u32 low = base/2;
+
+ /*
+ * Don't fill below 1Mb going downwards as there
+ * is an ISA hole in the way.
+ */
+
+ if(base <= 1024*1024)
+ low = 0;
+
+ /*
+ * See how much space we could cover by filling below
+ * the ISA hole
+ */
+
+ if(floor == 0)
+ fspace = 512*1024;
+ else if(floor ==512*1024)
+ fspace = 128*1024;
+
+ /* And forget ROM space */
+
+ /*
+ * Now install the largest coverage we get
+ */
+
+ if(fspace > high && fspace > low)
+ {
+ winchip_mcr_insert(ct, floor, fspace, key);
+ floor += fspace;
+ }
+ else if(high > low)
+ {
+ winchip_mcr_insert(ct, top, high, key);
+ top += high;
+ }
+ else if(low > 0)
+ {
+ base -= low;
+ winchip_mcr_insert(ct, base, low, key);
+ }
+ else break;
+ ct++;
+ }
+ /*
+ * We loaded ct values. We now need to set the mask. The caller
+ * must do this bit.
+ */
+
+ return ct;
+}
+
+static void __init winchip_create_optimal_mcr(void)
+{
+ int i;
+ /*
+ * Allocate up to 6 mcrs to mark as much of ram as possible
+ * as write combining and weak write ordered.
+ *
+ * To experiment with: Linux never uses stack operations for
+ * mmio spaces so we could globally enable stack operation wc
+ *
+ * Load the registers with type 31 - full write combining, all
+ * writes weakly ordered.
+ */
+ int used = winchip_mcr_compute(6, 31);
+
+ /*
+ * Wipe unused MCRs
+ */
+
+ for(i=used;i<8;i++)
+ wrmsr(MSR_IDT_MCR0+i, 0, 0);
+}
+
+static void __init winchip2_create_optimal_mcr(void)
+{
+ u32 lo, hi;
+ int i;
+
+ /*
+ * Allocate up to 6 mcrs to mark as much of ram as possible
+ * as write combining, weak store ordered.
+ *
+ * Load the registers with type 25
+ * 8 - weak write ordering
+ * 16 - weak read ordering
+ * 1 - write combining
+ */
+
+ int used = winchip_mcr_compute(6, 25);
+
+ /*
+ * Mark the registers we are using.
+ */
+
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ for(i=0;i<used;i++)
+ lo|=1<<(9+i);
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+
+ /*
+ * Wipe unused MCRs
+ */
+
+ for(i=used;i<8;i++)
+ wrmsr(MSR_IDT_MCR0+i, 0, 0);
+}
+
+/*
+ * Handle the MCR key on the Winchip 2.
+ */
+
+static void __init winchip2_unprotect_mcr(void)
+{
+ u32 lo, hi;
+ u32 key;
+
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ lo&=~0x1C0; /* blank bits 8-6 */
+ key = (lo>>17) & 7;
+ lo |= key<<6; /* replace with unlock key */
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+}
+
+static void __init winchip2_protect_mcr(void)
+{
+ u32 lo, hi;
+
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ lo&=~0x1C0; /* blank bits 8-6 */
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+}
+
+#endif
+
static void __init init_centaur(struct cpuinfo_x86 *c)
{
enum {
fcr_clr=DPDC;
printk(KERN_NOTICE "Disabling bugged TSC.\n");
clear_bit(X86_FEATURE_TSC, &c->x86_capability);
+#ifdef CONFIG_X86_OOSTORE
+ winchip_create_optimal_mcr();
+ /* Enable
+ write combining on non-stack, non-string
+ write combining on string, all types
+ weak write ordering
+
+ The C6 original lacks weak read order
+
+ Note 0x120 is write only on Winchip 1 */
+
+ wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
+#endif
break;
case 8:
switch(c->x86_mask) {
}
fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
fcr_clr=DPDC;
+#ifdef CONFIG_X86_OOSTORE
+ winchip2_unprotect_mcr();
+ winchip2_create_optimal_mcr();
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ /* Enable
+ write combining on non-stack, non-string
+ write combining on string, all types
+ weak write ordering
+ */
+ lo|=31;
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ winchip2_protect_mcr();
+#endif
break;
case 9:
name="3";
fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
fcr_clr=DPDC;
+#ifdef CONFIG_X86_OOSTORE
+ winchip2_unprotect_mcr();
+ winchip2_create_optimal_mcr();
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ /* Enable
+ write combining on non-stack, non-string
+ write combining on string, all types
+ weak write ordering
+ */
+ lo|=31;
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ winchip2_protect_mcr();
+#endif
break;
case 10:
name="4";
return -EFAULT;
return 0;
- case BLKGETSIZE:
- return put_user (mfm[minor].nr_sects, (unsigned long *)arg);
- case BLKGETSIZE64:
- return put_user ((u64)mfm[minor].nr_sects << 9, (u64 *)arg);
-
case BLKFRASET:
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
return -EACCES;
return mfm_reread_partitions(dev);
+ case BLKGETSIZE:
+ case BLKGETSIZE64:
case BLKFLSBUF:
case BLKROSET:
case BLKROGET:
if (dev >= mfm_drives)
return -ENODEV;
- MOD_INC_USE_COUNT;
while (mfm_info[dev].busy)
sleep_on (&mfm_wait_open);
static int mfm_release(struct inode *inode, struct file *file)
{
mfm_info[DEVICE_NR(MINOR(inode->i_rdev))].access_count--;
- MOD_DEC_USE_COUNT;
return 0;
}
static struct block_device_operations mfm_fops =
{
+ owner: THIS_MODULE,
open: mfm_open,
release: mfm_release,
ioctl: mfm_ioctl,
#include <asm/bitops.h>
#include <asm/irq.h>
#include <asm/hardware.h>
+#include <asm/keyboard.h>
#include <asm/io.h>
#include <asm/hardware/iomd.h>
#include <asm/system.h>
};
#ifdef CONFIG_MAGIC_SYSRQ
-unsigned char ps2kbd_sysrq_xlate[] =
+static unsigned char ps2kbd_sysrq_xlate[] =
{
27, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
status = 0;
}
-void ps2kbd_leds(unsigned int leds)
+static void ps2kbd_leds(unsigned char leds)
{
ps2kbd_sendbyte(KBD_SETLEDS);
ps2kbd_sendbyte(leds);
{
}
+static int ps2kbd_translate(unsigned char scancode, unsigned char *keycode, char rawmode)
+{
+ *keycode = scancode;
+ return 1;
+}
+
+static char ps2kbd_unexpected_up(unsigned char scancode)
+{
+ return 0200;
+}
+
int __init ps2kbd_init_hw(void)
{
/* Reset the keyboard state machine. */
if (request_irq (IRQ_KEYBOARDTX, ps2kbd_tx, 0, "keyboard", NULL) != 0)
panic("Could not allocate keyboard transmit IRQ!");
+ k_translate = ps2kbd_translate;
+ k_unexpected_up = ps2kbd_unexpected_up;
+ k_leds = ps2kbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+ k_sysrq_xlate = ps2kbd_sysrq_xlate;
+ k_sysrq_key = 13;
+#endif
+
return 0;
}
#endif
#undef STAT
-#ifndef HOSTS_C
#define NCR5380_implementation_fields \
int port, ctrl
tristate 'ATM over TCP' CONFIG_ATM_TCP
fi
if [ "$CONFIG_PCI" = "y" ]; then
+ tristate 'Efficient Networks Speedstream 3010' CONFIG_ATM_LANAI
tristate 'Efficient Networks ENI155P' CONFIG_ATM_ENI
if [ "$CONFIG_ATM_ENI" != "n" ]; then
bool ' Enable extended debugging' CONFIG_ATM_ENI_DEBUG
obj-$(CONFIG_ATM_TCP) += atmtcp.o
obj-$(CONFIG_ATM_IA) += iphase.o suni.o
obj-$(CONFIG_ATM_FIRESTREAM) += firestream.o
+obj-$(CONFIG_ATM_LANAI) += lanai.o
ifeq ($(CONFIG_ATM_FORE200E_PCA),y)
FORE200E_FW_OBJS += fore200e_pca_fw.o
#ifdef CONFIG_ATM_FORE200E
extern int fore200e_detect(void);
#endif
+#ifdef CONFIG_ATM_LANAI
+extern int lanai_detect(void);
+#endif
/*
#endif
#ifdef CONFIG_ATM_FORE200E
devs += fore200e_detect();
+#endif
+#ifdef CONFIG_ATM_LANAI
+ devs += lanai_detect();
#endif
return devs;
}
--- /dev/null
+/* lanai.c -- Copyright 1999 by Mitchell Blank Jr <mitch@sfgoth.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This driver supports ATM cards based on the Efficient "Lanai"
+ * chipset such as the Speedstream 3010 and the ENI-25p. The
+ * Speedstream 3060 is currently not supported since we don't
+ * have the code to drive the on-board Alcatel DSL chipset (yet).
+ *
+ * Thanks to Efficient for supporting this project with hardware,
+ * documentation, and by answering my questions.
+ *
+ * Things not working yet:
+ *
+ * o We're only set up to compile as a module currently. i.e.
+ * you should put the source in drivers/atm/lanai.c and then
+ * just do "make drivers/atm/lanai.o" from the main
+ * source directory. This will produce a drivers/atm/lanai.o
+ * file suitable for insmod'ing
+ *
+ * o We don't support the Speedstream 3060 yet - this card has
+ * an on-board DSL modem chip by Alcatel and the driver will
+ * need some extra code added to handle it
+ *
+ * o Note that due to limitations of the Lanai only one VCC can be
+ * in CBR at once
+ *
+ * o We don't currently parse the EEPROM at all. The code is all
+ * there as per the spec, but it doesn't actually work. I think
+ * there may be some issues with the docs. Anyway, do NOT
+ * enable it yet - bugs in that code may actually damage your
+ * hardware! Because of this you should hardware an ESI before
+ * trying to use this in a LANE or MPOA environment.
+ *
+ * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:
+ * vcc_tx_aal0() needs to send or queue a SKB
+ * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
+ * vcc_rx_aal0() needs to handle AAL0 interrupts
+ * This isn't too much work - I just wanted to get other things
+ * done first.
+ *
+ * o lanai_change_qos() isn't written yet
+ *
+ * o There aren't any ioctl's yet -- I'd like to eventually support
+ * setting loopback and LED modes that way. (see lanai_ioctl)
+ *
+ * o If the segmentation engine or DMA gets shut down we should restart
+ * card as per section 17.0i. (see lanai_reset)
+ *
+ * o setsockopt(SO_CIRANGE) isn't done (although despite what the
+ * API says it isn't exactly commonly implemented)
+ */
+
+/* Version history:
+ * v.0.02 -- 11-JAN-2000 -- Endian fixes
+ * v.0.01 -- 30-NOV-1999 -- Initial release
+ */
+
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/atmdev.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <linux/spinlock.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#ifndef PCI_VENDOR_ID_EF_ATM_LANAI2
+/* These need to eventually go into <linux/pci.h> - they're here for now */
+#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003
+#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005
+#endif
+
+/* -------------------- TUNABLE PARAMATERS: */
+
+/*
+ * Maximum number of VCIs per card. Setting it lower could theoretically
+ * save some memory, but since we allocate our vcc list with get_free_pages,
+ * it's not really likely for most architectures
+ */
+#define NUM_VCI (1024)
+
+/*
+ * Enable extra debugging
+ */
+#define DEBUG
+/*
+ * Debug _all_ register operations with card, except the memory test.
+ * Also disables the timed poll to prevent extra chattiness. This
+ * isn't for normal use
+ */
+#undef DEBUG_RW
+
+/*
+ * The programming guide specifies a full test of the on-board SRAM
+ * at initialization time. Undefine to remove this
+ */
+#define FULL_MEMORY_TEST
+
+/*
+ * This is the number of (4 byte) service entries that we will
+ * try to allocate at startup. Note that we will end up with
+ * one PAGE_SIZE's worth regardless of what this is set to
+ */
+#define SERVICE_ENTRIES (1024)
+/* TODO: make above a module load-time option */
+
+/*
+ * We normally read the onboard EEPROM in order to discover our MAC
+ * address. Undefine to _not_ do this
+ */
+/* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
+/* TODO: make above a module load-time option (also) */
+
+/*
+ * Depth of TX fifo (in 128 byte units; range 2-31)
+ * Smaller numbers are better for network latency
+ * Larger numbers are better for PCI latency
+ * I'm really sure where the best tradeoff is, but the BSD driver uses
+ * 7 and it seems to work ok.
+ */
+#define TX_FIFO_DEPTH (7)
+/* TODO: make above a module load-time option */
+
+/*
+ * How often (in jiffies) we will try to unstick stuck connections -
+ * shouldn't need to happen much
+ */
+#define LANAI_POLL_PERIOD (10*HZ)
+/* TODO: make above a module load-time option */
+
+/*
+ * When allocating an AAL5 receiving buffer, try to make it at least
+ * large enough to hold this many max_sdu sized PDUs
+ */
+#define AAL5_RX_MULTIPLIER (3)
+/* TODO: make above a module load-time option */
+
+/*
+ * Same for transmitting buffer
+ */
+#define AAL5_TX_MULTIPLIER (3)
+/* TODO: make above a module load-time option */
+
+/*
+ * When allocating an AAL0 transmiting buffer, how many cells should fit.
+ * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
+ * really critical
+ */
+#define AAL0_TX_MULTIPLIER (40)
+/* TODO: make above a module load-time option */
+
+/*
+ * How large should we make the AAL0 receiving buffer. Remember that this
+ * is shared between all AAL0 VC's
+ */
+#define AAL0_RX_BUFFER_SIZE (PAGE_SIZE)
+/* TODO: make above a module load-time option */
+
+/*
+ * Should we use Lanai's "powerdown" feature when no vcc's are bound?
+ */
+/* #define USE_POWERDOWN */
+/* TODO: make above a module load-time option (also) */
+
+/* -------------------- DEBUGGING AIDS: */
+
+#define DEV_LABEL "lanai"
+
+#ifdef DEBUG
+
+#define DPRINTK(format, args...) \
+ printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
+#define APRINTK(truth, format, args...) \
+ do { \
+ if (!(truth)) \
+ printk(KERN_ERR DEV_LABEL ": " format, ##args); \
+ } while (0)
+
+#else /* !DEBUG */
+
+#define DPRINTK(format, args...)
+#define APRINTK(truth, format, args...)
+
+#endif /* DEBUG */
+
+#ifdef DEBUG_RW
+#define RWDEBUG(format, args...) \
+ printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
+#else /* !DEBUG_RW */
+#define RWDEBUG(format, args...)
+#endif
+
+/* -------------------- DATA DEFINITIONS: */
+
+#define LANAI_MAPPING_SIZE (0x40000)
+#define LANAI_EEPROM_SIZE (128)
+
+typedef int vci_t;
+typedef unsigned long bus_addr_t;
+
+/* A bitfield large enough for NUM_VCI */
+#define VCI_BITFIELD_NELEM ((NUM_VCI + BITS_PER_LONG - 1) / BITS_PER_LONG)
+typedef struct {
+ unsigned long ul[VCI_BITFIELD_NELEM];
+} vci_bitfield;
+
+/* DMA buffer in host memory for TX, RX, or service list. */
+struct lanai_buffer {
+ u32 *start; /* From get_free_pages */
+ u32 *end; /* One past last byte */
+ u32 *ptr; /* Pointer to current host location */
+ int order; /* log2(size/PAGE_SIZE) */
+};
+
+struct lanai_vcc_stats {
+ unsigned rx_nomem;
+ union {
+ struct {
+ unsigned rx_badlen;
+ unsigned service_trash;
+ unsigned service_stream;
+ unsigned service_rxcrc;
+ } aal5;
+ struct {
+ } aal0;
+ } x;
+};
+
+struct lanai_dev; /* Forward declaration */
+
+/*
+ * This is the card-specific per-vcc data. Note that unlike some other
+ * drivers there is NOT a 1-to-1 correspondance between these and
+ * atm_vcc's - each one of these represents an actual 2-way vcc, but
+ * an atm_vcc can be 1-way and share with a 1-way vcc in the other
+ * direction. To make it weirder, there can even be 0-way vccs
+ * bound to us, waiting to do a change_qos
+ */
+struct lanai_vcc {
+ bus_addr_t vbase; /* Base of VCC's registers */
+ struct lanai_vcc_stats stats;
+ int nref; /* # of atm_vcc's who reference us */
+ vci_t vci;
+ struct {
+ struct lanai_buffer buf;
+ struct atm_vcc *atmvcc; /* atm_vcc who is receiver */
+ } rx;
+ struct {
+ struct lanai_buffer buf;
+ struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */
+ int endptr; /* last endptr from service entry */
+ struct sk_buff_head backlog;
+ struct sk_buff *inprogress; /* We're streaming this PDU */
+ unsigned char *pptr; /* Where we are in above */
+ int inprogleft; /* Bytes left to send "inprogress" */
+ void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
+ } tx;
+};
+
+enum lanai_type {
+ lanai2 = PCI_VENDOR_ID_EF_ATM_LANAI2,
+ lanaihb = PCI_VENDOR_ID_EF_ATM_LANAIHB
+};
+
+struct lanai_dev_stats {
+ unsigned ovfl_trash; /* # of cells dropped - buffer overflow */
+ unsigned vci_trash; /* # of cells dropped - closed vci */
+ unsigned hec_err; /* # of cells dropped - bad HEC */
+ unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */
+ unsigned pcierr_parity_detect;
+ unsigned pcierr_serr_set;
+ unsigned pcierr_master_abort;
+ unsigned pcierr_m_target_abort;
+ unsigned pcierr_s_target_abort;
+ unsigned pcierr_master_parity;
+ unsigned service_novcc_rx;
+ unsigned service_novcc_tx;
+ unsigned service_notx;
+ unsigned service_norx;
+ unsigned service_rxnotaal5;
+ unsigned dma_reenable;
+ unsigned card_reset;
+};
+
+struct lanai_dev {
+ bus_addr_t base;
+ struct lanai_dev_stats stats;
+ struct lanai_buffer service;
+ struct lanai_vcc **vccs;
+#ifdef USE_POWERDOWN
+ int nbound; /* number of bound vccs */
+#endif
+ enum lanai_type type;
+ vci_t num_vci; /* Currently just NUM_VCI */
+ u8 eeprom[LANAI_EEPROM_SIZE];
+ u32 serialno, magicno;
+ struct pci_dev *pci;
+ vci_bitfield backlog_vccs; /* VCCs that are backlogged */
+ vci_bitfield transmit_ready; /* VCCs that have transmit space */
+ struct timer_list timer;
+ int naal0;
+ struct lanai_buffer aal0buf; /* AAL0 RX buffers */
+ u32 conf1, conf2; /* CONFIG[12] registers */
+ u32 status; /* STATUS register */
+ spinlock_t txlock;
+ spinlock_t servicelock;
+ struct atm_vcc *cbrvcc;
+ int number;
+ int board_rev;
+ u8 pci_revision;
+/* TODO - look at race conditions with maintence of conf1/conf2 */
+/* TODO - transmit locking: should we use _irq not _irqsave? */
+/* TODO - organize above in some rational fashion (see <asm/cache.h>) */
+};
+
+/* -------------------- VCI_BITFIELD UTILITIES: */
+
+/*
+ * These functions assume that BITS_PER_LONG is a power of two, which
+ * should be safe
+ */
+#if (BITS_PER_LONG & (BITS_PER_LONG - 1))
+#error lanai driver requires type long to have a power of two number of bits
+#endif
+
+/*
+ * In vci_bitfield_{set,clear} we do the operation in three
+ * parts to ensure that gcc doesn't cast anything down to
+ * 32 bits (and then sign extend them later) on 64-bit
+ * platforms like the alpha
+ */
+static inline void vci_bitfield_set(vci_bitfield *bf, vci_t vci)
+{
+ unsigned long bit = 1;
+ bit <<= (unsigned long) (vci & (BITS_PER_LONG - 1));
+ bf->ul[vci / BITS_PER_LONG] |= bit;
+}
+
+static inline void vci_bitfield_clear(vci_bitfield *bf, vci_t vci)
+{
+ unsigned long bit = 1;
+ bit <<= (unsigned long) (vci & (BITS_PER_LONG - 1));
+ bf->ul[vci / BITS_PER_LONG] &= ~bit;
+}
+
+static inline void vci_bitfield_init(vci_bitfield *bf)
+{
+ memset(bf, 0, sizeof(*bf));
+}
+
+static void vci_bitfield_iterate(struct lanai_dev *lanai,
+ const vci_bitfield *bf, void (*func)(struct lanai_dev *,vci_t vci))
+{
+ vci_t vci;
+ unsigned long mask;
+ const unsigned long *lp = &(bf->ul[0]);
+ for (vci = 0; vci < NUM_VCI; lp++)
+ if (*lp == 0)
+ vci += BITS_PER_LONG;
+ else
+ for (mask = 1; mask != 0; mask <<= 1, vci++)
+ if (*lp & mask)
+ func(lanai, vci);
+}
+
+/* -------------------- BUFFER UTILITIES: */
+
+/*
+ * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
+ * we assume that any page allocation will do. I'm sure this is
+ * never going to be a problem, but it's good to document assumtions
+ */
+#if PAGE_SIZE < 1024
+#error PAGE_SIZE too small to support LANAI chipset
+#endif
+/*
+ * We also assume that the maximum buffer size will be some number
+ * of whole pages, although that wouldn't be too hard to fix
+ */
+#if PAGE_SIZE > (128 * 1024)
+#error PAGE_SIZE too large to support LANAI chipset
+#endif
+
+/* Convert a size to "order" for __get_free_pages */
+static int bytes_to_order(int bytes)
+{
+ int order = 0;
+ if (bytes > (128 * 1024))
+ bytes = 128 * 1024; /* Max buffer size for lanai */
+ while ((PAGE_SIZE << order) < bytes)
+ order++;
+ return order;
+}
+
+/*
+ * Allocate a buffer in host RAM for service list, RX, or TX
+ * Returns buf->order<0 if no memory
+ * Note that the size will be rounded up to an "order" of pages, and
+ * if we can't allocate that we'll settle for something smaller
+ * until minbytes
+ *
+ * NOTE: buffer must be 32-bit DMA capable - when linux can
+ * make distinction, this will need tweaking for this
+ * to work on BIG memory machines.
+ */
+static void lanai_buf_allocate(struct lanai_buffer *buf,
+ int bytes, int minbytes)
+{
+ unsigned long address;
+ int order = bytes_to_order(bytes);
+ do {
+ address = __get_free_pages(GFP_KERNEL, order);
+ if (address != 0) { /* Success */
+ bytes = PAGE_SIZE << order;
+ buf->start = buf->ptr = (u32 *) address;
+ buf->end = (u32 *) (address + bytes);
+ memset((void *) address, 0, bytes);
+ break;
+ }
+ if ((PAGE_SIZE << --order) < minbytes)
+ order = -1; /* Too small - give up */
+ } while (order >= 0);
+ buf->order = order;
+}
+
+static inline void lanai_buf_deallocate(struct lanai_buffer *buf)
+{
+ if (buf->order >= 0) {
+ APRINTK(buf->start != 0, "lanai_buf_deallocate: start==0!\n");
+ free_pages((unsigned long) buf->start, buf->order);
+ buf->start = buf->end = buf->ptr = 0;
+ }
+}
+
+/* size of buffer in bytes */
+static inline int lanai_buf_size(const struct lanai_buffer *buf)
+{
+ return ((unsigned long) buf->end) - ((unsigned long) buf->start);
+}
+
+/* size of buffer as "card order" (0=1k .. 7=128k) */
+static inline int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
+{
+ return buf->order + PAGE_SHIFT - 10;
+}
+
+/* DMA-able address for this buffer */
+static unsigned long lanai_buf_dmaaddr(const struct lanai_buffer *buf)
+{
+ unsigned long r = virt_to_bus(buf->start);
+ APRINTK((r & ~0xFFFFFF00) == 0, "bad dmaaddr: 0x%lx\n", (long) r);
+ return r;
+}
+
+/* -------------------- HANDLE BACKLOG_VCCS BITFIELD: */
+
+static inline void vcc_mark_backlogged(struct lanai_dev *lanai,
+ const struct lanai_vcc *lvcc)
+{
+ APRINTK(lvcc->vbase != 0, "vcc_mark_backlogged: zero vbase!\n");
+ vci_bitfield_set(&lanai->backlog_vccs, lvcc->vci);
+}
+
+static inline void vcc_unmark_backlogged(struct lanai_dev *lanai,
+ const struct lanai_vcc *lvcc)
+{
+ APRINTK(lvcc->vbase != 0, "vcc_unmark_backlogged: zero vbase!\n");
+ vci_bitfield_clear(&lanai->backlog_vccs, lvcc->vci);
+}
+
+static inline void vcc_backlog_init(struct lanai_dev *lanai)
+{
+ vci_bitfield_init(&lanai->backlog_vccs);
+}
+
+static inline int vcc_is_backlogged(/*const*/ struct lanai_vcc *lvcc)
+{
+ return lvcc->tx.inprogress != NULL ||
+ !skb_queue_empty(&lvcc->tx.backlog);
+}
+
+/* -------------------- PORT I/O UTILITIES: */
+
+/* Registers (and their bit-fields) */
+enum lanai_register {
+ Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
+#define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */
+#define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */
+#define BOARD_ID_LANAI256 (0) /* 25.6M adaptor card */
+ Endian_Reg = 0x04, /* Endian setting */
+ IntStatus_Reg = 0x08, /* Interrupt status */
+ IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */
+ IntAck_Reg = 0x10, /* Interrupt acknowledge */
+ IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */
+ IntStatusSet_Reg = 0x18, /* Get status + enable/disable */
+ IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */
+ IntControlEna_Reg = 0x20, /* Interrupt control enable */
+ IntControlDis_Reg = 0x24, /* Interrupt control disable */
+ Status_Reg = 0x28, /* Status */
+#define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */
+#define STATUS_WAITING (0x00000002) /* Interrupt being delayed */
+#define STATUS_SOOL (0x00000004) /* SOOL alarm */
+#define STATUS_LOCD (0x00000008) /* LOCD alarm */
+#define STATUS_LED (0x00000010) /* LED (HAPPI) output */
+#define STATUS_GPIN (0x00000020) /* GPIN pin */
+#define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */
+ Config1_Reg = 0x2C, /* Config word 1; bits: */
+#define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */
+#define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */
+#define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */
+#define READMODE_PLAIN (0) /* Plain memory read */
+#define READMODE_LINE (2) /* Memory read line */
+#define READMODE_MULTIPLE (3) /* Memory read multiple */
+#define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */
+#define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */
+#define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */
+#define LOOPMODE_NORMAL (0) /* Normal - no loop */
+#define LOOPMODE_TIME (1)
+#define LOOPMODE_DIAG (2)
+#define LOOPMODE_LINE (3)
+#define CONFIG1_MASK_LOOPMODE (0x00000180)
+#define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */
+#define LEDMODE_NOT_SOOL (0) /* !SOOL */
+#define LEDMODE_OFF (1) /* 0 */
+#define LEDMODE_ON (2) /* 1 */
+#define LEDMODE_NOT_LOCD (3) /* !LOCD */
+#define LEDMORE_GPIN (4) /* GPIN */
+#define LEDMODE_NOT_GPIN (7) /* !GPIN */
+#define CONFIG1_MASK_LEDMODE (0x00000E00)
+#define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */
+#define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */
+#define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
+ Config2_Reg = 0x30, /* Config word 2; bits: */
+#define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */
+#define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */
+#define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */
+#define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */
+#define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */
+#define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
+#define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */
+#define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */
+#define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */
+ Statistics_Reg = 0x34, /* Statistics; bits: */
+#define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */
+#define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */
+#define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */
+#define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */
+ ServiceStuff_Reg = 0x38, /* Service stuff; bits: */
+#define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */
+#define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */
+ ServWrite_Reg = 0x3C, /* ServWrite Pointer */
+ ServRead_Reg = 0x40, /* ServRead Pointer */
+ TxDepth_Reg = 0x44, /* FIFO Transmit Depth */
+ Butt_Reg = 0x48, /* Butt register */
+ CBR_ICG_Reg = 0x50,
+ CBR_PTR_Reg = 0x54,
+ PingCount_Reg = 0x58, /* Ping count */
+ DMA_Addr_Reg = 0x5C /* DMA address */
+};
+
+static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
+ enum lanai_register reg)
+{
+ return lanai->base + (bus_addr_t) reg;
+}
+
+
+static inline u32 reg_read(const struct lanai_dev *lanai,
+ enum lanai_register reg)
+{
+ u32 t;
+ t = readl(reg_addr(lanai, reg));
+ RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
+ (int) reg, t);
+ return t;
+}
+
+static inline void reg_write(const struct lanai_dev *lanai, u32 val,
+ enum lanai_register reg)
+{
+ RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
+ (int) reg, val);
+ writel(val, reg_addr(lanai, reg));
+ mdelay(1);
+}
+
+static inline void conf1_write(const struct lanai_dev *lanai)
+{
+ reg_write(lanai, lanai->conf1, Config1_Reg);
+}
+
+static inline void conf2_write(const struct lanai_dev *lanai)
+{
+ reg_write(lanai, lanai->conf2, Config2_Reg);
+}
+
+static inline void reset_board(const struct lanai_dev *lanai)
+{
+ DPRINTK("about to reset board\n");
+ reg_write(lanai, 0, Reset_Reg);
+ /*
+ * If we don't delay a little while here then we can end up
+ * leaving the card in a VERY weird state and lock up the
+ * PCI bus. This isn't documented anywhere but I've convinced
+ * myself after a lot of painful experimentation
+ */
+ udelay(5);
+}
+
+/* -------------------- VCC LIST LOCK: */
+
+/*
+ * The linux-atm code disables local IRQs while managing the list of
+ * VCCs on a card. This is good, but it doesn't save us against
+ * SMP. Unfortunately, fixing this will require changes in the
+ * API which will have to wait a little bit. It's a hard race to
+ * trigger accidentally, so it isn't TOO horrible so far.
+ *
+ * One possible solution would be to have an rwlock which is
+ * always grabbed _irq-style on writing. This would automatically
+ * be grabbed (for writing) by the higher layers on things that
+ * would result in a change in the vcc list (_open, _close,
+ * probably _change_qos) - thus it would also protect the
+ * higher-level list of vccs on each device (atm_dev->vccs).
+ * The driver would be responsible for grabbing it as a read_lock
+ * anytime it wants to consult its table of vccs - for instance
+ * when handling an incoming PDU. This also explains why we would
+ * probably want the write_lock while in _change_qos - to prevent
+ * handling of PDUs while possibly in an inconsistant state.
+ * Also, _send would grab the lock for reading.
+ *
+ * One problem with this is that _open and _close could no longer
+ * do anything that might provoke a schedule. First, it would
+ * force us to use GFP_ATOMIC memory (which is bad), but also
+ * some devices pretty much require scheduling due to long
+ * delays (see lanai_close for an example). So in this case
+ * we need a way to schedule without losing the spinlock.
+ * The cleanest way to do this is probably have a way to mark a
+ * VCC as "in progress" so that the interrupt handler can
+ * still disregard any traffic for it while _open or _close
+ * are sleeping on it. Then it will need to be _open and
+ * _close's job to relinquish the write_lock. Thus, the
+ * lock could be dropped around the times that scheduling
+ * might occur. Perhaps the _READY flag can be used for
+ * this purpose.
+ *
+ * One short note about this "upper layer grabs, driver
+ * relinquishes" write lock - since this needs to be
+ * an _irq lock we're going to have problem saving
+ * and restoring flags (_irqsave/_irqrestore). This
+ * shouldn't be a problem, however - we must just
+ * require that those syscalls are never called with
+ * interrupts disabled so we can use the non-flags-saving
+ * versions.
+ *
+ * Anyway, all of the above is vaporware currently - fixing
+ * this right will require changes in the API and all of
+ * the drivers - this will wait until 2.5.x most likely.
+ * The following NOP macros are just here to mark where
+ * the locks will be needed in the future.
+ */
+#define vcclist_read_lock() do {} while (0)
+#define vcclist_read_unlock() do {} while (0)
+#define vcclist_write_lock() do {} while (0)
+#define vcclist_write_unlock() do {} while (0)
+
+/* -------------------- CARD SRAM UTILITIES: */
+
+/* The SRAM is mapped into normal PCI memory space - the only catch is
+ * that it is only 16-bits wide but must be accessed as 32-bit. The
+ * 16 high bits will be zero. We don't hide this, since they get
+ * programmed mostly like discrete registers anyway
+ */
+#define SRAM_START (0x20000)
+#define SRAM_BYTES (0x20000) /* Again, half don't really exist */
+
+static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
+{
+ return lanai->base + SRAM_START + offset;
+}
+
+static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
+{
+ return readl(sram_addr(lanai, offset));
+}
+
+static inline void sram_write(const struct lanai_dev *lanai,
+ u32 val, int offset)
+{
+ writel(val, sram_addr(lanai, offset));
+}
+
+static int __init sram_test_word(
+ const struct lanai_dev *lanai, int offset, u32 pattern)
+{
+ u32 readback;
+ sram_write(lanai, pattern, offset);
+ readback = sram_read(lanai, offset);
+ if (readback == pattern)
+ return 0;
+ printk(KERN_ERR DEV_LABEL
+ "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
+ lanai->number, offset, pattern, readback);
+ return -EIO;
+}
+
+static int __init sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
+{
+ int offset, result = 0;
+ for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
+ result = sram_test_word(lanai, offset, pattern);
+ return result;
+}
+
+static int __init sram_test_and_clear(const struct lanai_dev *lanai)
+{
+#ifdef FULL_MEMORY_TEST
+ int result;
+ DPRINTK("testing SRAM\n");
+ if ((result = sram_test_pass(lanai, 0x5555)) != 0)
+ return result;
+ if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
+ return result;
+#endif
+ DPRINTK("clearing SRAM\n");
+ return sram_test_pass(lanai, 0x0000);
+}
+
+/* -------------------- CARD-BASED VCC TABLE UTILITIES: */
+
+/* vcc table */
+enum lanai_vcc_offset {
+ vcc_rxaddr1 = 0x00, /* Location1, plus bits: */
+#define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */
+#define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */
+#define RMMODE_TRASH (0) /* discard */
+#define RMMODE_PRESERVE (1) /* input as AAL0 */
+#define RMMODE_PIPE (2) /* pipe to coscheduler */
+#define RMMODE_PIPEALL (3) /* pipe non-RM too */
+#define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */
+#define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */
+#define RXMODE_TRASH (0) /* discard */
+#define RXMODE_AAL0 (1) /* non-AAL5 mode */
+#define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */
+#define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */
+ vcc_rxaddr2 = 0x04, /* Location2 */
+ vcc_rxcrc1 = 0x08, /* RX CRC claculation space */
+ vcc_rxcrc2 = 0x0C,
+ vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */
+#define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */
+#define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */
+#define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */
+ vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */
+#define RXBUFSTART_CLP (0x00004000)
+#define RXBUFSTART_CI (0x00008000)
+ vcc_rxreadptr = 0x18, /* RX readptr */
+ vcc_txicg = 0x1C, /* TX ICG */
+ vcc_txaddr1 = 0x20, /* Location1, plus bits: */
+#define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */
+#define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */
+ vcc_txaddr2 = 0x24, /* Location2 */
+ vcc_txcrc1 = 0x28, /* TX CRC claculation space */
+ vcc_txcrc2 = 0x2C,
+ vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */
+#define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
+#define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */
+ vcc_txendptr = 0x34, /* TX Endptr, plus bits: */
+#define TXENDPTR_CLP (0x00002000)
+#define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */
+#define PDUMODE_AAL0 (0*0x04000)
+#define PDUMODE_AAL5 (2*0x04000)
+#define PDUMODE_AAL5STREAM (3*0x04000)
+ vcc_txwriteptr = 0x38, /* TX Writeptr */
+#define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
+ vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
+#define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */
+};
+
+#define CARDVCC_SIZE (0x40)
+
+static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
+ vci_t vci)
+{
+ return sram_addr(lanai, vci * CARDVCC_SIZE);
+}
+
+static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
+ enum lanai_vcc_offset offset)
+{
+ u32 val;
+ APRINTK(lvcc->vbase != 0, "cardvcc_read: unbound vcc!\n");
+ val= readl(lvcc->vbase + (bus_addr_t) offset);
+ RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
+ lvcc->vci, (int) offset, val);
+ return val;
+}
+
+static inline void cardvcc_write(const struct lanai_vcc *lvcc,
+ u32 val, enum lanai_vcc_offset offset)
+{
+ APRINTK(lvcc->vbase != 0, "cardvcc_write: unbound vcc!\n");
+ APRINTK((val & ~0xFFFF) == 0,
+ "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
+ val, lvcc->vci, (int) offset);
+ RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
+ lvcc->vci, (int) offset, val);
+ writel(val, lvcc->vbase + (bus_addr_t) offset);
+}
+
+/* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
+
+/* How many bytes will an AAL5 PDU take to transmit - remember that:
+ * o we need to add 8 bytes for length, CPI, UU, and CRC
+ * o we need to round up to 48 bytes for cells
+ */
+static inline int aal5_size(int size)
+{
+ int cells = (size + 8 + 47) / 48;
+ return cells * 48;
+}
+
+/* How many bytes can we send if we have "space" space, assuming we have
+ * to send full cells
+ */
+static inline int aal5_spacefor(int space)
+{
+ int cells = space / 48;
+ return cells * 48;
+}
+
+/* -------------------- FREE AN ATM SKB: */
+
+static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
+{
+ if (atmvcc->pop != NULL)
+ atmvcc->pop(atmvcc, skb);
+ else
+ dev_kfree_skb_any(skb);
+}
+
+/* -------------------- TURN VCCS ON AND OFF: */
+
+static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
+{
+ u32 addr1;
+ if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
+ unsigned long dmaaddr = lanai_buf_dmaaddr(&lvcc->rx.buf);
+ cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
+ cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
+ cardvcc_write(lvcc, 0, vcc_rxwriteptr);
+ cardvcc_write(lvcc, 0, vcc_rxbufstart);
+ cardvcc_write(lvcc, 0, vcc_rxreadptr);
+ cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
+ addr1 = ((dmaaddr >> 8) & 0xFF) |
+ RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
+ RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */
+ /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */
+ RXADDR1_SET_MODE(RXMODE_AAL5);
+ } else
+ addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
+ RXADDR1_OAM_PRESERVE | /* ??? */
+ RXADDR1_SET_MODE(RXMODE_AAL0);
+ /* This one must be last! */
+ cardvcc_write(lvcc, addr1, vcc_rxaddr1);
+}
+
+static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
+{
+ unsigned long dmaaddr = lanai_buf_dmaaddr(&lvcc->tx.buf);
+ cardvcc_write(lvcc, 0, vcc_txicg);
+ cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
+ cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
+ cardvcc_write(lvcc, 0, vcc_txreadptr);
+ cardvcc_write(lvcc, 0, vcc_txendptr);
+ cardvcc_write(lvcc, 0, vcc_txwriteptr);
+ cardvcc_write(lvcc,
+ (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
+ TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
+ cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
+ cardvcc_write(lvcc,
+ ((dmaaddr >> 8) & 0xFF) |
+ TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
+ vcc_txaddr1);
+}
+
+/* Shutdown receiving on card */
+static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
+{
+ if (lvcc->vbase == 0) /* We were never bound to a VCI */
+ return;
+ /* 15.1.1 - set to trashing, wait one cell time (15us) */
+ cardvcc_write(lvcc,
+ RXADDR1_SET_RMMODE(RMMODE_TRASH) |
+ RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
+ udelay(15);
+ /* 15.1.2 - clear rest of entries */
+ cardvcc_write(lvcc, 0, vcc_rxaddr2);
+ cardvcc_write(lvcc, 0, vcc_rxcrc1);
+ cardvcc_write(lvcc, 0, vcc_rxcrc2);
+ cardvcc_write(lvcc, 0, vcc_rxwriteptr);
+ cardvcc_write(lvcc, 0, vcc_rxbufstart);
+ cardvcc_write(lvcc, 0, vcc_rxreadptr);
+}
+
+/* Shutdown transmitting on card.
+ * Unfortunately the lanai needs us to wait until all the data
+ * drains out of the buffer before we can dealloc it, so this
+ * can take awhile -- up to 370ms for a full 128KB buffer
+ * assuming everone else is quiet. In theory the time is
+ * boundless if there's a CBR VCC holding things up.
+ */
+static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
+ struct lanai_vcc *lvcc)
+{
+ struct sk_buff *skb;
+ unsigned long flags, timeout;
+ int read, write, lastread = -1;
+ APRINTK(!in_interrupt(),
+ "lanai_shutdown_tx_vci called w/o process context!\n");
+ if (lvcc->vbase == 0) /* We were never bound to a VCI */
+ return;
+ /* 15.2.1 - wait for queue to drain */
+ spin_lock_irqsave(&lanai->txlock, flags);
+ if (lvcc->tx.inprogress != NULL) {
+ lanai_free_skb(lvcc->tx.atmvcc, lvcc->tx.inprogress);
+ lvcc->tx.inprogress = NULL;
+ }
+ while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
+ lanai_free_skb(lvcc->tx.atmvcc, skb);
+ vcc_unmark_backlogged(lanai, lvcc);
+ spin_unlock_irqrestore(&lanai->txlock, flags);
+ timeout = jiffies + ((lanai_buf_size(&lvcc->tx.buf) * HZ) >> 17);
+ write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
+ goto start;
+ while (time_before_eq(jiffies, timeout)) {
+ schedule_timeout(HZ / 25);
+ start:
+ read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
+ if (read == write && /* Is TX buffer empty? */
+ (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
+ (cardvcc_read(lvcc, vcc_txcbr_next) &
+ TXCBR_NEXT_BOZO) == 0))
+ goto done;
+ if (read != lastread) { /* Has there been any progress? */
+ lastread = read;
+ timeout += HZ / 10;
+ }
+ }
+ printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on backlog closing "
+ "vci %d\n", lvcc->tx.atmvcc->dev->number, lvcc->vci);
+ DPRINTK("read, write = %d, %d\n", read, write);
+ done:
+ /* 15.2.2 - clear out all tx registers */
+ cardvcc_write(lvcc, 0, vcc_txreadptr);
+ cardvcc_write(lvcc, 0, vcc_txwriteptr);
+ cardvcc_write(lvcc, 0, vcc_txendptr);
+ cardvcc_write(lvcc, 0, vcc_txcrc1);
+ cardvcc_write(lvcc, 0, vcc_txcrc2);
+ cardvcc_write(lvcc, 0, vcc_txaddr2);
+ cardvcc_write(lvcc, 0, vcc_txaddr1);
+}
+
+/* -------------------- MANAGING AAL0 RX BUFFER: */
+
+static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
+{
+ DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
+ lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80);
+ return (lanai->aal0buf.order < 0) ? -ENOMEM : 0;
+}
+
+static inline void aal0_buffer_free(struct lanai_dev *lanai)
+{
+ DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
+ lanai_buf_deallocate(&lanai->aal0buf);
+}
+
+/* -------------------- EEPROM UTILITIES: */
+
+/* Offsets of data in the EEPROM */
+#define EEPROM_COPYRIGHT (0)
+#define EEPROM_COPYRIGHT_LEN (44)
+#define EEPROM_CHECKSUM (62)
+#define EEPROM_CHECKSUM_REV (63)
+#define EEPROM_MAC (64)
+#define EEPROM_MAC_REV (70)
+#define EEPROM_SERIAL (112)
+#define EEPROM_SERIAL_REV (116)
+#define EEPROM_MAGIC (120)
+#define EEPROM_MAGIC_REV (124)
+
+#define EEPROM_MAGIC_VALUE (0x5AB478D2)
+
+#ifndef READ_EEPROM
+
+/* Stub functions to use if EEPROM reading is disabled */
+static int __init eeprom_read(struct lanai_dev *lanai)
+{
+ printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
+ lanai->number);
+ memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
+ return 0;
+}
+
+static int __init eeprom_validate(struct lanai_dev *lanai)
+{
+ lanai->serialno = 0;
+ lanai->magicno = EEPROM_MAGIC_VALUE;
+ return 0;
+}
+
+#else /* READ_EEPROM */
+
+static int __init eeprom_read(struct lanai_dev *lanai)
+{
+ int i, address;
+ u8 data;
+ u32 tmp;
+#define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
+ } while (0)
+#define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
+#define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
+#define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
+#define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
+#define pre_read() do { data_h(); clock_h(); udelay(5); } while (0)
+#define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
+#define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \
+ data_h(); udelay(5); } while (0)
+ /* start with both clock and data high */
+ data_h(); clock_h(); udelay(5);
+ for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
+ data = (address << 1) | 1; /* Command=read + address */
+ /* send start bit */
+ data_l(); udelay(5);
+ clock_l(); udelay(5);
+ for (i = 128; i != 0; i >>= 1) { /* write command out */
+ tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
+ (data & i) ? CONFIG1_PROMDATA : 0;
+ if (lanai->conf1 != tmp) {
+ set_config1(tmp);
+ udelay(5); /* Let new data settle */
+ }
+ clock_h(); udelay(5); clock_l(); udelay(5);
+ }
+ /* look for ack */
+ data_h(); clock_h(); udelay(5);
+ if (read_pin() != 0)
+ goto error; /* No ack seen */
+ clock_l(); udelay(5);
+ /* read back result */
+ for (data = 0, i = 7; i >= 0; i--) {
+ data_h(); clock_h(); udelay(5);
+ data = (data << 1) | !!read_pin();
+ clock_l(); udelay(5);
+ }
+ /* look again for ack */
+ data_h(); clock_h(); udelay(5);
+ if (read_pin() == 0)
+ goto error; /* Spurious ack */
+ clock_l(); udelay(5);
+ send_stop();
+ lanai->eeprom[address] = data;
+ DPRINTK("EEPROM 0x%04X %02X\n", address, data);
+ }
+ return 0;
+ error:
+ clock_l(); udelay(5); /* finish read */
+ send_stop();
+ printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
+ lanai->number, address);
+ return -EIO;
+#undef set_config1
+#undef clock_h
+#undef clock_l
+#undef data_h
+#undef data_l
+#undef pre_read
+#undef read_pin
+#undef send_stop
+}
+
+/* read a big-endian 4-byte value out of eeprom */
+static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
+{
+ return be32_to_cpup((u32 *) (&lanai->eeprom[address]));
+}
+
+/* Checksum/validate EEPROM contents */
+static int __init eeprom_validate(struct lanai_dev *lanai)
+{
+ int i, s;
+ u32 v;
+ const u8 *e = lanai->eeprom;
+#ifdef DEBUG
+ /* First, see if we can get an ASCIIZ string out of the copyright */
+ for (i = EEPROM_COPYRIGHT;
+ i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
+ if (e[i] < 0x20 || e[i] > 0x7E)
+ break;
+ if ( i != EEPROM_COPYRIGHT &&
+ i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
+ DPRINTK("eeprom: copyright = \"%s\"\n",
+ (char *) &e[EEPROM_COPYRIGHT]);
+ else
+ DPRINTK("eeprom: copyright not found\n");
+#endif
+ /* Validate checksum */
+ for (i = s = 0; i < EEPROM_CHECKSUM; i++)
+ s += e[i];
+ s &= 0xFF;
+ if (s != e[EEPROM_CHECKSUM]) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
+ "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
+ s, e[EEPROM_CHECKSUM]);
+ return -EIO;
+ }
+ s ^= 0xFF;
+ if (s != e[EEPROM_CHECKSUM_REV]) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
+ "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
+ s, e[EEPROM_CHECKSUM_REV]);
+ return -EIO;
+ }
+ /* Verify MAC address */
+ for (i = 0; i < 6; i++)
+ if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
+ printk(KERN_ERR DEV_LABEL
+ "(itf %d) : EEPROM MAC addresses don't match "
+ "(0x%02X, inverse 0x%02X)\n", lanai->number,
+ e[EEPROM_MAC + i], e[EEPROM_MAC_REV + i]);
+ return -EIO;
+ }
+ DPRINTK("eeprom: MAC address = %02X:%02X:%02X:%02X:%02X:%02X\n",
+ e[EEPROM_MAC + 0], e[EEPROM_MAC + 1], e[EEPROM_MAC + 2],
+ e[EEPROM_MAC + 3], e[EEPROM_MAC + 4], e[EEPROM_MAC + 5]);
+ /* Verify serial number */
+ lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
+ v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
+ if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
+ "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
+ lanai->serialno, v);
+ return -EIO;
+ }
+ DPRINTK("eeprom: Serial number = %d\n", lanai->serialno);
+ /* Verify magic number */
+ lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
+ v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
+ if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
+ "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
+ lanai->magicno, v);
+ return -EIO;
+ }
+ DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
+ if (lanai->magicno != EEPROM_MAGIC_VALUE)
+ printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
+ "magic not what expected (got 0x%08X, not 0x%08X)\n",
+ lanai->number, lanai->magicno, EEPROM_MAGIC_VALUE);
+ return 0;
+}
+
+#endif /* READ_EEPROM */
+
+static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
+{
+ return &lanai->eeprom[EEPROM_MAC];
+}
+
+/* -------------------- INTERRUPT HANDLING UTILITIES: */
+
+/* Interrupt types */
+#define INT_STATS (0x00000002) /* Statistics counter overflow */
+#define INT_SOOL (0x00000004) /* SOOL changed state */
+#define INT_LOCD (0x00000008) /* LOCD changed state */
+#define INT_LED (0x00000010) /* LED (HAPPI) changed state */
+#define INT_GPIN (0x00000020) /* GPIN changed state */
+#define INT_PING (0x00000040) /* PING_COUNT fulfilled */
+#define INT_WAKE (0x00000080) /* Lanai wants bus */
+#define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
+#define INT_LOCK (0x00000200) /* Service list overflow */
+#define INT_MISMATCH (0x00000400) /* TX magic list mismatch */
+#define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */
+#define INT_AAL0 (0x00001000) /* Non-AAL5 data available */
+#define INT_SERVICE (0x00002000) /* Service list entries available */
+#define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
+#define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */
+#define INT_TIMEOUTBM (0x00010000) /* No response to bus master */
+#define INT_PCIPARITY (0x00020000) /* Parity error on PCI */
+
+/* Sets of the above */
+#define INT_ALL (0x0003FFFE) /* All interrupts */
+#define INT_STATUS (0x0000003C) /* Some status pin changed */
+#define INT_DMASHUT (0x00038000) /* DMA engine got shut down */
+#define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */
+
+static inline u32 intr_pending(const struct lanai_dev *lanai)
+{
+ return reg_read(lanai, IntStatusMasked_Reg);
+}
+
+static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
+{
+ reg_write(lanai, i, IntControlEna_Reg);
+}
+
+static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
+{
+ reg_write(lanai, i, IntControlDis_Reg);
+}
+
+/* -------------------- CARD/PCI STATUS: */
+
+static void status_message(int itf, const char *name, int status)
+{
+ static const char *onoff[2] = { "off to on", "on to off" };
+ printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
+ itf, name, onoff[!status]);
+}
+
+static void lanai_check_status(struct lanai_dev *lanai)
+{
+ u32 new = reg_read(lanai, Status_Reg);
+ u32 changes = new ^ lanai->status;
+ lanai->status = new;
+#define e(flag, name) \
+ if (changes & flag) \
+ status_message(lanai->number, name, new & flag)
+ e(STATUS_SOOL, "SOOL");
+ e(STATUS_LOCD, "LOCD");
+ e(STATUS_LED, "LED");
+ e(STATUS_GPIN, "GPIN");
+#undef e
+}
+
+static void pcistatus_got(int itf, const char *name)
+{
+ printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
+}
+
+static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
+{
+ u16 s;
+ int result;
+ result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
+ "%d\n", lanai->number, result);
+ return;
+ }
+ s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
+ PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
+ PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
+ if (s == 0)
+ return;
+ result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
+ if (result != PCIBIOS_SUCCESSFUL)
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
+ "%d\n", lanai->number, result);
+ if (clearonly)
+ return;
+#define e(flag, name, stat) \
+ if (s & flag) { \
+ pcistatus_got(lanai->number, name); \
+ ++lanai->stats.pcierr_##stat; \
+ }
+ e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
+ e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
+ e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
+ e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
+ e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
+ e(PCI_STATUS_PARITY, "master parity", master_parity);
+#undef e
+}
+
+/* -------------------- VCC TX BUFFER UTILITIES: */
+
+/* space left in tx buffer in bytes */
+static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
+{
+ int r;
+ r = endptr * 16;
+ r -= ((unsigned long) lvcc->tx.buf.ptr) -
+ ((unsigned long) lvcc->tx.buf.start);
+ r -= 16; /* Leave "bubble" - if start==end it looks empty */
+ if (r < 0)
+ r += lanai_buf_size(&lvcc->tx.buf);
+ return r;
+}
+
+/* Bit fields in the segmentation buffer descriptor */
+#define DESCRIPTOR_MAGIC (0xD0000000)
+#define DESCRIPTOR_AAL5 (0x00008000)
+#define DESCRIPTOR_AAL5_STREAM (0x00004000)
+#define DESCRIPTOR_CLP (0x00002000)
+
+/* Add 32-bit descriptor with it's padding */
+static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
+ u32 flags, int len)
+{
+ int pos;
+ APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
+ "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
+ lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */
+ pos = ((unsigned char *) lvcc->tx.buf.ptr) -
+ (unsigned char *) lvcc->tx.buf.start;
+ APRINTK((pos & ~0x0001FFF0) == 0,
+ "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
+ "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
+ lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
+ pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
+ APRINTK((pos & ~0x0001FFF0) == 0,
+ "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
+ "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
+ lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
+ lvcc->tx.buf.ptr[-1] =
+ cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
+ ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
+ DESCRIPTOR_CLP : 0) | flags | pos >> 4);
+ if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
+ lvcc->tx.buf.ptr = lvcc->tx.buf.start;
+}
+
+/* Add 32-bit AAL5 trailer and leave room for its CRC */
+static inline void vcc_tx_add_aal5trailer(struct lanai_vcc *lvcc,
+ int len, int cpi, int uu)
+{
+ APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
+ "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
+ lvcc->tx.buf.ptr += 2;
+ lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
+ if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
+ lvcc->tx.buf.ptr = lvcc->tx.buf.start;
+}
+
+static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
+ const unsigned char *src, int n)
+{
+ unsigned char *e;
+ int m;
+ e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
+ m = e - (unsigned char *) lvcc->tx.buf.end;
+ if (m < 0)
+ m = 0;
+ memcpy(lvcc->tx.buf.ptr, src, n - m);
+ if (m != 0) {
+ memcpy(lvcc->tx.buf.start, src + n - m, m);
+ e = ((unsigned char *) lvcc->tx.buf.start) + m;
+ }
+ lvcc->tx.buf.ptr = (u32 *) e;
+}
+
+static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
+{
+ unsigned char *e;
+ int m;
+ if (n == 0)
+ return;
+ e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
+ m = e - (unsigned char *) lvcc->tx.buf.end;
+ if (m < 0)
+ m = 0;
+ memset(lvcc->tx.buf.ptr, 0, n - m);
+ if (m != 0) {
+ memset(lvcc->tx.buf.start, 0, m);
+ e = ((unsigned char *) lvcc->tx.buf.start) + m;
+ }
+ lvcc->tx.buf.ptr = (u32 *) e;
+}
+
+/* Update "butt" register to specify new WritePtr */
+static inline void lanai_endtx(const struct lanai_dev *lanai,
+ const struct lanai_vcc *lvcc)
+{
+ int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
+ (unsigned char *) lvcc->tx.buf.start;
+ APRINTK((ptr & ~0x0001FFF0) == 0,
+ "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
+ ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
+ lvcc->tx.buf.end);
+ /*
+ * We need to check if the "butt busy" bit is set before
+ * updating the butt register. In theory this should
+ * never happen because the ATM card is plenty fast at
+ * updating the register. Still, we should make sure
+ */
+ for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
+ if (i > 50) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
+ "always busy!\n", lanai->number);
+ break;
+ }
+ udelay(5);
+ }
+ reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
+}
+
+/* Try to fill the buffer - don't call unless there is backlog */
+static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
+ struct lanai_vcc *lvcc, int endptr)
+{
+ int pad, n;
+ struct sk_buff *skb;
+ int space = vcc_tx_space(lvcc, endptr);
+ APRINTK(vcc_is_backlogged(lvcc),
+ "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
+ lvcc->vci);
+ if (space < 64)
+ return; /* No space for even 1 cell+descriptor */
+ if (lvcc->tx.inprogress != NULL) {
+ APRINTK((lvcc->tx.inprogleft % 48) == 0,
+ "vcc_tx_unqueue_aal5: bad progleft=%d\n",
+ lvcc->tx.inprogleft);
+ if (lvcc->tx.inprogleft + 16 > space) { /* Can't send all? */
+ n = aal5_spacefor(space - 16); /* Bytes to send */
+ vcc_tx_add_aal5_descriptor(lvcc,
+ DESCRIPTOR_AAL5_STREAM, n);
+ pad = lvcc->tx.pptr + n - lvcc->tx.inprogress->tail;
+ if (pad < 0)
+ pad = 0;
+ vcc_tx_memcpy(lvcc, lvcc->tx.pptr, n - pad);
+ vcc_tx_memzero(lvcc, pad);
+ lvcc->tx.pptr += n;
+ lvcc->tx.inprogleft -= n;
+ goto end; /* Buffer is now full */
+ }
+ /* OK, there's at least space for all of "inprogress" skb */
+ vcc_tx_add_aal5_descriptor(lvcc, 0,
+ lvcc->tx.inprogleft);
+ pad = lvcc->tx.pptr + lvcc->tx.inprogleft -
+ lvcc->tx.inprogress->tail;
+ if (pad >= lvcc->tx.inprogleft) { /* Nothing but pad left */
+ APRINTK(lvcc->tx.inprogleft == 48,
+ "vcc_tx_unqueue_aal5: bad pure-pad=%d\n",
+ lvcc->tx.inprogleft);
+ pad = 48;
+ } else
+ vcc_tx_memcpy(lvcc, lvcc->tx.pptr,
+ lvcc->tx.inprogleft - pad);
+ vcc_tx_memzero(lvcc, pad - 8);
+ vcc_tx_add_aal5trailer(lvcc, lvcc->tx.inprogress->len, 0, 0);
+ lanai_free_skb(lvcc->tx.atmvcc, lvcc->tx.inprogress);
+ lvcc->tx.inprogress = NULL;
+ space -= lvcc->tx.inprogleft + 16;
+ atomic_inc(&lvcc->tx.atmvcc->stats->tx);
+ }
+ while (space >= 64) {
+ if ((skb = skb_dequeue(&lvcc->tx.backlog)) == NULL)
+ break;
+ n = aal5_size(skb->len);
+ if (n + 16 > space) { /* Can only send part */
+ int m = aal5_spacefor(space - 16); /* Bytes to send */
+ vcc_tx_add_aal5_descriptor(lvcc,
+ DESCRIPTOR_AAL5_STREAM, m);
+ lvcc->tx.pptr = skb->data + m;
+ pad = lvcc->tx.pptr - skb->tail;
+ if (pad < 0)
+ pad = 0;
+ vcc_tx_memcpy(lvcc, skb->data, m - pad);
+ vcc_tx_memzero(lvcc, pad);
+ lvcc->tx.inprogleft = n - m;
+ lvcc->tx.inprogress = skb;
+ goto end;
+ }
+ vcc_tx_add_aal5_descriptor(lvcc, 0, n);
+ pad = n - skb->len - 8;
+ vcc_tx_memcpy(lvcc, skb->data, skb->len);
+ vcc_tx_memzero(lvcc, pad);
+ lanai_free_skb(lvcc->tx.atmvcc, skb);
+ vcc_tx_add_aal5trailer(lvcc, skb->len, 0, 0);
+ space -= n + 16;
+ atomic_inc(&lvcc->tx.atmvcc->stats->tx);
+ }
+ if (skb_queue_empty(&lvcc->tx.backlog))
+ vcc_unmark_backlogged(lanai, lvcc);
+ end:
+ lanai_endtx(lanai, lvcc);
+}
+
+/* Given an skb that we want to transmit either send it now or queue */
+static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
+ struct sk_buff *skb)
+{
+ int space, n, pad;
+ if (vcc_is_backlogged(lvcc)) /* Already backlogged */
+ goto queue_it;
+ space = vcc_tx_space(lvcc, TXREADPTR_GET_PTR(cardvcc_read(lvcc,
+ vcc_txreadptr)));
+ if (space < 64) {
+ vcc_mark_backlogged(lanai, lvcc); /* No space */
+ goto queue_it;
+ }
+ if (space >= 16 + (n = aal5_size(skb->len))) {
+ /* We can send the whole thing now */
+ vcc_tx_add_aal5_descriptor(lvcc, 0, n);
+ pad = n - skb->len;
+ vcc_tx_memcpy(lvcc, skb->data, skb->len);
+ vcc_tx_memzero(lvcc, pad - 8);
+ vcc_tx_add_aal5trailer(lvcc, skb->len, 0, 0);
+ lanai_free_skb(lvcc->tx.atmvcc, skb);
+ atomic_inc(&lvcc->tx.atmvcc->stats->tx);
+ } else { /* Space for only part of skb */
+ int bytes = aal5_spacefor(space - 16); /* Bytes to send */
+ vcc_tx_add_aal5_descriptor(lvcc,
+ DESCRIPTOR_AAL5_STREAM, bytes);
+ pad = bytes - skb->len;
+ if (pad < 0)
+ pad = 0;
+ vcc_tx_memcpy(lvcc, skb->data, bytes - pad);
+ vcc_tx_memzero(lvcc, pad);
+ lvcc->tx.inprogress = skb;
+ lvcc->tx.inprogleft = n - bytes;
+ lvcc->tx.pptr = skb->data + bytes;
+ vcc_mark_backlogged(lanai, lvcc);
+ }
+ lanai_endtx(lanai, lvcc);
+ return;
+ queue_it:
+ skb_queue_tail(&lvcc->tx.backlog, skb);
+}
+
+static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
+ struct lanai_vcc *lvcc, int endptr)
+{
+ printk(KERN_INFO DEV_LABEL
+ ": vcc_tx_unqueue_aal0: not implemented\n");
+}
+
+static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
+ struct sk_buff *skb)
+{
+ printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
+ /* Remember to increment lvcc->tx.atmvcc->stats->tx */
+ lanai_free_skb(lvcc->tx.atmvcc, skb);
+}
+
+/* Try to undequeue 1 backlogged vcc */
+static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
+{
+ struct lanai_vcc *lvcc = lanai->vccs[vci];
+ int endptr;
+ if (lvcc == NULL || !vcc_is_backlogged(lvcc)) {
+ vci_bitfield_clear(&lanai->backlog_vccs, vci);
+ return;
+ }
+ endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
+ lvcc->tx.unqueue(lanai, lvcc, endptr);
+}
+
+/* Try a dequeue on all backlogged connections */
+static inline void vcc_tx_dequeue_all(struct lanai_dev *lanai)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&lanai->txlock, flags);
+ vci_bitfield_iterate(lanai, &lanai->backlog_vccs, iter_dequeue);
+ spin_unlock_irqrestore(&lanai->txlock, flags);
+}
+
+/* -------------------- VCC RX BUFFER UTILITIES: */
+
+/* unlike the _tx_ cousins, this doesn't update ptr */
+static inline void vcc_rx_memcpy(unsigned char *dest,
+ const struct lanai_vcc *lvcc, int n)
+{
+ int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
+ ((const unsigned char *) (lvcc->rx.buf.end));
+ if (m < 0)
+ m = 0;
+ memcpy(dest, lvcc->rx.buf.ptr, n - m);
+ memcpy(dest + n - m, lvcc->rx.buf.start, m);
+}
+
+/* Receive AAL5 data on a VCC with a particular endptr */
+static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
+{
+ int size;
+ struct sk_buff *skb;
+ /*const*/ u32 *x, *end = &lvcc->rx.buf.start[endptr * 4];
+ int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
+ if (n < 0)
+ n += lanai_buf_size(&lvcc->rx.buf);
+ APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
+ "vcc_rx_aal5: n out of range (%d/%d)\n",
+ n, lanai_buf_size(&lvcc->rx.buf));
+ /* Recover the second-to-last word to get true pdu length */
+ if ((x = &end[-2]) < lvcc->rx.buf.start)
+ x = &lvcc->rx.buf.end[-2];
+ size = be32_to_cpup(x) & 0xffff;
+ if (n != aal5_size(size)) { /* Make sure size matches padding */
+ printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
+ "on vci=%d - size=%d n=%d\n",
+ lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
+ lvcc->stats.x.aal5.rx_badlen++;
+ goto out;
+ }
+ skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
+ if (skb == NULL) {
+ lvcc->stats.rx_nomem++;
+ goto out;
+ }
+ skb_put(skb, size);
+ ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
+ skb->stamp = xtime;
+ vcc_rx_memcpy(skb->data, lvcc, size);
+ lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
+ atomic_inc(&lvcc->rx.atmvcc->stats->rx);
+ out:
+ lvcc->rx.buf.ptr = end;
+ cardvcc_write(lvcc, endptr, vcc_rxreadptr);
+}
+
+static void vcc_rx_aal0(struct lanai_dev *lanai)
+{
+ printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
+ /* Remember to get vcclist_read_lock while looking up VC */
+ /* Remember to increment lvcc->rx.atmvcc->stats->rx */
+}
+
+/* -------------------- MANAGING HOST-BASED VCC TABLE: */
+
+/* Decide whether to use vmalloc or get_free_page for VCC table */
+#if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
+#define VCCTABLE_GETFREEPAGE
+#else
+#include <linux/vmalloc.h>
+#endif
+
+static int __init vcc_table_allocate(struct lanai_dev *lanai)
+{
+#ifdef VCCTABLE_GETFREEPAGE
+ APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
+ "vcc table > PAGE_SIZE!");
+ lanai->vccs = (struct lanai_vcc **) get_free_page(GFP_KERNEL);
+ return (lanai->vccs == NULL) ? -ENOMEM : 0;
+#else
+ int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
+ lanai->vccs = (struct lanai_vcc **) vmalloc(bytes);
+ if (lanai->vccs == NULL)
+ return -ENOMEM;
+ memset(lanai->vccs, 0, bytes);
+ return 0;
+#endif
+}
+
+static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
+{
+#ifdef VCCTABLE_GETFREEPAGE
+ free_page((unsigned long) lanai->vccs);
+#else
+ vfree(lanai->vccs);
+#endif
+}
+
+/* Allocate a fresh lanai_vcc, with the appropriate things cleared */
+static inline struct lanai_vcc *new_lanai_vcc(void)
+{
+ struct lanai_vcc *lvcc;
+ lvcc = (struct lanai_vcc *) kmalloc(sizeof(*lvcc), GFP_KERNEL);
+ if (lvcc != NULL) {
+ lvcc->vbase = 0;
+ lvcc->rx.atmvcc = lvcc->tx.atmvcc = NULL;
+ lvcc->nref = 0;
+ memset(&lvcc->stats, 0, sizeof lvcc->stats);
+ lvcc->rx.buf.start = lvcc->tx.buf.start = NULL;
+ skb_queue_head_init(&lvcc->tx.backlog);
+ lvcc->tx.inprogress = NULL;
+#ifdef DEBUG
+ lvcc->tx.unqueue = NULL;
+ lvcc->vci = -1;
+#endif
+ }
+ return lvcc;
+}
+
+static int lanai_get_sized_buffer(int number, struct lanai_buffer *buf,
+ int max_sdu, int multiplier, int min, const char *name)
+{
+ int size;
+ if (max_sdu < 1)
+ max_sdu = 1;
+ max_sdu = aal5_size(max_sdu);
+ size = (max_sdu + 16) * multiplier + 16;
+ lanai_buf_allocate(buf, size, min);
+ if (buf->order < 0)
+ return -ENOMEM;
+ if (lanai_buf_size(buf) < size)
+ printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
+ "for %s buffer, got only %d\n", number, size, name,
+ lanai_buf_size(buf));
+ DPRINTK("Allocated %d byte %s buffer\n", lanai_buf_size(buf), name);
+ return 0;
+}
+
+/* Setup a RX buffer for a currently unbound AAL5 vci */
+static inline int lanai_setup_rx_vci_aal5(int number, struct lanai_vcc *lvcc,
+ const struct atm_qos *qos)
+{
+ return lanai_get_sized_buffer(number, &lvcc->rx.buf,
+ qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, qos->rxtp.max_sdu + 32,
+ "RX");
+}
+
+/* Setup a TX buffer for a currently unbound AAL5 vci */
+static int lanai_setup_tx_vci(int number, struct lanai_vcc *lvcc,
+ const struct atm_qos *qos)
+{
+ int max_sdu, multiplier;
+ if (qos->aal == ATM_AAL0) {
+ lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
+ max_sdu = ATM_CELL_SIZE - 1;
+ multiplier = AAL0_TX_MULTIPLIER;
+ } else {
+ lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
+ max_sdu = qos->txtp.max_sdu;
+ multiplier = AAL5_TX_MULTIPLIER;
+ }
+ return lanai_get_sized_buffer(number, &lvcc->tx.buf, max_sdu,
+ multiplier, 80, "TX");
+}
+
+static inline void host_vcc_bind(struct lanai_dev *lanai,
+ struct lanai_vcc *lvcc, vci_t vci)
+{
+ if (lvcc->vbase != 0)
+ return; /* We already were bound in the other direction */
+ DPRINTK("Binding vci %d\n", vci);
+#ifdef USE_POWERDOWN
+ if (lanai->nbound++ == 0) {
+ DPRINTK("Coming out of powerdown\n");
+ lanai->conf1 &= ~CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+ conf2_write(lanai);
+ }
+#endif
+ lvcc->vbase = cardvcc_addr(lanai, vci);
+ lanai->vccs[lvcc->vci = vci] = lvcc;
+}
+
+static inline void host_vcc_unbind(struct lanai_dev *lanai,
+ struct lanai_vcc *lvcc)
+{
+ if (lvcc->vbase == 0)
+ return; /* This vcc was never bound */
+ DPRINTK("Unbinding vci %d\n", lvcc->vci);
+ lvcc->vbase = 0;
+ lanai->vccs[lvcc->vci] = NULL;
+#ifdef USE_POWERDOWN
+ if (--lanai->nbound == 0) {
+ DPRINTK("Going into powerdown\n");
+ lanai->conf1 |= CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+ }
+#endif
+}
+
+/* -------------------- RESET CARD: */
+
+static void lanai_reset(struct lanai_dev *lanai)
+{
+ printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not "
+ "implemented\n", lanai->number);
+ /* TODO */
+ /* The following is just a hack until we write the real
+ * resetter - at least ack whatever interrupt sent us
+ * here
+ */
+ reg_write(lanai, INT_ALL, IntAck_Reg);
+ lanai->stats.card_reset++;
+}
+
+/* -------------------- SERVICE LIST UTILITIES: */
+
+/*
+ * Allocate service buffer and tell card about it
+ */
+static int __init service_buffer_allocate(struct lanai_dev *lanai)
+{
+ lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 0);
+ if (lanai->service.order < 0)
+ return -ENOMEM;
+ DPRINTK("allocated service buffer at 0x%08lX, size %d(%d)\n",
+ (unsigned long) lanai->service.start,
+ lanai_buf_size(&lanai->service),
+ lanai_buf_size_cardorder(&lanai->service));
+ /* Clear ServWrite register to be safe */
+ reg_write(lanai, 0, ServWrite_Reg);
+ /* ServiceStuff register contains size and address of buffer */
+ reg_write(lanai,
+ SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
+ SSTUFF_SET_ADDR(lanai_buf_dmaaddr(&lanai->service)),
+ ServiceStuff_Reg);
+ return 0;
+}
+
+static inline void service_buffer_deallocate(struct lanai_dev *lanai)
+{
+ lanai_buf_deallocate(&lanai->service);
+}
+
+/* Bitfields in service list */
+#define SERVICE_TX (0x80000000) /* Was from transmission */
+#define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */
+#define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */
+#define SERVICE_CI (0x10000000) /* RXed PDU had CI set */
+#define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */
+#define SERVICE_STREAM (0x04000000) /* RX Stream mode */
+#define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
+#define SERVICE_GET_END(x) ((x)&0x1FFF)
+
+/* Handle one thing from the service list - returns true if it marked a
+ * VCC ready for xmit
+ */
+static int handle_service(struct lanai_dev *lanai, u32 s)
+{
+ vci_t vci = SERVICE_GET_VCI(s);
+ struct lanai_vcc *lvcc;
+ vcclist_read_lock();
+ lvcc = lanai->vccs[vci];
+ if (lvcc == NULL) {
+ vcclist_read_unlock();
+ DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
+ "vcc %d\n", lanai->number, s, vci);
+ if (s & SERVICE_TX)
+ lanai->stats.service_novcc_tx++;
+ else
+ lanai->stats.service_novcc_rx++;
+ return 0;
+ }
+ if (s & SERVICE_TX) { /* segmentation interrupt */
+ if (lvcc->tx.atmvcc == NULL) {
+ vcclist_read_unlock();
+ DPRINTK("(itf %d) got service entry 0x%X for non-TX "
+ "vcc %d\n", lanai->number, s, vci);
+ lanai->stats.service_notx++;
+ return 0;
+ }
+ vci_bitfield_set(&lanai->transmit_ready, vci);
+ lvcc->tx.endptr = SERVICE_GET_END(s);
+ vcclist_read_unlock();
+ return 1;
+ }
+ if (lvcc->rx.atmvcc == NULL) {
+ vcclist_read_unlock();
+ DPRINTK("(itf %d) got service entry 0x%X for non-RX "
+ "vcc %d\n", lanai->number, s, vci);
+ lanai->stats.service_norx++;
+ return 0;
+ }
+ if (lvcc->rx.atmvcc->qos.aal != ATM_AAL5) {
+ vcclist_read_unlock();
+ DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
+ "vcc %d\n", lanai->number, s, vci);
+ lanai->stats.service_rxnotaal5++;
+ atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
+ return 0;
+ }
+ if ((s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)) == 0) {
+ vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
+ vcclist_read_unlock();
+ return 0;
+ }
+ if (s & SERVICE_TRASH) {
+ int bytes;
+ vcclist_read_unlock();
+ DPRINTK("got trashed rx pdu on vci %d\n", vci);
+ atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
+ lvcc->stats.x.aal5.service_trash++;
+ bytes = (SERVICE_GET_END(s) * 16) -
+ (((unsigned long) lvcc->rx.buf.ptr) -
+ ((unsigned long) lvcc->rx.buf.start)) + 47;
+ if (bytes < 0)
+ bytes += lanai_buf_size(&lvcc->rx.buf);
+ lanai->stats.ovfl_trash += (bytes / 48);
+ return 0;
+ }
+ if (s & SERVICE_STREAM) {
+ vcclist_read_unlock();
+ atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
+ lvcc->stats.x.aal5.service_stream++;
+ printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
+ "PDU on VCI %d!\n", lanai->number, vci);
+ lanai_reset(lanai);
+ return 0;
+ }
+ DPRINTK("got rx crc error on vci %d\n", vci);
+ atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
+ lvcc->stats.x.aal5.service_rxcrc++;
+ lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
+ cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
+ vcclist_read_unlock();
+ return 0;
+}
+
+/* Try transmitting on all VCIs that we marked ready to serve */
+static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
+{
+ struct lanai_vcc *lvcc = lanai->vccs[vci];
+ if (!vcc_is_backlogged(lvcc))
+ return;
+ lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
+}
+
+/* Run service queue -- called from interrupt context or with
+ * interrupts otherwise disabled and with the lanai->servicelock
+ * lock held
+ */
+static void run_service(struct lanai_dev *lanai)
+{
+ int ntx = 0;
+ u32 wreg = reg_read(lanai, ServWrite_Reg);
+ const u32 *end = lanai->service.start + wreg;
+ while (lanai->service.ptr != end) {
+ ntx += handle_service(lanai,
+ le32_to_cpup(lanai->service.ptr++));
+ if (lanai->service.ptr >= lanai->service.end)
+ lanai->service.ptr = lanai->service.start;
+ }
+ reg_write(lanai, wreg, ServRead_Reg);
+ if (ntx != 0) {
+ spin_lock(&lanai->txlock);
+ vcclist_read_lock();
+ vci_bitfield_iterate(lanai, &lanai->transmit_ready,
+ iter_transmit);
+ vci_bitfield_init(&lanai->transmit_ready);
+ vcclist_read_unlock();
+ spin_unlock(&lanai->txlock);
+ }
+}
+
+/* -------------------- GATHER STATISTICS: */
+
+static void get_statistics(struct lanai_dev *lanai)
+{
+ u32 statreg = reg_read(lanai, Statistics_Reg);
+ lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
+ lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
+ lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
+ lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
+}
+
+/* -------------------- POLLING TIMER: */
+
+static void lanai_timed_poll(unsigned long arg)
+{
+#ifndef DEBUG_RW
+ struct lanai_dev *lanai = (struct lanai_dev *) arg;
+ unsigned long flags;
+#ifdef USE_POWERDOWN
+ if (lanai->conf1 & CONFIG1_POWERDOWN)
+ return;
+#endif
+ spin_lock_irqsave(&lanai->servicelock, flags);
+ run_service(lanai);
+ spin_unlock_irqrestore(&lanai->servicelock, flags);
+ vcc_tx_dequeue_all(lanai);
+ get_statistics(lanai);
+ mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
+#endif /* DEBUG_RW */
+}
+
+static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
+{
+ init_timer(&lanai->timer);
+ lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
+ lanai->timer.data = (unsigned long) lanai;
+ lanai->timer.function = lanai_timed_poll;
+ add_timer(&lanai->timer);
+}
+
+static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
+{
+ del_timer(&lanai->timer);
+}
+
+/* -------------------- INTERRUPT SERVICE: */
+
+static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
+{
+ u32 ack = 0;
+ if (reason & INT_SERVICE) {
+ ack = INT_SERVICE;
+ spin_lock(&lanai->servicelock);
+ run_service(lanai);
+ spin_unlock(&lanai->servicelock);
+ }
+ if (reason & (INT_AAL0_STR | INT_AAL0)) {
+ ack |= reason & (INT_AAL0_STR | INT_AAL0);
+ vcc_rx_aal0(lanai);
+ }
+ if (reason & INT_STATS) {
+ reason &= ~INT_STATS; /* No need to ack */
+ get_statistics(lanai);
+ }
+ if (reason & INT_STATUS) {
+ ack |= reason & INT_STATUS;
+ lanai_check_status(lanai);
+ }
+ if (reason & INT_DMASHUT) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
+ "shutdown, reason=0x%08X, address=0x%08X\n",
+ lanai->number, reason & INT_DMASHUT,
+ reg_read(lanai, DMA_Addr_Reg));
+ if (reason & INT_TABORTBM) {
+ lanai_reset(lanai);
+ return;
+ }
+ ack |= (reason & INT_DMASHUT);
+ printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
+ lanai->number);
+ conf1_write(lanai);
+ lanai->stats.dma_reenable++;
+ pcistatus_check(lanai, 0);
+ }
+ if (reason & INT_TABORTSENT) {
+ ack |= (reason & INT_TABORTSENT);
+ printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
+ lanai->number);
+ pcistatus_check(lanai, 0);
+ }
+ if (reason & INT_SEGSHUT) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
+ "segmentation shutdown, reason=0x%08X\n", lanai->number,
+ reason & INT_SEGSHUT);
+ lanai_reset(lanai);
+ return;
+ }
+ if (reason & (INT_PING | INT_WAKE)) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
+ "unexpected interrupt 0x%08X, resetting\n",
+ lanai->number, reason & (INT_PING | INT_WAKE));
+ lanai_reset(lanai);
+ return;
+ }
+#ifdef DEBUG
+ if (ack != reason) {
+ DPRINTK("unacked ints: 0x%08X\n", reason & ~ack);
+ ack = reason;
+ }
+#endif
+ if (ack != 0)
+ reg_write(lanai, ack, IntAck_Reg);
+}
+
+static void lanai_int(int irq, void *devid, struct pt_regs *regs)
+{
+ struct lanai_dev *lanai = (struct lanai_dev *) devid;
+ u32 reason;
+ (void) irq; (void) regs; /* unused variables */
+#ifdef USE_POWERDOWN
+ if (lanai->conf1 & CONFIG1_POWERDOWN) {
+ lanai->conf1 &= ~CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+ printk(KERN_WARNING DEV_LABEL "(itf %d): Got interrupt "
+ "0x%08X while in POWERDOWN, powering up\n", lanai->conf1,
+ intr_pending(lanai));
+ conf2_write(lanai);
+ }
+#endif
+ while ((reason = intr_pending(lanai)) != 0)
+ lanai_int_1(lanai, reason);
+}
+
+/* TODO - it would be nice if we could use the "delayed interrupt" system
+ * to some advantage
+ */
+
+/* -------------------- CHECK BOARD ID/REV: */
+
+/*
+ * The board id and revision are stored both in the reset register and
+ * in the PCI configuration space - the documentation says to check
+ * each of them. If revp!=NULL we store the revision there
+ */
+static int check_board_id_and_rev(const char *name, u32 val, int *revp)
+{
+ DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
+ RESET_GET_BOARD_ID(val), RESET_GET_BOARD_REV(val));
+ if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
+ printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
+ "Lanai 25.6\n", name, RESET_GET_BOARD_ID(val));
+ return -ENODEV;
+ }
+ if (revp != NULL)
+ *revp = RESET_GET_BOARD_REV(val);
+ return 0;
+}
+
+/* -------------------- PCI INITIALIZATION/SHUTDOWN: */
+
+static inline int __init lanai_pci_start(struct lanai_dev *lanai)
+{
+ struct pci_dev *pci = lanai->pci;
+ int result;
+ u16 w;
+ /* Get the pci revision byte */
+ result = pci_read_config_byte(pci, PCI_REVISION_ID,
+ &lanai->pci_revision);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
+ "PCI_REVISION_ID: %d\n", lanai->number, result);
+ return -EINVAL;
+ }
+ result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't read ""
+ PCI_SUBSYSTEM_ID: %d\n", lanai->number, result);
+ return -EINVAL;
+ }
+ if ((result = check_board_id_and_rev("PCI", w, NULL)) != 0)
+ return result;
+ /* Set latency timer to zero as per lanai docs */
+ result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
+ "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
+ return -EINVAL;
+ }
+ result = pci_read_config_word(pci, PCI_COMMAND, &w);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
+ "PCI_COMMAND: %d\n", lanai->number, result);
+ return -EINVAL;
+ }
+ w |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR |
+ PCI_COMMAND_PARITY);
+ result = pci_write_config_word(pci, PCI_COMMAND, w);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't "
+ "write PCI_COMMAND: %d\n", lanai->number, result);
+ return -EINVAL;
+ }
+ pcistatus_check(lanai, 1);
+ pcistatus_check(lanai, 0);
+ return 0;
+}
+
+static void lanai_pci_stop(struct lanai_dev *lanai)
+{
+ struct pci_dev *pci = lanai->pci;
+ int result;
+ u16 pci_command;
+ result = pci_read_config_word(pci, PCI_COMMAND, &pci_command);
+ if (result != PCIBIOS_SUCCESSFUL) {
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't "
+ "read PCI_COMMAND: %d\n", lanai->number, result);
+ return;
+ }
+ pci_command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ result = pci_write_config_word(pci, PCI_COMMAND, pci_command);
+ if (result != PCIBIOS_SUCCESSFUL)
+ printk(KERN_ERR DEV_LABEL "(itf %d): can't "
+ "write PCI_COMMAND: %d\n", lanai->number, result);
+}
+
+/* -------------------- VPI/VCI ALLOCATION: */
+
+/*
+ * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
+ * get a CBRZERO interrupt), and we can use it only if noone is receiving
+ * AAL0 traffic (since they will use the same queue) - according to the
+ * docs we shouldn't even use it for AAL0 traffic
+ */
+static inline int vci0_is_ok(struct lanai_dev *lanai,
+ const struct atm_qos *qos)
+{
+ if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
+ return 0;
+ if (qos->rxtp.traffic_class != ATM_NONE) {
+ if (lanai->naal0 != 0)
+ return 0;
+ lanai->conf2 |= CONFIG2_VCI0_NORMAL;
+#ifdef USE_POWERDOWN
+ if ((lanai->conf1 & CONFIG1_POWERDOWN) == 0)
+#endif
+ conf2_write(lanai);
+ }
+ return 1;
+}
+
+/* return true if vci is currently unused, or if requested qos is
+ * compatible
+ */
+static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
+ const struct atm_vcc *atmvcc)
+{
+ const struct atm_qos *qos = &atmvcc->qos;
+ const struct lanai_vcc *lvcc = lanai->vccs[vci];
+ if (vci == 0 && !vci0_is_ok(lanai, qos))
+ return 0;
+ if (lvcc != NULL) {
+ if (qos->rxtp.traffic_class != ATM_NONE &&
+ lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
+ return 0;
+ if (qos->txtp.traffic_class != ATM_NONE &&
+ lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
+ return 0;
+ if (qos->txtp.traffic_class == ATM_CBR &&
+ lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
+ return 0;
+ }
+ if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
+ qos->rxtp.traffic_class != ATM_NONE) {
+ const struct lanai_vcc *vci0 = lanai->vccs[0];
+ if (vci0 != NULL && vci0->rx.atmvcc != NULL)
+ return 0;
+ lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
+#ifdef USE_POWERDOWN
+ if ((lanai->conf1 & CONFIG1_POWERDOWN) == 0)
+#endif
+ conf2_write(lanai);
+ }
+ return 1;
+}
+
+static int lanai_normalize_ci(struct lanai_dev *lanai,
+ const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
+{
+ switch (*vpip) {
+ case ATM_VPI_ANY:
+ *vpip = 0;
+ /* FALLTHROUGH */
+ case 0:
+ break;
+ default:
+ return -EADDRINUSE;
+ }
+ switch (*vcip) {
+ case ATM_VCI_ANY:
+ for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
+ (*vcip)++)
+ if (vci_is_ok(lanai, *vcip, atmvcc))
+ return 0;
+ return -EADDRINUSE;
+ default:
+ if (*vcip >= lanai->num_vci || *vcip < 0 ||
+ !vci_is_ok(lanai, *vcip, atmvcc))
+ return -EADDRINUSE;
+ }
+ return 0;
+}
+
+/* -------------------- MANAGE CBR: */
+
+/*
+ * CBR ICG is stored as a fixed-point number with 4 fractional bits.
+ * Note that storing a number greater than 2046.0 will result in
+ * incorrect shaping
+ */
+#define CBRICG_FRAC_BITS (4)
+#define CBRICG_MAX (2046 << CBRICG_FRAC_BITS)
+
+/*
+ * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
+ * where MAXPCR is (according to the docs) 25600000/(54*8),
+ * which is equal to (3125<<9)/27.
+ *
+ * Solving for ICG, we get:
+ * ICG = MAXPCR/PCR - 1
+ * ICG = (3125<<9)/(27*PCR) - 1
+ * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
+ *
+ * The end result is supposed to be a fixed-point number with FRAC_BITS
+ * bits of a fractional part, so we keep everything in the numerator
+ * shifted by that much as we compute
+ *
+ */
+static int pcr_to_cbricg(/*const*/ struct atm_qos *qos)
+{
+ int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */
+ int x, icg, pcr = atm_pcr_goal(&qos->txtp);
+ if (pcr == 0) /* Use maximum bandwidth */
+ return 0;
+ if (pcr < 0) {
+ rounddown = 1;
+ pcr = -pcr;
+ }
+ x = pcr * 27;
+ icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
+ if (rounddown)
+ icg += x - 1;
+ icg /= x;
+ if (icg > CBRICG_MAX)
+ icg = CBRICG_MAX;
+ DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
+ pcr, rounddown ? 'Y' : 'N', icg);
+ return icg;
+}
+
+static inline void lanai_cbr_setup(struct lanai_dev *lanai)
+{
+ reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
+ reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
+ lanai->conf2 |= CONFIG2_CBR_ENABLE;
+ conf2_write(lanai);
+}
+
+static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
+{
+ lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
+ conf2_write(lanai);
+}
+
+/* -------------------- OPERATIONS: */
+
+/* setup a newly detected device */
+static int __init lanai_dev_open(struct atm_dev *atmdev)
+{
+ struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
+ unsigned long raw_base;
+ int result;
+
+ DPRINTK("In lanai_dev_open()\n");
+ /* Basic device fields */
+ lanai->number = atmdev->number;
+ lanai->num_vci = NUM_VCI;
+ vci_bitfield_init(&lanai->backlog_vccs);
+ vci_bitfield_init(&lanai->transmit_ready);
+ lanai->naal0 = 0;
+#ifdef USE_POWERDOWN
+ lanai->nbound = 0;
+#endif
+ lanai->cbrvcc = NULL;
+ memset(&lanai->stats, 0, sizeof lanai->stats);
+ spin_lock_init(&lanai->txlock);
+ spin_lock_init(&lanai->servicelock);
+ atmdev->ci_range.vpi_bits = 0;
+ atmdev->ci_range.vci_bits = 0;
+ while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
+ atmdev->ci_range.vci_bits++;
+ atmdev->link_rate = ((25600000 / 8 - 8000) / 54);
+
+ /* 3.2: PCI initialization */
+ if ((result = lanai_pci_start(lanai)) != 0)
+ goto error;
+ raw_base = (bus_addr_t) lanai->pci->resource[0].start;
+ lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
+ if (lanai->base == 0) {
+ printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
+ goto error_pci;
+ }
+ /* 3.3: Reset lanai and PHY */
+ reset_board(lanai);
+ lanai->conf1 = reg_read(lanai, Config1_Reg);
+ lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
+ CONFIG1_MASK_LEDMODE);
+ lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
+ reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
+ udelay(1000);
+ conf1_write(lanai);
+
+ /*
+ * 3.4: Turn on endian mode for big-endian hardware
+ * We don't actually want to do this - the actual bit fields
+ * in the endian register are not documented anywhere.
+ * Instead we do the bit-flipping ourselves on big-endian
+ * hardware.
+ *
+ * 3.5: get the board ID/rev by reading the reset register
+ */
+ result = check_board_id_and_rev("register",
+ reg_read(lanai, Reset_Reg), &lanai->board_rev);
+ if (result != 0)
+ goto error_unmap;
+
+ /* 3.6: read EEPROM */
+ if ((result = eeprom_read(lanai)) != 0)
+ goto error_unmap;
+ if ((result = eeprom_validate(lanai)) != 0)
+ goto error_unmap;
+
+ /* 3.7: re-reset PHY, do loopback tests, setup PHY */
+ reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
+ udelay(1000);
+ conf1_write(lanai);
+ /* TODO - loopback tests */
+ lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
+ conf1_write(lanai);
+
+ /* 3.8/3.9: test and initialize card SRAM */
+ if ((result = sram_test_and_clear(lanai)) != 0)
+ goto error_unmap;
+
+ /* 3.10: initialize lanai registers */
+ lanai->conf1 |= CONFIG1_DMA_ENABLE;
+ conf1_write(lanai);
+ if ((result = service_buffer_allocate(lanai)) != 0)
+ goto error_unmap;
+ if ((result = vcc_table_allocate(lanai)) != 0)
+ goto error_service;
+ lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
+ CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE;
+ conf2_write(lanai);
+ reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
+ reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
+ if ((result = request_irq(lanai->pci->irq, lanai_int, SA_SHIRQ,
+ "lanai", lanai)) != 0) {
+ printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
+ goto error_vcctable;
+ }
+ MOD_INC_USE_COUNT; /* At this point we can't fail */
+ intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
+ /* 3.11: initialize loop mode (i.e. turn looping off) */
+ lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
+ CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
+ CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
+ conf1_write(lanai);
+ lanai->status = reg_read(lanai, Status_Reg);
+ /* We're now done initializing this card */
+#ifdef USE_POWERDOWN
+ lanai->conf1 |= CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+#endif
+ memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
+ lanai_timed_poll_start(lanai);
+ printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%d "
+ "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
+ lanai->pci_revision, (long) lanai->base, lanai->pci->irq,
+ atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
+ atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
+ printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%d(0x%X), "
+ "board_rev=%d\n", lanai->number,
+ lanai->type==lanai2 ? "2" : "HB", lanai->serialno,
+ lanai->serialno, lanai->board_rev);
+ return 0;
+
+ error_vcctable:
+ vcc_table_deallocate(lanai);
+ error_service:
+ service_buffer_deallocate(lanai);
+ error_unmap:
+ reset_board(lanai);
+#ifdef USE_POWERDOWN
+ lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+#endif
+ iounmap((void *) lanai->base);
+ error_pci:
+ lanai_pci_stop(lanai);
+ error:
+ return result;
+}
+
+/* called when device is being shutdown, and all vcc's are gone - higher
+ * levels will deallocate the atm device for us
+ */
+static void lanai_dev_close(struct atm_dev *atmdev)
+{
+ struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
+ printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
+ lanai->number);
+ lanai_timed_poll_stop(lanai);
+#ifdef USE_POWERDOWN
+ lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+#endif
+ intr_disable(lanai, INT_ALL);
+ free_irq(lanai->pci->irq, lanai);
+ reset_board(lanai);
+#ifdef USE_POWERDOWN
+ lanai->conf1 |= CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+#endif
+ lanai_pci_stop(lanai);
+ vcc_table_deallocate(lanai);
+ service_buffer_deallocate(lanai);
+ iounmap((void *) lanai->base);
+ kfree(lanai);
+ MOD_DEC_USE_COUNT;
+}
+
+/* close a vcc */
+static void lanai_close(struct atm_vcc *atmvcc)
+{
+ struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
+ struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
+ if (lvcc == NULL)
+ return;
+ clear_bit(ATM_VF_READY, &atmvcc->flags);
+ clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
+ if (lvcc->rx.atmvcc == atmvcc) {
+ lanai_shutdown_rx_vci(lvcc);
+ if (atmvcc->qos.aal == ATM_AAL0) {
+ if (--lanai->naal0 <= 0)
+ aal0_buffer_free(lanai);
+ } else
+ lanai_buf_deallocate(&lvcc->rx.buf);
+ lvcc->rx.atmvcc = NULL;
+ }
+ if (lvcc->tx.atmvcc == atmvcc) {
+ if (atmvcc == lanai->cbrvcc) {
+ if (lvcc->vbase != 0)
+ lanai_cbr_shutdown(lanai);
+ lanai->cbrvcc = NULL;
+ }
+ lanai_shutdown_tx_vci(lanai, lvcc);
+ lanai_buf_deallocate(&lvcc->tx.buf);
+ lvcc->tx.atmvcc = NULL;
+ }
+ if (--lvcc->nref == 0) {
+ host_vcc_unbind(lanai, lvcc);
+ kfree(lvcc);
+ }
+ atmvcc->dev_data = NULL;
+ clear_bit(ATM_VF_ADDR, &atmvcc->flags);
+}
+
+/* open a vcc on the card to vpi/vci */
+static int lanai_open(struct atm_vcc *atmvcc, short vpi, int vci)
+{
+ struct lanai_dev *lanai;
+ struct lanai_vcc *lvcc;
+ int result = 0;
+ /* we don't support partial open - it's not really useful anyway */
+ if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
+ (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
+ return -EINVAL;
+ lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
+ if ((result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci)) != 0)
+ goto out;
+ atmvcc->vpi = vpi;
+ atmvcc->vci = vci;
+ set_bit(ATM_VF_ADDR, &atmvcc->flags);
+ lvcc = lanai->vccs[vci];
+ if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
+ return -EINVAL;
+#if 0
+ DPRINTK(DEV_LABEL "(itf %d): open %d.%d flags=0x%X\n",
+ lanai->number, vpi, vci, (unsigned long) atmvcc->flags);
+#else
+ DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number, vpi, vci);
+#endif
+ if (lvcc == NULL && (lvcc = new_lanai_vcc()) == NULL)
+ return -ENOMEM;
+ atmvcc->dev_data = lvcc;
+ lvcc->nref++;
+ if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
+ APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
+ vci);
+ if (atmvcc->qos.aal == ATM_AAL0) {
+ if (lanai->naal0 == 0)
+ result = aal0_buffer_allocate(lanai);
+ } else
+ result = lanai_setup_rx_vci_aal5(
+ lanai->number, lvcc, &atmvcc->qos);
+ if (result != 0)
+ goto out_free;
+ lvcc->rx.atmvcc = atmvcc;
+ lvcc->stats.rx_nomem = 0;
+ lvcc->stats.x.aal5.rx_badlen = 0;
+ lvcc->stats.x.aal5.service_trash = 0;
+ lvcc->stats.x.aal5.service_stream = 0;
+ lvcc->stats.x.aal5.service_rxcrc = 0;
+ if (atmvcc->qos.aal == ATM_AAL0)
+ lanai->naal0++;
+ }
+ if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
+ APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
+ vci);
+ result = lanai_setup_tx_vci(lanai->number, lvcc, &atmvcc->qos);
+ if (result != 0)
+ goto out_free;
+ lvcc->tx.atmvcc = atmvcc;
+ if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
+ APRINTK(lanai->cbrvcc == NULL,
+ "cbrvcc!=NULL, vci=%d\n", vci);
+ lanai->cbrvcc = atmvcc;
+ }
+ }
+ host_vcc_bind(lanai, lvcc, vci);
+ if (atmvcc == lvcc->rx.atmvcc)
+ host_vcc_start_rx(lvcc);
+ if (atmvcc == lvcc->tx.atmvcc) {
+ host_vcc_start_tx(lvcc);
+ if (lanai->cbrvcc == atmvcc)
+ lanai_cbr_setup(lanai);
+ }
+ set_bit(ATM_VF_READY, &atmvcc->flags);
+ return 0;
+ out_free:
+ lanai_close(atmvcc);
+ out:
+ return result;
+}
+
+/* ioctl operations for card */
+/* NOTE: these are all DEBUGGING ONLY currently */
+static int lanai_ioctl(struct atm_dev *atmdev, unsigned int cmd, void *arg)
+{
+ int result = 0;
+ struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
+ switch(cmd) {
+ case 2106275:
+ shutdown_atm_dev(atmdev);
+ return 0;
+ case 2200000: {
+ unsigned long flags;
+ spin_lock_irqsave(&lanai->servicelock, flags);
+ run_service(lanai);
+ spin_unlock_irqrestore(&lanai->servicelock, flags);
+ return 0; }
+ case 2200001:
+ vcc_tx_dequeue_all(lanai);
+ return 0;
+ case 2200002:
+ get_statistics(lanai);
+ return 0;
+ case 2200003: {
+ int i;
+ for (i = 0; i <= 0x5C ; i += 4) {
+ if (i==0x48) /* Write-only butt reg */
+ continue;
+ printk(KERN_CRIT DEV_LABEL " 0x%02X: "
+ "0x%08X\n", i,
+ (u32) readl(lanai->base + i));
+ barrier(); mb();
+ pcistatus_check(lanai, 0);
+ barrier(); mb();
+ }
+ return 0; }
+ case 2200004: {
+ u8 b;
+ u16 w;
+ u32 dw;
+ struct pci_dev *pci = lanai->pci;
+ (void) pci_read_config_word(pci, PCI_VENDOR_ID, &w);
+ DPRINTK("vendor = 0x%X\n", w);
+ (void) pci_read_config_word(pci, PCI_DEVICE_ID, &w);
+ DPRINTK("device = 0x%X\n", w);
+ (void) pci_read_config_word(pci, PCI_COMMAND, &w);
+ DPRINTK("command = 0x%X\n", w);
+ (void) pci_read_config_word(pci, PCI_STATUS, &w);
+ DPRINTK("status = 0x%X\n", w);
+ (void) pci_read_config_dword(pci,
+ PCI_CLASS_REVISION, &dw);
+ DPRINTK("class/revision = 0x%X\n", dw);
+ (void) pci_read_config_byte(pci,
+ PCI_CACHE_LINE_SIZE, &b);
+ DPRINTK("cache line size = 0x%X\n", b);
+ (void) pci_read_config_byte(pci, PCI_LATENCY_TIMER, &b);
+ DPRINTK("latency = %d (0x%X)\n", b, b);
+ (void) pci_read_config_byte(pci, PCI_HEADER_TYPE, &b);
+ DPRINTK("header type = 0x%X\n", b);
+ (void) pci_read_config_byte(pci, PCI_BIST, &b);
+ DPRINTK("bist = 0x%X\n", b);
+ /* skipping a few here */
+ (void) pci_read_config_byte(pci,
+ PCI_INTERRUPT_LINE, &b);
+ DPRINTK("pci_int_line = 0x%X\n", b);
+ (void) pci_read_config_byte(pci,
+ PCI_INTERRUPT_PIN, &b);
+ DPRINTK("pci_int_pin = 0x%X\n", b);
+ (void) pci_read_config_byte(pci, PCI_MIN_GNT, &b);
+ DPRINTK("min_gnt = 0x%X\n", b);
+ (void) pci_read_config_byte(pci, PCI_MAX_LAT, &b);
+ DPRINTK("max_lat = 0x%X\n", b); }
+ return 0;
+#ifdef USE_POWERDOWN
+ case 2200005:
+ DPRINTK("Coming out of powerdown\n");
+ lanai->conf1 &= ~CONFIG1_POWERDOWN;
+ conf1_write(lanai);
+ return 0;
+#endif
+ default:
+ result = -EINVAL;
+ }
+ return result;
+}
+
+static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
+{
+ struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
+ struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
+ unsigned long flags;
+ if (lvcc == NULL || lvcc->vbase == 0 || lvcc->tx.atmvcc != atmvcc)
+ goto einval;
+#ifdef DEBUG
+ if (skb == NULL) {
+ DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
+ goto einval;
+ }
+ if (lanai == NULL) {
+ DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
+ goto einval;
+ }
+#endif
+ ATM_SKB(skb)->vcc = atmvcc;
+ switch (atmvcc->qos.aal) {
+ case ATM_AAL5:
+ spin_lock_irqsave(&lanai->txlock, flags);
+ vcc_tx_aal5(lanai, lvcc, skb);
+ spin_unlock_irqrestore(&lanai->txlock, flags);
+ return 0;
+ case ATM_AAL0:
+ if (skb->len != ATM_CELL_SIZE-1)
+ goto einval;
+ /* NOTE - this next line is technically invalid - we haven't unshared skb */
+ cpu_to_be32s((u32 *) skb->data);
+ spin_lock_irqsave(&lanai->txlock, flags);
+ vcc_tx_aal0(lanai, lvcc, skb);
+ spin_unlock_irqrestore(&lanai->txlock, flags);
+ return 0;
+ }
+ DPRINTK("lanai_send: bad aal=%d on vci=%d\n", atmvcc->qos.aal,
+ atmvcc->vci);
+ einval:
+ lanai_free_skb(atmvcc, skb);
+ return -EINVAL;
+}
+
+static int lanai_change_qos(struct atm_vcc *atmvcc,
+ /*const*/ struct atm_qos *qos, int flags)
+{
+ return -EBUSY; /* TODO: need to write this */
+}
+
+#ifndef CONFIG_PROC_FS
+#define lanai_proc_read NULL
+#else
+static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
+{
+ struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
+ loff_t left = *pos;
+ struct lanai_vcc *lvcc;
+ if (left-- == 0)
+ return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
+ "serial=%d, magic=0x%08X, num_vci=%d\n",
+ atmdev->number, lanai->type==lanai2 ? "2" : "HB",
+ lanai->serialno, lanai->magicno, lanai->num_vci);
+ if (left-- == 0)
+ return sprintf(page, "revision: board=%d, pci_if=%d\n",
+ lanai->board_rev, lanai->pci_revision);
+ if (left-- == 0)
+ return sprintf(page, "EEPROM ESI: "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ lanai->eeprom[EEPROM_MAC + 0],
+ lanai->eeprom[EEPROM_MAC + 1],
+ lanai->eeprom[EEPROM_MAC + 2],
+ lanai->eeprom[EEPROM_MAC + 3],
+ lanai->eeprom[EEPROM_MAC + 4],
+ lanai->eeprom[EEPROM_MAC + 5]);
+ if (left-- == 0)
+ return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
+ "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
+ (lanai->status & STATUS_LOCD) ? 1 : 0,
+ (lanai->status & STATUS_LED) ? 1 : 0,
+ (lanai->status & STATUS_GPIN) ? 1 : 0);
+ if (left-- == 0)
+ return sprintf(page, "global buffer sizes: service=%d, "
+ "aal0_rx=%d\n", lanai_buf_size(&lanai->service),
+ lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
+ if (left-- == 0) {
+ get_statistics(lanai);
+ return sprintf(page, "cells in error: overflow=%d, "
+ "closed_vci=%d, bad_HEC=%d, rx_fifo=%d\n",
+ lanai->stats.ovfl_trash, lanai->stats.vci_trash,
+ lanai->stats.hec_err, lanai->stats.atm_ovfl);
+ }
+ if (left-- == 0)
+ return sprintf(page, "PCI errors: parity_detect=%d, "
+ "master_abort=%d, master_target_abort=%d,\n",
+ lanai->stats.pcierr_parity_detect,
+ lanai->stats.pcierr_serr_set,
+ lanai->stats.pcierr_m_target_abort);
+ if (left-- == 0)
+ return sprintf(page, " slave_target_abort=%d, "
+ "master_parity=%d\n", lanai->stats.pcierr_s_target_abort,
+ lanai->stats.pcierr_master_parity);
+ if (left-- == 0)
+ return sprintf(page, "service list errors: no_vcc_rx=%d, "
+ "no_vcc_tx=%d,\n", lanai->stats.service_novcc_rx,
+ lanai->stats.service_novcc_tx);
+ if (left-- == 0)
+ return sprintf(page, " no_tx=%d, "
+ "no_rx=%d, bad_rx_aal=%d\n", lanai->stats.service_norx,
+ lanai->stats.service_notx,
+ lanai->stats.service_rxnotaal5);
+ if (left-- == 0)
+ return sprintf(page, "resets: dma=%d, card=%d\n",
+ lanai->stats.dma_reenable, lanai->stats.card_reset);
+ /* At this point, "left" should be the VCI we're looking for */
+ vcclist_read_lock();
+ for (; ; left++) {
+ if (left >= NUM_VCI) {
+ left = 0;
+ goto out;
+ }
+ if ((lvcc = lanai->vccs[left]) != NULL)
+ break;
+ (*pos)++;
+ }
+ /* Note that we re-use "left" here since we're done with it */
+ left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%d", (vci_t) left,
+ lvcc->nref, lvcc->stats.rx_nomem);
+ if (lvcc->rx.atmvcc != NULL) {
+ left += sprintf(&page[left], ",\n rx_AAL=%d",
+ lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
+ if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
+ left += sprintf(&page[left], ", rx_buf_size=%d, "
+ "rx_bad_len=%d,\n rx_service_trash=%d, "
+ "rx_service_stream=%d, rx_bad_crc=%d",
+ lanai_buf_size(&lvcc->rx.buf),
+ lvcc->stats.x.aal5.rx_badlen,
+ lvcc->stats.x.aal5.service_trash,
+ lvcc->stats.x.aal5.service_stream,
+ lvcc->stats.x.aal5.service_rxcrc);
+ }
+ if (lvcc->tx.atmvcc != NULL)
+ left += sprintf(&page[left], ",\n tx_AAL=%d, "
+ "tx_buf_size=%d, tx_qos=%cBR, tx_backlogged=%c",
+ lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
+ lanai_buf_size(&lvcc->tx.buf),
+ lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
+ vcc_is_backlogged(lvcc) ? 'Y' : 'N');
+ page[left++] = '\n';
+ page[left] = '\0';
+ out:
+ vcclist_read_unlock();
+ return left;
+}
+#endif /* CONFIG_PROC_FS */
+
+/* -------------------- HOOKS: */
+
+static const struct atmdev_ops ops = {
+ dev_close: lanai_dev_close,
+ open: lanai_open,
+ close: lanai_close,
+ ioctl: lanai_ioctl,
+ getsockopt: NULL,
+ setsockopt: NULL,
+ send: lanai_send,
+ sg_send: NULL, /* no scatter-gather on card */
+ send_oam: NULL, /* OAM support not in linux yet */
+ phy_put: NULL,
+ phy_get: NULL,
+ feedback: NULL,
+ change_qos: lanai_change_qos,
+ free_rx_skb: NULL,
+ proc_read: lanai_proc_read
+};
+
+/* detect one type of card LANAI2 or LANAIHB */
+static int __init lanai_detect_1(unsigned int vendor, unsigned int device)
+{
+ struct pci_dev *pci = NULL;
+ struct lanai_dev *lanai;
+ struct atm_dev *atmdev;
+ int count = 0, result;
+ while ((pci = pci_find_device(vendor, device, pci)) != NULL) {
+ lanai = (struct lanai_dev *)
+ kmalloc(sizeof *lanai, GFP_KERNEL);
+ if (lanai == NULL) {
+ printk(KERN_ERR DEV_LABEL ": couldn't allocate "
+ "dev_data structure!\n");
+ break;
+ }
+ atmdev = atm_dev_register(DEV_LABEL, &ops, -1, 0);
+ if (atmdev == NULL) {
+ printk(KERN_ERR DEV_LABEL ": couldn't register "
+ "atm device!\n");
+ kfree(lanai);
+ break;
+ }
+ atmdev->dev_data = lanai;
+ lanai->pci = pci;
+ lanai->type = (enum lanai_type) device;
+ if ((result = lanai_dev_open(atmdev)) != 0) {
+ DPRINTK("lanai_start() failed, err=%d\n", -result);
+ atm_dev_deregister(atmdev);
+ kfree(lanai);
+ continue;
+ }
+ count++;
+ }
+ return count;
+}
+
+#ifdef MODULE
+static
+#endif
+int __init lanai_detect(void)
+{
+ return lanai_detect_1(PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAI2) +
+ lanai_detect_1(PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAIHB);
+}
+
+#ifdef MODULE
+
+int init_module(void)
+{
+ if (lanai_detect() == 0) {
+ printk(KERN_ERR DEV_LABEL ": no adaptor found\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+void cleanup_module(void)
+{
+ /* We'll only get called when all the interfaces are already
+ * gone, so there isn't much to do
+ */
+ DPRINTK("cleanup_module()\n");
+}
+
+MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
+MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
+MODULE_LICENSE("GPL");
+
+#endif /* MODULE */
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
#elif (NS_LGBUFSIZE == 4096)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
-#eliif (NS_LGBUFSIZE == 8192)
+#elif (NS_LGBUFSIZE == 8192)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
#elif (NS_LGBUFSIZE == 16384)
#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
static BlockDeviceOperations_T
DAC960_BlockDeviceOperations =
- { open: DAC960_Open,
+ { owner: THIS_MODULE,
+ open: DAC960_Open,
release: DAC960_Release,
ioctl: DAC960_IOCTL };
Controller->ControllerUsageCount++;
Controller->LogicalDriveUsageCount[LogicalDriveNumber]++;
ModuleOnly:
- MOD_INC_USE_COUNT;
return 0;
}
Controller->LogicalDriveUsageCount[LogicalDriveNumber]--;
Controller->ControllerUsageCount--;
ModuleOnly:
- MOD_DEC_USE_COUNT;
return 0;
}
acsi_prevent_removal(device, 1);
}
access_count[device]++;
- MOD_INC_USE_COUNT;
if (filp && filp->f_mode) {
check_disk_change( inode->i_rdev );
int device = DEVICE_NR(MINOR(inode->i_rdev));
if (--access_count[device] == 0 && acsi_info[device].removable)
acsi_prevent_removal(device, 0);
- MOD_DEC_USE_COUNT;
return( 0 );
}
#endif
static struct block_device_operations acsi_fops = {
+ owner: THIS_MODULE,
open: acsi_open,
release: acsi_release,
ioctl: acsi_ioctl,
}
static struct block_device_operations floppy_fops = {
+ owner: THIS_MODULE,
open: floppy_open,
release: floppy_release,
ioctl: fd_ioctl,
if (fd_ref[drive] == -1 || (fd_ref[drive] && filp->f_flags & O_EXCL))
return -EBUSY;
- MOD_INC_USE_COUNT;
-
if (filp->f_flags & O_EXCL)
fd_ref[drive] = -1;
else
fd_ref[drive] = 0;
}
- MOD_DEC_USE_COUNT;
return 0;
}
static struct block_device_operations floppy_fops = {
+ owner: THIS_MODULE,
open: floppy_open,
release: floppy_release,
ioctl: fd_ioctl,
#endif /* CONFIG_PROC_FS */
static struct block_device_operations cciss_fops = {
+ owner: THIS_MODULE,
open: cciss_open,
release: cciss_release,
ioctl: cciss_ioctl,
hba[ctlr]->drv[dsk].usage_count++;
hba[ctlr]->usage_count++;
- MOD_INC_USE_COUNT;
return 0;
}
/*
hba[ctlr]->drv[dsk].usage_count--;
hba[ctlr]->usage_count--;
- MOD_DEC_USE_COUNT;
return 0;
}
}
static struct block_device_operations ida_fops = {
+ owner: THIS_MODULE,
open: ida_open,
release: ida_release,
ioctl: ida_ioctl,
hba[ctlr]->drv[dsk].usage_count++;
hba[ctlr]->usage_count++;
- MOD_INC_USE_COUNT;
return 0;
}
hba[ctlr]->drv[dsk].usage_count--;
hba[ctlr]->usage_count--;
- MOD_DEC_USE_COUNT;
return 0;
}
static struct floppy_drive_params drive_params[N_DRIVE];
static struct floppy_drive_struct drive_state[N_DRIVE];
static struct floppy_write_errors write_errors[N_DRIVE];
+static struct timer_list motor_off_timer[N_DRIVE];
static struct floppy_raw_cmd *raw_cmd, default_raw_cmd;
/*
set_dor(FDC(nr), mask, 0);
}
-static struct timer_list motor_off_timer[N_DRIVE] = {
- { data: 0, function: motor_off_callback },
- { data: 1, function: motor_off_callback },
- { data: 2, function: motor_off_callback },
- { data: 3, function: motor_off_callback },
- { data: 4, function: motor_off_callback },
- { data: 5, function: motor_off_callback },
- { data: 6, function: motor_off_callback },
- { data: 7, function: motor_off_callback }
-};
-
/* schedules motor off */
static void floppy_off(unsigned int drive)
{
}
static struct block_device_operations floppy_fops = {
+ owner: THIS_MODULE,
open: floppy_open,
release: floppy_release,
ioctl: fd_ioctl,
DPRINT("bad drive for set_cmos\n");
return;
}
+#if N_FDC > 1
if (current_drive >= 4 && !FDC2)
FDC2 = 0x370;
+#endif
DP->cmos = ints[2];
DPRINT("setting CMOS code to %d\n", ints[2]);
}
{ "dma", 0, &FLOPPY_DMA, 2, 0 },
{ "daring", daring, 0, 1, 0},
-
+#if N_FDC > 1
{ "two_fdc", 0, &FDC2, 0x370, 0 },
{ "one_fdc", 0, &FDC2, 0, 0 },
-
+#endif
{ "thinkpad", floppy_set_flags, 0, 1, FD_INVERTED_DCL },
{ "broken_dcl", floppy_set_flags, 0, 1, FD_BROKEN_DCL },
{ "messages", floppy_set_flags, 0, 1, FTD_MSG },
{ "unexpected_interrupts", 0, &print_unex, 1, 0 },
{ "no_unexpected_interrupts", 0, &print_unex, 0, 0 },
{ "L40SX", 0, &print_unex, 0, 0 }
+
+ EXTRA_FLOPPY_PARAMS
};
static int __init floppy_setup(char *str)
}
for (drive = 0; drive < N_DRIVE; drive++) {
+ motor_off_timer[drive].data = drive;
+ motor_off_timer[drive].function = motor_off_callback;
if (!(allowed_drive_mask & (1 << drive)))
continue;
if (fdc_state[FDC(drive)].version == FDC_NONE)
* asumme it has free buffers and check waiters
*/
if (q) {
+ /*
+ * If nobody is waiting for requests, don't bother
+ * batching up.
+ */
+ if (!list_empty(&q->request_freelist[rw])) {
+ list_add(&req->queue, &q->request_freelist[rw]);
+ return;
+ }
+
/*
* Add to pending free list and batch wakeups
*/
/*
* Batch frees according to queue length
*/
- batch_requests = queue_nr_requests >> 3;
+ batch_requests = queue_nr_requests/3;
printk("block: %d slots per queue, batch=%d\n", queue_nr_requests, batch_requests);
#ifdef CONFIG_AMIGA_Z2RAM
}
static struct block_device_operations lo_fops = {
+ owner: THIS_MODULE,
open: lo_open,
release: lo_release,
ioctl: lo_ioctl,
return -ENODEV;
nbd_dev[dev].refcnt++;
- MOD_INC_USE_COUNT;
return 0;
}
printk(KERN_ALERT "nbd_release: refcount(%d) <= 0\n", lo->refcnt);
lo->refcnt--;
/* N.B. Doesn't lo->file need an fput?? */
- MOD_DEC_USE_COUNT;
return 0;
}
static struct block_device_operations nbd_fops =
{
+ owner: THIS_MODULE.
open: nbd_open,
release: nbd_release,
ioctl: nbd_ioctl,
int pcd_init(void);
void cleanup_module( void );
-static int pcd_dev_open(struct inode *inode, struct file *file);
-static void pcd_dev_release(struct inode *inode, struct file *file);
static int pcd_open(struct cdrom_device_info *cdi, int purpose);
static void pcd_release(struct cdrom_device_info *cdi);
static int pcd_drive_status(struct cdrom_device_info *cdi, int slot_nr);
/* kernel glue structures */
-struct block_device_operations pcd_bdops = {
- open: pcd_dev_open,
- release: pcd_dev_release,
+static struct block_device_operations pcd_bdops = {
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
}
return 0;
}
-static int pcd_dev_open(struct inode *inode, struct file *file)
-{
- int err;
-
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int pcd_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
static int pcd_open(struct cdrom_device_info *cdi, int purpose)
{ int unit = DEVICE_NR(cdi->dev);
};
static struct block_device_operations pd_fops = {
+ owner: THIS_MODULE,
open: pd_open,
release: pd_release,
ioctl: pd_ioctl,
if ((unit >= PD_UNITS) || (!PD.present)) return -ENODEV;
- MOD_INC_USE_COUNT;
-
wait_event (pd_wait_open, pd_valid);
PD.access++;
if (!PD.access && PD.removable)
pd_doorlock(unit,IDE_DOORUNLOCK);
- MOD_DEC_USE_COUNT;
-
return 0;
}
/* kernel glue structures */
static struct block_device_operations pf_fops = {
+ owner: THIS_MODULE,
open: pf_open,
release: pf_release,
ioctl: pf_ioctl,
if ((unit >= PF_UNITS) || (!PF.present)) return -ENODEV;
- MOD_INC_USE_COUNT;
-
pf_identify(unit);
- if (PF.media_status == PF_NM) {
- MOD_DEC_USE_COUNT;
+ if (PF.media_status == PF_NM)
return -ENODEV;
- }
- if ((PF.media_status == PF_RO) && (file ->f_mode & 2)) {
- MOD_DEC_USE_COUNT;
+ if ((PF.media_status == PF_RO) && (file ->f_mode & 2))
return -EROFS;
- }
PF.access++;
if (PF.removable) pf_lock(unit,1);
if (!PF.access && PF.removable)
pf_lock(unit,0);
- MOD_DEC_USE_COUNT;
-
return 0;
}
static struct block_device_operations ps2esdi_fops =
{
+ owner: THIS_MODULE,
open: ps2esdi_open,
release: ps2esdi_release,
ioctl: ps2esdi_ioctl,
rd_bdev[unit]->bd_inode->i_mapping->a_ops = &ramdisk_aops;
}
- MOD_INC_USE_COUNT;
-
- return 0;
-}
-
-static int rd_release(struct inode * inode, struct file * filp)
-{
- MOD_DEC_USE_COUNT;
return 0;
}
static struct block_device_operations rd_bd_op = {
+ owner: THIS_MODULE,
open: rd_open,
- release: rd_release,
ioctl: rd_ioctl,
};
};
static struct block_device_operations xd_fops = {
+ owner: THIS_MODULE,
open: xd_open,
release: xd_release,
ioctl: xd_ioctl,
{
int dev = DEVICE_NR(inode->i_rdev);
- MOD_INC_USE_COUNT;
-
if (dev < xd_drives) {
while (!xd_valid[dev])
sleep_on(&xd_wait_open);
return (0);
}
- MOD_DEC_USE_COUNT;
return -ENXIO;
}
static int xd_release (struct inode *inode, struct file *file)
{
int target = DEVICE_NR(inode->i_rdev);
- if (target < xd_drives) {
+ if (target < xd_drives)
xd_access[target]--;
- MOD_DEC_USE_COUNT;
- }
return 0;
}
sizeof( z2ram_map[0] );
int rc = -ENOMEM;
- MOD_INC_USE_COUNT;
-
device = DEVICE_NR( inode->i_rdev );
if ( current_device != -1 && current_device != device )
err_out_kfree:
kfree( z2ram_map );
err_out:
- MOD_DEC_USE_COUNT;
return rc;
}
* FIXME: unmap memory
*/
- MOD_DEC_USE_COUNT;
-
return 0;
}
static struct block_device_operations z2_fops =
{
+ owner: THIS_MODULE,
open: z2_open,
release: z2_release,
};
int aztcd_init(void);
static struct block_device_operations azt_fops = {
+ owner:THIS_MODULE,
open:aztcd_open,
release:aztcd_release,
ioctl:aztcd_ioctl,
if (aztPresent == 0)
return -ENXIO; /* no hardware */
- MOD_INC_USE_COUNT;
-
if (!azt_open_count && azt_state == AZT_S_IDLE) {
azt_invalidate_buffers();
return 0;
err_out:
- MOD_DEC_USE_COUNT;
return -EIO;
}
printk("inode: %p, inode->i_rdev: %x file: %p\n", inode,
inode->i_rdev, file);
#endif
- MOD_DEC_USE_COUNT;
if (!--azt_open_count) {
azt_invalidate_buffers();
aztUnlockDoor();
return 0;
}
-static int scd_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int scd_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
/*
* Open the drive for operations. Spin the drive up and read the table of
* contents if these have not already been done.
struct block_device_operations scd_bdops =
{
- open: scd_dev_open,
- release: scd_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
}
}
-static int cm206_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int cm206_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
struct block_device_operations cm206_bdops =
{
- open: cm206_dev_open,
- release: cm206_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
static struct timer_list gscd_timer;
static struct block_device_operations gscd_fops = {
+ owner:THIS_MODULE,
open:gscd_open,
release:gscd_release,
ioctl:gscd_ioctl,
if (gscdPresent == 0)
return -ENXIO; /* no hardware */
- MOD_INC_USE_COUNT;
-
get_status();
st = disk_state & (ST_NO_DISK | ST_DOOR_OPEN);
if (st) {
printk("GSCD: no disk or door open\n");
- MOD_DEC_USE_COUNT;
return -ENXIO;
}
gscd_bn = -1;
- MOD_DEC_USE_COUNT;
return 0;
}
void *arg);
int mcd_drive_status(struct cdrom_device_info *cdi, int slot_nr);
-static int mcd_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int mcd_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
struct block_device_operations mcd_bdops =
{
- open: mcd_dev_open,
- release: mcd_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
int mcdx_init(void);
void do_mcdx_request(request_queue_t * q);
-static int mcdx_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int mcdx_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
struct block_device_operations mcdx_bdops =
{
- open: mcdx_dev_open,
- release: mcdx_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
{
DEBUG((DEBUG_VFS, "starting opt_open"));
- MOD_INC_USE_COUNT;
-
if (!open_count && state == S_IDLE) {
int status;
return 0;
err_out:
- MOD_DEC_USE_COUNT;
return -EIO;
}
del_timer(&delay_timer);
del_timer(&req_timer);
}
- MOD_DEC_USE_COUNT;
return 0;
}
static struct block_device_operations opt_fops = {
+ owner: THIS_MODULE,
open: opt_open,
release: opt_release,
ioctl: opt_ioctl,
}
/*==========================================================================*/
-static int sbpcd_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int sbpcd_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
static struct block_device_operations sbpcd_bdops =
{
- open: sbpcd_dev_open,
- release: sbpcd_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
if (fp->f_mode & 2)
return (-EROFS);
- MOD_INC_USE_COUNT;
-
if (sjcd_open_count == 0) {
int s, sjcd_open_tries;
/* We don't know that, do we? */
return (0);
err_out:
- MOD_DEC_USE_COUNT;
return (-EIO);
}
#if defined( SJCD_TRACE )
printk("SJCD: release\n");
-#endif
-#ifdef MODULE
- MOD_DEC_USE_COUNT;
#endif
if (--sjcd_open_count == 0) {
sjcd_invalidate_buffers();
* A list of file operations allowed for this cdrom.
*/
static struct block_device_operations sjcd_fops = {
+ owner:THIS_MODULE,
open:sjcd_open,
release:sjcd_release,
ioctl:sjcd_ioctl,
if (check_drive_status() != 0)
return -EIO;
sony_inuse = 1;
- MOD_INC_USE_COUNT;
if (spin_up_drive(status) != 0) {
printk(CDU535_MESSAGE_NAME " error 0x%.2x (cdu_open, spin up)\n",
status[0]);
sony_inuse = 0;
- MOD_DEC_USE_COUNT;
return -EIO;
}
sony_get_toc();
cmd_buff[0] = SONY535_SPIN_DOWN;
do_sony_cmd(cmd_buff, 1, status, NULL, 0, 0);
sony_inuse = 0;
- MOD_DEC_USE_COUNT;
return -EIO;
}
if (inode) {
Byte status[2], cmd_no;
sony_inuse = 0;
- MOD_DEC_USE_COUNT;
if (0 < sony_usage) {
sony_usage--;
return 0;
}
-
static struct block_device_operations cdu_fops =
{
+ owner: THIS_MODULE,
open: cdu_open,
release: cdu_release,
ioctl: cdu_ioctl,
source drivers/char/pcmcia/Config.in
fi
-tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
+if [ "$CONFIG_X86" = "y" ]; then
+ tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
+fi
endmenu
"PCI2000PFB"
};
+static struct pci_device_id applicom_pci_tbl[] = {
+ { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCIGENERIC,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000PFB,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { 0 }
+};
+MODULE_DEVICE_TABLE(pci, applicom_pci_tbl);
+
MODULE_AUTHOR("David Woodhouse & Applicom International");
MODULE_DESCRIPTION("Driver for Applicom Profibus card");
MODULE_LICENSE("GPL");
}
/* We may not have actually slept */
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
remove_wait_queue(&apbs[IndexCard].FlagSleepSend, &wait);
writeb(1, apbs[IndexCard].RamIO + DATA_FROM_PC_READY);
--- /dev/null
+/*
+ * Eurotech CPU-1220/1410 on board WDT driver for Linux 2.4.x
+ *
+ * (c) Copyright 2001 Ascensit <support@ascensit.com>
+ * (c) Copyright 2001 Rodolfo Giometti <giometti@ascensit.com>
+ *
+ * Based on wdt.c.
+ * Original copyright messages:
+ *
+ * (c) Copyright 1996-1997 Alan Cox <alan@redhat.com>, All Rights Reserved.
+ * http://www.redhat.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
+ * warranty for any of this software. This material is provided
+ * "AS-IS" and at no charge.
+ *
+ * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>*
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/smp_lock.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/fcntl.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/smp_lock.h>
+
+static int eurwdt_is_open;
+static int eurwdt_timeout;
+static spinlock_t eurwdt_lock;
+
+/*
+ * You must set these - there is no sane way to probe for this board.
+ * You can use wdt=x,y to set these now.
+ */
+
+static int io = 0x3f0;
+static int irq = 10;
+static char *ev = "int";
+
+#define WDT_TIMEOUT 60 /* 1 minute */
+
+
+/*
+ * Some symbolic names
+ */
+
+#define WDT_CTRL_REG 0x30
+#define WDT_OUTPIN_CFG 0xe2
+ #define WDT_EVENT_INT 0x00
+ #define WDT_EVENT_REBOOT 0x08
+#define WDT_UNIT_SEL 0xf1
+ #define WDT_UNIT_SECS 0x80
+#define WDT_TIMEOUT_VAL 0xf2
+#define WDT_TIMER_CFG 0xf3
+
+
+#ifndef MODULE
+
+/**
+ * eurwdt_setup:
+ * @str: command line string
+ *
+ * Setup options. The board isn't really probe-able so we have to
+ * get the user to tell us the configuration. Sane people build it
+ * modular but the others come here.
+ */
+
+static int __init eurwdt_setup(char *str)
+{
+ int ints[4];
+
+ str = get_options (str, ARRAY_SIZE(ints), ints);
+
+ if (ints[0] > 0) {
+ io = ints[1];
+ if (ints[0] > 1)
+ irq = ints[2];
+ }
+
+ return 1;
+}
+
+__setup("wdt=", eurwdt_setup);
+
+#endif /* !MODULE */
+
+MODULE_PARM(io, "i");
+MODULE_PARM_DESC(io, "Eurotech WDT io port (default=0x3f0)");
+MODULE_PARM(irq, "i");
+MODULE_PARM_DESC(irq, "Eurotech WDT irq (default=10)");
+MODULE_PARM(ev, "s");
+MODULE_PARM_DESC(ev, "Eurotech WDT event type (default is `reboot')");
+
+
+/*
+ * Programming support
+ */
+
+static inline void eurwdt_write_reg(u8 index, u8 data)
+{
+ outb(index, io);
+ outb(data, io+1);
+}
+
+static inline void eurwdt_lock_chip(void)
+{
+ outb(0xaa, io);
+}
+
+static inline void eurwdt_unlock_chip(void)
+{
+ outb(0x55, io);
+ eurwdt_write_reg(0x07, 0x08); /* set the logical device */
+}
+
+static inline void eurwdt_set_timeout(int timeout)
+{
+ eurwdt_write_reg(WDT_TIMEOUT_VAL, (u8) timeout);
+}
+
+static inline void eurwdt_disable_timer(void)
+{
+ eurwdt_set_timeout(0);
+}
+
+static void eurwdt_activate_timer(void)
+{
+ eurwdt_disable_timer();
+ eurwdt_write_reg(WDT_CTRL_REG, 0x01); /* activate the WDT */
+ eurwdt_write_reg(WDT_OUTPIN_CFG, !strcmp("int", ev) ?
+ WDT_EVENT_INT : WDT_EVENT_REBOOT);
+ /* Setting interrupt line */
+ if (irq == 2 || irq > 15 || irq < 0) {
+ printk(KERN_ERR ": invalid irq number\n");
+ irq = 0; /* if invalid we disable interrupt */
+ }
+ if (irq == 0)
+ printk(KERN_INFO ": interrupt disabled\n");
+ eurwdt_write_reg(WDT_TIMER_CFG, irq<<4);
+
+ eurwdt_write_reg(WDT_UNIT_SEL, WDT_UNIT_SECS); /* we use seconds */
+ eurwdt_set_timeout(0); /* the default timeout */
+}
+
+
+/*
+ * Kernel methods.
+ */
+
+void eurwdt_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ printk(KERN_CRIT "timeout WDT timeout\n");
+
+#ifdef ONLY_TESTING
+ printk(KERN_CRIT "Would Reboot.\n");
+#else
+ printk(KERN_CRIT "Initiating system reboot.\n");
+ machine_restart(NULL);
+#endif
+}
+
+
+/**
+ * eurwdt_ping:
+ *
+ * Reload counter one with the watchdog timeout.
+ */
+
+static void eurwdt_ping(void)
+{
+ /* Write the watchdog default value */
+ eurwdt_set_timeout(eurwdt_timeout);
+}
+
+/**
+ * eurwdt_write:
+ * @file: file handle to the watchdog
+ * @buf: buffer to write (unused as data does not matter here
+ * @count: count of bytes
+ * @ppos: pointer to the position to write. No seeks allowed
+ *
+ * A write to a watchdog device is defined as a keepalive signal. Any
+ * write of data will do, as we we don't define content meaning.
+ */
+
+static ssize_t eurwdt_write(struct file *file, const char *buf, size_t count,
+loff_t *ppos)
+{
+ /* Can't seek (pwrite) on this device */
+ if (ppos != &file->f_pos)
+ return -ESPIPE;
+
+ if (count) {
+ eurwdt_ping(); /* the default timeout */
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * eurwdt_ioctl:
+ * @inode: inode of the device
+ * @file: file handle to the device
+ * @cmd: watchdog command
+ * @arg: argument pointer
+ *
+ * The watchdog API defines a common set of functions for all watchdogs
+ * according to their available features.
+ */
+
+static int eurwdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ static struct watchdog_info ident = {
+ options : WDIOF_CARDRESET,
+ firmware_version : 1,
+ identity : "WDT Eurotech CPU-1220/1410"
+ };
+
+ int time;
+
+ switch(cmd) {
+ default:
+ return -ENOTTY;
+
+ case WDIOC_GETSUPPORT:
+ return copy_to_user((struct watchdog_info *)arg, &ident,
+ sizeof(ident)) ? -EFAULT : 0;
+
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, (int *) arg);
+
+ case WDIOC_KEEPALIVE:
+ eurwdt_ping();
+ return 0;
+
+ case WDIOC_SETTIMEOUT:
+ if (copy_from_user(&time, (int *) arg, sizeof(int)))
+ return -EFAULT;
+
+ /* Sanity check */
+ if (time < 0 || time > 255)
+ return -EINVAL;
+
+ eurwdt_timeout = time;
+ eurwdt_set_timeout(time);
+ return 0;
+ }
+}
+
+/**
+ * eurwdt_open:
+ * @inode: inode of device
+ * @file: file handle to device
+ *
+ * The misc device has been opened. The watchdog device is single
+ * open and on opening we load the counter.
+ */
+
+static int eurwdt_open(struct inode *inode, struct file *file)
+{
+ switch (MINOR(inode->i_rdev)) {
+ case WATCHDOG_MINOR:
+ spin_lock(&eurwdt_lock);
+ if (eurwdt_is_open) {
+ spin_unlock(&eurwdt_lock);
+ return -EBUSY;
+ }
+
+ eurwdt_is_open = 1;
+ eurwdt_timeout = WDT_TIMEOUT; /* initial timeout */
+
+ /* Activate the WDT */
+ eurwdt_activate_timer();
+
+ spin_unlock(&eurwdt_lock);
+
+ MOD_INC_USE_COUNT;
+
+ return 0;
+
+ case TEMP_MINOR:
+ return 0;
+
+ default:
+ return -ENODEV;
+ }
+}
+
+/**
+ * eurwdt_release:
+ * @inode: inode to board
+ * @file: file handle to board
+ *
+ * The watchdog has a configurable API. There is a religious dispute
+ * between people who want their watchdog to be able to shut down and
+ * those who want to be sure if the watchdog manager dies the machine
+ * reboots. In the former case we disable the counters, in the latter
+ * case you have to open it again very soon.
+ */
+
+static int eurwdt_release(struct inode *inode, struct file *file)
+{
+ if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) {
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+ eurwdt_disable_timer();
+#endif
+ eurwdt_is_open = 0;
+
+ MOD_DEC_USE_COUNT;
+ }
+
+ return 0;
+}
+
+/**
+ * eurwdt_notify_sys:
+ * @this: our notifier block
+ * @code: the event being reported
+ * @unused: unused
+ *
+ * Our notifier is called on system shutdowns. We want to turn the card
+ * off at reboot otherwise the machine will reboot again during memory
+ * test or worse yet during the following fsck. This would suck, in fact
+ * trust me - if it happens it does suck.
+ */
+
+static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code,
+ void *unused)
+{
+ if (code == SYS_DOWN || code == SYS_HALT) {
+ /* Turn the card off */
+ eurwdt_disable_timer();
+ }
+
+ return NOTIFY_DONE;
+}
+
+/*
+ * Kernel Interfaces
+ */
+
+
+static struct file_operations eurwdt_fops = {
+ owner: THIS_MODULE,
+ llseek: no_llseek,
+ write: eurwdt_write,
+ ioctl: eurwdt_ioctl,
+ open: eurwdt_open,
+ release: eurwdt_release,
+};
+
+static struct miscdevice eurwdt_miscdev =
+{
+ WATCHDOG_MINOR,
+ "watchdog",
+ &eurwdt_fops
+};
+
+/*
+ * The WDT card needs to learn about soft shutdowns in order to
+ * turn the timebomb registers off.
+ */
+
+static struct notifier_block eurwdt_notifier =
+{
+ eurwdt_notify_sys,
+ NULL,
+ 0
+};
+
+/**
+ * cleanup_module:
+ *
+ * Unload the watchdog. You cannot do this with any file handles open.
+ * If your watchdog is set to continue ticking on close and you unload
+ * it, well it keeps ticking. We won't get the interrupt but the board
+ * will not touch PC memory so all is fine. You just have to load a new
+ * module in 60 seconds or reboot.
+ */
+
+static void __exit eurwdt_exit(void)
+{
+ eurwdt_lock_chip();
+
+ misc_deregister(&eurwdt_miscdev);
+
+ unregister_reboot_notifier(&eurwdt_notifier);
+ release_region(io, 2);
+ free_irq(irq, NULL);
+}
+
+/**
+ * eurwdt_init:
+ *
+ * Set up the WDT watchdog board. After grabbing the resources
+ * we require we need also to unlock the device.
+ * The open() function will actually kick the board off.
+ */
+
+static int __init eurwdt_init(void)
+{
+ int ret;
+
+ ret = misc_register(&eurwdt_miscdev);
+ if (ret) {
+ printk(KERN_ERR "eurwdt: can't misc_register on minor=%d\n",
+ WATCHDOG_MINOR);
+ goto out;
+ }
+
+ ret = request_irq(irq, eurwdt_interrupt, SA_INTERRUPT, "eurwdt", NULL);
+ if(ret) {
+ printk(KERN_ERR "eurwdt: IRQ %d is not free.\n", irq);
+ goto outmisc;
+ }
+
+ if (!request_region(io, 2, "eurwdt")) {
+ printk(KERN_ERR "eurwdt: IO %X is not free.\n", io);
+ ret = -EBUSY;
+ goto outirq;
+ }
+
+ ret = register_reboot_notifier(&eurwdt_notifier);
+ if (ret) {
+ printk(KERN_ERR "eurwdt: can't register reboot notifier (err=%d)\n", ret);
+ goto outreg;
+ }
+
+ eurwdt_unlock_chip();
+
+ ret = 0;
+ printk(KERN_INFO "Eurotech WDT driver 0.01 at %X (Interrupt %d)"
+ " - timeout event: %s\n",
+ io, irq, (!strcmp("int", ev) ? "int" : "reboot"));
+
+ spin_lock_init(&eurwdt_lock);
+
+ out:
+ return ret;
+
+ outreg:
+ release_region(io, 2);
+
+ outirq:
+ free_irq(irq, NULL);
+
+ outmisc:
+ misc_deregister(&eurwdt_miscdev);
+ goto out;
+}
+
+module_init(eurwdt_init);
+module_exit(eurwdt_exit);
+
+MODULE_AUTHOR("Rodolfo Giometti");
+MODULE_DESCRIPTION("Driver for Eurotech CPU-1220/1410 on board watchdog");
+MODULE_LICENSE("GPL");
+EXPORT_NO_SYMBOLS;
#endif
#endif
+static struct pci_device_id istallion_pci_tbl[] = {
+ { PCI_VENDOR_ID_STALLION, PCI_DEVICE_ID_ECRA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { 0 }
+};
+MODULE_DEVICE_TABLE(pci, istallion_pci_tbl);
+
/*****************************************************************************/
/*
printk("stli_delay(len=%d)\n", len);
#endif
if (len > 0) {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(len);
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
}
}
#define DELTA(x,y) ((y)-(x))
#define TIME_NAME "TSC"
#elif __alpha__
-#define GET_TIME(x) get_cycles(x)
+#define GET_TIME(x) ((x) = get_cycles())
#define DELTA(x,y) ((y)-(x))
#define TIME_NAME "PCC"
#else
"CP-204J series",
};
-typedef struct {
- unsigned short vendor_id;
- unsigned short device_id;
- unsigned short board_type;
-} moxa_pciinfo;
-
-static moxa_pciinfo moxa_pcibrds[] =
-{
- {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C218, MOXA_BOARD_C218_PCI},
- {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C320, MOXA_BOARD_C320_PCI},
- {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_CP204J, MOXA_BOARD_CP204J},
+static struct pci_device_id moxa_pcibrds[] = {
+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C218, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, MOXA_BOARD_C218_PCI },
+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C320, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, MOXA_BOARD_C320_PCI },
+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_CP204J, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, MOXA_BOARD_CP204J },
+ { 0 }
};
+MODULE_DEVICE_TABLE(pci, moxa_pcibrds);
typedef struct _moxa_isa_board_conf {
int boardType;
#ifdef CONFIG_PCI
{
struct pci_dev *p = NULL;
- n = sizeof(moxa_pcibrds) / sizeof(moxa_pciinfo);
+ n = (sizeof(moxa_pcibrds) / sizeof(moxa_pcibrds[0])) - 1;
i = 0;
while (i < n) {
- while((p = pci_find_device(moxa_pcibrds[i].vendor_id, moxa_pcibrds[i].device_id, p))!=NULL)
+ while ((p = pci_find_device(moxa_pcibrds[i].vendor, moxa_pcibrds[i].device, p))!=NULL)
{
if (pci_enable_device(p))
continue;
if (verbose)
printk("More than %d MOXA Intellio family boards found. Board is ignored.", MAX_BOARDS);
} else {
- moxa_get_PCI_conf(p, moxa_pcibrds[i].board_type,
+ moxa_get_PCI_conf(p, moxa_pcibrds[i].driver_data,
&moxa_boards[numBoards]);
numBoards++;
}
ch->tty = 0;
if (ch->blocked_open) {
if (ch->close_delay) {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(ch->close_delay);
}
wake_up_interruptible(&ch->open_wait);
restore_flags(flags);
ch->blocked_open++;
while (1) {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
if (tty_hung_up_p(filp) ||
!(ch->asyncflags & ASYNC_INITIALIZED)) {
#ifdef SERIAL_DO_RESTART
}
schedule();
}
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
remove_wait_queue(&ch->open_wait, &wait);
if (!tty_hung_up_p(filp))
ch->count++;
#define MOXA_GET_CUMAJOR (MOXA + 64)
#define MOXA_GETMSTATUS (MOXA + 65)
-typedef struct {
- unsigned short vendor_id;
- unsigned short device_id;
- unsigned short board_type;
-} mxser_pciinfo;
-
-static mxser_pciinfo mxser_pcibrds[] =
-{
- {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C168, MXSER_BOARD_C168_PCI},
- {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C104, MXSER_BOARD_C104_PCI},
+static struct pci_device_id mxser_pcibrds[] = {
+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C168, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ MXSER_BOARD_C168_PCI },
+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_C104, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ MXSER_BOARD_C104_PCI },
+ { 0 }
};
+MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
static int ioaddr[MXSER_BOARDS];
static int ttymajor = MXSERMAJOR;
{
struct pci_dev *pdev = NULL;
- n = sizeof(mxser_pcibrds) / sizeof(mxser_pciinfo);
+ n = (sizeof(mxser_pcibrds) / sizeof(mxser_pcibrds[0])) - 1;
index = 0;
for (b = 0; b < n; b++) {
- pdev = pci_find_device(mxser_pcibrds[b].vendor_id,
- mxser_pcibrds[b].device_id, pdev);
+ pdev = pci_find_device(mxser_pcibrds[b].vendor,
+ mxser_pcibrds[b].device, pdev);
if (!pdev || pci_enable_device(pdev))
continue;
hwconf.pdev = pdev;
printk("Found MOXA %s board(BusNo=%d,DevNo=%d)\n",
- mxser_brdname[mxser_pcibrds[b].board_type],
+ mxser_brdname[mxser_pcibrds[b].driver_data],
pdev->bus->number, PCI_SLOT(pdev->devfn));
if (m >= MXSER_BOARDS) {
printk("Too many Smartio family boards found (maximum %d),board not configured\n", MXSER_BOARDS);
} else {
retval = mxser_get_PCI_conf(pdev,
- mxser_pcibrds[b].board_type, &hwconf);
+ mxser_pcibrds[b].driver_data, &hwconf);
if (retval < 0) {
if (retval == MXSER_ERR_IRQ)
printk("Invalid interrupt number,board not configured\n");
*/
timeout = jiffies + HZ;
while (!(inb(info->base + UART_LSR) & UART_LSR_TEMT)) {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(5);
if (jiffies > timeout)
break;
info->tty = 0;
if (info->blocked_open) {
if (info->close_delay) {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(info->close_delay);
}
wake_up_interruptible(&info->open_wait);
outb(inb(info->base + UART_MCR) | UART_MCR_DTR | UART_MCR_RTS,
info->base + UART_MCR);
restore_flags(flags);
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)) {
#ifdef SERIAL_DO_RESTART
if (info->flags & ASYNC_HUP_NOTIFY)
}
schedule();
}
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
remove_wait_queue(&info->open_wait, &wait);
if (!tty_hung_up_p(filp))
info->count++;
unsigned long flags;
if (!info->base)
return;
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
save_flags(flags);
cli();
outb(inb(info->base + UART_LCR) | UART_LCR_SBC, info->base + UART_LCR);
#include <linux/compatmac.h>
#include <linux/generic_serial.h>
+#if BITS_PER_LONG != 32
+# error FIXME: this driver only works on 32-bit platforms
+#endif
#include "linux_compat.h"
#include "typdef.h"
static int ataraid_readahead[256];
static struct block_device_operations ataraid_fops = {
+ owner: THIS_MODULE,
open: ataraid_open,
release: ataraid_release,
ioctl: ataraid_ioctl,
int ataraid_get_device(struct raid_device_operations *fops)
{
int bit;
- MOD_INC_USE_COUNT;
down(&ataraid_sem);
if (ataraiduse==~0U) {
up(&ataraid_sem);
- MOD_DEC_USE_COUNT;
return -ENODEV;
}
bit=ffz(ataraiduse);
ataraiduse &= ~(1<<device);
ataraid_ops[device] = NULL;
up(&ataraid_sem);
- MOD_DEC_USE_COUNT;
}
void ataraid_register_disk(int device,long size)
/*
- * linux/drivers/ide/buddha.c -- Amiga Buddha and Catweasel IDE Driver
+ * linux/drivers/ide/buddha.c -- Amiga Buddha, Catweasel and X-Surf IDE Driver
*
* Copyright (C) 1997 by Geert Uytterhoeven
*
- * This driver was written by based on the specifications in README.buddha.
+ * This driver was written by based on the specifications in README.buddha and
+ * the X-Surf info from Inside_XSurf.txt available at
+ * http://www.jschoenfeld.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
/*
- * The Buddha has 2 IDE interfaces, the Catweasel has 3
+ * The Buddha has 2 IDE interfaces, the Catweasel has 3, X-Surf has 2
*/
#define BUDDHA_NUM_HWIFS 2
#define CATWEASEL_NUM_HWIFS 3
-
+#define XSURF_NUM_HWIFS 2
/*
* Bases of the IDE interfaces (relative to the board address)
#define BUDDHA_BASE2 0xa00
#define BUDDHA_BASE3 0xc00
+#define XSURF_BASE1 0xb000 /* 2.5" Interface */
+#define XSURF_BASE2 0xd000 /* 3.5" Interface */
+
static u_int buddha_bases[CATWEASEL_NUM_HWIFS] __initdata = {
BUDDHA_BASE1, BUDDHA_BASE2, BUDDHA_BASE3
};
+static const u_int xsurf_bases[XSURF_NUM_HWIFS] __initdata = {
+ XSURF_BASE1, XSURF_BASE2
+};
+
/*
* Offsets from one of the above bases
#define BUDDHA_SELECT 0x1a /* 101dhhhh , d=drive, hhhh=head */
#define BUDDHA_STATUS 0x1e /* see status-bits */
#define BUDDHA_CONTROL 0x11a
+#define XSURF_CONTROL -1 /* X-Surf has no CS1* (Control/AltStat) */
static int buddha_offsets[IDE_NR_PORTS] __initdata = {
BUDDHA_DATA, BUDDHA_ERROR, BUDDHA_NSECTOR, BUDDHA_SECTOR, BUDDHA_LCYL,
- BUDDHA_HCYL, BUDDHA_SELECT, BUDDHA_STATUS, BUDDHA_CONTROL
+ BUDDHA_HCYL, BUDDHA_SELECT, BUDDHA_STATUS, BUDDHA_CONTROL, -1
};
+static int xsurf_offsets[IDE_NR_PORTS] __initdata = {
+ BUDDHA_DATA, BUDDHA_ERROR, BUDDHA_NSECTOR, BUDDHA_SECTOR, BUDDHA_LCYL,
+ BUDDHA_HCYL, BUDDHA_SELECT, BUDDHA_STATUS, XSURF_CONTROL, -1
+};
/*
* Other registers
#define BUDDHA_IRQ2 0xf40 /* interrupt */
#define BUDDHA_IRQ3 0xf80
+#define XSURF_IRQ1 0x7e
+#define XSURF_IRQ2 0x7e
+
static int buddha_irqports[CATWEASEL_NUM_HWIFS] __initdata = {
BUDDHA_IRQ1, BUDDHA_IRQ2, BUDDHA_IRQ3
};
+static const int xsurf_irqports[XSURF_NUM_HWIFS] __initdata = {
+ XSURF_IRQ1, XSURF_IRQ2
+};
+
#define BUDDHA_IRQ_MR 0xfc0 /* master interrupt enable */
* Board information
*/
-static u_long buddha_board;
-static int buddha_num_hwifs = -1;
+enum BuddhaType_Enum {BOARD_BUDDHA, BOARD_CATWEASEL, BOARD_XSURF};
+typedef enum BuddhaType_Enum BuddhaType;
/*
{
unsigned char ch;
- ch = inb(hwif->io_ports[IDE_IRQ_OFFSET]);
+ ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
if (!(ch & 0x80))
- return 0;
+ return 0;
return 1;
}
-
- /*
- * Any Buddha or Catweasel boards present?
- */
-
-static int __init find_buddha(void)
+static int xsurf_ack_intr(ide_hwif_t *hwif)
{
- struct zorro_dev *z = NULL;
-
- buddha_num_hwifs = 0;
- while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
- unsigned long board;
- if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA)
- buddha_num_hwifs = BUDDHA_NUM_HWIFS;
- else if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL)
- buddha_num_hwifs = CATWEASEL_NUM_HWIFS;
- else
- continue;
- board = z->resource.start;
- if (!request_mem_region(board+BUDDHA_BASE1, 0x800, "IDE"))
- continue;
- buddha_board = ZTWO_VADDR(board);
- /* write to BUDDHA_IRQ_MR to enable the board IRQ */
- *(char *)(buddha_board+BUDDHA_IRQ_MR) = 0;
- break;
- }
- return buddha_num_hwifs;
-}
+ unsigned char ch;
+ ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
+ /* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */
+ z_writeb(0, hwif->io_ports[IDE_IRQ_OFFSET]);
+ if (!(ch & 0x80))
+ return 0;
+ return 1;
+}
/*
* Probe for a Buddha or Catweasel IDE interface
- * We support only _one_ of them, no multiple boards!
*/
void __init buddha_init(void)
{
- hw_regs_t hw;
- int i, index;
-
- if (buddha_num_hwifs < 0 && !find_buddha())
- return;
-
- for (i = 0; i < buddha_num_hwifs; i++) {
- ide_setup_ports(&hw, (ide_ioreg_t)(buddha_board+buddha_bases[i]),
- buddha_offsets, 0,
- (ide_ioreg_t)(buddha_board+buddha_irqports[i]),
- buddha_ack_intr, IRQ_AMIGA_PORTS);
- index = ide_register_hw(&hw, NULL);
- if (index != -1)
- printk("ide%d: %s IDE interface\n", index,
- buddha_num_hwifs == BUDDHA_NUM_HWIFS ? "Buddha" :
- "Catweasel");
- }
+ hw_regs_t hw;
+ int i, index;
+
+ struct zorro_dev *z = NULL;
+ u_long buddha_board = 0;
+ BuddhaType type;
+ int buddha_num_hwifs;
+
+ while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
+ unsigned long board;
+ if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA) {
+ buddha_num_hwifs = BUDDHA_NUM_HWIFS;
+ type=BOARD_BUDDHA;
+ } else if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL) {
+ buddha_num_hwifs = CATWEASEL_NUM_HWIFS;
+ type=BOARD_CATWEASEL;
+ } else if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF) {
+ buddha_num_hwifs = XSURF_NUM_HWIFS;
+ type=BOARD_XSURF;
+ } else
+ continue;
+
+ board = z->resource.start;
+
+ if(type != BOARD_XSURF) {
+ if (!request_mem_region(board+BUDDHA_BASE1, 0x800, "IDE"))
+ continue;
+ } else {
+ if (!request_mem_region(board+XSURF_BASE1, 0x1000, "IDE"))
+ continue;
+ if (!request_mem_region(board+XSURF_BASE2, 0x1000, "IDE"))
+ continue;
+ if (!request_mem_region(board+XSURF_IRQ1, 0x8, "IDE"))
+ continue;
+ }
+ buddha_board = ZTWO_VADDR(board);
+
+ /* write to BUDDHA_IRQ_MR to enable the board IRQ */
+ /* X-Surf doesn't have this. IRQs are always on */
+ if(type != BOARD_XSURF) *(char *)(buddha_board+BUDDHA_IRQ_MR) = 0;
+
+ for(i=0;i<buddha_num_hwifs;i++) {
+ if(type != BOARD_XSURF) {
+ ide_setup_ports(&hw, (ide_ioreg_t)(buddha_board+buddha_bases[i]),
+ buddha_offsets, 0,
+ (ide_ioreg_t)(buddha_board+buddha_irqports[i]),
+ buddha_ack_intr, IRQ_AMIGA_PORTS);
+ } else {
+ ide_setup_ports(&hw, (ide_ioreg_t)(buddha_board+xsurf_bases[i]),
+ xsurf_offsets, 0,
+ (ide_ioreg_t)(buddha_board+xsurf_irqports[i]),
+ xsurf_ack_intr, IRQ_AMIGA_PORTS);
+ }
+
+ index = ide_register_hw(&hw, NULL);
+ if (index != -1) {
+ printk("ide%d: ", index);
+ switch(type) {
+ case BOARD_BUDDHA:
+ printk("Buddha");
+ break;
+ case BOARD_CATWEASEL:
+ printk("Catweasel");
+ break;
+ case BOARD_XSURF:
+ printk("X-Surf");
+ break;
+ }
+ printk(" IDE interface\n");
+ }
+ }
+ }
}
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
-
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/ide.h>
#include <linux/init.h>
+#include <asm/setup.h>
#include <asm/atarihw.h>
#include <asm/atariints.h>
#include <asm/atari_stdma.h>
#define ATA_HD_STATUS 0x1d /* see status-bits */
#define ATA_HD_CONTROL 0x39
-static int __init falconide_offsets[IDE_NR_PORTS] = {
+static int falconide_offsets[IDE_NR_PORTS] __initdata = {
ATA_HD_DATA, ATA_HD_ERROR, ATA_HD_NSECTOR, ATA_HD_SECTOR, ATA_HD_LCYL,
ATA_HD_HCYL, ATA_HD_SELECT, ATA_HD_STATUS, ATA_HD_CONTROL, -1
};
return icside_config_if(drive, speed);
}
+/*
+ * dma_intr() is the handler for disk read/write DMA interrupts
+ */
+static ide_startstop_t icside_dmaintr(ide_drive_t *drive)
+{
+ int i;
+ byte stat, dma_stat;
+
+ dma_stat = HWIF(drive)->dmaproc(ide_dma_end, drive);
+ stat = GET_STAT(); /* get drive status */
+ if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
+ if (!dma_stat) {
+ struct request *rq = HWGROUP(drive)->rq;
+ rq = HWGROUP(drive)->rq;
+ for (i = rq->nr_sectors; i > 0;) {
+ i -= rq->current_nr_sectors;
+ ide_end_request(1, HWGROUP(drive));
+ }
+ return ide_stopped;
+ }
+ printk("%s: dma_intr: bad DMA status (dma_stat=%x)\n",
+ drive->name, dma_stat);
+ }
+ return ide_error(drive, "dma_intr", stat);
+}
+
+/*
+ * The following is a sick duplication from ide-dma.c ;(
+ *
+ * This should be defined in one place only.
+ */
+struct drive_list_entry {
+ char * id_model;
+ char * id_firmware;
+};
+
+static struct drive_list_entry drive_whitelist [] = {
+ { "Micropolis 2112A", "ALL" },
+ { "CONNER CTMA 4000", "ALL" },
+ { "CONNER CTT8000-A", "ALL" },
+ { "ST34342A", "ALL" },
+ { NULL, 0 }
+};
+
+static struct drive_list_entry drive_blacklist [] = {
+ { "WDC AC11000H", "ALL" },
+ { "WDC AC22100H", "ALL" },
+ { "WDC AC32500H", "ALL" },
+ { "WDC AC33100H", "ALL" },
+ { "WDC AC31600H", "ALL" },
+ { "WDC AC32100H", "24.09P07" },
+ { "WDC AC23200L", "21.10N21" },
+ { "Compaq CRD-8241B", "ALL" },
+ { "CRD-8400B", "ALL" },
+ { "CRD-8480B", "ALL" },
+ { "CRD-8480C", "ALL" },
+ { "CRD-8482B", "ALL" },
+ { "CRD-84", "ALL" },
+ { "SanDisk SDP3B", "ALL" },
+ { "SanDisk SDP3B-64", "ALL" },
+ { "SANYO CD-ROM CRD", "ALL" },
+ { "HITACHI CDR-8", "ALL" },
+ { "HITACHI CDR-8335", "ALL" },
+ { "HITACHI CDR-8435", "ALL" },
+ { "Toshiba CD-ROM XM-6202B", "ALL" },
+ { "CD-532E-A", "ALL" },
+ { "E-IDE CD-ROM CR-840", "ALL" },
+ { "CD-ROM Drive/F5A", "ALL" },
+ { "RICOH CD-R/RW MP7083A", "ALL" },
+ { "WPI CDD-820", "ALL" },
+ { "SAMSUNG CD-ROM SC-148C", "ALL" },
+ { "SAMSUNG CD-ROM SC-148F", "ALL" },
+ { "SAMSUNG CD-ROM SC", "ALL" },
+ { "SanDisk SDP3B-64", "ALL" },
+ { "SAMSUNG CD-ROM SN-124", "ALL" },
+ { "PLEXTOR CD-R PX-W8432T", "ALL" },
+ { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
+ { "_NEC DV5800A", "ALL" },
+ { NULL, 0 }
+};
+
+static int in_drive_list(struct hd_driveid *id, struct drive_list_entry * drive_table)
+{
+ for ( ; drive_table->id_model ; drive_table++)
+ if ((!strcmp(drive_table->id_model, id->model)) &&
+ ((!strstr(drive_table->id_firmware, id->fw_rev)) ||
+ (!strcmp(drive_table->id_firmware, "ALL"))))
+ return 1;
+ return 0;
+}
+
+/*
+ * For both Blacklisted and Whitelisted drives.
+ * This is setup to be called as an extern for future support
+ * to other special driver code.
+ */
+static int check_drive_lists(ide_drive_t *drive, int good_bad)
+{
+ struct hd_driveid *id = drive->id;
+
+ if (good_bad) {
+ return in_drive_list(id, drive_whitelist);
+ } else {
+ int blacklist = in_drive_list(id, drive_blacklist);
+ if (blacklist)
+ printk("%s: Disabling DMA for %s\n", drive->name, id->model);
+ return(blacklist);
+ }
+ return 0;
+}
+
static int
icside_dma_check(ide_drive_t *drive)
{
/*
* Consult the list of known "bad" drives
*/
- if (ide_dmaproc(ide_dma_bad_drive, drive)) {
+ if (check_drive_lists(drive, 0)) {
func = ide_dma_off;
goto out;
}
/*
* Consult the list of known "good" drives
*/
- if (ide_dmaproc(ide_dma_good_drive, drive)) {
+ if (check_drive_lists(drive, 1)) {
if (id->eide_dma_time > 150)
goto out;
xfer_mode = XFER_MW_DMA_1;
return hwif->dmaproc(func, drive);
}
+static int
+icside_dma_verbose(ide_drive_t *drive)
+{
+ printk(", DMA");
+ return 1;
+}
+
static int
icside_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
{
int count, reading = 0;
switch (func) {
+ case ide_dma_off:
+ printk("%s: DMA disabled\n", drive->name);
+ /*FALLTHROUGH*/
+
+ case ide_dma_off_quietly:
+ case ide_dma_on:
+ drive->using_dma = (func == ide_dma_on);
+ return 0;
+
case ide_dma_check:
return icside_dma_check(drive);
if (drive->media != ide_disk)
return 0;
- ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
+ ide_set_handler(drive, &icside_dmaintr, WAIT_CMD, NULL);
OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA,
IDE_COMMAND_REG);
case ide_dma_test_irq:
return inb((unsigned long)hwif->hw.priv) & 1;
+ case ide_dma_bad_drive:
+ case ide_dma_good_drive:
+ return check_drive_lists(drive, (func == ide_dma_good_drive));
+
+ case ide_dma_verbose:
+ return icside_dma_verbose(drive);
+
+ case ide_dma_timeout:
default:
- return ide_dmaproc(func, drive);
+ printk("icside_dmaproc: unsupported %s func: %d\n",
+ ide_dmafunc_verbose(func), func);
}
+ return 1;
}
static int
for (index = 0; index < MAX_HWIFS; ++index) {
hwif = &ide_hwifs[index];
- if (hwif->hw.io_ports[IDE_DATA_OFFSET] == (ide_ioreg_t)dataport)
+ if (hwif->io_ports[IDE_DATA_OFFSET] == (ide_ioreg_t)dataport)
goto found;
}
for (index = 0; index < MAX_HWIFS; ++index) {
hwif = &ide_hwifs[index];
- if (!hwif->hw.io_ports[IDE_DATA_OFFSET])
+ if (!hwif->io_ports[IDE_DATA_OFFSET])
goto found;
}
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hwif->hw.io_ports[i] = (ide_ioreg_t)port;
+ hwif->io_ports[i] = (ide_ioreg_t)port;
port += 1 << info->stepping;
}
hwif->hw.io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
+ hwif->io_ports[IDE_CONTROL_OFFSET] = base + info->ctrloffset;
hwif->hw.irq = irq;
+ hwif->irq = irq;
hwif->hw.dma = NO_DMA;
hwif->noprobe = 0;
hwif->chipset = ide_acorn;
icside_setup_dma(mate, autodma);
}
}
-#endif
-
no_dma:
+#endif
return hwif || mate ? 0 : -1;
}
#define DEVID_PIIX4NX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX})
#define DEVID_PIIX4U3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9})
#define DEVID_PIIX4U4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8})
+#define DEVID_PIIX4U5 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10})
#define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
#define DEVID_MR_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1})
#define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
{DEVID_PIIX4NX, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4U3, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4U4, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
+ {DEVID_PIIX4U5, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_MR_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
{DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
static int ide_open (struct inode * inode, struct file * filp)
{
ide_drive_t *drive;
- int rc;
if ((drive = get_info_ptr(inode->i_rdev)) == NULL)
return -ENXIO;
- MOD_INC_USE_COUNT;
if (drive->driver == NULL)
ide_driver_module();
#ifdef CONFIG_KMOD
while (drive->busy)
sleep_on(&drive->wqueue);
drive->usage++;
- if (drive->driver != NULL) {
- if ((rc = DRIVER(drive)->open(inode, filp, drive)))
- MOD_DEC_USE_COUNT;
- return rc;
- }
+ if (drive->driver != NULL)
+ return DRIVER(drive)->open(inode, filp, drive);
printk ("%s: driver not present\n", drive->name);
drive->usage--;
- MOD_DEC_USE_COUNT;
return -ENXIO;
}
drive->usage--;
if (drive->driver != NULL)
DRIVER(drive)->release(inode, file, drive);
- MOD_DEC_USE_COUNT;
}
return 0;
}
}
struct block_device_operations ide_fops[] = {{
+ owner: THIS_MODULE,
open: ide_open,
release: ide_release,
ioctl: ide_ioctl,
if (((ultra_66) || (ultra_100)) && (EP & c_mask)) {
#ifdef DEBUG
- printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary", "Primary");
+ printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary" : "Primary");
printk(" Switching to Ultra33 mode.\n");
#endif /* DEBUG */
/* Primary : zero out second bit */
switch(bmide_dev->device) {
case PCI_DEVICE_ID_INTEL_82801BA_8:
case PCI_DEVICE_ID_INTEL_82801BA_9:
+ case PCI_DEVICE_ID_INTEL_82801CA_10:
p += sprintf(p, "\n Intel PIIX4 Ultra 100 Chipset.\n");
break;
case PCI_DEVICE_ID_INTEL_82372FB_1:
byte udma_66 = eighty_ninty_three(drive);
int ultra100 = ((dev->device == PCI_DEVICE_ID_INTEL_82801BA_8) ||
- (dev->device == PCI_DEVICE_ID_INTEL_82801BA_9)) ? 1 : 0;
+ (dev->device == PCI_DEVICE_ID_INTEL_82801BA_9) ||
+ (dev->device == PCI_DEVICE_ID_INTEL_82801CA_10)) ? 1 : 0;
int ultra66 = ((ultra100) ||
(dev->device == PCI_DEVICE_ID_INTEL_82801AA_1) ||
(dev->device == PCI_DEVICE_ID_INTEL_82372FB_1)) ? 1 : 0;
* Offsets from one of the above bases
*/
+
+/* HD_DATA was redefined in asm-m68k/ide.h */
#undef HD_DATA
#define HD_DATA 0x1f0
+
#define PCIDE_REG(x) ((q40ide_ioreg_t)(HD_##x-PCIDE_BASE1))
static const int pcide_offsets[IDE_NR_PORTS] = {
static struct file_operations lvm_chr_fops =
{
+ owner: THIS_MODULE,
open: lvm_chr_open,
release: lvm_chr_close,
ioctl: lvm_chr_ioctl,
/* block device operations structure needed for 2.3.38? and above */
static struct block_device_operations lvm_blk_dops =
{
+ owner: THIS_MODULE,
open: lvm_blk_open,
release: lvm_blk_close,
ioctl: lvm_blk_ioctl,
lvm_chr_open_count++;
- MOD_INC_USE_COUNT;
-
return 0;
} /* lvm_chr_open() */
wake_up_interruptible(&lvm_wait);
}
- MOD_DEC_USE_COUNT;
-
return 0;
} /* lvm_chr_close() */
if (lv_ptr->lv_open == 0) vg_ptr->lv_open++;
lv_ptr->lv_open++;
- MOD_INC_USE_COUNT;
-
#ifdef DEBUG_LVM_BLK_OPEN
printk(KERN_DEBUG
"%s -- lvm_blk_open MINOR: %d VG#: %d LV#: %d size: %d\n",
if (lv_ptr->lv_open == 1) vg_ptr->lv_open--;
lv_ptr->lv_open--;
- MOD_DEC_USE_COUNT;
-
return 0;
} /* lvm_blk_close() */
static struct block_device_operations md_fops=
{
+ owner: THIS_MODULE,
open: md_open,
release: md_release,
ioctl: md_ioctl,
#ifdef MODULE
MODULE_PARM(video_nr,"i");
-MODULE_AUTHOR("Scott J. Bertin <sbertin@mindspring.com> & Peter Pregler <Peter_Pregler@email.com> & Johannes Erdfelt <johannes@erdfelt.com>");
+MODULE_AUTHOR("Scott J. Bertin <sbertin@mindspring.com> & Peter Pregler <Peter_Pregler@email.com> & Johannes Erdfelt <jerdfelt@valinux.com>");
MODULE_DESCRIPTION("V4L-driver for Vision CPiA based cameras");
+MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("video");
#endif
/* set video size */
video_size = match_videosize(vm.width, vm.height);
- if (cam->video_size < 0) {
+ if (video_size < 0) {
retval = -EINVAL;
break;
}
}
}
-/****************************************************************************
- *
- * Module routines
- *
- ***************************************************************************/
-
-#ifdef MODULE
-int init_module(void)
-{
- printk(KERN_INFO "%s v%d.%d.%d\n", ABOUT,
- CPIA_MAJ_VER, CPIA_MIN_VER, CPIA_PATCH_VER);
-#ifdef CONFIG_PROC_FS
- proc_cpia_create();
-#endif
-#ifdef CONFIG_KMOD
-#ifdef CONFIG_VIDEO_CPIA_PP_MODULE
- request_module("cpia_pp");
-#endif
-#ifdef CONFIG_VIDEO_CPIA_USB_MODULE
- request_module("cpia_usb");
-#endif
-#endif
-return 0;
-}
-
-void cleanup_module(void)
-{
-#ifdef CONFIG_PROC_FS
- proc_cpia_destroy();
-#endif
-}
-
-#else
-
-int cpia_init(struct video_init *unused)
+static int __init cpia_init(void)
{
printk(KERN_INFO "%s v%d.%d.%d\n", ABOUT,
CPIA_MAJ_VER, CPIA_MIN_VER, CPIA_PATCH_VER);
return 0;
}
+static void __exit cpia_exit(void)
+{
+#ifdef CONFIG_PROC_FS
+ proc_cpia_destroy();
+#endif
+}
+
+module_init(cpia_init);
+module_exit(cpia_exit);
+
/* Exported symbols for modules. */
EXPORT_SYMBOL(cpia_register_camera);
EXPORT_SYMBOL(cpia_unregister_camera);
-
-#endif
} while (0)
+static inline void cpia_add_to_list(struct cam_data* l, struct cam_data* drv)
+{
+ drv->next = l;
+ drv->previous = &l;
+ l = drv;
+}
+
+
+static inline void cpia_remove_from_list(struct cam_data* drv)
+{
+ if (drv->previous != NULL) {
+ if (drv->next != NULL)
+ drv->next->previous = drv->previous;
+ *(drv->previous) = drv->next;
+ drv->previous = NULL;
+ drv->next = NULL;
+ }
+}
+
+
#endif /* __KERNEL__ */
#endif /* cpia_h */
MODULE_AUTHOR("B. Huisman <bhuism@cs.utwente.nl> & Peter Pregler <Peter_Pregler@email.com>");
MODULE_DESCRIPTION("Parallel port driver for Vision CPiA based cameras");
+MODULE_LICENSE("GPL");
+
MODULE_PARM(parport, "1-" __MODULE_STRING(PARPORT_MAX) "s");
MODULE_PARM_DESC(parport, "'auto' or a list of parallel port numbers. Just like lp.");
#else
};
static struct cam_data *cam_list;
+static spinlock_t cam_list_lock_pp;
#ifdef _CPIA_DEBUG_
#define DEB_PORT(port) { \
kfree(cam);
return -ENXIO;
}
- ADD_TO_LIST(cam_list, cpia);
+ spin_lock( &cam_list_lock_pp );
+ cpia_add_to_list(cam_list, cpia);
+ spin_unlock( &cam_list_lock_pp );
return 0;
}
{
struct cam_data *cpia;
+ spin_lock( &cam_list_lock_pp );
for(cpia = cam_list; cpia != NULL; cpia = cpia->next) {
struct pp_cam_entry *cam = cpia->lowlevel_data;
if (cam && cam->port->number == port->number) {
- REMOVE_FROM_LIST(cpia);
-
+ cpia_remove_from_list(cpia);
+ spin_unlock( &cam_list_lock_pp );
cpia_unregister_camera(cpia);
if(cam->open_count > 0) {
LOG ("unable to register with parport\n");
return -EIO;
}
+
+ cam_list = NULL;
+ spin_lock_init( &cam_list_lock_pp );
return 0;
}
};
static struct cam_data *cam_list;
+static spinlock_t cam_list_lock_usb;
static void cpia_usb_complete(struct urb *urb)
{
goto fail_all;
}
- ADD_TO_LIST(cam_list, cam);
+ spin_lock( &cam_list_lock_usb );
+ cpia_add_to_list(cam_list, cam);
+ spin_unlock( &cam_list_lock_usb );
return cam;
};
MODULE_DEVICE_TABLE (usb, cpia_id_table);
+MODULE_LICENSE("GPL");
+
static struct usb_driver cpia_driver = {
name: "cpia",
struct cam_data *cam = (struct cam_data *) ptr;
struct usb_cpia *ucpia = (struct usb_cpia *) cam->lowlevel_data;
- REMOVE_FROM_LIST(cam);
-
+ spin_lock( &cam_list_lock_usb );
+ cpia_remove_from_list(cam);
+ spin_unlock( &cam_list_lock_usb );
+
/* Don't even try to reset the altsetting if we're disconnected */
cpia_usb_free_resources(ucpia, 0);
static int __init usb_cpia_init(void)
{
cam_list = NULL;
-
+ spin_lock_init(&cam_list_lock_usb);
return usb_register(&cpia_driver);
}
#include <linux/delay.h>
#include <linux/wrapper.h>
#include <linux/interrupt.h>
+#include <linux/vmalloc.h>
#include "meye.h"
#include "linux/meye.h"
MODULE_DESCRIPTION("video4linux driver for the MotionEye camera");
MODULE_LICENSE("GPL");
+EXPORT_NO_SYMBOLS;
MODULE_PARM(gbuffers,"i");
MODULE_PARM_DESC(gbuffers,"number of capture buffers, default is 2 (32 max)");
#if 0
#define IDEBUG(x...) printk(KERN_DEBUG ## x) /* Debug interrupt part */
-#endif
+#else
#define IDEBUG(x...) /* Don't debug interrupt part */
#endif
DEBUG("Unclaim\n");
}
- MOD_DEC_USE_COUNT;
return 0;
}
i2o_post_wait(dev->controller, msg, 20, 2);
DEBUG("Ready.\n");
}
- MOD_INC_USE_COUNT;
return 0;
}
for(i=unit;i<=unit+15;i++)
{
- if(d->controller->type == I2O_TYPE_PCI && d->controller->bus.pci.queue_buggy)
+ i2ob_max_sectors[i] = 256;
+ i2ob_dev[i].max_segments = (d->controller->status_block->inbound_frame_size - 8)/2;
+
+ if(d->controller->type == I2O_TYPE_PCI && d->controller->bus.pci.queue_buggy == 2)
+ i2ob_dev[i].depth = 32;
+
+ if(d->controller->type == I2O_TYPE_PCI && d->controller->bus.pci.queue_buggy == 1)
{
i2ob_max_sectors[i] = 32;
i2ob_dev[i].max_segments = 8;
i2ob_dev[i].depth = 4;
}
- else if(d->controller->type == I2O_TYPE_PCI && d->controller->bus.pci.short_req)
+
+ if(d->controller->type == I2O_TYPE_PCI && d->controller->bus.pci.short_req)
{
i2ob_max_sectors[i] = 8;
i2ob_dev[i].max_segments = 8;
}
- else
- {
- /* MAX_SECTORS was used but 255 is a dumb number for
- striped RAID */
- i2ob_max_sectors[i]=256;
- i2ob_dev[i].max_segments = (d->controller->status_block->inbound_frame_size - 8)/2;
- }
}
- printk(KERN_INFO "Max segments set to %d\n",
- i2ob_dev[unit].max_segments);
- printk(KERN_INFO "Byte limit is %d.\n", limit);
- i2ob_query_device(dev, 0x0000, 0, &type, 1);
-
sprintf(d->dev_name, "%s%c", i2ob_gendisk.major_name, 'a' + (unit>>4));
+ printk(KERN_INFO "%s: Max segments %d, queue depth %d, byte limit %d.\n",
+ d->dev_name, i2ob_dev[unit].max_segments, i2ob_dev[unit].depth, limit);
+
+ i2ob_query_device(dev, 0x0000, 0, &type, 1);
+
printk(KERN_INFO "%s: ", d->dev_name);
switch(type)
{
printk(KERN_INFO " Not loaded.\n");
return 1;
}
- printk("- %dMb, %d byte sectors",
+ printk(": %dMB, %d byte sectors",
(int)(size>>20), blocksize);
if(status&(1<<0))
{
static struct block_device_operations i2ob_fops =
{
+ owner: THIS_MODULE,
open: i2ob_open,
release: i2ob_release,
ioctl: i2ob_ioctl,
if(dev->subsystem_vendor == PCI_VENDOR_ID_PROMISE)
{
c->bus.pci.queue_buggy=1;
+ if (dev->subsystem_device == 0x0000) /* SX6000 ???? */
+ c->bus.pci.queue_buggy=2;
printk(KERN_INFO "I2O: Promise workarounds activated.\n");
}
i2o_driver_result_table *result;
i2o_driver_store_table *dst;
- spin_lock(&i2o_proc_lock);
len = 0;
if(result == NULL)
return -ENOMEM;
+ spin_lock(&i2o_proc_lock);
+
token = i2o_query_table(I2O_PARAMS_TABLE_GET,
c, ADAPTER_TID, 0x0005, -1, NULL, 0,
result, sizeof(*result));
};
#else
static struct block_device_operations ftl_blk_fops = {
+ owner: THIS_MODULE,
open: ftl_open,
release: ftl_close,
ioctl: ftl_ioctl,
if (ftl_gendisk.part[minor].nr_sects == 0)
return -ENXIO;
- MOD_INC_USE_COUNT;
-
- if (!get_mtd_device(partition->mtd, -1)) {
- MOD_DEC_USE_COUNT;
+ if (!get_mtd_device(partition->mtd, -1))
return /* -E'SBUGGEREDOFF */ -ENXIO;
- }
-
+
if ((file->f_mode & 2) && !(partition->mtd->flags & MTD_CLEAR_BITS) ) {
put_mtd_device(partition->mtd);
- MOD_DEC_USE_COUNT;
return -EROFS;
}
atomic_dec(&part->open);
put_mtd_device(part->mtd);
- MOD_DEC_USE_COUNT;
release_return(0);
} /* ftl_close */
return -ENODEV;
}
- MOD_INC_USE_COUNT;
-
spin_lock(&mtdblks_lock);
/* If it's already open, no need to piss about. */
mtdblk = kmalloc(sizeof(struct mtdblk_dev), GFP_KERNEL);
if (!mtdblk) {
put_mtd_device(mtd);
- MOD_DEC_USE_COUNT;
return -ENOMEM;
}
memset(mtdblk, 0, sizeof(*mtdblk));
if (!mtdblk->cache_data) {
put_mtd_device(mtdblk->mtd);
kfree(mtdblk);
- MOD_DEC_USE_COUNT;
return -ENOMEM;
}
}
DEBUG(MTD_DEBUG_LEVEL1, "ok\n");
- MOD_DEC_USE_COUNT;
release_return(0);
}
#else
static struct block_device_operations mtd_fops =
{
+ owner: THIS_MODULE,
open: mtdblock_open,
release: mtdblock_release,
ioctl: mtdblock_ioctl
return -EINVAL;
}
- MOD_INC_USE_COUNT;
-
mtd_sizes[dev] = mtd->size>>9;
DEBUG(1, "ok\n");
if (!mtd) {
printk(KERN_WARNING "MTD device is absent on mtd_release!\n");
- MOD_DEC_USE_COUNT;
release_return(-ENODEV);
}
DEBUG(1, "ok\n");
- MOD_DEC_USE_COUNT;
release_return(0);
}
#else
static struct block_device_operations mtd_fops =
{
+ owner: THIS_MODULE,
open: mtdblock_open,
release: mtdblock_release,
ioctl: mtdblock_ioctl
#endif /* !CONFIG_NFTL_RW */
thisNFTL->usecount++;
- MOD_INC_USE_COUNT;
- if (!get_mtd_device(thisNFTL->mtd, -1)) {
- MOD_DEC_USE_COUNT;
+ if (!get_mtd_device(thisNFTL->mtd, -1))
return /* -E'SBUGGEREDOFF */ -ENXIO;
- }
return 0;
}
if (thisNFTL->mtd->sync)
thisNFTL->mtd->sync(thisNFTL->mtd);
thisNFTL->usecount--;
- MOD_DEC_USE_COUNT;
put_mtd_device(thisNFTL->mtd);
#else
static struct block_device_operations nftl_fops =
{
+ owner: THIS_MODULE,
open: nftl_open,
release: nftl_release,
ioctl: nftl_ioctl
See the file COPYING in this distribution for more information.
- TODO:
+ TODO, in rough priority order:
* dev->tx_timeout
+ * LinkChg interrupt
+ * ETHTOOL_[GS]SET
+ * Support forcing media type with a module parameter,
+ like dl2k.c/sundance.c
+ * Implement PCI suspend/resume
* Constants (module parms?) for Rx work limit
* support 64-bit PCI DMA
- * ETHTOOL_[GS]SET, ETHTOOL_GREGS, ETHTOOL_[GS]WOL,
- ETHTOOL_[GS]MSGLVL, ETHTOOL_NWAY_RST
* Complete reset on PciErr
- * LinkChg and LenChg interrupts
* Consider Rx interrupt mitigation using TimerIntr
- * Implement 8139C+ statistics dump
- * Support forcing media type with a module parameter,
- like dl2k.c/sundance.c
+ * Implement 8139C+ statistics dump; maybe not...
+ h/w stats can be reset only by software reset
* Rx checksumming
* Tx checksumming
+ * ETHTOOL_GREGS, ETHTOOL_[GS]WOL,
+ ETHTOOL_[GS]MSGLVL, ETHTOOL_NWAY_RST
* Jumbo frames / dev->change_mtu
- * Tx abort stops Tx DMA?
- * Investigate IntrStatus bit 10 purpose and use
* Investigate using skb->priority with h/w VLAN priority
* Investigate using High Priority Tx Queue with skb->priority
* Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
+#define RCS_ID "$Id: scc.c,v 1.75 1998/11/04 15:15:01 jreuter Exp jreuter $"
+
#define VERSION "3.0"
/*
********************************************************************
- Copyright (c) 1993, 2001 Joerg Reuter DL1BKE
+ Copyright (c) 1993, 2000 Joerg Reuter DL1BKE
portions (c) 1993 Guido ten Dolle PE1NNZ
2000-02-13 Fixed for new network driver interface changes, still
does TX timeouts itself since it uses its own queue
scheme.
- 2001-10-05 Set skb to NULL on Rx_OVR in scc_spint() (tnx everybody
- who insisted that the skb gets in fact re-used by the
- following code otherwise. I think we have another Z8530
- bug here...)
Thanks to all who contributed to this driver with ideas and bug
reports!
if (skb != NULL)
dev_kfree_skb_irq(skb);
scc->rx_buff = skb = NULL;
- skb = NULL; /* avoid skb being reused */
}
if(status & END_FR && skb != NULL) /* end of frame */
dep_tristate ' Greenwich GIrBIL dongle' CONFIG_GIRBIL_DONGLE $CONFIG_IRDA
dep_tristate ' Parallax LiteLink dongle' CONFIG_LITELINK_DONGLE $CONFIG_IRDA
dep_tristate ' Old Belkin dongle' CONFIG_OLD_BELKIN_DONGLE $CONFIG_IRDA
+ if [ "$CONFIG_ARCH_EP7211" = "y" ]; then
+ dep_tristate ' EP7211 I/R support' CONFIG_EP7211_IR $CONFIG_IRDA
+ fi
fi
comment 'FIR device drivers'
dep_tristate 'ALi M5123 FIR (Experimental)' CONFIG_ALI_FIR $CONFIG_IRDA
dep_tristate 'VLSI 82C147 SIR/MIR/FIR (Experimental)' CONFIG_VLSI_FIR $CONFIG_IRDA
fi
+if [ "$CONFIG_ARCH_SA1100" = "y" ]; then
+ dep_tristate 'SA1100 Internal IR' CONFIG_SA1100_FIR $CONFIG_IRDA
+fi
endmenu
+# File: drivers/irda/Makefile
#
# Makefile for the Linux IrDA infrared port device drivers.
#
obj-$(CONFIG_USB_IRDA) += irda-usb.o
obj-$(CONFIG_NSC_FIR) += nsc-ircc.o
obj-$(CONFIG_WINBOND_FIR) += w83977af_ir.o
+obj-$(CONFIG_SA1100_FIR) += sa1100_ir.o
obj-$(CONFIG_TOSHIBA_FIR) += toshoboe.o
obj-$(CONFIG_SMC_IRCC_FIR) += smc-ircc.o irport.o
obj-$(CONFIG_ALI_FIR) += ali-ircc.o
obj-$(CONFIG_GIRBIL_DONGLE) += girbil.o
obj-$(CONFIG_LITELINK_DONGLE) += litelink.o
obj-$(CONFIG_OLD_BELKIN_DONGLE) += old_belkin.o
+obj-$(CONFIG_EP7211_IR) += ep7211_ir.o
include $(TOPDIR)/Rules.make
--- /dev/null
+/*
+ * IR port driver for the Cirrus Logic EP7211 processor.
+ *
+ * Copyright 2001, Blue Mug Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/tty.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+
+#include <net/irda/irda.h>
+#include <net/irda/irmod.h>
+#include <net/irda/irda_device.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+
+#define MIN_DELAY 25 /* 15 us, but wait a little more to be sure */
+#define MAX_DELAY 10000 /* 1 ms */
+
+static void ep7211_ir_open(dongle_t *self, struct qos_info *qos);
+static void ep7211_ir_close(dongle_t *self);
+static int ep7211_ir_change_speed(struct irda_task *task);
+static int ep7211_ir_reset(struct irda_task *task);
+
+static struct dongle_reg dongle = {
+ Q_NULL,
+ IRDA_EP7211_IR,
+ ep7211_ir_open,
+ ep7211_ir_close,
+ ep7211_ir_reset,
+ ep7211_ir_change_speed,
+};
+
+static void ep7211_ir_open(dongle_t *self, struct qos_info *qos)
+{
+ unsigned int syscon1, flags;
+
+ save_flags(flags); cli();
+
+ /* Turn on the SIR encoder. */
+ syscon1 = clps_readl(SYSCON1);
+ syscon1 |= SYSCON1_SIREN;
+ clps_writel(syscon1, SYSCON1);
+
+ /* XXX: We should disable modem status interrupts on the first
+ UART (interrupt #14). */
+
+ restore_flags(flags);
+
+ MOD_INC_USE_COUNT;
+}
+
+static void ep7211_ir_close(dongle_t *self)
+{
+ unsigned int syscon1, flags;
+
+ save_flags(flags); cli();
+
+ /* Turn off the SIR encoder. */
+ syscon1 = clps_readl(SYSCON1);
+ syscon1 &= ~SYSCON1_SIREN;
+ clps_writel(syscon1, SYSCON1);
+
+ /* XXX: If we've disabled the modem status interrupts, we should
+ reset them back to their original state. */
+
+ restore_flags(flags);
+
+ MOD_DEC_USE_COUNT;
+}
+
+/*
+ * Function ep7211_ir_change_speed (task)
+ *
+ * Change speed of the EP7211 I/R port. We don't really have to do anything
+ * for the EP7211 as long as the rate is being changed at the serial port
+ * level.
+ */
+static int ep7211_ir_change_speed(struct irda_task *task)
+{
+ irda_task_next_state(task, IRDA_TASK_DONE);
+ return 0;
+}
+
+/*
+ * Function ep7211_ir_reset (task)
+ *
+ * Reset the EP7211 I/R. We don't really have to do anything.
+ *
+ */
+static int ep7211_ir_reset(struct irda_task *task)
+{
+ irda_task_next_state(task, IRDA_TASK_DONE);
+ return 0;
+}
+
+/*
+ * Function ep7211_ir_init(void)
+ *
+ * Initialize EP7211 I/R module
+ *
+ */
+int __init ep7211_ir_init(void)
+{
+ return irda_device_register_dongle(&dongle);
+}
+
+/*
+ * Function ep7211_ir_cleanup(void)
+ *
+ * Cleanup EP7211 I/R module
+ *
+ */
+static void __exit ep7211_ir_cleanup(void)
+{
+ irda_device_unregister_dongle(&dongle);
+}
+
+MODULE_AUTHOR("Jon McClintock <jonm@bluemug.com>");
+MODULE_DESCRIPTION("EP7211 I/R driver");
+MODULE_LICENSE("GPL");
+
+#ifdef MODULE
+module_init(ep7211_ir_init);
+#endif /* MODULE */
+module_exit(ep7211_ir_cleanup);
--- /dev/null
+/*
+ * linux/drivers/net/irda/sa1100_ir.c
+ *
+ * Copyright (C) 2000-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Infra-red driver for the StrongARM SA1100 embedded microprocessor
+ *
+ * Note that we don't have to worry about the SA1111's DMA bugs in here,
+ * so we use the straight forward pci_map_* functions with a null pointer.
+ * IMHO we should really be using our own machine specific set.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/slab.h>
+#include <linux/rtnetlink.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+
+#include <net/irda/irda.h>
+#include <net/irda/irmod.h>
+#include <net/irda/wrapper.h>
+#include <net/irda/irda_device.h>
+
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/assabet.h>
+
+#ifndef CONFIG_SA1100_H3600
+#define clr_h3600_egpio(x) do { } while (0)
+#define set_h3600_egpio(x) do { } while (0)
+#endif
+
+#ifndef GPIO_IRDA_FIR
+#define GPIO_IRDA_FIR (0)
+#endif
+
+#ifndef GPIO_IRDA_POWER
+#define GPIO_IRDA_POWER (0)
+#endif
+
+static int power_level = 3;
+static int tx_lpm = 0;
+
+/*
+ * Our netdevice. There is only ever one of these.
+ */
+static struct net_device *netdev;
+
+struct sa1100_irda {
+ unsigned char hscr0;
+ unsigned char utcr4;
+ unsigned char power;
+ unsigned char open;
+
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ dma_addr_t txbuf_dma;
+ dma_addr_t rxbuf_dma;
+ int txdma;
+ int rxdma;
+
+ struct net_device_stats stats;
+ struct irlap_cb *irlap;
+ struct pm_dev *pmdev;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+};
+
+#define IS_FIR(si) ((si)->speed >= 4000000)
+
+#define HPSIR_MAX_RXLEN 2047
+
+/*
+ * Allocate and map the receive buffer, unless it is already allocated.
+ */
+static int sa1100_irda_rx_alloc(struct sa1100_irda *si)
+{
+ if (si->rxskb)
+ return 0;
+
+ si->rxskb = alloc_skb(HPSIR_MAX_RXLEN + 1, GFP_ATOMIC);
+
+ if (!si->rxskb) {
+ printk(KERN_ERR "sa1100_ir: out of memory for RX SKB\n");
+ return -ENOMEM;
+ }
+
+ /*
+ * Align any IP headers that may be contained
+ * within the frame.
+ */
+ skb_reserve(si->rxskb, 1);
+
+ si->rxbuf_dma = pci_map_single(NULL, si->rxskb->data,
+ HPSIR_MAX_RXLEN,
+ PCI_DMA_FROMDEVICE);
+ return 0;
+}
+
+/*
+ * We want to get here as soon as possible, and get the receiver setup.
+ * We use the existing buffer.
+ */
+static void sa1100_irda_rx_dma_start(struct sa1100_irda *si)
+{
+ if (!si->rxskb) {
+ printk(KERN_ERR "sa1100_ir: rx buffer went missing\n");
+ return;
+ }
+
+ /*
+ * First empty receive FIFO
+ */
+ Ser2HSCR0 = si->hscr0 | HSCR0_HSSP;
+
+ /*
+ * Enable the DMA, receiver and recieve interrupt.
+ */
+ sa1100_dma_flush_all(si->rxdma);
+ sa1100_dma_queue_buffer(si->rxdma, NULL, si->rxbuf_dma, HPSIR_MAX_RXLEN);
+ Ser2HSCR0 = si->hscr0 | HSCR0_HSSP | HSCR0_RXE;
+}
+
+/*
+ * Set the IrDA communications speed.
+ */
+static int sa1100_irda_set_speed(struct sa1100_irda *si, int speed)
+{
+ unsigned long flags;
+ int brd, ret = -EINVAL;
+
+ switch (speed) {
+ case 9600: case 19200: case 38400:
+ case 57600: case 115200:
+ brd = 3686400 / (16 * speed) - 1;
+
+ /*
+ * Stop the receive DMA.
+ */
+ if (IS_FIR(si))
+ sa1100_dma_stop(si->rxdma);
+
+ local_irq_save(flags);
+
+ Ser2UTCR3 = 0;
+ Ser2HSCR0 = HSCR0_UART;
+
+ Ser2UTCR1 = brd >> 8;
+ Ser2UTCR2 = brd;
+
+ /*
+ * Clear status register
+ */
+ Ser2UTSR0 = UTSR0_REB | UTSR0_RBB | UTSR0_RID;
+ Ser2UTCR3 = UTCR3_RIE | UTCR3_RXE | UTCR3_TXE;
+
+ if (machine_is_assabet())
+ ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
+ if (machine_is_h3600())
+ clr_h3600_egpio(EGPIO_H3600_IR_FSEL);
+ if (machine_is_yopy())
+ PPSR &= ~GPIO_IRDA_FIR;
+
+ si->speed = speed;
+
+ local_irq_restore(flags);
+ ret = 0;
+ break;
+
+ case 4000000:
+ save_flags(flags);
+ cli();
+
+ si->hscr0 = 0;
+
+ Ser2HSSR0 = 0xff;
+ Ser2HSCR0 = si->hscr0 | HSCR0_HSSP;
+ Ser2UTCR3 = 0;
+
+ si->speed = speed;
+
+ if (machine_is_assabet())
+ ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
+ if (machine_is_h3600())
+ set_h3600_egpio(EGPIO_H3600_IR_FSEL);
+ if (machine_is_yopy())
+ PPSR |= GPIO_IRDA_FIR;
+
+ sa1100_irda_rx_alloc(si);
+ sa1100_irda_rx_dma_start(si);
+
+ restore_flags(flags);
+
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * This sets the IRDA power level on the Assabet.
+ */
+static inline int
+sa1100_irda_set_power_assabet(struct sa1100_irda *si, unsigned int state)
+{
+ static unsigned int bcr_state[4] = {
+ ASSABET_BCR_IRDA_MD0,
+ ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0,
+ ASSABET_BCR_IRDA_MD1,
+ 0
+ };
+
+ if (state < 4) {
+ state = bcr_state[state];
+ ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1|
+ ASSABET_BCR_IRDA_MD0));
+ ASSABET_BCR_set(state);
+ }
+ return 0;
+}
+
+/*
+ * This turns the IRDA power on or off on the Compaq H3600
+ */
+static inline int
+sa1100_irda_set_power_h3600(struct sa1100_irda *si, unsigned int state)
+{
+ if (state)
+ set_h3600_egpio(EGPIO_H3600_IR_ON);
+ else
+ clr_h3600_egpio(EGPIO_H3600_IR_ON);
+ return 0;
+}
+
+/*
+ * This turns the IRDA power on or off on the Yopy
+ */
+static inline int
+sa1100_irda_set_power_yopy(struct sa1100_irda *si, unsigned int state)
+{
+ if (state)
+ PPSR &= ~GPIO_IRDA_POWER;
+ else
+ PPSR |= GPIO_IRDA_POWER;
+ return 0;
+}
+
+/*
+ * Control the power state of the IrDA transmitter.
+ * State:
+ * 0 - off
+ * 1 - short range, lowest power
+ * 2 - medium range, medium power
+ * 3 - maximum range, high power
+ *
+ * Currently, only assabet is known to support this.
+ */
+static int
+__sa1100_irda_set_power(struct sa1100_irda *si, unsigned int state)
+{
+ int ret = 0;
+
+ if (machine_is_assabet())
+ ret = sa1100_irda_set_power_assabet(si, state);
+ if (machine_is_h3600())
+ ret = sa1100_irda_set_power_h3600(si, state);
+ if (machine_is_yopy())
+ ret = sa1100_irda_set_power_yopy(si, state);
+
+ return ret;
+}
+
+static inline int
+sa1100_set_power(struct sa1100_irda *si, unsigned int state)
+{
+ int ret;
+
+ ret = __sa1100_irda_set_power(si, state);
+ if (ret == 0)
+ si->power = state;
+
+ return ret;
+}
+
+static int sa1100_irda_startup(struct sa1100_irda *si)
+{
+ int ret;
+
+ /*
+ * Ensure that the ports for this device are setup correctly.
+ */
+ if (machine_is_yopy()) {
+ PPDR |= GPIO_IRDA_POWER | GPIO_IRDA_FIR;
+ PPSR |= GPIO_IRDA_POWER | GPIO_IRDA_FIR;
+ PSDR |= GPIO_IRDA_POWER | GPIO_IRDA_FIR;
+ }
+
+ /*
+ * Configure PPC for IRDA - we want to drive TXD2 low.
+ * We also want to drive this pin low during sleep.
+ */
+ PPSR &= ~PPC_TXD2;
+ PSDR &= ~PPC_TXD2;
+ PPDR |= PPC_TXD2;
+
+ /*
+ * Enable HP-SIR modulation, and ensure that the port is disabled.
+ */
+ Ser2UTCR3 = 0;
+ Ser2HSCR0 = HSCR0_UART;
+ Ser2UTCR4 = si->utcr4;
+ Ser2UTCR0 = UTCR0_8BitData;
+ Ser2HSCR2 = HSCR2_TrDataH | HSCR2_RcDataL;
+
+ /*
+ * Clear status register
+ */
+ Ser2UTSR0 = UTSR0_REB | UTSR0_RBB | UTSR0_RID;
+
+ ret = sa1100_irda_set_speed(si, si->speed = 9600);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void sa1100_irda_shutdown(struct sa1100_irda *si)
+{
+ /*
+ * Stop all DMA activity.
+ */
+ sa1100_dma_stop(si->rxdma);
+ sa1100_dma_stop(si->txdma);
+
+ /* Disable the port. */
+ Ser2UTCR3 = 0;
+ Ser2HSCR0 = 0;
+}
+
+#ifdef CONFIG_PM
+/*
+ * Suspend the IrDA interface.
+ */
+static int sa1100_irda_suspend(struct net_device *dev, int state)
+{
+ struct sa1100_irda *si = dev->priv;
+
+ if (si && si->open) {
+ /*
+ * Stop the transmit queue
+ */
+ netif_device_detach(dev);
+ disable_irq(dev->irq);
+ sa1100_irda_shutdown(si);
+ __sa1100_irda_set_power(si, 0);
+ }
+
+ return 0;
+}
+
+/*
+ * Resume the IrDA interface.
+ */
+static int sa1100_irda_resume(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+
+ if (si && si->open) {
+ /*
+ * If we missed a speed change, initialise at the new speed
+ * directly. It is debatable whether this is actually
+ * required, but in the interests of continuing from where
+ * we left off it is desireable. The converse argument is
+ * that we should re-negotiate at 9600 baud again.
+ */
+ if (si->newspeed) {
+ si->speed = si->newspeed;
+ si->newspeed = 0;
+ }
+
+ sa1100_irda_startup(si);
+ __sa1100_irda_set_power(si, si->power);
+ enable_irq(dev->irq);
+
+ /*
+ * This automatically wakes up the queue
+ */
+ netif_device_attach(dev);
+ }
+
+ return 0;
+}
+
+static int sa1100_irda_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
+{
+ int ret;
+
+ if (!dev->data)
+ return -EINVAL;
+
+ switch (rqst) {
+ case PM_SUSPEND:
+ ret = sa1100_irda_suspend((struct net_device *)dev->data,
+ (int)data);
+ break;
+
+ case PM_RESUME:
+ ret = sa1100_irda_resume((struct net_device *)dev->data);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+#endif
+
+/*
+ * HP-SIR format interrupt service routines.
+ */
+static void sa1100_irda_hpsir_irq(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+ int status;
+
+ status = Ser2UTSR0;
+
+ /*
+ * Deal with any receive errors first. The bytes in error may be
+ * the only bytes in the receive FIFO, so we do this first.
+ */
+ while (status & UTSR0_EIF) {
+ int stat, data;
+
+ stat = Ser2UTSR1;
+ data = Ser2UTDR;
+
+ if (stat & (UTSR1_FRE | UTSR1_ROR)) {
+ si->stats.rx_errors++;
+ if (stat & UTSR1_FRE)
+ si->stats.rx_frame_errors++;
+ if (stat & UTSR1_ROR)
+ si->stats.rx_fifo_errors++;
+ } else
+ async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
+
+ status = Ser2UTSR0;
+ }
+
+ /*
+ * We must clear certain bits.
+ */
+ Ser2UTSR0 = status & (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
+
+ if (status & UTSR0_RFS) {
+ /*
+ * There are at least 4 bytes in the FIFO. Read 3 bytes
+ * and leave the rest to the block below.
+ */
+ async_unwrap_char(dev, &si->stats, &si->rx_buff, Ser2UTDR);
+ async_unwrap_char(dev, &si->stats, &si->rx_buff, Ser2UTDR);
+ async_unwrap_char(dev, &si->stats, &si->rx_buff, Ser2UTDR);
+ }
+
+ if (status & (UTSR0_RFS | UTSR0_RID)) {
+ /*
+ * Fifo contains more than 1 character.
+ */
+ do {
+ async_unwrap_char(dev, &si->stats, &si->rx_buff,
+ Ser2UTDR);
+ } while (Ser2UTSR1 & UTSR1_RNE);
+
+ dev->last_rx = jiffies;
+ }
+
+ if (status & UTSR0_TFS && si->tx_buff.len) {
+ /*
+ * Transmitter FIFO is not full
+ */
+ do {
+ Ser2UTDR = *si->tx_buff.data++;
+ si->tx_buff.len -= 1;
+ } while (Ser2UTSR1 & UTSR1_TNF && si->tx_buff.len);
+
+ if (si->tx_buff.len == 0) {
+ si->stats.tx_packets++;
+ si->stats.tx_bytes += si->tx_buff.data -
+ si->tx_buff.head;
+
+ /*
+ * We need to ensure that the transmitter has
+ * finished.
+ */
+ do
+ rmb();
+ while (Ser2UTSR1 & UTSR1_TBY);
+
+ /*
+ * Ok, we've finished transmitting. Now enable
+ * the receiver. Sometimes we get a receive IRQ
+ * immediately after a transmit...
+ */
+ Ser2UTSR0 = UTSR0_REB | UTSR0_RBB | UTSR0_RID;
+ Ser2UTCR3 = UTCR3_RIE | UTCR3_RXE | UTCR3_TXE;
+
+ if (si->newspeed) {
+ sa1100_irda_set_speed(si, si->newspeed);
+ si->newspeed = 0;
+ }
+
+ /* I'm hungry! */
+ netif_wake_queue(dev);
+ }
+ }
+}
+
+static void sa1100_irda_fir_error(struct sa1100_irda *si, struct net_device *dev)
+{
+ struct sk_buff *skb = si->rxskb;
+ dma_addr_t dma_addr;
+ unsigned int len, stat, data;
+
+ if (!skb) {
+ printk(KERN_ERR "sa1100_ir: SKB is NULL!\n");
+ return;
+ }
+
+ /*
+ * Get the current data position.
+ */
+ sa1100_dma_get_current(si->rxdma, NULL, &dma_addr);
+ len = dma_addr - si->rxbuf_dma;
+ pci_unmap_single(NULL, si->rxbuf_dma, len, PCI_DMA_FROMDEVICE);
+
+ do {
+ /*
+ * Read Status, and then Data.
+ */
+ stat = Ser2HSSR1;
+ rmb();
+ data = Ser2HSDR;
+
+ if (stat & (HSSR1_CRE | HSSR1_ROR)) {
+ si->stats.rx_errors++;
+ if (stat & HSSR1_CRE)
+ si->stats.rx_crc_errors++;
+ if (stat & HSSR1_ROR)
+ si->stats.rx_frame_errors++;
+ } else
+ skb->data[len++] = data;
+
+ /*
+ * If we hit the end of frame, there's
+ * no point in continuing.
+ */
+ if (stat & HSSR1_EOF)
+ break;
+ } while (Ser2HSSR0 & HSSR0_EIF);
+
+ if (stat & HSSR1_EOF) {
+ si->rxskb = NULL;
+
+ skb_put(skb, len);
+ skb->dev = dev;
+ skb->mac.raw = skb->data;
+ skb->protocol = htons(ETH_P_IRDA);
+ si->stats.rx_packets++;
+ si->stats.rx_bytes += len;
+
+ /*
+ * Before we pass the buffer up, allocate a new one.
+ */
+ sa1100_irda_rx_alloc(si);
+
+ netif_rx(skb);
+ } else {
+ /*
+ * Remap the buffer.
+ */
+ si->rxbuf_dma = pci_map_single(NULL, si->rxskb->data,
+ HPSIR_MAX_RXLEN,
+ PCI_DMA_FROMDEVICE);
+ }
+}
+
+/*
+ * FIR format interrupt service routine. We only have to
+ * handle RX events; transmit events go via the TX DMA handler.
+ *
+ * No matter what, we disable RX, process, and the restart RX.
+ */
+static void sa1100_irda_fir_irq(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+
+ /*
+ * Stop RX DMA
+ */
+ sa1100_dma_stop(si->rxdma);
+
+ /*
+ * Framing error - we throw away the packet completely.
+ * Clearing RXE flushes the error conditions and data
+ * from the fifo.
+ */
+ if (Ser2HSSR0 & (HSSR0_FRE | HSSR0_RAB)) {
+ si->stats.rx_errors++;
+
+ if (Ser2HSSR0 & HSSR0_FRE)
+ si->stats.rx_frame_errors++;
+
+ /*
+ * Clear out the DMA...
+ */
+ Ser2HSCR0 = si->hscr0 | HSCR0_HSSP;
+
+ /*
+ * Clear selected status bits now, so we
+ * don't miss them next time around.
+ */
+ Ser2HSSR0 = HSSR0_FRE | HSSR0_RAB;
+ }
+
+ /*
+ * Deal with any receive errors. The any of the lowest
+ * 8 bytes in the FIFO may contain an error. We must read
+ * them one by one. The "error" could even be the end of
+ * packet!
+ */
+ if (Ser2HSSR0 & HSSR0_EIF)
+ sa1100_irda_fir_error(si, dev);
+
+ /*
+ * No matter what happens, we must restart reception.
+ */
+ sa1100_irda_rx_dma_start(si);
+}
+
+static void sa1100_irda_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct net_device *dev = dev_id;
+ if (IS_FIR(((struct sa1100_irda *)dev->priv)))
+ sa1100_irda_fir_irq(dev);
+ else
+ sa1100_irda_hpsir_irq(dev);
+}
+
+/*
+ * TX DMA completion handler.
+ */
+static void sa1100_irda_txdma_irq(void *id, int len)
+{
+ struct net_device *dev = id;
+ struct sa1100_irda *si = dev->priv;
+ struct sk_buff *skb = si->txskb;
+
+ si->txskb = NULL;
+
+ /*
+ * Wait for the transmission to complete. Unfortunately,
+ * the hardware doesn't give us an interrupt to indicate
+ * "end of frame".
+ */
+ do
+ rmb();
+ while (!(Ser2HSSR0 & HSSR0_TUR) || Ser2HSSR1 & HSSR1_TBY);
+
+ /*
+ * Clear the transmit underrun bit.
+ */
+ Ser2HSSR0 = HSSR0_TUR;
+
+ /*
+ * Do we need to change speed? Note that we're lazy
+ * here - we don't free the old rxskb. We don't need
+ * to allocate a buffer either.
+ */
+ if (si->newspeed) {
+ sa1100_irda_set_speed(si, si->newspeed);
+ si->newspeed = 0;
+ }
+
+ /*
+ * Start reception. This disables the transmitter for
+ * us. This will be using the existing RX buffer.
+ */
+ sa1100_irda_rx_dma_start(si);
+
+ /*
+ * Account and free the packet.
+ */
+ if (skb) {
+ pci_unmap_single(NULL, si->txbuf_dma, len, PCI_DMA_TODEVICE);
+ si->stats.tx_packets ++;
+ si->stats.tx_bytes += len;
+ dev_kfree_skb_irq(skb);
+ }
+
+ /*
+ * Make sure that the TX queue is available for sending
+ * (for retries). TX has priority over RX at all times.
+ */
+ netif_wake_queue(dev);
+}
+
+/*
+ * Note that we will never build up a backlog of frames; the protocol is a
+ * half duplex protocol which basically means we transmit a frame, we
+ * receive a frame, we transmit the next frame etc.
+ */
+static int sa1100_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+ int speed = irda_get_next_speed(skb);
+
+ /*
+ * Does this packet contain a request to change the interface
+ * speed? If so, remember it until we complete the transmission
+ * of this frame.
+ */
+ if (speed != si->speed && speed != -1)
+ si->newspeed = speed;
+
+ /*
+ * If this is an empty frame, we can bypass a lot.
+ */
+ if (skb->len == 0) {
+ if (si->newspeed) {
+ si->newspeed = 0;
+ sa1100_irda_set_speed(si, speed);
+ }
+ dev_kfree_skb(skb);
+ return 0;
+ }
+
+ if (!IS_FIR(si)) {
+ si->tx_buff.data = si->tx_buff.head;
+ si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data,
+ si->tx_buff.truesize);
+
+ /*
+ * Set the transmit interrupt enable. This will fire
+ * off an interrupt immediately. Note that we disable
+ * the receiver so we won't get spurious characteres
+ * received.
+ */
+ Ser2UTCR3 = UTCR3_TIE | UTCR3_TXE;
+
+ dev_kfree_skb(skb);
+ } else {
+ int mtt = irda_get_mtt(skb);
+
+ /*
+ * We must not be transmitting...
+ */
+ if (si->txskb)
+ BUG();
+
+ netif_stop_queue(dev);
+
+ si->txskb = skb;
+ si->txbuf_dma = pci_map_single(NULL, skb->data,
+ skb->len, PCI_DMA_TODEVICE);
+
+ sa1100_dma_queue_buffer(si->txdma, dev, si->txbuf_dma,
+ skb->len);
+
+ /*
+ * If we have a mean turn-around time, impose the specified
+ * specified delay. We could shorten this by timing from
+ * the point we received the packet.
+ */
+ if (mtt)
+ udelay(mtt);
+
+ Ser2HSCR0 = si->hscr0 | HSCR0_HSSP | HSCR0_TXE;
+ }
+
+ dev->trans_start = jiffies;
+
+ return 0;
+}
+
+static int
+sa1100_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
+{
+ struct if_irda_req *rq = (struct if_irda_req *)ifreq;
+ struct sa1100_irda *si = dev->priv;
+ int ret = -EOPNOTSUPP;
+
+ switch (cmd) {
+ case SIOCSBANDWIDTH:
+ if (capable(CAP_NET_ADMIN)) {
+ /*
+ * We are unable to set the speed if the
+ * device is not running.
+ */
+ if (si->open) {
+ ret = sa1100_irda_set_speed(si,
+ rq->ifr_baudrate);
+ } else {
+ printk("sa1100_irda_ioctl: SIOCSBANDWIDTH: !netif_running\n");
+ ret = 0;
+ }
+ }
+ break;
+
+ case SIOCSMEDIABUSY:
+ ret = -EPERM;
+ if (capable(CAP_NET_ADMIN)) {
+ irda_device_set_media_busy(dev, TRUE);
+ ret = 0;
+ }
+ break;
+
+ case SIOCGRECEIVING:
+ rq->ifr_receiving = IS_FIR(si) ? 0
+ : si->rx_buff.state != OUTSIDE_FRAME;
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static struct net_device_stats *sa1100_irda_stats(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+ return &si->stats;
+}
+
+static int sa1100_irda_start(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+ int err;
+
+ MOD_INC_USE_COUNT;
+
+ si->speed = 9600;
+
+ err = request_irq(dev->irq, sa1100_irda_irq, 0, dev->name, dev);
+ if (err)
+ goto err_irq;
+
+ err = sa1100_request_dma(&si->rxdma, "IrDA receive", DMA_Ser2HSSPRd);
+ if (err)
+ goto err_rx_dma;
+
+ err = sa1100_request_dma(&si->txdma, "IrDA transmit", DMA_Ser2HSSPWr);
+ if (err)
+ goto err_tx_dma;
+
+ /*
+ * The interrupt must remain disabled for now.
+ */
+ disable_irq(dev->irq);
+
+ /*
+ * Setup the serial port for the specified speed.
+ */
+ err = sa1100_irda_startup(si);
+ if (err)
+ goto err_startup;
+
+ /*
+ * Open a new IrLAP layer instance.
+ */
+ si->irlap = irlap_open(dev, &si->qos, "sa1100");
+ err = -ENOMEM;
+ if (!si->irlap)
+ goto err_irlap;
+
+ sa1100_dma_set_callback(si->txdma, sa1100_irda_txdma_irq);
+
+ /*
+ * Now enable the interrupt and start the queue
+ */
+ si->open = 1;
+ sa1100_set_power(si, power_level); /* low power mode */
+ enable_irq(dev->irq);
+ netif_start_queue(dev);
+ return 0;
+
+err_irlap:
+ si->open = 0;
+ sa1100_irda_shutdown(si);
+err_startup:
+ sa1100_free_dma(si->txdma);
+err_tx_dma:
+ sa1100_free_dma(si->rxdma);
+err_rx_dma:
+ free_irq(dev->irq, dev);
+err_irq:
+ MOD_DEC_USE_COUNT;
+ return err;
+}
+
+static int sa1100_irda_stop(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+
+ disable_irq(dev->irq);
+ sa1100_irda_shutdown(si);
+
+ /*
+ * If we have been doing DMA receive, make sure we
+ * tidy that up cleanly.
+ */
+ if (si->rxskb) {
+ pci_unmap_single(NULL, si->rxbuf_dma, HPSIR_MAX_RXLEN,
+ PCI_DMA_FROMDEVICE);
+ dev_kfree_skb(si->rxskb);
+ si->rxskb = NULL;
+ }
+
+ /* Stop IrLAP */
+ if (si->irlap) {
+ irlap_close(si->irlap);
+ si->irlap = NULL;
+ }
+
+ netif_stop_queue(dev);
+ si->open = 0;
+
+ /*
+ * Free resources
+ */
+ sa1100_free_dma(si->txdma);
+ sa1100_free_dma(si->rxdma);
+ free_irq(dev->irq, dev);
+
+ sa1100_set_power(si, 0);
+
+ MOD_DEC_USE_COUNT;
+
+ return 0;
+}
+
+static int sa1100_irda_init_iobuf(iobuff_t *io, int size)
+{
+ io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
+ if (io->head != NULL) {
+ io->truesize = size;
+ io->in_frame = FALSE;
+ io->state = OUTSIDE_FRAME;
+ io->data = io->head;
+ }
+ return io->head ? 0 : -ENOMEM;
+}
+
+static int sa1100_irda_net_init(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+ unsigned int baudrate_mask;
+ int err = -ENOMEM;
+
+ si = kmalloc(sizeof(struct sa1100_irda), GFP_KERNEL);
+ if (!si)
+ goto out;
+
+ memset(si, 0, sizeof(*si));
+
+ /*
+ * Initialise the HP-SIR buffers
+ */
+ err = sa1100_irda_init_iobuf(&si->rx_buff, 14384);
+ if (err)
+ goto out;
+ err = sa1100_irda_init_iobuf(&si->tx_buff, 4000);
+ if (err)
+ goto out_free_rx;
+
+ dev->priv = si;
+ dev->hard_start_xmit = sa1100_irda_hard_xmit;
+ dev->open = sa1100_irda_start;
+ dev->stop = sa1100_irda_stop;
+ dev->do_ioctl = sa1100_irda_ioctl;
+ dev->get_stats = sa1100_irda_stats;
+
+ irda_device_setup(dev);
+ irda_init_max_qos_capabilies(&si->qos);
+
+ /*
+ * We support original IRDA up to 115k2. (we don't currently
+ * support 4Mbps). Min Turn Time set to 1ms or greater.
+ */
+ baudrate_mask = IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
+ baudrate_mask |= IR_4000000 << 8;
+ si->qos.baud_rate.bits &= baudrate_mask;
+ si->qos.min_turn_time.bits = 7;
+
+ irda_qos_bits_to_value(&si->qos);
+
+ si->utcr4 = UTCR4_HPSIR;
+ if (tx_lpm)
+ si->utcr4 |= UTCR4_Z1_6us;
+
+ /*
+ * Initially enable HP-SIR modulation, and ensure that the port
+ * is disabled.
+ */
+ Ser2UTCR3 = 0;
+ Ser2UTCR4 = si->utcr4;
+ Ser2HSCR0 = HSCR0_UART;
+
+#ifdef CONFIG_PM
+ /*
+ * Power-Management is optional.
+ */
+ si->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, sa1100_irda_pmproc);
+ if (si->pmdev)
+ si->pmdev->data = dev;
+#endif
+
+ return 0;
+
+ kfree(si->tx_buff.head);
+out_free_rx:
+ kfree(si->rx_buff.head);
+out:
+ kfree(si);
+
+ return err;
+}
+
+/*
+ * Remove all traces of this driver module from the kernel, so we can't be
+ * called. Note that the device has already been stopped, so we don't have
+ * to worry about interrupts or dma.
+ */
+static void sa1100_irda_net_uninit(struct net_device *dev)
+{
+ struct sa1100_irda *si = dev->priv;
+
+ dev->hard_start_xmit = NULL;
+ dev->open = NULL;
+ dev->stop = NULL;
+ dev->do_ioctl = NULL;
+ dev->get_stats = NULL;
+ dev->priv = NULL;
+
+ pm_unregister(si->pmdev);
+
+ kfree(si->tx_buff.head);
+ kfree(si->rx_buff.head);
+ kfree(si);
+}
+
+#ifdef MODULE
+static
+#endif
+int __init sa1100_irda_init(void)
+{
+ struct net_device *dev;
+ int err;
+
+ /*
+ * Limit power level a sensible range.
+ */
+ if (power_level < 1)
+ power_level = 1;
+ if (power_level > 3)
+ power_level = 3;
+
+ err = request_mem_region(__PREG(Ser2UTCR0), 0x24, "IrDA") ? 0 : -EBUSY;
+ if (err)
+ goto err_mem_1;
+ err = request_mem_region(__PREG(Ser2HSCR0), 0x1c, "IrDA") ? 0 : -EBUSY;
+ if (err)
+ goto err_mem_2;
+ err = request_mem_region(__PREG(Ser2HSCR2), 0x04, "IrDA") ? 0 : -EBUSY;
+ if (err)
+ goto err_mem_3;
+
+ rtnl_lock();
+ dev = dev_alloc("irda%d", &err);
+ if (dev) {
+ dev->irq = IRQ_Ser2ICP;
+ dev->init = sa1100_irda_net_init;
+ dev->uninit = sa1100_irda_net_uninit;
+
+ err = register_netdevice(dev);
+
+ if (err)
+ kfree(dev);
+ else
+ netdev = dev;
+ }
+ rtnl_unlock();
+
+ if (err) {
+ release_mem_region(__PREG(Ser2HSCR2), 0x04);
+err_mem_3:
+ release_mem_region(__PREG(Ser2HSCR0), 0x1c);
+err_mem_2:
+ release_mem_region(__PREG(Ser2UTCR0), 0x24);
+ }
+err_mem_1:
+ return err;
+}
+
+static void __exit sa1100_irda_exit(void)
+{
+ struct net_device *dev = netdev;
+
+ netdev = NULL;
+ if (dev) {
+ rtnl_lock();
+ unregister_netdevice(dev);
+ rtnl_unlock();
+ }
+
+ release_mem_region(__PREG(Ser2HSCR2), 0x04);
+ release_mem_region(__PREG(Ser2HSCR0), 0x1c);
+ release_mem_region(__PREG(Ser2UTCR0), 0x24);
+
+ /*
+ * We now know that the netdevice is no longer in use, and all
+ * references to our driver have been removed. The only structure
+ * which may still be present is the netdevice, which will get
+ * cleaned up by net/core/dev.c
+ */
+}
+
+#ifdef MODULE
+module_init(sa1100_irda_init);
+module_exit(sa1100_irda_exit);
+#endif
+
+MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
+MODULE_DESCRIPTION("StrongARM SA1100 IrDA driver");
+MODULE_LICENSE("GPL");
+MODULE_PARM(power_level, "i");
+MODULE_PARM_DESC(power_level, "IrDA power level, 1 (low) to 3 (high)");
+MODULE_PARM(tx_lpm, "i");
+MODULE_PARM_DESC(tx_lpm, "Enable transmitter low power (1.6us) mode");
+EXPORT_NO_SYMBOLS;
* use long for ee_addr (various)
* print pointers properly (DaveM)
* include asm/irq.h (?)
+
+ version 1.0.11:
+ * check and reset if PHY errors appear (Adrian Sun)
+ * WoL cleanup (Tim Hockin)
+ * Magic number cleanup (Tim Hockin)
+ * Don't reload EEPROM on every reset (Tim Hockin)
+ * Save and restore EEPROM state across reset (Tim Hockin)
+ * MDIO Cleanup (Tim Hockin)
+ * Reformat register offsets/bits (jgarzik)
TODO:
* big endian support with CFG:BEM instead of cpu_to_le32
*/
#define DRV_NAME "natsemi"
-#define DRV_VERSION "1.07+LK1.0.10"
-#define DRV_RELDATE "Oct 09, 2001"
-
+#define DRV_VERSION "1.07+LK1.0.11"
+#define DRV_RELDATE "Oct 19, 2001"
/* Updated to recommendations in pci-skeleton v2.03. */
c-help-name: National Semiconductor DP8381x series PCI Ethernet support
c-help-symbol: CONFIG_NATSEMI
c-help: This driver is for the National Semiconductor DP8381x series,
-c-help: including the 83815 chip.
+c-help: including the 8381[56] chips.
c-help: More specific information and updates are available from
c-help: http://www.scyld.com/network/natsemi.html
*/
/* The user-configurable values.
These may be modified when a driver module is loaded.*/
-static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
+static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
+
/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
static int max_interrupt_work = 20;
static int mtu;
+
/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
This chip uses a 512 element hash table based on the Ethernet CRC. */
static int multicast_filter_limit = 100;
bonding and packet priority.
There are no ill effects from too-large receive rings. */
#define TX_RING_SIZE 16
-#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
-#define RX_RING_SIZE 32
+#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
+#define RX_RING_SIZE 64
/* Operational parameters that usually are not changed. */
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT (2*HZ)
#define NATSEMI_HW_TIMEOUT 400
+#define NATSEMI_TIMER_FREQ 3*HZ
-#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
+#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
#if !defined(__OPTIMIZE__)
#warning You must compile this file with the correct options!
#include <linux/delay.h>
#include <linux/rtnetlink.h>
#include <linux/mii.h>
-#include <asm/processor.h> /* Processor type for cache alignment. */
+#include <asm/processor.h> /* Processor type for cache alignment. */
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/irq.h>
const char *name;
unsigned long flags;
} natsemi_pci_info[] __devinitdata = {
- { "NatSemi DP83815", PCI_IOTYPE },
+ { "NatSemi DP8381[56]", PCI_IOTYPE },
};
static struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
- { 0x100B, 0x0020, PCI_ANY_ID, PCI_ANY_ID, },
+ { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
device.
*/
enum register_offsets {
- ChipCmd=0x00, ChipConfig=0x04, EECtrl=0x08, PCIBusCfg=0x0C,
- IntrStatus=0x10, IntrMask=0x14, IntrEnable=0x18,
- TxRingPtr=0x20, TxConfig=0x24,
- RxRingPtr=0x30, RxConfig=0x34, ClkRun=0x3C,
- WOLCmd=0x40, PauseCmd=0x44, RxFilterAddr=0x48, RxFilterData=0x4C,
- BootRomAddr=0x50, BootRomData=0x54, SiliconRev=0x58, StatsCtrl=0x5C,
- StatsData=0x60, RxPktErrs=0x60, RxMissed=0x68, RxCRCErrs=0x64,
- BasicControl=0x80, BasicStatus=0x84,
- AnegAdv=0x90, AnegPeer = 0x94, PhyStatus=0xC0, MIntrCtrl=0xC4,
- MIntrStatus=0xC8, PhyCtrl=0xE4,
+ ChipCmd = 0x00,
+ ChipConfig = 0x04,
+ EECtrl = 0x08,
+ PCIBusCfg = 0x0C,
+ IntrStatus = 0x10,
+ IntrMask = 0x14,
+ IntrEnable = 0x18,
+ TxRingPtr = 0x20,
+ TxConfig = 0x24,
+ RxRingPtr = 0x30,
+ RxConfig = 0x34,
+ ClkRun = 0x3C,
+ WOLCmd = 0x40,
+ PauseCmd = 0x44,
+ RxFilterAddr = 0x48,
+ RxFilterData = 0x4C,
+ BootRomAddr = 0x50,
+ BootRomData = 0x54,
+ SiliconRev = 0x58,
+ StatsCtrl = 0x5C,
+ StatsData = 0x60,
+ RxPktErrs = 0x60,
+ RxMissed = 0x68,
+ RxCRCErrs = 0x64,
+ BasicControl = 0x80,
+ BasicStatus = 0x84,
+ AnegAdv = 0x90,
+ AnegPeer = 0x94,
+ PhyStatus = 0xC0,
+ MIntrCtrl = 0xC4,
+ MIntrStatus = 0xC8,
+ PhyCtrl = 0xE4,
/* These are from the spec, around page 78... on a separate table.
* The meaning of these registers depend on the value of PGSEL. */
- PGSEL=0xCC, PMDCSR=0xE4, TSTDAT=0xFC, DSPCFG=0xF4, SDCFG=0x8C
+ PGSEL = 0xCC,
+ PMDCSR = 0xE4,
+ TSTDAT = 0xFC,
+ DSPCFG = 0xF4,
+ SDCFG = 0xF8
};
+/* the values for the 'magic' registers above (PGSEL=1) */
+#define PMDCSR_VAL 0x189C
+#define TSTDAT_VAL 0x0
+#define DSPCFG_VAL 0x5040
+#define SDCFG_VAL 0x008c
/* misc PCI space registers */
-enum PCISpaceRegs {
- PCIPM=0x44,
+enum pci_register_offsets {
+ PCIPM = 0x44,
+};
+
+enum ChipCmd_bits {
+ ChipReset = 0x100,
+ RxReset = 0x20,
+ TxReset = 0x10,
+ RxOff = 0x08,
+ RxOn = 0x04,
+ TxOff = 0x02,
+ TxOn = 0x01,
+};
+
+enum ChipConfig_bits {
+ CfgPhyDis = 0x200,
+ CfgPhyRst = 0x400,
+ CfgAnegEnable = 0x2000,
+ CfgAneg100 = 0x4000,
+ CfgAnegFull = 0x8000,
+ CfgAnegDone = 0x8000000,
+ CfgFullDuplex = 0x20000000,
+ CfgSpeed100 = 0x40000000,
+ CfgLink = 0x80000000,
};
-/* Bit in ChipCmd. */
-enum ChipCmdBits {
- ChipReset=0x100, RxReset=0x20, TxReset=0x10, RxOff=0x08, RxOn=0x04,
- TxOff=0x02, TxOn=0x01,
+enum EECtrl_bits {
+ EE_ShiftClk = 0x04,
+ EE_DataIn = 0x01,
+ EE_ChipSelect = 0x08,
+ EE_DataOut = 0x02,
};
-enum PCIBusCfgBits {
- EepromReload=0x4,
+enum PCIBusCfg_bits {
+ EepromReload = 0x4,
};
/* Bits in the interrupt status/mask registers. */
-enum intr_status_bits {
- IntrRxDone=0x0001, IntrRxIntr=0x0002, IntrRxErr=0x0004, IntrRxEarly=0x0008,
- IntrRxIdle=0x0010, IntrRxOverrun=0x0020,
- IntrTxDone=0x0040, IntrTxIntr=0x0080, IntrTxErr=0x0100,
- IntrTxIdle=0x0200, IntrTxUnderrun=0x0400,
- StatsMax=0x0800, LinkChange=0x4000,
- WOLPkt=0x2000,
- RxResetDone=0x1000000, TxResetDone=0x2000000,
- IntrPCIErr=0x00f00000,
- IntrNormalSummary=0x025f, IntrAbnormalSummary=0xCD20,
+enum IntrStatus_bits {
+ IntrRxDone = 0x0001,
+ IntrRxIntr = 0x0002,
+ IntrRxErr = 0x0004,
+ IntrRxEarly = 0x0008,
+ IntrRxIdle = 0x0010,
+ IntrRxOverrun = 0x0020,
+ IntrTxDone = 0x0040,
+ IntrTxIntr = 0x0080,
+ IntrTxErr = 0x0100,
+ IntrTxIdle = 0x0200,
+ IntrTxUnderrun = 0x0400,
+ StatsMax = 0x0800,
+ SWInt = 0x1000,
+ WOLPkt = 0x2000,
+ LinkChange = 0x4000,
+ IntrHighBits = 0x8000,
+ RxStatusFIFOOver = 0x10000,
+ IntrPCIErr = 0xf00000,
+ RxResetDone = 0x1000000,
+ TxResetDone = 0x2000000,
+ IntrAbnormalSummary = 0xCD20,
};
+/*
+ * Default Interrupts:
+ * Rx OK, Rx Packet Error, Rx Overrun,
+ * Tx OK, Tx Packet Error, Tx Underrun,
+ * MIB Service, Phy Interrupt, High Bits,
+ * Rx Status FIFO overrun,
+ * Received Target Abort, Received Master Abort,
+ * Signalled System Error, Received Parity Error
+ */
#define DEFAULT_INTR 0x00f1cd65
-/* Bits in the RxMode register. */
-enum rx_mode_bits {
- AcceptErr=0x20, AcceptRunt=0x10,
- AcceptBroadcast=0xC0000000,
- AcceptMulticast=0x00200000, AcceptAllMulticast=0x20000000,
- AcceptAllPhys=0x10000000, AcceptMyPhys=0x08000000,
+enum TxConfig_bits {
+ TxDrthMask = 0x3f,
+ TxFlthMask = 0x3f00,
+ TxMxdmaMask = 0x700000,
+ TxMxdma_512 = 0x0,
+ TxMxdma_4 = 0x100000,
+ TxMxdma_8 = 0x200000,
+ TxMxdma_16 = 0x300000,
+ TxMxdma_32 = 0x400000,
+ TxMxdma_64 = 0x500000,
+ TxMxdma_128 = 0x600000,
+ TxMxdma_256 = 0x700000,
+ TxCollRetry = 0x800000,
+ TxAutoPad = 0x10000000,
+ TxMacLoop = 0x20000000,
+ TxHeartIgn = 0x40000000,
+ TxCarrierIgn = 0x80000000
+};
+
+enum RxConfig_bits {
+ RxDrthMask = 0x3e,
+ RxMxdmaMask = 0x700000,
+ RxMxdma_512 = 0x0,
+ RxMxdma_4 = 0x100000,
+ RxMxdma_8 = 0x200000,
+ RxMxdma_16 = 0x300000,
+ RxMxdma_32 = 0x400000,
+ RxMxdma_64 = 0x500000,
+ RxMxdma_128 = 0x600000,
+ RxMxdma_256 = 0x700000,
+ RxAcceptLong = 0x8000000,
+ RxAcceptTx = 0x10000000,
+ RxAcceptRunt = 0x40000000,
+ RxAcceptErr = 0x80000000
};
-/* Bits in WOLCmd register. */
-enum wol_bits {
- WakePhy=0x1, WakeUnicast=0x2, WakeMulticast=0x4, WakeBroadcast=0x8,
- WakeArp=0x10, WakePMatch0=0x20, WakePMatch1=0x40, WakePMatch2=0x80,
- WakePMatch3=0x100, WakeMagic=0x200, WakeMagicSecure=0x400,
- SecureHack=0x100000, WokePhy=0x400000, WokeUnicast=0x800000,
- WokeMulticast=0x1000000, WokeBroadcast=0x2000000, WokeArp=0x4000000,
- WokePMatch0=0x8000000, WokePMatch1=0x10000000, WokePMatch2=0x20000000,
- WokePMatch3=0x40000000, WokeMagic=0x80000000, WakeOptsSummary=0x7ff
+enum ClkRun_bits {
+ PMEEnable = 0x100,
+ PMEStatus = 0x8000,
};
-enum aneg_bits {
- Aneg10BaseT=0x20, Aneg10BaseTFull=0x40,
- Aneg100BaseT=0x80, Aneg100BaseTFull=0x100,
+enum WolCmd_bits {
+ WakePhy = 0x1,
+ WakeUnicast = 0x2,
+ WakeMulticast = 0x4,
+ WakeBroadcast = 0x8,
+ WakeArp = 0x10,
+ WakePMatch0 = 0x20,
+ WakePMatch1 = 0x40,
+ WakePMatch2 = 0x80,
+ WakePMatch3 = 0x100,
+ WakeMagic = 0x200,
+ WakeMagicSecure = 0x400,
+ SecureHack = 0x100000,
+ WokePhy = 0x400000,
+ WokeUnicast = 0x800000,
+ WokeMulticast = 0x1000000,
+ WokeBroadcast = 0x2000000,
+ WokeArp = 0x4000000,
+ WokePMatch0 = 0x8000000,
+ WokePMatch1 = 0x10000000,
+ WokePMatch2 = 0x20000000,
+ WokePMatch3 = 0x40000000,
+ WokeMagic = 0x80000000,
+ WakeOptsSummary = 0x7ff
};
-enum config_bits {
- CfgPhyDis=0x200, CfgPhyRst=0x400, CfgAnegEnable=0x2000,
- CfgAneg100=0x4000, CfgAnegFull=0x8000, CfgAnegDone=0x8000000,
- CfgFullDuplex=0x20000000,
- CfgSpeed100=0x40000000, CfgLink=0x80000000,
+enum RxFilterAddr_bits {
+ RFCRAddressMask = 0x3ff,
+ AcceptMulticast = 0x00200000,
+ AcceptMyPhys = 0x08000000,
+ AcceptAllPhys = 0x10000000,
+ AcceptAllMulticast = 0x20000000,
+ AcceptBroadcast = 0x40000000,
+ RxFilterEnable = 0x80000000
};
-enum bmcr_bits {
- BMCRDuplex=0x100, BMCRAnegRestart=0x200, BMCRAnegEnable=0x1000,
- BMCRSpeed=0x2000, BMCRPhyReset=0x8000,
+enum StatsCtrl_bits {
+ StatsWarn = 0x1,
+ StatsFreeze = 0x2,
+ StatsClear = 0x4,
+ StatsStrobe = 0x8,
};
+enum MIntrCtrl_bits {
+ MICRIntEn = 0x2,
+};
+
+enum PhyCtrl_bits {
+ PhyAddrMask = 0xf,
+};
+
+#define SRR_REV_C 0x0302
+#define SRR_REV_D 0x0403
+
/* The Rx and Tx buffer descriptors. */
/* Note that using only 32 bit fields simplifies conversion to big-endian
architectures. */
/* Bits in network_desc.status */
enum desc_status_bits {
DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
- DescNoCRC=0x10000000,
- DescPktOK=0x08000000, RxTooLong=0x00400000,
+ DescNoCRC=0x10000000, DescPktOK=0x08000000,
+ DescSizeMask=0xfff,
+
+ DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
+ DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
+ DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
+ DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
+
+ DescRxAbort=0x04000000, DescRxOver=0x02000000,
+ DescRxDest=0x01800000, DescRxLong=0x00400000,
+ DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
+ DescRxCRC=0x00080000, DescRxAlign=0x00040000,
+ DescRxLoop=0x00020000, DesRxColl=0x00010000,
};
struct netdev_private {
u32 tx_config, rx_config;
/* original contents of ClkRun register */
u32 SavedClkRun;
+ /* silicon revision */
+ u32 srr;
/* MII transceiver section. */
- u16 advertising; /* NWay media advertisement */
+ u16 advertising; /* NWay media advertisement */
unsigned int iosize;
spinlock_t lock;
};
-static int eeprom_read(long ioaddr, int location);
-static int mdio_read(struct net_device *dev, int phy_id, int location);
+static int eeprom_read(long ioaddr, int location);
+static int mdio_read(struct net_device *dev, int phy_id, int reg);
+static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 data);
static void natsemi_reset(struct net_device *dev);
+static void natsemi_reload_eeprom(struct net_device *dev);
static void natsemi_stop_rxtx(struct net_device *dev);
-static int netdev_open(struct net_device *dev);
+static int netdev_open(struct net_device *dev);
static void check_link(struct net_device *dev);
static void netdev_timer(unsigned long data);
static void tx_timeout(struct net_device *dev);
static void drain_ring(struct net_device *dev);
static void free_ring(struct net_device *dev);
static void init_registers(struct net_device *dev);
-static int start_tx(struct sk_buff *skb, struct net_device *dev);
+static int start_tx(struct sk_buff *skb, struct net_device *dev);
static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
static void netdev_error(struct net_device *dev, int intr_status);
static void netdev_rx(struct net_device *dev);
static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
static void enable_wol_mode(struct net_device *dev, int enable_intr);
-static int netdev_close(struct net_device *dev);
+static int netdev_close(struct net_device *dev);
\f
static int __devinit natsemi_probe1 (struct pci_dev *pdev,
* to be brought to D0 in this manner.
*/
pci_read_config_dword(pdev, PCIPM, &tmp);
- if (tmp & (0x03|0x100)) {
+ if (tmp & PCI_PM_CTRL_STATE_MASK) {
/* D0 state, disable PME assertion */
- u32 newtmp = tmp & ~(0x03|0x100);
+ u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
pci_write_config_dword(pdev, PCIPM, newtmp);
}
spin_lock_init(&np->lock);
/* Reset the chip to erase previous misconfiguration. */
+ natsemi_reload_eeprom(dev);
natsemi_reset(dev);
+
option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
if (dev->mem_start)
option = dev->mem_start;
printk("%2.2x:", dev->dev_addr[i]);
printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
- np->advertising = mdio_read(dev, 1, 4);
+ np->advertising = mdio_read(dev, 1, MII_ADVERTISE);
if ((readl(ioaddr + ChipConfig) & 0xe000) != 0xe000) {
u32 chip_config = readl(ioaddr + ChipConfig);
printk(KERN_INFO "%s: Transceiver default autonegotiation %s "
"10%s %s duplex.\n",
dev->name,
- chip_config & 0x2000 ? "enabled, advertise" : "disabled, force",
- chip_config & 0x4000 ? "0" : "",
- chip_config & 0x8000 ? "full" : "half");
+ chip_config & CfgAnegEnable ? "enabled, advertise" : "disabled, force",
+ chip_config & CfgAneg100 ? "0" : "",
+ chip_config & CfgAnegFull ? "full" : "half");
}
printk(KERN_INFO "%s: Transceiver status 0x%4.4x advertising %4.4x.\n",
- dev->name, (int)readl(ioaddr + BasicStatus),
+ dev->name, (int)mdio_read(dev, 1, MII_BMSR),
np->advertising);
+ /* save the silicon revision for later querying */
+ np->srr = readl(ioaddr + SiliconRev);
+
return 0;
}
*/
#define eeprom_delay(ee_addr) readl(ee_addr)
-enum EEPROM_Ctrl_Bits {
- EE_ShiftClk=0x04, EE_DataIn=0x01, EE_ChipSelect=0x08, EE_DataOut=0x02,
-};
#define EE_Write0 (EE_ChipSelect)
#define EE_Write1 (EE_ChipSelect | EE_DataIn)
The 83815 series has an internal transceiver, and we present the
management registers as if they were MII connected. */
-static int mdio_read(struct net_device *dev, int phy_id, int location)
+static int mdio_read(struct net_device *dev, int phy_id, int reg)
{
- if (phy_id == 1 && location < 32)
- return readl(dev->base_addr+BasicControl+(location<<2))&0xffff;
+ if (phy_id == 1 && reg < 32)
+ return readl(dev->base_addr+BasicControl+(reg<<2))&0xffff;
else
return 0xffff;
}
+static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 data)
+{
+ struct netdev_private *np = dev->priv;
+ if (phy_id == 1 && reg < 32) {
+ writew(data, dev->base_addr+BasicControl+(reg<<2));
+ switch (reg) {
+ case MII_ADVERTISE: np->advertising = data; break;
+ }
+ }
+}
+
+/* CFG bits [13:16] [18:23] */
+#define CFG_RESET_SAVE 0xfde000
+/* WCSR bits [0:4] [9:10] */
+#define WCSR_RESET_SAVE 0x61f
+/* RFCR bits [20] [22] [27:31] */
+#define RFCR_RESET_SAVE 0xf8500000;
+
static void natsemi_reset(struct net_device *dev)
{
int i;
+ u32 cfg;
+ u32 wcsr;
+ u32 rfcr;
+ u16 pmatch[3];
+ u16 sopass[3];
+
+ /*
+ * Resetting the chip causes some registers to be lost.
+ * Natsemi suggests NOT reloading the EEPROM while live, so instead
+ * we save the state that would have been loaded from EEPROM
+ * on a normal power-up (see the spec EEPROM map). This assumes
+ * whoever calls this will follow up with init_registers() eventually.
+ */
+ /* CFG */
+ cfg = readl(dev->base_addr + ChipConfig) & CFG_RESET_SAVE;
+ /* WCSR */
+ wcsr = readl(dev->base_addr + WOLCmd) & WCSR_RESET_SAVE;
+ /* RFCR */
+ rfcr = readl(dev->base_addr + RxFilterAddr) & RFCR_RESET_SAVE;
+ /* PMATCH */
+ for (i = 0; i < 3; i++) {
+ writel(i*2, dev->base_addr + RxFilterAddr);
+ pmatch[i] = readw(dev->base_addr + RxFilterData);
+ }
+ /* SOPAS */
+ for (i = 0; i < 3; i++) {
+ writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
+ sopass[i] = readw(dev->base_addr + RxFilterData);
+ }
+
+ /* now whack the chip */
writel(ChipReset, dev->base_addr + ChipCmd);
for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
if (!(readl(dev->base_addr + ChipCmd) & ChipReset))
dev->name, i*5);
}
+ /* restore CFG */
+ cfg |= readl(dev->base_addr + ChipConfig) & ~CFG_RESET_SAVE;
+ writel(cfg, dev->base_addr + ChipConfig);
+ /* restore WCSR */
+ wcsr |= readl(dev->base_addr + WOLCmd) & ~WCSR_RESET_SAVE;
+ writel(wcsr, dev->base_addr + WOLCmd);
+ /* read RFCR */
+ rfcr |= readl(dev->base_addr + RxFilterAddr) & ~RFCR_RESET_SAVE;
+ /* restore PMATCH */
+ for (i = 0; i < 3; i++) {
+ writel(i*2, dev->base_addr + RxFilterAddr);
+ writew(pmatch[i], dev->base_addr + RxFilterData);
+ }
+ for (i = 0; i < 3; i++) {
+ writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
+ writew(sopass[i], dev->base_addr + RxFilterData);
+ }
+ /* restore RFCR */
+ writel(rfcr, dev->base_addr + RxFilterAddr);
+
+}
+
+static void natsemi_reload_eeprom(struct net_device *dev)
+{
+ int i;
+
writel(EepromReload, dev->base_addr + PCIBusCfg);
for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
if (!(readl(dev->base_addr + PCIBusCfg) & EepromReload))
/* Set the timer to check for link beat. */
init_timer(&np->timer);
- np->timer.expires = jiffies + 3*HZ;
+ np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
np->timer.data = (unsigned long)dev;
- np->timer.function = &netdev_timer; /* timer handler */
+ np->timer.function = &netdev_timer; /* timer handler */
add_timer(&np->timer);
return 0;
int duplex;
int chipcfg = readl(ioaddr + ChipConfig);
- if(!(chipcfg & 0x80000000)) {
+ if(!(chipcfg & CfgLink)) {
if (netif_carrier_ok(dev)) {
if (debug)
printk(KERN_INFO "%s: no link. Disabling watchdog.\n",
netif_carrier_on(dev);
}
- duplex = np->full_duplex || (chipcfg & 0x20000000 ? 1 : 0);
+ duplex = np->full_duplex || (chipcfg & CfgFullDuplex ? 1 : 0);
/* if duplex is set then bit 28 must be set, too */
- if (duplex ^ !!(np->rx_config & 0x10000000)) {
+ if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
if (debug)
printk(KERN_INFO "%s: Setting %s-duplex based on negotiated link"
" capability.\n", dev->name,
duplex ? "full" : "half");
if (duplex) {
- np->rx_config |= 0x10000000;
- np->tx_config |= 0xC0000000;
+ np->rx_config |= RxAcceptTx;
+ np->tx_config |= TxCarrierIgn | TxHeartIgn;
} else {
- np->rx_config &= ~0x10000000;
- np->tx_config &= ~0xC0000000;
+ np->rx_config &= ~RxAcceptTx;
+ np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
}
writel(np->tx_config, ioaddr + TxConfig);
writel(np->rx_config, ioaddr + RxConfig);
long ioaddr = dev->base_addr;
int i;
+ /* save the silicon revision for later */
if (debug > 4)
printk(KERN_DEBUG "%s: found silicon revision %xh.\n",
- dev->name, readl(ioaddr + SiliconRev));
+ dev->name, np->srr);
+
+ for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
+ if (readl(dev->base_addr + ChipConfig) & CfgAnegDone)
+ break;
+ udelay(10);
+ }
+ if (i==NATSEMI_HW_TIMEOUT && debug) {
+ printk(KERN_INFO
+ "%s: autonegotiation did not complete in %d usec.\n",
+ dev->name, i*10);
+ }
/* On page 78 of the spec, they recommend some settings for "optimum
performance" to be done in sequence. These settings optimize some
Kennedy) recommends always setting them. If you don't, you get
errors on some autonegotiations that make the device unusable.
*/
- writew(0x0001, ioaddr + PGSEL);
- writew(0x189C, ioaddr + PMDCSR);
- writew(0x0000, ioaddr + TSTDAT);
- writew(0x5040, ioaddr + DSPCFG);
- writew(0x008C, ioaddr + SDCFG);
- writew(0x0000, ioaddr + PGSEL);
+ writew(1, ioaddr + PGSEL);
+ writew(PMDCSR_VAL, ioaddr + PMDCSR);
+ writew(TSTDAT_VAL, ioaddr + TSTDAT);
+ writew(DSPCFG_VAL, ioaddr + DSPCFG);
+ writew(SDCFG_VAL, ioaddr + SDCFG);
+ writew(0, ioaddr + PGSEL);
/* Enable PHY Specific event based interrupts. Link state change
and Auto-Negotiation Completion are among the affected.
+ Read the intr status to clear it (needed for wake events).
*/
- writew(0x0002, ioaddr + MIntrCtrl);
+ readw(ioaddr + MIntrStatus);
+ writew(MICRIntEn, ioaddr + MIntrCtrl);
- writel(np->ring_dma, ioaddr + RxRingPtr);
- writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), ioaddr + TxRingPtr);
+ /* clear any interrupts that are pending, such as wake events */
+ readl(ioaddr + IntrStatus);
- for (i = 0; i < ETH_ALEN; i += 2) {
- writel(i, ioaddr + RxFilterAddr);
- writew(dev->dev_addr[i] + (dev->dev_addr[i+1] << 8),
- ioaddr + RxFilterData);
- }
+ writel(np->ring_dma, ioaddr + RxRingPtr);
+ writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
+ ioaddr + TxRingPtr);
/* Initialize other registers.
* Configure the PCI bus bursts and FIFO thresholds.
* ECRETRY=1
* ATP=1
*/
- np->tx_config = 0x10f01002;
+ np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
+ writel(np->tx_config, ioaddr + TxConfig);
+
/* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
* MXDMA 0: up to 256 byte bursts
*/
- np->rx_config = 0x700020;
- writel(np->tx_config, ioaddr + TxConfig);
+ np->rx_config = RxMxdma_256 | 0x20;
writel(np->rx_config, ioaddr + RxConfig);
/* Disable PME:
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
np->SavedClkRun = readl(ioaddr + ClkRun);
- writel(np->SavedClkRun & ~0x100, ioaddr + ClkRun);
+ writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
+ if (np->SavedClkRun & PMEStatus) {
+ printk(KERN_NOTICE "%s: Wake-up event %8.8x\n",
+ dev->name, readl(ioaddr + WOLCmd));
+ }
check_link(dev);
__set_rx_mode(dev);
/* Enable interrupts by setting the interrupt mask. */
- writel(DEFAULT_INTR, ioaddr + IntrMask);
+ writel(DEFAULT_INTR, ioaddr + IntrMask);
writel(1, ioaddr + IntrEnable);
writel(RxOn | TxOn, ioaddr + ChipCmd);
- writel(4, ioaddr + StatsCtrl); /* Clear Stats */
+ writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
}
+/*
+ * The frequency on this has been increased because of a nasty little problem.
+ * It seems that a reference set for this chip went out with incorrect info,
+ * and there exist boards that aren't quite right. An unexpected voltage drop
+ * can cause the PHY to get itself in a weird state (basically reset..).
+ * NOTE: this only seems to affect revC chips.
+ */
static void netdev_timer(unsigned long data)
{
struct net_device *dev = (struct net_device *)data;
struct netdev_private *np = dev->priv;
- int next_tick = 60*HZ;
+ int next_tick = 5*HZ;
+ long ioaddr = dev->base_addr;
+ u16 dspcfg;
if (debug > 3) {
/* DO NOT read the IntrStatus register,
printk(KERN_DEBUG "%s: Media selection timer tick.\n",
dev->name);
}
- spin_lock_irq(&np->lock);
- check_link(dev);
- spin_unlock_irq(&np->lock);
- np->timer.expires = jiffies + next_tick;
- add_timer(&np->timer);
+
+ /* check for a nasty random phy-reset - use dspcfg as a flag */
+ writew(1, ioaddr+PGSEL);
+ dspcfg = readw(ioaddr+DSPCFG);
+ writew(0, ioaddr+PGSEL);
+ if (dspcfg != DSPCFG_VAL) {
+ if (!netif_queue_stopped(dev)) {
+ printk(KERN_INFO
+ "%s: possible phy reset: re-initializing\n",
+ dev->name);
+ disable_irq(dev->irq);
+ spin_lock_irq(&np->lock);
+ init_registers(dev);
+ spin_unlock_irq(&np->lock);
+ enable_irq(dev->irq);
+ } else {
+ /* hurry back */
+ next_tick = HZ;
+ }
+ } else {
+ /* init_registers() calls check_link() for the above case */
+ spin_lock_irq(&np->lock);
+ check_link(dev);
+ spin_unlock_irq(&np->lock);
+ }
+ mod_timer(&np->timer, jiffies + next_tick);
}
static void dump_ring(struct net_device *dev)
if (debug > 2) {
int i;
printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
- for (i = 0; i < TX_RING_SIZE; i++)
+ for (i = 0; i < TX_RING_SIZE; i++) {
printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
i, np->tx_ring[i].next_desc,
- np->tx_ring[i].cmd_status, np->tx_ring[i].addr);
+ np->tx_ring[i].cmd_status,
+ np->tx_ring[i].addr);
+ }
printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
for (i = 0; i < RX_RING_SIZE; i++) {
printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
i, np->rx_ring[i].next_desc,
- np->rx_ring[i].cmd_status, np->rx_ring[i].addr);
+ np->rx_ring[i].cmd_status,
+ np->rx_ring[i].addr);
}
}
}
struct netdev_private *np = dev->priv;
long ioaddr = dev->base_addr;
-
disable_irq(dev->irq);
spin_lock_irq(&np->lock);
if (netif_device_present(dev)) {
printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
- " resetting...\n", dev->name, readl(ioaddr + IntrStatus));
+ " resetting...\n",
+ dev->name, readl(ioaddr + IntrStatus));
dump_ring(dev);
natsemi_reset(dev);
init_ring(dev);
init_registers(dev);
} else {
- printk(KERN_WARNING "%s: tx_timeout while in suspended state?\n",
- dev->name);
+ printk(KERN_WARNING
+ "%s: tx_timeout while in suspended state?\n",
+ dev->name);
}
spin_unlock_irq(&np->lock);
enable_irq(dev->irq);
for (i = 0; i < RX_RING_SIZE; i++) {
np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
+sizeof(struct netdev_desc)
- *((i+1)%RX_RING_SIZE));
+ *((i+1)%RX_RING_SIZE));
np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
np->rx_skbuff[i] = NULL;
}
if (netif_device_present(dev)) {
np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
- /* StrongARM: Explicitly cache flush np->tx_ring and skb->data,skb->len. */
+ /* StrongARM: Explicitly cache flush np->tx_ring and
+ * skb->data,skb->len. */
wmb();
np->cur_tx++;
if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
printk(KERN_DEBUG "%s: tx frame #%d finished with status %8.8xh.\n",
dev->name, np->dirty_tx,
le32_to_cpu(np->tx_ring[entry].cmd_status));
- if (np->tx_ring[entry].cmd_status & cpu_to_le32(0x08000000)) {
+ if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
np->stats.tx_packets++;
np->stats.tx_bytes += np->tx_skbuff[entry]->len;
- } else { /* Various Tx errors */
+ } else { /* Various Tx errors */
int tx_status = le32_to_cpu(np->tx_ring[entry].cmd_status);
- if (tx_status & 0x04010000) np->stats.tx_aborted_errors++;
- if (tx_status & 0x02000000) np->stats.tx_fifo_errors++;
- if (tx_status & 0x01000000) np->stats.tx_carrier_errors++;
- if (tx_status & 0x00200000) np->stats.tx_window_errors++;
+ if (tx_status & (DescTxAbort|DescTxExcColl))
+ np->stats.tx_aborted_errors++;
+ if (tx_status & DescTxFIFO)
+ np->stats.tx_fifo_errors++;
+ if (tx_status & DescTxCarrier)
+ np->stats.tx_carrier_errors++;
+ if (tx_status & DescTxOOWCol)
+ np->stats.tx_window_errors++;
np->stats.tx_errors++;
}
pci_unmap_single(np->pci_dev,np->tx_dma[entry],
}
} while (1);
- if (debug > 3)
+ if (debug > 4)
printk(KERN_DEBUG "%s: exiting interrupt.\n",
dev->name);
}
entry, desc_status);
if (--boguscnt < 0)
break;
- if ((desc_status & (DescMore|DescPktOK|RxTooLong)) != DescPktOK) {
+ if ((desc_status & (DescMore|DescPktOK|DescRxLong)) != DescPktOK) {
if (desc_status & DescMore) {
printk(KERN_WARNING "%s: Oversized(?) Ethernet frame spanned "
"multiple buffers, entry %#x status %x.\n",
printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
desc_status);
np->stats.rx_errors++;
- if (desc_status & 0x06000000) np->stats.rx_over_errors++;
- if (desc_status & 0x00600000) np->stats.rx_length_errors++;
- if (desc_status & 0x00140000) np->stats.rx_frame_errors++;
- if (desc_status & 0x00080000) np->stats.rx_crc_errors++;
+ if (desc_status & (DescRxAbort|DescRxOver))
+ np->stats.rx_over_errors++;
+ if (desc_status & (DescRxLong|DescRxRunt))
+ np->stats.rx_length_errors++;
+ if (desc_status & (DescRxInvalid|DescRxAlign))
+ np->stats.rx_frame_errors++;
+ if (desc_status & DescRxCRC)
+ np->stats.rx_crc_errors++;
}
} else {
struct sk_buff *skb;
- int pkt_len = (desc_status & 0x0fff) - 4; /* Omit CRC size. */
+ /* Omit CRC size. */
+ int pkt_len = (desc_status & DescSizeMask) - 4;
/* Check if the packet is long enough to accept without copying
to a minimally-sized skbuff. */
if (pkt_len < rx_copybreak
spin_lock(&np->lock);
if (intr_status & LinkChange) {
- printk(KERN_NOTICE "%s: Link changed: Autonegotiation advertising"
- " %4.4x partner %4.4x.\n", dev->name,
- (int)readl(ioaddr + AnegAdv),
- (int)readl(ioaddr + AnegPeer));
+ printk(KERN_NOTICE
+ "%s: Link changed: Autonegotiation advertising"
+ " %4.4x partner %4.4x.\n", dev->name,
+ (int)mdio_read(dev, 1, MII_ADVERTISE),
+ (int)mdio_read(dev, 1, MII_LPA));
/* read MII int status to clear the flag */
readw(ioaddr + MIntrStatus);
check_link(dev);
__get_stats(dev);
}
if (intr_status & IntrTxUnderrun) {
- if ((np->tx_config & 0x3f) < 62)
+ if ((np->tx_config & TxDrthMask) < 62)
np->tx_config += 2;
if (debug > 2)
printk(KERN_NOTICE "%s: increasing Tx theshold, new tx cfg %8.8xh.\n",
printk(KERN_NOTICE "%s: Link wake-up event %8.8x\n",
dev->name, wol_status);
}
- if ((intr_status & ~(LinkChange|StatsMax|RxResetDone|TxResetDone|0xA7ff))
- && debug)
- printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
- dev->name, intr_status);
+ if (intr_status & RxStatusFIFOOver && debug) {
+ printk(KERN_NOTICE "%s: Rx status FIFO overrun\n", dev->name);
+ }
/* Hmmmmm, it's not clear how to recover from PCI faults. */
if (intr_status & IntrPCIErr) {
+ if (debug) {
+ printk(KERN_NOTICE "%s: PCI error %08x\n", dev->name,
+ intr_status & IntrPCIErr);
+ }
np->stats.tx_fifo_errors++;
np->stats.rx_fifo_errors++;
}
if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
/* Unconditionally log net taps. */
printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
- rx_mode = AcceptBroadcast | AcceptAllMulticast | AcceptAllPhys
- | AcceptMyPhys;
+ rx_mode = RxFilterEnable | AcceptBroadcast
+ | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
} else if ((dev->mc_count > multicast_filter_limit)
|| (dev->flags & IFF_ALLMULTI)) {
- rx_mode = AcceptBroadcast | AcceptAllMulticast | AcceptMyPhys;
+ rx_mode = RxFilterEnable | AcceptBroadcast
+ | AcceptAllMulticast | AcceptMyPhys;
} else {
struct dev_mc_list *mclist;
int i;
set_bit_le(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff,
mc_filter);
}
- rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
+ rx_mode = RxFilterEnable | AcceptBroadcast
+ | AcceptMulticast | AcceptMyPhys;
for (i = 0; i < 64; i += 2) {
writew(HASH_TABLE + i, ioaddr + RxFilterAddr);
- writew((mc_filter[i+1]<<8) + mc_filter[i], ioaddr + RxFilterData);
+ writew((mc_filter[i+1]<<8) + mc_filter[i],
+ ioaddr + RxFilterData);
}
}
writel(rx_mode, ioaddr + RxFilterAddr);
static int netdev_set_wol(struct net_device *dev, u32 newval)
{
+ struct netdev_private *np = dev->priv;
u32 data = readl(dev->base_addr + WOLCmd) & ~WakeOptsSummary;
/* translate to bitmasks this chip understands */
data |= WakeArp;
if (newval & WAKE_MAGIC)
data |= WakeMagic;
- if (newval & WAKE_MAGICSECURE)
- data |= WakeMagicSecure;
+ if (np->srr >= SRR_REV_D) {
+ if (newval & WAKE_MAGICSECURE) {
+ data |= WakeMagicSecure;
+ }
+ }
writel(data, dev->base_addr + WOLCmd);
- /* should we burn these into the EEPROM? */
-
return 0;
}
static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
{
+ struct netdev_private *np = dev->priv;
u32 regval = readl(dev->base_addr + WOLCmd);
*supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
- | WAKE_ARP | WAKE_MAGIC | WAKE_MAGICSECURE);
+ | WAKE_ARP | WAKE_MAGIC);
+
+ if (np->srr >= SRR_REV_D) {
+ /* SOPASS works on revD and higher */
+ *supported |= WAKE_MAGICSECURE;
+ }
*cur = 0;
+
/* translate from chip bitmasks */
- if (regval & 0x1)
+ if (regval & WakePhy)
*cur |= WAKE_PHY;
- if (regval & 0x2)
+ if (regval & WakeUnicast)
*cur |= WAKE_UCAST;
- if (regval & 0x4)
+ if (regval & WakeMulticast)
*cur |= WAKE_MCAST;
- if (regval & 0x8)
+ if (regval & WakeBroadcast)
*cur |= WAKE_BCAST;
- if (regval & 0x10)
+ if (regval & WakeArp)
*cur |= WAKE_ARP;
- if (regval & 0x200)
+ if (regval & WakeMagic)
*cur |= WAKE_MAGIC;
- if (regval & 0x400)
+ if (regval & WakeMagicSecure) {
+ /* this can be on in revC, but it's broken */
*cur |= WAKE_MAGICSECURE;
+ }
return 0;
}
static int netdev_set_sopass(struct net_device *dev, u8 *newval)
{
+ struct netdev_private *np = dev->priv;
u16 *sval = (u16 *)newval;
- u32 addr = readl(dev->base_addr + RxFilterAddr) & ~0x3ff;
+ u32 addr;
+
+ if (np->srr < SRR_REV_D) {
+ return 0;
+ }
/* enable writing to these registers by disabling the RX filter */
- addr &= ~0x80000000;
+ addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
+ addr &= ~RxFilterEnable;
writel(addr, dev->base_addr + RxFilterAddr);
/* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
writew(sval[2], dev->base_addr + RxFilterData);
/* re-enable the RX filter */
- writel(addr | 0x80000000, dev->base_addr + RxFilterAddr);
-
- /* should we burn this into the EEPROM? */
+ writel(addr | RxFilterEnable, dev->base_addr + RxFilterAddr);
return 0;
}
static int netdev_get_sopass(struct net_device *dev, u8 *data)
{
+ struct netdev_private *np = dev->priv;
u16 *sval = (u16 *)data;
- u32 addr = readl(dev->base_addr + RxFilterAddr) & ~0x3ff;
+ u32 addr;
+
+ if (np->srr < SRR_REV_D) {
+ sval[0] = sval[1] = sval[2] = 0;
+ return 0;
+ }
/* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
+ addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
+
writel(addr | 0xa, dev->base_addr + RxFilterAddr);
sval[0] = readw(dev->base_addr + RxFilterData);
writel(addr | 0xe, dev->base_addr + RxFilterAddr);
sval[2] = readw(dev->base_addr + RxFilterData);
+ writel(addr, dev->base_addr + RxFilterAddr);
+
return 0;
}
ecmd->transceiver = XCVR_INTERNAL;
/* this isn't fully supported at higher layers */
- ecmd->phy_address = readw(dev->base_addr + PhyCtrl) & 0xf;
+ ecmd->phy_address = readw(dev->base_addr + PhyCtrl) & PhyAddrMask;
- tmp = readl(dev->base_addr + AnegAdv);
ecmd->advertising = ADVERTISED_TP;
- if (tmp & Aneg10BaseT)
+ tmp = mdio_read(dev, 1, MII_ADVERTISE);
+ if (tmp & ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
- if (tmp & Aneg10BaseTFull)
+ if (tmp & ADVERTISE_10FULL)
ecmd->advertising |= ADVERTISED_10baseT_Full;
- if (tmp & Aneg100BaseT)
+ if (tmp & ADVERTISE_100HALF)
ecmd->advertising |= ADVERTISED_100baseT_Half;
- if (tmp & Aneg100BaseTFull)
+ if (tmp & ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
tmp = readl(dev->base_addr + ChipConfig);
}
writel(tmp, dev->base_addr + ChipConfig);
/* turn on autonegotiation, and force a renegotiate */
- tmp = readl(dev->base_addr + BasicControl);
- tmp |= BMCRAnegEnable | BMCRAnegRestart;
- writel(tmp, dev->base_addr + BasicControl);
- np->advertising = mdio_read(dev, 1, 4);
+ tmp = mdio_read(dev, 1, MII_BMCR);
+ tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ mdio_write(dev, 1, MII_BMCR, tmp);
+ np->advertising = mdio_read(dev, 1, MII_ADVERTISE);
} else {
/* turn off auto negotiation, set speed and duplexity */
- tmp = readl(dev->base_addr + BasicControl);
- tmp &= ~(BMCRAnegEnable | BMCRSpeed | BMCRDuplex);
+ tmp = mdio_read(dev, 1, MII_BMCR);
+ tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
if (ecmd->speed == SPEED_100) {
- tmp |= BMCRSpeed;
+ tmp |= BMCR_SPEED100;
}
if (ecmd->duplex == DUPLEX_FULL) {
- tmp |= BMCRDuplex;
+ tmp |= BMCR_FULLDPLX;
} else {
np->full_duplex = 0;
}
- writel(tmp, dev->base_addr + BasicControl);
+ mdio_write(dev, 1, MII_BMCR, tmp);
}
return 0;
}
static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
- struct netdev_private *np = dev->priv;
struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
switch(cmd) {
case SIOCGMIIREG: /* Read MII PHY register. */
case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
- data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
+ data->val_out = mdio_read(dev, data->phy_id & 0x1f,
+ data->reg_num & 0x1f);
return 0;
case SIOCSMIIREG: /* Write MII PHY register. */
case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
if (!capable(CAP_NET_ADMIN))
return -EPERM;
- if (data->phy_id == 1) {
- u16 miireg = data->reg_num & 0x1f;
- u16 value = data->val_in;
- writew(value, dev->base_addr + BasicControl
- + (miireg << 2));
- switch (miireg) {
- case 4: np->advertising = value; break;
- }
- }
+ mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f,
+ data->val_in);
return 0;
default:
return -EOPNOTSUPP;
static void enable_wol_mode(struct net_device *dev, int enable_intr)
{
long ioaddr = dev->base_addr;
+ struct netdev_private *np = dev->priv;
if (debug > 1)
printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
dev->name);
+
/* For WOL we must restart the rx process in silent mode.
* Write NULL to the RxRingPtr. Only possible if
* rx process is stopped
*/
writel(0, ioaddr + RxRingPtr);
+ /* read WoL status to clear */
+ readl(ioaddr + WOLCmd);
+
+ /* PME on, clear status */
+ writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
+
/* and restart the rx process */
writel(RxOn, ioaddr + ChipCmd);
struct netdev_private *np = dev->priv;
netif_stop_queue(dev);
+ netif_carrier_off(dev);
if (debug > 1) {
- printk(KERN_DEBUG "%s: Shutting down ethercard, status was %4.4x.\n",
+ printk(KERN_DEBUG "%s: Shutting down ethercard, status was %4.4x.\n",
dev->name, (int)readl(ioaddr + ChipCmd));
printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
disable_irq(dev->irq);
spin_lock_irq(&np->lock);
+ /* Disable and clear interrupts */
writel(0, ioaddr + IntrEnable);
- writel(0, ioaddr + IntrMask);
- writel(2, ioaddr + StatsCtrl); /* Freeze Stats */
+ readl(ioaddr + IntrMask);
+ readw(ioaddr + MIntrStatus);
+
+ /* Freeze Stats */
+ writel(StatsFreeze, ioaddr + StatsCtrl);
/* Stop the chip's Tx and Rx processes. */
natsemi_stop_rxtx(dev);
{
u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
- u32 clkrun = np->SavedClkRun;
- /* Restore PME enable bit */
if (wol) {
/* restart the NIC in WOL mode.
* The nic must be stopped for this.
*/
enable_wol_mode(dev, 0);
- /* make sure to enable PME */
- clkrun |= 0x100;
+ } else {
+ /* Restore PME enable bit unmolested */
+ writel(np->SavedClkRun, ioaddr + ClkRun);
}
- writel(clkrun, ioaddr + ClkRun);
-#if 0
- writel(0x0200, ioaddr + ChipConfig); /* Power down Xcvr. */
-#endif
}
return 0;
}
* * intr_handler: doesn't acquire the spinlock. suspend calls
* disable_irq() to enforce synchronization.
*
- * netif_device_detach must occur under spin_unlock_irq(), interrupts from a detached
- * device would cause an irq storm.
+ * netif_device_detach must occur under spin_unlock_irq(), interrupts from a
+ * detached device would cause an irq storm.
*/
static int natsemi_suspend (struct pci_dev *pdev, u32 state)
drain_ring(dev);
{
u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
- u32 clkrun = np->SavedClkRun;
/* Restore PME enable bit */
if (wol) {
/* restart the NIC in WOL mode.
* FIXME: use the WOL interupt
*/
enable_wol_mode(dev, 0);
- /* make sure to enable PME */
- clkrun |= 0x100;
+ } else {
+ /* Restore PME enable bit unmolested */
+ writel(np->SavedClkRun, ioaddr + ClkRun);
}
- writel(clkrun, ioaddr + ClkRun);
}
} else {
netif_device_detach(dev);
netif_device_attach(dev);
spin_unlock_irq(&np->lock);
- np->timer.expires = jiffies + 1*HZ;
- add_timer(&np->timer);
+ mod_timer(&np->timer, jiffies + 1*HZ);
} else {
netif_device_attach(dev);
}
#include <linux/init.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
-#include <asm/processor.h> /* Processor type for cache alignment. */
+
+#include <asm/io.h>
+#include <asm/processor.h> /* Processor type for cache alignment. */
#include <asm/uaccess.h>
#include <linux/delay.h>
#include <linux/if_ether.h>
+#include <asm/byteorder.h>
/*
* Limits and constants
0011 National PCI System I/O
0012 USB Controller
0020 DP83815
+ 0022 DP83820
d001 87410 IDE
100c Tseng Labs Inc
3202 ET4000/W32p rev A
1384 Reality Simulation Systems Inc
1385 Netgear
620a GA620
+ 622a GA622
f311 FA311
1386 Video Domain Technologies
1387 Systran Corp
if [ "$CONFIG_PCI" != "n" ]; then
bool ' CardBus support' CONFIG_CARDBUS
fi
+ bool ' i82092 compatible bridge support' CONFIG_I82092
bool ' i82365 compatible bridge support' CONFIG_I82365
bool ' Databook TCIC host bridge support' CONFIG_TCIC
if [ "$CONFIG_HD64465" = "y" ]; then
ifeq ($(CONFIG_I82365),y)
obj-y += i82365.o
endif
+ ifeq ($(CONFIG_I82092),y)
+ obj-y += i82092.o
+ endif
ifeq ($(CONFIG_TCIC),y)
obj-y += tcic.o
endif
ifeq ($(CONFIG_I82365),y)
obj-m += i82365.o
endif
+ ifeq ($(CONFIG_I82092),y)
+ obj-m += i82092.o
+ endif
ifeq ($(CONFIG_TCIC),y)
obj-m += tcic.o
endif
if (signal_pending(current))
return -EINTR;
}
- put_user(get_queued_event(user), (int *)buf);
- return 4;
+
+ return put_user(get_queued_event(user), (int *)buf) ? -EFAULT : 4;
} /* ds_read */
/*====================================================================*/
--- /dev/null
+/*
+ * Driver for Intel I82092AA PCI-PCMCIA bridge.
+ *
+ * (C) 2001 Red Hat, Inc.
+ *
+ * Author: Arjan Van De Ven <arjanv@redhat.com>
+ * Loosly based on i82365.c from the pcmcia-cs package
+ *
+ * $Id: i82092aa.c,v 1.2 2001/10/23 14:43:34 arjanv Exp $
+ */
+
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <pcmcia/cs_types.h>
+#include <pcmcia/ss.h>
+#include <pcmcia/cs.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+
+#include "i82092aa.h"
+#include "i82365.h"
+
+/* PCI core routines */
+static struct pci_device_id i82092aa_pci_ids[] = {
+ {
+ vendor:PCI_VENDOR_ID_INTEL,
+ device:PCI_DEVICE_ID_INTEL_82092AA_0,
+ subvendor:PCI_ANY_ID,
+ subdevice:PCI_ANY_ID,
+ class: 0, class_mask:0,
+
+ },
+ {}
+};
+
+static struct pci_driver i82092aa_pci_drv = {
+ name: "i82092aa",
+ id_table: i82092aa_pci_ids,
+ probe: i82092aa_pci_probe,
+ remove: i82092aa_pci_remove,
+ suspend: NULL,
+ resume: NULL
+};
+
+
+/* the pccard structure and its functions */
+static struct pccard_operations i82092aa_operations = {
+ init: i82092aa_init,
+ suspend: i82092aa_suspend,
+ register_callback: i82092aa_register_callback,
+ inquire_socket: i82092aa_inquire_socket,
+ get_status: i82092aa_get_status,
+ get_socket: i82092aa_get_socket,
+ set_socket: i82092aa_set_socket,
+ get_io_map: i82092aa_get_io_map,
+ set_io_map: i82092aa_set_io_map,
+ get_mem_map: i82092aa_get_mem_map,
+ set_mem_map: i82092aa_set_mem_map,
+ proc_setup: i82092aa_proc_setup,
+};
+
+/* The card can do upto 4 sockets, allocate a structure for each of them */
+
+struct socket_info {
+ int card_state; /* 0 = no socket,
+ 1 = empty socket,
+ 2 = card but not initialized,
+ 3 = operational card */
+ int io_base; /* base io address of the socket */
+ socket_cap_t cap;
+
+ unsigned int pending_events; /* Pending events on this interface */
+
+ void (*handler)(void *info, u_int events);
+ /* callback to the driver of the card */
+ void *info; /* to be passed to the handler */
+
+ struct pci_dev *dev; /* The PCI device for the socket */
+};
+
+#define MAX_SOCKETS 4
+static struct socket_info sockets[MAX_SOCKETS];
+static int socket_count; /* shortcut */
+
+
+static int __init i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+ unsigned char configbyte;
+ int i;
+
+ enter("i82092aa_pci_probe");
+
+ if (pci_enable_device(dev))
+ return -EIO;
+
+ pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */
+ switch(configbyte&6) {
+ case 0:
+ printk(KERN_INFO "i82092aa: configured as a 2 socket device.\n");
+ socket_count = 2;
+ break;
+ case 2:
+ printk(KERN_INFO "i82092aa: configured as a 1 socket device.\n");
+ socket_count = 1;
+ break;
+ case 4:
+ case 6:
+ printk(KERN_INFO "i82092aa: configured as a 4 socket device.\n");
+ socket_count = 4;
+ break;
+
+ default:
+ printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
+ return -EIO;
+ break;
+ }
+
+ for (i = 0;i<socket_count;i++) {
+ sockets[i].card_state = 1; /* 1 = present but empty */
+ sockets[i].io_base = (dev->resource[0].start & ~1);
+ if (sockets[i].io_base > 0)
+ request_region(sockets[i].io_base, 2, "i82092aa");
+
+
+ sockets[i].cap.features |= SS_CAP_PCCARD;
+ sockets[i].cap.map_size = 0x1000;
+ sockets[i].cap.irq_mask = 0;
+ sockets[i].cap.pci_irq = dev->irq;
+
+ if (card_present(i)) {
+ sockets[i].card_state = 3;
+ dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i);
+ } else {
+ dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i);
+ }
+ }
+
+ /* Now, specifiy that all interrupts are to be done as PCI interrupts */
+ configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
+ pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
+
+
+ /* Register the interrupt handler */
+ dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
+ if (request_irq(dev->irq, i82092aa_interrupt, SA_SHIRQ, "i82092aa", i82092aa_interrupt)) {
+ printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
+ return -EIO;
+ }
+
+
+ if (register_ss_entry(socket_count, &i82092aa_operations) != 0)
+ printk(KERN_NOTICE "i82092aa: register_ss_entry() failed\n");
+
+ leave("i82092aa_pci_probe");
+ return 0;
+}
+
+static void __exit i82092aa_pci_remove(struct pci_dev *dev)
+{
+ enter("i82092aa_pci_remove");
+
+ free_irq(dev->irq, i82092aa_interrupt);
+
+ leave("i82092aa_pci_remove");
+}
+
+static spinlock_t port_lock = SPIN_LOCK_UNLOCKED;
+
+/* basic value read/write functions */
+
+static unsigned char indirect_read(int socket, unsigned short reg)
+{
+ unsigned short int port;
+ unsigned char val;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg += socket * 0x40;
+ port = sockets[socket].io_base;
+ outb(reg,port);
+ val = inb(port+1);
+ spin_unlock_irqrestore(&port_lock,flags);
+ return val;
+}
+
+static unsigned short indirect_read16(int socket, unsigned short reg)
+{
+ unsigned short int port;
+ unsigned short tmp;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg = reg + socket * 0x40;
+ port = sockets[socket].io_base;
+ outb(reg,port);
+ tmp = inb(port+1);
+ reg++;
+ outb(reg,port);
+ tmp = tmp | (inb(port+1)<<8);
+ spin_unlock_irqrestore(&port_lock,flags);
+ return tmp;
+}
+
+static void indirect_write(int socket, unsigned short reg, unsigned char value)
+{
+ unsigned short int port;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg = reg + socket * 0x40;
+ port = sockets[socket].io_base;
+ outb(reg,port);
+ outb(value,port+1);
+ spin_unlock_irqrestore(&port_lock,flags);
+}
+
+static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
+{
+ unsigned short int port;
+ unsigned char val;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg = reg + socket * 0x40;
+ port = sockets[socket].io_base;
+ outb(reg,port);
+ val = inb(port+1);
+ val |= mask;
+ outb(reg,port);
+ outb(val,port+1);
+ spin_unlock_irqrestore(&port_lock,flags);
+}
+
+
+static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask)
+{
+ unsigned short int port;
+ unsigned char val;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg = reg + socket * 0x40;
+ port = sockets[socket].io_base;
+ outb(reg,port);
+ val = inb(port+1);
+ val &= ~mask;
+ outb(reg,port);
+ outb(val,port+1);
+ spin_unlock_irqrestore(&port_lock,flags);
+}
+
+static void indirect_write16(int socket, unsigned short reg, unsigned short value)
+{
+ unsigned short int port;
+ unsigned char val;
+ unsigned long flags;
+ spin_lock_irqsave(&port_lock,flags);
+ reg = reg + socket * 0x40;
+ port = sockets[socket].io_base;
+
+ outb(reg,port);
+ val = value & 255;
+ outb(val,port+1);
+
+ reg++;
+
+ outb(reg,port);
+ val = value>>8;
+ outb(val,port+1);
+ spin_unlock_irqrestore(&port_lock,flags);
+}
+
+/* simple helper functions */
+/* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
+static int cycle_time = 120;
+
+static int to_cycles(int ns)
+{
+ if (cycle_time!=0)
+ return ns/cycle_time;
+ else
+ return 0;
+}
+
+static int to_ns(int cycles)
+{
+ return cycle_time*cycles;
+}
+
+
+/* Interrupt handler functionality */
+
+static void i82092aa_bh(void *dummy)
+{
+ unsigned int events;
+ int i;
+
+ for (i=0; i < socket_count; i++) {
+ events = xchg(&(sockets[i].pending_events),0);
+ printk("events = %x \n",events);
+ if (sockets[i].handler)
+ sockets[i].handler(sockets[i].info, events);
+ }
+}
+
+
+static struct tq_struct i82092aa_task = {
+ routine: i82092aa_bh
+};
+
+
+static void i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+ int i;
+ int loopcount = 0;
+
+ unsigned int events, active=0;
+
+/* enter("i82092aa_interrupt");*/
+
+ while (1) {
+ loopcount++;
+ if (loopcount>20) {
+ printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n");
+ break;
+ }
+
+ active = 0;
+
+ for (i=0;i<socket_count;i++) {
+ int csc;
+ if (sockets[i].card_state==0) /* Inactive socket, should not happen */
+ continue;
+
+ csc = indirect_read(i,I365_CSC); /* card status change register */
+
+ if ((csc==0) || /* no events on this socket */
+ (sockets[i].handler==NULL)) /* no way to handle events */
+ continue;
+ events = 0;
+
+ if (csc & I365_CSC_DETECT) {
+ events |= SS_DETECT;
+ printk("Card detected in socket %i!\n",i);
+ }
+
+ if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) {
+ /* For IO/CARDS, bit 0 means "read the card" */
+ events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
+ } else {
+ /* Check for battery/ready events */
+ events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
+ events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
+ events |= (csc & I365_CSC_READY) ? SS_READY : 0;
+ }
+
+ if (events) {
+ sockets[i].pending_events |= events;
+ schedule_task(&i82092aa_task);
+ }
+ active |= events;
+ }
+
+ if (active==0) /* no more events to handle */
+ break;
+
+ }
+
+/* leave("i82092aa_interrupt");*/
+}
+
+
+
+/* socket functions */
+
+static int card_present(int socketno)
+{
+ unsigned int val;
+ enter("card_present");
+
+ if ((socketno<0) || (socketno > MAX_SOCKETS))
+ return 0;
+ if (sockets[socketno].io_base == 0)
+ return 0;
+
+
+ val = indirect_read(socketno, 1); /* Interface status register */
+ if ((val&12)==12) {
+ leave("card_present 1");
+ return 1;
+ }
+
+ leave("card_present 0");
+ return 0;
+}
+
+static void set_bridge_state(int sock)
+{
+ enter("set_bridge_state");
+ indirect_write(sock, I365_GBLCTL,0x00);
+ indirect_write(sock, I365_GENCTL,0x00);
+
+ indirect_setbit(sock, I365_INTCTL,0x08);
+ leave("set_bridge_state");
+}
+
+
+
+
+
+
+static int i82092aa_init(unsigned int s)
+{
+ int i;
+ pccard_io_map io = { 0, 0, 0, 0, 1 };
+ pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
+
+ enter("i82092aa_init");
+
+ mem.sys_stop = 0x0fff;
+ i82092aa_set_socket(s, &dead_socket);
+ for (i = 0; i < 2; i++) {
+ io.map = i;
+ i82092aa_set_io_map(s, &io);
+ }
+ for (i = 0; i < 5; i++) {
+ mem.map = i;
+ i82092aa_set_mem_map(s, &mem);
+ }
+
+ leave("i82092aa_init");
+ return 0;
+}
+
+static int i82092aa_suspend(unsigned int sock)
+{
+ int retval;
+ enter("i82092aa_suspend");
+ retval = i82092aa_set_socket(sock, &dead_socket);
+ leave("i82092aa_suspend");
+ return retval;
+}
+
+static int i82092aa_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info)
+{
+ enter("i82092aa_register_callback");
+ sockets[sock].handler = handler;
+ sockets[sock].info = info;
+ if (handler == NULL) {
+ MOD_DEC_USE_COUNT;
+ } else {
+ MOD_INC_USE_COUNT;
+ }
+ leave("i82092aa_register_callback");
+ return 0;
+} /* i82092aa_register_callback */
+
+static int i82092aa_inquire_socket(unsigned int sock, socket_cap_t *cap)
+{
+ enter("i82092aa_inquire_socket");
+ *cap = sockets[sock].cap;
+ leave("i82092aa_inquire_socket");
+ return 0;
+} /* i82092aa_inquire_socket */
+
+
+static int i82092aa_get_status(unsigned int sock, u_int *value)
+{
+ unsigned int status;
+
+ enter("i82092aa_get_status");
+
+ status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
+ *value = 0;
+
+ if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
+ *value |= SS_DETECT;
+ }
+
+ /* IO cards have a different meaning of bits 0,1 */
+ /* Also notice the inverse-logic on the bits */
+ if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
+ /* IO card */
+ if (!(status & I365_CS_STSCHG))
+ *value |= SS_STSCHG;
+ } else { /* non I/O card */
+ if (!(status & I365_CS_BVD1))
+ *value |= SS_BATDEAD;
+ if (!(status & I365_CS_BVD2))
+ *value |= SS_BATWARN;
+
+ }
+
+ if (status & I365_CS_WRPROT)
+ (*value) |= SS_WRPROT; /* card is write protected */
+
+ if (status & I365_CS_READY)
+ (*value) |= SS_READY; /* card is not busy */
+
+ if (status & I365_CS_POWERON)
+ (*value) |= SS_POWERON; /* power is applied to the card */
+
+
+ leave("i82092aa_get_status");
+ return 0;
+}
+
+
+static int i82092aa_get_socket(unsigned int sock, socket_state_t *state)
+{
+ unsigned char reg,vcc,vpp;
+
+ enter("i82092aa_get_socket");
+ state->flags = 0;
+ state->Vcc = 0;
+ state->Vpp = 0;
+ state->io_irq = 0;
+ state->csc_mask = 0;
+
+ /* First the power status of the socket */
+ reg = indirect_read(sock,I365_POWER); /* PCTRL - Power Control Register */
+
+ if (reg & I365_PWR_AUTO)
+ state->flags |= SS_PWR_AUTO; /* Automatic Power Switch */
+
+ if (reg & I365_PWR_OUT)
+ state->flags |= SS_OUTPUT_ENA; /* Output signals are enabled */
+
+ vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
+
+ if (reg & I365_VCC_5V) { /* Can still be 3.3V, in this case the Vcc value will be overwritten later */
+ state->Vcc = 50;
+
+ if (vpp == I365_VPP1_5V)
+ state->Vpp = 50;
+ if (vpp == I365_VPP1_12V)
+ state->Vpp = 120;
+
+ }
+
+ if ((reg & I365_VCC_3V)==I365_VCC_3V)
+ state->Vcc = 33;
+
+
+ /* Now the IO card, RESET flags and IO interrupt */
+
+ reg = indirect_read(sock, I365_INTCTL); /* IGENC, Interrupt and General Control */
+
+ if ((reg & I365_PC_RESET)==0)
+ state->flags |= SS_RESET;
+ if (reg & I365_PC_IOCARD)
+ state->flags |= SS_IOCARD; /* This is an IO card */
+
+ /* Set the IRQ number */
+ if (sockets[sock].dev!=NULL)
+ state->io_irq = sockets[sock].dev->irq;
+
+ /* Card status change */
+ reg = indirect_read(sock, I365_CSCINT); /* CSCICR, Card Status Change Interrupt Configuration */
+
+ if (reg & I365_CSC_DETECT)
+ state->csc_mask |= SS_DETECT; /* Card detect is enabled */
+
+ if (state->flags & SS_IOCARD) {/* IO Cards behave different */
+ if (reg & I365_CSC_STSCHG)
+ state->csc_mask |= SS_STSCHG;
+ } else {
+ if (reg & I365_CSC_BVD1)
+ state->csc_mask |= SS_BATDEAD;
+ if (reg & I365_CSC_BVD2)
+ state->csc_mask |= SS_BATWARN;
+ if (reg & I365_CSC_READY)
+ state->csc_mask |= SS_READY;
+ }
+
+ leave("i82092aa_get_socket");
+ return 0;
+}
+
+static int i82092aa_set_socket(unsigned int sock, socket_state_t *state)
+{
+ unsigned char reg;
+
+ enter("i82092aa_set_socket");
+
+ /* First, set the global controller options */
+
+ set_bridge_state(sock);
+
+ /* Values for the IGENC register */
+
+ reg = 0;
+ if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */
+ reg = reg | I365_PC_RESET;
+ if (state->flags & SS_IOCARD)
+ reg = reg | I365_PC_IOCARD;
+
+ indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
+
+ /* Power registers */
+
+ reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
+
+ if (state->flags & SS_PWR_AUTO) {
+ printk("Auto power\n");
+ reg |= I365_PWR_AUTO; /* automatic power mngmnt */
+ }
+ if (state->flags & SS_OUTPUT_ENA) {
+ printk("Power Enabled \n");
+ reg |= I365_PWR_OUT; /* enable power */
+ }
+
+ switch (state->Vcc) {
+ case 0:
+ break;
+ case 50:
+ printk("setting voltage to Vcc to 5V on socket %i\n",sock);
+ reg |= I365_VCC_5V;
+ break;
+ default:
+ printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
+ leave("i82092aa_set_socket");
+ return -EINVAL;
+ }
+
+
+ switch (state->Vpp) {
+ case 0:
+ printk("not setting Vpp on socket %i\n",sock);
+ break;
+ case 50:
+ printk("setting Vpp to 5.0 for socket %i\n",sock);
+ reg |= I365_VPP1_5V | I365_VPP2_5V;
+ break;
+ case 120:
+ printk("setting Vpp to 12.0\n");
+ reg |= I365_VPP1_12V | I365_VPP2_12V;
+ break;
+ default:
+ printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
+ leave("i82092aa_set_socket");
+ return -EINVAL;
+ }
+
+ if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
+ indirect_write(sock,I365_POWER,reg);
+
+ /* Enable specific interrupt events */
+
+ reg = 0x00;
+ if (state->csc_mask & SS_DETECT) {
+ reg |= I365_CSC_DETECT;
+ }
+ if (state->flags & SS_IOCARD) {
+ if (state->csc_mask & SS_STSCHG)
+ reg |= I365_CSC_STSCHG;
+ } else {
+ if (state->csc_mask & SS_BATDEAD)
+ reg |= I365_CSC_BVD1;
+ if (state->csc_mask & SS_BATWARN)
+ reg |= I365_CSC_BVD2;
+ if (state->csc_mask & SS_READY)
+ reg |= I365_CSC_READY;
+
+ }
+
+ /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
+
+ indirect_write(sock,I365_CSCINT,reg);
+ (void)indirect_read(sock,I365_CSC);
+
+ leave("i82092aa_set_socket");
+ return 0;
+}
+
+static int i82092aa_get_io_map(unsigned int sock, struct pccard_io_map *io)
+{
+ unsigned char map, ioctl, addr;
+
+ enter("i82092aa_get_io_map");
+ map = io->map;
+ if (map > 1) {
+ leave("i82092aa_get_io_map with -EINVAL");
+ return -EINVAL;
+ }
+
+ /* FIXME: How does this fit in with the PCI resource (re)allocation */
+ io->start = indirect_read16(sock, I365_IO(map)+I365_W_START);
+ io->stop = indirect_read16(sock, I365_IO(map)+I365_W_START);
+
+ ioctl = indirect_read(sock,I365_IOCTL); /* IOCREG: I/O Control Register */
+ addr = indirect_read(sock,I365_ADDRWIN); /* */
+
+ io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0; /* check this out later */
+ io->flags = 0;
+
+ if (addr & I365_IOCTL_16BIT(map))
+ io->flags |= MAP_AUTOSZ;
+
+ leave("i82092aa_get_io_map");
+ return 0;
+}
+
+static int i82092aa_set_io_map(unsigned sock, struct pccard_io_map *io)
+{
+ unsigned char map, ioctl;
+
+ enter("i82092aa_set_io_map");
+
+ map = io->map;
+
+ /* Check error conditions */
+ if (map > 1) {
+ leave("i82092aa_set_io_map with invalid map");
+ return -EINVAL;
+ }
+ if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
+ leave("i82092aa_set_io_map with invalid io");
+ return -EINVAL;
+ }
+
+ /* Turn off the window before changing anything */
+ if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
+ indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
+
+/* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */
+
+ /* write the new values */
+ indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);
+ indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);
+
+ ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
+
+ if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
+ ioctl |= I365_IOCTL_16BIT(map);
+
+ indirect_write(sock,I365_IOCTL,ioctl);
+
+ /* Turn the window back on if needed */
+ if (io->flags & MAP_ACTIVE)
+ indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
+
+ leave("i82092aa_set_io_map");
+ return 0;
+}
+
+static int i82092aa_get_mem_map(unsigned sock, struct pccard_mem_map *mem)
+{
+ unsigned short base, i;
+ unsigned char map, addr;
+
+ enter("i82092aa_get_mem_map");
+
+ mem->flags = 0;
+ mem->speed = 0;
+ map = mem->map;
+ if (map > 4) {
+ leave("i82092aa_get_mem_map: -EINVAL");
+ return -EINVAL;
+ }
+
+ addr = indirect_read(sock, I365_ADDRWIN);
+
+ if (addr & I365_ENA_MEM(map))
+ mem->flags |= MAP_ACTIVE; /* yes this mapping is active */
+
+ base = I365_MEM(map);
+
+ /* Find the start address - this register also has mapping info */
+
+ i = indirect_read16(sock,base+I365_W_START);
+ if (i & I365_MEM_16BIT)
+ mem->flags |= MAP_16BIT;
+ if (i & I365_MEM_0WS)
+ mem->flags |= MAP_0WS;
+
+ mem->sys_start = ((unsigned long)(i & 0x0fff) << 12);
+
+ /* Find the end address - this register also has speed info */
+ i = indirect_read16(sock,base+I365_W_STOP);
+ if (i & I365_MEM_WS0)
+ mem->speed = 1;
+ if (i & I365_MEM_WS1)
+ mem->speed += 2;
+ mem->speed = to_ns(mem->speed);
+ mem->sys_stop = ( (unsigned long)(i & 0x0fff) << 12) + 0x0fff;
+
+ /* Find the card start address, also some more MAP attributes */
+
+ i = indirect_read16(sock, base+I365_W_OFF);
+ if (i & I365_MEM_WRPROT)
+ mem->flags |= MAP_WRPROT;
+ if (i & I365_MEM_REG)
+ mem->flags |= MAP_ATTRIB;
+ mem->card_start = ( (unsigned long)(i & 0x3fff)<12) + mem->sys_start;
+ mem->card_start &= 0x3ffffff;
+
+ printk("Card %i is from %x to %x \n",sock,mem->sys_start,mem->sys_stop);
+
+ leave("i82092aa_get_mem_map");
+ return 0;
+
+}
+
+static int i82092aa_set_mem_map(unsigned sock, struct pccard_mem_map *mem)
+{
+ unsigned short base, i;
+ unsigned char map;
+
+ enter("i82092aa_set_mem_map");
+
+ map = mem->map;
+ if (map > 4) {
+ leave("i82092aa_set_mem_map: invalid map");
+ return -EINVAL;
+ }
+
+
+ if ( (mem->card_start > 0x3ffffff) || (mem->sys_start > mem->sys_stop) ||
+ (mem->speed > 1000) ) {
+ leave("i82092aa_set_mem_map: invalid address / speed");
+ printk("invalid mem map for socket %i : %x to %x with a start of %x \n",sock,mem->sys_start, mem->sys_stop, mem->card_start);
+ return -EINVAL;
+ }
+
+ /* Turn off the window before changing anything */
+ if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
+ indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
+
+
+/* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, mem->sys_start,mem->sys_stop,sock,mem->speed,mem->flags & MAP_ACTIVE); */
+
+ /* write the start address */
+ base = I365_MEM(map);
+ i = (mem->sys_start >> 12) & 0x0fff;
+ if (mem->flags & MAP_16BIT)
+ i |= I365_MEM_16BIT;
+ if (mem->flags & MAP_0WS)
+ i |= I365_MEM_0WS;
+ indirect_write16(sock,base+I365_W_START,i);
+
+ /* write the stop address */
+
+ i= (mem->sys_stop >> 12) & 0x0fff;
+ switch (to_cycles(mem->speed)) {
+ case 0:
+ break;
+ case 1:
+ i |= I365_MEM_WS0;
+ break;
+ case 2:
+ i |= I365_MEM_WS1;
+ break;
+ default:
+ i |= I365_MEM_WS1 | I365_MEM_WS0;
+ break;
+ }
+
+ indirect_write16(sock,base+I365_W_STOP,i);
+
+ /* card start */
+
+ i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
+ if (mem->flags & MAP_WRPROT)
+ i |= I365_MEM_WRPROT;
+ if (mem->flags & MAP_ATTRIB) {
+/* printk("requesting attribute memory for socket %i\n",sock);*/
+ i |= I365_MEM_REG;
+ } else {
+/* printk("requesting normal memory for socket %i\n",sock);*/
+ }
+ indirect_write16(sock,base+I365_W_OFF,i);
+
+ /* Enable the window if necessary */
+ if (mem->flags & MAP_ACTIVE)
+ indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
+
+ leave("i82092aa_set_mem_map");
+ return 0;
+}
+
+static void i82092aa_proc_setup(unsigned int sock, struct proc_dir_entry *base)
+{
+
+}
+/* Module stuff */
+
+static int i82092aa_module_init(void)
+{
+ enter("i82092aa_module_init");
+ pci_register_driver(&i82092aa_pci_drv);
+ leave("i82092aa_module_init");
+ return 0;
+}
+
+static void i82092aa_module_exit(void)
+{
+ int i;
+ enter("i82092aa_module_exit");
+ pci_unregister_driver(&i82092aa_pci_drv);
+ unregister_ss_entry(&i82092aa_operations);
+ if (sockets[0].io_base>0)
+ release_region(sockets[0].io_base, 2);
+ leave("i82092aa_module_exit");
+}
+
+module_init(i82092aa_module_init);
+module_exit(i82092aa_module_exit);
+
--- /dev/null
+#ifndef _INCLUDE_GUARD_i82092aa_H_
+#define _INCLUDE_GUARD_i82092aa_H_
+
+/* $Id: i82092aa.h,v 1.1.1.1 2001/09/19 14:53:15 dwmw2 Exp $ */
+
+/* Debuging defines */
+#ifdef NOTRACE
+#define enter(x) printk("Enter: %s, %s line %i\n",x,__FILE__,__LINE__)
+#define leave(x) printk("Leave: %s, %s line %i\n",x,__FILE__,__LINE__)
+#define dprintk printk
+#else
+#define enter(x) do {} while (0)
+#define leave(x) do {} while (0)
+#define dprintk(...) do {} while (0)
+#endif
+
+
+
+/* prototypes */
+
+static int i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id);
+static void i82092aa_pci_remove(struct pci_dev *dev);
+static int card_present(int socketno);
+static void i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs);
+
+
+
+
+static int i82092aa_get_status(unsigned int sock, u_int *value);
+static int i82092aa_get_socket(unsigned int sock, socket_state_t *state);
+static int i82092aa_set_socket(unsigned int sock, socket_state_t *state);
+static int i82092aa_get_io_map(unsigned int sock, struct pccard_io_map *io);
+static int i82092aa_set_io_map(unsigned int sock, struct pccard_io_map *io);
+static int i82092aa_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
+static int i82092aa_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
+static int i82092aa_init(unsigned int s);
+static int i82092aa_suspend(unsigned int sock);
+static int i82092aa_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info);
+static int i82092aa_inquire_socket(unsigned int sock, socket_cap_t *cap);
+static void i82092aa_proc_setup(unsigned int sock, struct proc_dir_entry *base);
+
+#endif
+
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/pcmcia.h>
-
+#include <asm/arch/assabet.h>
static int assabet_pcmcia_init(struct pcmcia_init *init){
int irq, res;
/* Enable CF bus: */
- BCR_clear(BCR_CF_BUS_OFF);
+ ASSABET_BCR_clear(ASSABET_BCR_CF_BUS_OFF);
/* All those are inputs */
- GPDR &= ~(GPIO_CF_CD | GPIO_CF_BVD2 | GPIO_CF_BVD1 | GPIO_CF_IRQ);
+ GPDR &= ~(ASSABET_GPIO_CF_CD | ASSABET_GPIO_CF_BVD2 | ASSABET_GPIO_CF_BVD1 | ASSABET_GPIO_CF_IRQ);
/* Set transition detect */
- set_GPIO_IRQ_edge( GPIO_CF_CD|GPIO_CF_BVD2|GPIO_CF_BVD1, GPIO_BOTH_EDGES );
- set_GPIO_IRQ_edge( GPIO_CF_IRQ, GPIO_FALLING_EDGE );
+ set_GPIO_IRQ_edge( ASSABET_GPIO_CF_CD|ASSABET_GPIO_CF_BVD2|ASSABET_GPIO_CF_BVD1, GPIO_BOTH_EDGES );
+ set_GPIO_IRQ_edge( ASSABET_GPIO_CF_IRQ, GPIO_FALLING_EDGE );
/* Register interrupts */
- irq = IRQ_GPIO_CF_CD;
+ irq = ASSABET_IRQ_GPIO_CF_CD;
res = request_irq( irq, init->handler, SA_INTERRUPT, "CF_CD", NULL );
if( res < 0 ) goto irq_err;
- irq = IRQ_GPIO_CF_BVD2;
+ irq = ASSABET_IRQ_GPIO_CF_BVD2;
res = request_irq( irq, init->handler, SA_INTERRUPT, "CF_BVD2", NULL );
if( res < 0 ) goto irq_err;
- irq = IRQ_GPIO_CF_BVD1;
+ irq = ASSABET_IRQ_GPIO_CF_BVD1;
res = request_irq( irq, init->handler, SA_INTERRUPT, "CF_BVD1", NULL );
if( res < 0 ) goto irq_err;
static int assabet_pcmcia_shutdown(void)
{
/* disable IRQs */
- free_irq( IRQ_GPIO_CF_CD, NULL );
- free_irq( IRQ_GPIO_CF_BVD2, NULL );
- free_irq( IRQ_GPIO_CF_BVD1, NULL );
+ free_irq( ASSABET_IRQ_GPIO_CF_CD, NULL );
+ free_irq( ASSABET_IRQ_GPIO_CF_BVD2, NULL );
+ free_irq( ASSABET_IRQ_GPIO_CF_BVD1, NULL );
/* Disable CF bus: */
- BCR_set(BCR_CF_BUS_OFF);
+ ASSABET_BCR_set(ASSABET_BCR_CF_BUS_OFF);
return 0;
}
levels=GPLR;
- state_array->state[1].detect=((levels & GPIO_CF_CD)==0)?1:0;
+ state_array->state[1].detect=((levels & ASSABET_GPIO_CF_CD)==0)?1:0;
- state_array->state[1].ready=(levels & GPIO_CF_IRQ)?1:0;
+ state_array->state[1].ready=(levels & ASSABET_GPIO_CF_IRQ)?1:0;
- state_array->state[1].bvd1=(levels & GPIO_CF_BVD1)?1:0;
+ state_array->state[1].bvd1=(levels & ASSABET_GPIO_CF_BVD1)?1:0;
- state_array->state[1].bvd2=(levels & GPIO_CF_BVD2)?1:0;
+ state_array->state[1].bvd2=(levels & ASSABET_GPIO_CF_BVD2)?1:0;
state_array->state[1].wrprot=0; /* Not available on Assabet. */
if(info->sock>1) return -1;
if(info->sock==1)
- info->irq=IRQ_GPIO_CF_IRQ;
+ info->irq=ASSABET_IRQ_GPIO_CF_IRQ;
return 0;
}
switch(configure->vcc){
case 0:
- value &= ~BCR_CF_PWR;
+ value &= ~ASSABET_BCR_CF_PWR;
break;
case 50:
__FUNCTION__);
case 33: /* Can only apply 3.3V to the CF slot. */
- value |= BCR_CF_PWR;
+ value |= ASSABET_BCR_CF_PWR;
break;
default:
return -1;
}
- value = (configure->reset) ? (value | BCR_CF_RST) : (value & ~BCR_CF_RST);
+ value = (configure->reset) ? (value | ASSABET_BCR_CF_RST) : (value & ~ASSABET_BCR_CF_RST);
/* Silently ignore Vpp, output enable, speaker enable. */
- BCR = BCR_value = value;
+ ASSABET_BCR = BCR_value = value;
restore_flags(flags);
static int cerf_pcmcia_init(struct pcmcia_init *init){
int irq, res;
- /* Enable CF bus: */
-// BCR_clear(BCR_CF_BUS_OFF);
-
- /* All those are inputs */
GPDR &= ~(GPIO_CF_CD | GPIO_CF_BVD2 | GPIO_CF_BVD1 | GPIO_CF_IRQ);
+ GPDR |= (GPIO_CF_RESET);
- /* Set transition detect */
set_GPIO_IRQ_edge( GPIO_CF_CD|GPIO_CF_BVD2|GPIO_CF_BVD1, GPIO_BOTH_EDGES );
set_GPIO_IRQ_edge( GPIO_CF_IRQ, GPIO_FALLING_EDGE );
- /* Register interrupts */
irq = IRQ_GPIO_CF_CD;
res = request_irq( irq, init->handler, SA_INTERRUPT, "CF_CD", NULL );
if( res < 0 ) goto irq_err;
res = request_irq( irq, init->handler, SA_INTERRUPT, "CF_BVD1", NULL );
if( res < 0 ) goto irq_err;
- /* There's only one slot, but it's "Slot 1": */
return 2;
irq_err:
static int cerf_pcmcia_shutdown(void)
{
- /* disable IRQs */
free_irq( IRQ_GPIO_CF_CD, NULL );
free_irq( IRQ_GPIO_CF_BVD2, NULL );
free_irq( IRQ_GPIO_CF_BVD1, NULL );
-
- /* Disable CF bus: */
-// BCR_set(BCR_CF_BUS_OFF);
return 0;
}
static int cerf_pcmcia_socket_state(struct pcmcia_state_array
*state_array){
unsigned long levels;
+#ifdef CONFIG_SA1100_CERF_CPLD
+ int i = 0;
+#else
+ int i = 1;
+#endif
if(state_array->size<2) return -1;
levels=GPLR;
- state_array->state[1].detect=((levels & GPIO_CF_CD)==0)?1:0;
+ state_array->state[i].detect=((levels & GPIO_CF_CD)==0)?1:0;
- state_array->state[1].ready=(levels & GPIO_CF_IRQ)?1:0;
+ state_array->state[i].ready=(levels & GPIO_CF_IRQ)?1:0;
- state_array->state[1].bvd1=(levels & GPIO_CF_BVD1)?1:0;
+ state_array->state[i].bvd1=(levels & GPIO_CF_BVD1)?1:0;
- state_array->state[1].bvd2=(levels & GPIO_CF_BVD2)?1:0;
+ state_array->state[i].bvd2=(levels & GPIO_CF_BVD2)?1:0;
- state_array->state[1].wrprot=0; /* Not available on Assabet. */
+ state_array->state[i].wrprot=0;
- state_array->state[1].vs_3v=1; /* Can only apply 3.3V on Assabet. */
+ state_array->state[i].vs_3v=1;
- state_array->state[1].vs_Xv=0;
+ state_array->state[i].vs_Xv=0;
return 1;
}
if(info->sock>1) return -1;
+#ifdef CONFIG_SA1100_CERF_CPLD
+ if(info->sock==0)
+#else
if(info->sock==1)
+#endif
info->irq=IRQ_GPIO_CF_IRQ;
return 0;
static int cerf_pcmcia_configure_socket(const struct pcmcia_configure
*configure)
{
- unsigned long value, flags;
+ unsigned long flags;
- if(configure->sock>1) return -1;
+ if(configure->sock>1)
+ return -1;
- if(configure->sock==0) return 0;
+#ifdef CONFIG_SA1100_CERF_CPLD
+ if(configure->sock==1)
+#else
+ if(configure->sock==0)
+#endif
+ return 0;
save_flags_cli(flags);
-// value = BCR_value;
-
switch(configure->vcc){
case 0:
-// value &= ~BCR_CF_PWR;
break;
case 50:
- printk(KERN_WARNING "%s(): CS asked for 5V, applying 3.3V...\n",
- __FUNCTION__);
-
- case 33: /* Can only apply 3.3V to the CF slot. */
-// value |= BCR_CF_PWR;
- break;
+ case 33:
+#ifdef CONFIG_SA1100_CERF_CPLD
+ GPDR |= GPIO_PWR_SHUTDOWN;
+ GPCR |= GPIO_PWR_SHUTDOWN;
+#endif
+ break;
default:
printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__,
return -1;
}
-// value = (configure->reset) ? (value | BCR_CF_RST) : (value & ~BCR_CF_RST);
-
- /* Silently ignore Vpp, output enable, speaker enable. */
-
-// BCR = BCR_value = value;
+ if(configure->reset)
+ {
+#ifdef CONFIG_SA1100_CERF_CPLD
+ GPDR |= GPIO_CF_RESET;
+ GPSR |= GPIO_CF_RESET;
+#endif
+ }
+ else
+ {
+#ifdef CONFIG_SA1100_CERF_CPLD
+ GPDR |= GPIO_CF_RESET;
+ GPCR |= GPIO_CF_RESET;
+#endif
+ }
restore_flags(flags);
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
+#include <asm/arch/assabet.h>
#include "sa1100.h"
*
* Returns: 0
*/
-static int sa1100_pcmcia_suspend(unsigned int sock){
+static int sa1100_pcmcia_suspend(unsigned int sock)
+{
+ struct pcmcia_configure conf;
+ int ret;
DEBUG(2, "%s(): suspending socket %u\n", __FUNCTION__, sock);
- return 0;
+ conf.sock = sock;
+ conf.vcc = 0;
+ conf.vpp = 0;
+ conf.output = 0;
+ conf.speaker = 0;
+ conf.reset = 1;
+
+ ret = pcmcia_low_level->configure_socket(&conf);
+
+ if (ret == 0)
+ sa1100_pcmcia_socket[sock].cs_state = dead_socket;
+
+ return ret;
}
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/pcmcia.h>
+#include <asm/arch/assabet.h>
static int neponset_pcmcia_init(struct pcmcia_init *init){
int return_val=0;
/*
- * drivers/pcmcia/sa1100_pangolin.c
+ * drivers/pcmcia/sa1100_simpad.c
*
* PCMCIA implementation routines for simpad
*
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/pcmcia.h>
+
+extern long get_cs3_shadow(void);
+extern void set_cs3_bit(int value);
+extern void clear_cs3_bit(int value);
+
static int simpad_pcmcia_init(struct pcmcia_init *init){
int irq, res;
/* set GPIO_CF_CD & GPIO_CF_IRQ as inputs */
GPDR &= ~(GPIO_CF_CD|GPIO_CF_IRQ);
- //init_simpad_cs3();
- printk("\nCS3:%x\n",cs3_shadow);
- PCMCIA_setbit(PCMCIA_RESET);
- PCMCIA_clearbit(PCMCIA_BUFF_DIS);
+
+ set_cs3_bit(PCMCIA_RESET);
+ clear_cs3_bit(PCMCIA_BUFF_DIS);
+ clear_cs3_bit(PCMCIA_RESET);
+
+ clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
/* Set transition detect */
set_GPIO_IRQ_edge( GPIO_CF_CD, GPIO_BOTH_EDGES );
{
/* disable IRQs */
free_irq( IRQ_GPIO_CF_CD, NULL );
-
+
/* Disable CF bus: */
-
- PCMCIA_setbit(PCMCIA_BUFF_DIS);
- PCMCIA_clearbit(PCMCIA_RESET);
+
+ //set_cs3_bit(PCMCIA_BUFF_DIS);
+ clear_cs3_bit(PCMCIA_RESET);
+
return 0;
}
*state_array)
{
unsigned long levels;
+ unsigned long *cs3reg = CS3_BASE;
if(state_array->size<2) return -1;
- memset(state_array->state, 0,
+ memset(state_array->state, 0,
(state_array->size)*sizeof(struct pcmcia_state));
levels=GPLR;
state_array->state[1].wrprot=0; /* Not available on Simpad. */
- state_array->state[1].vs_3v=1; /* Can only apply 3.3V on Simpad. */
-
- state_array->state[1].vs_Xv=0;
-
+
+ if((*cs3reg & 0x0c) == 0x0c) {
+ state_array->state[1].vs_3v=0;
+ state_array->state[1].vs_Xv=0;
+ } else
+ {
+ state_array->state[1].vs_3v=1;
+ state_array->state[1].vs_Xv=0;
+ }
return 1;
}
save_flags_cli(flags);
- /* Murphy: BUS_ON different from POWER ? */
+ /* Murphy: see table of MIC2562a-1 */
switch(configure->vcc){
case 0:
- PCMCIA_setbit(PCMCIA_BUFF_DIS);
+ clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
+ break;
+
+ case 33:
+ clear_cs3_bit(VCC_3V_EN|EN0);
+ set_cs3_bit(VCC_5V_EN|EN1);
break;
- case 33:
case 50:
- PCMCIA_setbit(PCMCIA_BUFF_DIS);
+ clear_cs3_bit(VCC_5V_EN|EN1);
+ set_cs3_bit(VCC_3V_EN|EN0);
break;
default:
printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__,
configure->vcc);
+ clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
restore_flags(flags);
return -1;
}
return 0;
}
-struct pcmcia_low_level simpad_pcmcia_ops = {
+struct pcmcia_low_level simpad_pcmcia_ops = {
simpad_pcmcia_init,
simpad_pcmcia_shutdown,
simpad_pcmcia_socket_state,
*/
switch (configure->vcc) {
case 0:
- storkClearLatchA(STORK_PCMCIA_PULL_UPS_POWER_ON);
+/* storkClearLatchA(STORK_PCMCIA_PULL_UPS_POWER_ON); */
storkClearLatchA(POWER);
break;
dep_tristate ' ISA Plug and Play support' CONFIG_ISAPNP $CONFIG_PNP
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
- dep_bool ' PNPBIOS support (EXPERIMENTAL)' CONFIG_PNPBIOS $CONFIG_PNP
-fi
-
endmenu
unsigned long flags;
dasd_device_t *device;
- MOD_INC_USE_COUNT;
if ((!inp) || !(inp->i_rdev)) {
rc = -EINVAL;
goto fail;
if (atomic_inc_return (&device->open_count) == 1 ) {
if ( device->discipline->owner )
__MOD_INC_USE_COUNT(device->discipline->owner);
- } else {
- MOD_DEC_USE_COUNT;
}
unlock:
spin_unlock_irqrestore(&discipline_lock,flags);
fail:
- if (rc) MOD_DEC_USE_COUNT;
return rc;
}
rc = -ENODEV;
goto out;
}
- // fsync_dev (inp->i_rdev); /* sync the device */
count = atomic_dec_return (&device->open_count);
if ( count == 0) {
invalidate_buffers (inp->i_rdev);
if ( device->discipline->owner )
__MOD_DEC_USE_COUNT(device->discipline->owner);
- MOD_DEC_USE_COUNT;
} else if ( count == -1 ) { /* paranoia only */
atomic_set (&device->open_count,0);
printk (KERN_WARNING PRINTK_HEADER
static struct
block_device_operations dasd_device_operations =
{
+ owner:THIS_MODULE,
open:dasd_open,
release:dasd_release,
ioctl:dasd_ioctl,
dev->size,dev->device_name, atomic_read(&(dev->usage)));
atomic_inc(&(dev->usage));
- MOD_INC_USE_COUNT;
return 0; /* success */
}
/* but flush it right now */
/* Everything is already flushed by caller -- AV */
}
- MOD_DEC_USE_COUNT;
return(0);
}
#if (XPRAM_VERSION == 24)
struct block_device_operations xpram_devops =
{
+ owner: THIS_MODULE,
ioctl: xpram_ioctl,
open: xpram_open,
release: xpram_release,
#else
static struct file_operations tapeblock_fops = {
#endif
+ owner : THIS_MODULE,
open : tapeblock_open, /* open */
release : tapeblock_release, /* release */
};
ti->cqr=NULL;
s390irq_spin_unlock_irqrestore (ti->devinfo.irq, lockflags);
-#ifdef MODULE
- MOD_INC_USE_COUNT;
-#endif /* MODULE */
return 0;
}
s390irq_spin_lock_irqsave (ti->devinfo.irq, lockflags);
tapestate_set (ti, TS_UNUSED);
s390irq_spin_unlock_irqrestore (ti->devinfo.irq, lockflags);
-#ifdef MODULE
- MOD_DEC_USE_COUNT;
-#endif /* MODULE */
invalidate_buffers(inode->i_rdev);
return 0;
}
#ifdef AURORA_DEBUG
printk("cleanup_module: aurora_release_drivers\n");
-#endif;
+#endif
aurora_release_drivers();
for (i = 0; i < AURORA_NBOARD; i++)
jdp = &jsf0.dv[dev];
jdp->refcnt++;
- MOD_INC_USE_COUNT;
return 0;
}
--jdp->refcnt;
}
/* N.B. Doesn't lo->file need an fput?? */
- MOD_DEC_USE_COUNT;
return 0;
}
static struct miscdevice jsf_dev = { JSF_MINOR, "jsflash", &jsf_fops };
static struct block_device_operations jsfd_fops = {
+ owner: THIS_MODULE,
open: jsfd_open,
release: jsfd_release,
ioctl: jsfd_ioctl,
*/
timeout = jiffies + 5 * HZ / 10;
- while ((hostdata->test_completed == -1) && jiffies < timeout)
+ while ((hostdata->test_completed == -1) && jiffies < timeout) {
barrier();
+ cpu_relax();
+ }
failed = 1;
if (hostdata->test_completed == -1)
restore_flags(flags);
timeout = jiffies + 5 * HZ; /* arbitrary */
- while ((hostdata->test_completed == -1) && jiffies < timeout)
+ while ((hostdata->test_completed == -1) && jiffies < timeout) {
barrier();
+ cpu_relax();
+ }
NCR53c7x0_write32 (DSA_REG, 0);
if (hostdata->test_completed == 2) {
return 1;
}
#endif /* def MODULE */
-
-static Scsi_Host_Template driver_template = NCR53c7xx;
-#include "scsi_module.c"
#ifndef NCR53c710_H
#define NCR53c710_H
-#include <linux/version.h>
-
-/*
- * Prevent name space pollution in hosts.c, and only provide the
- * define we need to get the NCR53c7x0 driver into the host template
- * array.
- */
-
-#include <scsi/scsicam.h>
-
-extern int NCR53c7xx_abort(Scsi_Cmnd *);
-extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
-extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
-extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
-#ifdef MODULE
-extern int NCR53c7xx_release(struct Scsi_Host *);
-#else
-#define NCR53c7xx_release NULL
-#endif
-
-#define NCR53c7xx {NULL, NULL, NULL, NULL, \
- "NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
- NULL, /* info */ NULL, /* command, deprecated */ NULL, \
- NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
- NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
- /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
- /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
#ifndef HOSTS_C
/* These could be more efficient, given that we are always memory mapped,
* but they don't give the same problems as the write macros, so leave
* them. */
+#ifdef __mc68000__
+#define NCR53c7x0_read8(address) \
+ ((unsigned int)raw_inb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) )
+
+#define NCR53c7x0_read16(address) \
+ ((unsigned int)raw_inw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)))
+#else
#define NCR53c7x0_read8(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int)readb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) : \
(NCR53c7x0_memory_mapped ? \
(unsigned int)readw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) : \
inw(NCR53c7x0_address_io + (address)))
+#endif /* mc68000 */
#else
#define NCR53c7x0_read8(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int)readw((u32)NCR53c7x0_address_memory + (u32)(address)) : \
inw(NCR53c7x0_address_io + (address)))
#endif
+
+#ifdef __mc68000__
+#define NCR53c7x0_read32(address) \
+ ((unsigned int) raw_inl((u32)NCR53c7x0_address_memory + (u32)(address)))
+#else
#define NCR53c7x0_read32(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int) readl((u32)NCR53c7x0_address_memory + (u32)(address)) : \
inl(NCR53c7x0_address_io + (address)))
+#endif /* mc68000*/
#ifdef BIG_ENDIAN
/* If we are big-endian, then we are not Intel, so probably don't have
struct Scsi_Host *instance;
unsigned long address;
struct zorro_dev *z = NULL;
+ wd33c93_regs regs;
if (!MACH_IS_AMIGA || called)
return 0;
instance->irq = IRQ_AMIGA_PORTS;
instance->unique_id = z->slotaddr;
DMA(instance)->DAWR = DAWR_A2091;
- wd33c93_init(instance, (wd33c93_regs *)&(DMA(instance)->SASR),
- dma_setup, dma_stop, WD33C93_FS_8_10);
+ regs.SASR = &(DMA(instance)->SASR);
+ regs.SCMD = &(DMA(instance)->SCMD);
+ wd33c93_init(instance, regs, dma_setup, dma_stop, WD33C93_FS_8_10);
if (num_a2091++ == 0) {
first_instance = instance;
a2091_template = instance->hostt;
int __init a3000_detect(Scsi_Host_Template *tpnt)
{
- static unsigned char called = 0;
-
- if (called)
- return 0;
+ wd33c93_regs regs;
if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
return 0;
if (!request_mem_region(0xDD0000, 256, "wd33c93"))
- return -EBUSY;
+ return 0;
tpnt->proc_name = "A3000";
tpnt->proc_info = &wd33c93_proc_info;
a3000_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata));
- if (a3000_host == NULL) {
- release_mem_region(0xDD0000, 256);
- return 0;
- }
+ if (a3000_host == NULL)
+ goto fail_register;
+
a3000_host->base = ZTWO_VADDR(0xDD0000);
a3000_host->irq = IRQ_AMIGA_PORTS;
DMA(a3000_host)->DAWR = DAWR_A3000;
- wd33c93_init(a3000_host, (wd33c93_regs *)&(DMA(a3000_host)->SASR),
- dma_setup, dma_stop, WD33C93_FS_12_15);
- request_irq(IRQ_AMIGA_PORTS, a3000_intr, SA_SHIRQ, "A3000 SCSI",
- a3000_intr);
+ regs.SASR = &(DMA(a3000_host)->SASR);
+ regs.SCMD = &(DMA(a3000_host)->SCMD);
+ wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15);
+ if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, SA_SHIRQ, "A3000 SCSI",
+ a3000_intr))
+ goto fail_irq;
DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;
- called = 1;
return 1;
+
+fail_irq:
+#ifdef MODULE
+ wd33c93_release();
+#endif /* MODULE */
+ scsi_unregister(a3000_host);
+fail_register:
+ release_mem_region(0xDD0000, 256);
+ return 0;
}
#define HOSTS_C
#include "scsi_module.c"
-int a3000_release(struct Scsi_Host *instance)
+int __exit a3000_release(struct Scsi_Host *instance)
{
#ifdef MODULE
wd33c93_release();
+#endif /* MODULE*/
DMA(instance)->CNTR = 0;
release_mem_region(0xDD0000, 256);
free_irq(IRQ_AMIGA_PORTS, a3000_intr);
-#endif
return 1;
}
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
- * notice immediately at the beginning of the file, without modification,
- * this list of conditions, and the following disclaimer.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7770.c#12 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7770.c#14 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7770.c,v 1.1 2000/09/16 20:02:27 gibbs Exp $
*/
/*
* Linux driver attachment glue for aic7770 based controllers.
*
- * Copyright (c) 2000 Adaptec Inc.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7770_linux.c#7 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7770_linux.c#9 $
*/
#include "aic7xxx_osm.h"
* Core routines and tables shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7xxx.c#44 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#50 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.61 2000/11/13 03:35:43 gibbs Exp $
*/
#include "aic7xxx_seq.h"
/**************************** Function Declarations ***************************/
+static void ahc_force_renegotiation(struct ahc_softc *ahc);
static struct ahc_tmode_tstate*
ahc_alloc_tstate(struct ahc_softc *ahc,
u_int scsi_id, char channel);
static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
static u_int ahc_rem_wscb(struct ahc_softc *ahc,
u_int scbpos, u_int prev);
-static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
- char channel, int lun, u_int tag,
- role_t role, uint32_t status);
static void ahc_reset_current_bus(struct ahc_softc *ahc);
#ifdef AHC_DUMP_SEQ
static void ahc_dumpseq(struct ahc_softc *ahc);
ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
+ ahc_outb(ahc, LASTPHASE, P_BUSFREE);
/*
* Ensure that the sequencer's idea of TQINPOS
MSG_TYPE_INITIATOR_MSGIN;
ahc->msgin_index = 0;
}
- } else {
+ }
+#if AHC_TARGET_MODE
+ else {
if (bus_phase == P_MESGOUT) {
ahc->msg_type =
MSG_TYPE_TARGET_MSGOUT;
ahc->msgin_index = 0;
}
-#if AHC_TARGET_MODE
else
ahc_setup_target_msgin(ahc,
&devinfo,
scb);
-#endif
}
+#endif
}
ahc_handle_message_phase(ahc);
else
ahc_outb(ahc, MSG_OUT, mesg_out);
}
+ /*
+ * Force a renegotiation with this target just in
+ * case we are out of sync for some external reason
+ * unknown (or unreported) by the target.
+ */
+ ahc_force_renegotiation(ahc);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
ahc_unpause(ahc);
} else if ((status & SELTO) != 0) {
- u_int scbptr;
+ u_int scbptr;
/* Stop the selection */
ahc_outb(ahc, SCSISEQ, 0);
ahc_freeze_devq(ahc, scb);
}
ahc_outb(ahc, CLRINT, CLRSCSIINT);
+ /*
+ * Force a renegotiation with this target just in
+ * case the cable was pulled and will later be
+ * re-attached. The target may forget its negotiation
+ * settings with us should it attempt to reselect
+ * during the interruption. The target will not issue
+ * a unit attention in this case, so we must always
+ * renegotiate.
+ */
+ ahc_force_renegotiation(ahc);
ahc_restart(ahc);
} else if ((status & BUSFREE) != 0
&& (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
printerror = 0;
} else if (ahc_sent_msg(ahc, AHCMSG_1B,
MSG_BUS_DEV_RESET, TRUE)) {
- struct ahc_devinfo devinfo;
#ifdef __FreeBSD__
/*
* Don't mark the user's request for this BDR
}
}
+/*
+ * Force renegotiation to occur the next time we initiate
+ * a command to the current device.
+ */
+static void
+ahc_force_renegotiation(struct ahc_softc *ahc)
+{
+ struct ahc_devinfo devinfo;
+ struct ahc_initiator_tinfo *targ_info;
+ struct ahc_tmode_tstate *tstate;
+
+ ahc_fetch_devinfo(ahc, &devinfo);
+ targ_info = ahc_fetch_transinfo(ahc,
+ devinfo.channel,
+ devinfo.our_scsiid,
+ devinfo.target,
+ &tstate);
+ ahc_update_neg_request(ahc, &devinfo, tstate,
+ targ_info, /*force*/TRUE);
+}
+
#define AHC_MAX_STEPS 2000
void
ahc_clear_critical_section(struct ahc_softc *ahc)
hscb->scsiid,
hscb->lun,
hscb->cdb_len);
- printf("Shared Data: %#02x %#02x %#02x %#02x\n",
- hscb->shared_data.cdb[0],
- hscb->shared_data.cdb[1],
- hscb->shared_data.cdb[2],
- hscb->shared_data.cdb[3]);
- printf(" %#02x %#02x %#02x %#02x\n",
- hscb->shared_data.cdb[4],
- hscb->shared_data.cdb[5],
- hscb->shared_data.cdb[6],
- hscb->shared_data.cdb[7]);
- printf(" %#02x %#02x %#02x %#02x\n",
- hscb->shared_data.cdb[8],
- hscb->shared_data.cdb[9],
- hscb->shared_data.cdb[10],
- hscb->shared_data.cdb[11]);
+ printf("Shared Data: ");
+ for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
+ printf("%#02x", hscb->shared_data.cdb[i]);
printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
ahc_le32toh(hscb->dataptr),
ahc_le32toh(hscb->datacnt),
}
/*
- * Build a wide negotiateion message in our message
+ * Build a wide negotiation message in our message
* buffer based on the input parameters.
*/
static void
ahc_outb(ahc, CLRSINT1, CLRATNO);
}
ahc_outb(ahc, MSG_OUT, MSG_NOOP);
+ ahc_outb(ahc, SEQ_FLAGS2,
+ ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
}
/*
}
break;
}
+#ifdef AHC_TARGET_MODE
case MSG_BUS_DEV_RESET:
ahc_handle_devreset(ahc, devinfo,
CAM_BDR_SENT,
case MSG_ABORT_TAG:
case MSG_ABORT:
case MSG_CLEAR_QUEUE:
-#ifdef AHC_TARGET_MODE
+ {
+ int tag;
+
/* Target mode messages */
if (devinfo->role != ROLE_TARGET) {
reject = TRUE;
break;
}
+ tag = SCB_LIST_NULL;
+ if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
+ tag = ahc_inb(ahc, INITIATOR_TAG);
ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
- devinfo->lun,
- ahc->msgin_buf[0] == MSG_ABORT_TAG
- ? SCB_LIST_NULL
- : ahc_inb(ahc, INITIATOR_TAG),
- ROLE_TARGET, CAM_REQ_ABORTED);
+ devinfo->lun, tag, ROLE_TARGET,
+ CAM_REQ_ABORTED);
tstate = ahc->enabled_targets[devinfo->our_scsiid];
if (tstate != NULL) {
ahc_queue_lstate_event(ahc, lstate,
devinfo->our_scsiid,
ahc->msgin_buf[0],
- /*arg*/0);
+ /*arg*/tag);
ahc_send_lstate_events(ahc, lstate);
}
}
- done = MSGLOOP_MSGCOMPLETE;
+ ahc_restart(ahc);
+ done = MSGLOOP_TERMINATED;
break;
+ }
#endif
case MSG_TERM_IO_PROC:
default:
{
/* The IRQMS bit is only valid on VL and EISA chips */
- if ((ahc->chip & AHC_PCI) != 0)
- ahc->unpause &= ~IRQMS;
+ if ((ahc->chip & AHC_PCI) == 0)
+ ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
+ else
+ ahc->unpause = 0;
ahc->pause = ahc->unpause | PAUSE;
/* XXX The shared scb data stuff should be deprecated */
if (ahc->scb_data == NULL) {
/* Allocate SCB resources */
scb_data->scbarray =
- (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX,
+ (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
M_DEVBUF, M_NOWAIT);
if (scb_data->scbarray == NULL)
return (ENOMEM);
- memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX);
+ memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
/* Determine the number of hardware SCBs and initialize them */
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
- AHC_SCB_MAX * sizeof(struct hardware_scb),
+ AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &scb_data->hscb_dmat) != 0) {
/* And permanently map them */
ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
scb_data->hscbs,
- AHC_SCB_MAX * sizeof(struct hardware_scb),
+ AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
scb_data->init_level++;
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
- AHC_SCB_MAX * sizeof(struct scsi_sense_data),
+ AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &scb_data->sense_dmat) != 0) {
/* And permanently map them */
ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
scb_data->sense,
- AHC_SCB_MAX * sizeof(struct scsi_sense_data),
+ AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
scb_data->init_level++;
scb_data->init_level++;
/* Perform initial CCB allocation */
- memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb));
+ memset(scb_data->hscbs, 0,
+ AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
ahc_alloc_scbs(ahc);
if (scb_data->numscbs == 0) {
int i;
scb_data = ahc->scb_data;
- if (scb_data->numscbs >= AHC_SCB_MAX)
+ if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
/* Can't allocate any more */
return;
physaddr = sg_map->sg_physaddr;
newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
- for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) {
+ newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
+ for (i = 0; i < newcount; i++) {
struct scb_platform_data *pdata;
#ifndef __linux__
int error;
if ((ahc->flags & AHC_PAGESCBS) != 0)
sprintf(buf, "%d/%d SCBs",
- ahc->scb_data->maxhscbs, AHC_SCB_MAX);
+ ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
else
sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
}
ahc_outb(ahc, SEQ_FLAGS, 0);
ahc_outb(ahc, SEQ_FLAGS2, 0);
- if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) {
+ if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
ahc->flags |= AHC_PAGESCBS;
} else {
ahc->flags &= ~AHC_PAGESCBS;
maxlun = lun + 1;
}
- for (;i < maxtarget; i++) {
- for (j = minlun;j < maxlun; j++)
- ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
- }
+ if (role != ROLE_TARGET) {
+ for (;i < maxtarget; i++) {
+ for (j = minlun;j < maxlun; j++) {
+ u_int scbid;
+ u_int tcl;
- /*
- * Go through the disconnected list and remove any entries we
- * have queued for completion, 0'ing their control byte too.
- * We save the active SCB and restore it ourselves, so there
- * is no reason for this search to restore it too.
- */
- ahc_search_disc_list(ahc, target, channel, lun, tag,
- /*stop_on_first*/FALSE, /*remove*/TRUE,
- /*save_state*/FALSE);
+ tcl = BUILD_TCL(i << 4, j);
+ scbid = ahc_index_busy_tcl(ahc, tcl);
+ scbp = ahc_lookup_scb(ahc, scbid);
+ if (scbp == NULL
+ || ahc_match_scb(ahc, scbp, target, channel,
+ lun, tag, role) == 0)
+ continue;
+ ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
+ }
+ }
+
+ /*
+ * Go through the disconnected list and remove any entries we
+ * have queued for completion, 0'ing their control byte too.
+ * We save the active SCB and restore it ourselves, so there
+ * is no reason for this search to restore it too.
+ */
+ ahc_search_disc_list(ahc, target, channel, lun, tag,
+ /*stop_on_first*/FALSE, /*remove*/TRUE,
+ /*save_state*/FALSE);
+ }
/*
* Go through the hardware SCB array looking for commands that
- * were active but not on any list.
+ * were active but not on any list. In some cases, these remnants
+ * might not still have mappings in the scbindex array (e.g. unexpected
+ * bus free with the same scb queued for an abort). Don't hold this
+ * against them.
*/
for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
u_int scbid;
ahc_outb(ahc, SCBPTR, i);
scbid = ahc_inb(ahc, SCB_TAG);
scbp = ahc_lookup_scb(ahc, scbid);
- if (scbp != NULL
- && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))
+ if ((scbp == NULL && scbid != SCB_LIST_NULL)
+ || (scbp != NULL
+ && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
ahc_add_curscb_to_free_list(ahc);
}
* Core definitions and data structures shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7xxx.h#29 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#34 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.30 2000/11/10 20:13:40 gibbs Exp $
*/
*/
#define AHC_MAX_QUEUE 253
+/*
+ * The maximum amount of SCB storage we allocate in host memory. This
+ * number should reflect the 1 additional SCB we require to handle our
+ * qinfifo mechanism.
+ */
+#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
+
/*
* Ring Buffer of incoming target commands.
* We allocate 256 to simplify the logic in the sequencer
* Target mode version of the shared data SCB segment.
*/
struct target_data {
- uint8_t target_phases; /* Bitmap of phases to execute */
- uint8_t data_phase; /* Data-In or Data-Out */
- uint8_t scsi_status; /* SCSI status to give to initiator */
- uint8_t initiator_tag; /* Initiator's transaction tag */
+ uint32_t residual_datacnt; /* Residual in the current S/G seg */
+ uint32_t residual_sg_ptr; /* The next S/G for this transfer */
+ uint8_t scsi_status; /* SCSI status to give to initiator */
+ uint8_t target_phases; /* Bitmap of phases to execute */
+ uint8_t data_phase; /* Data-In or Data-Out */
+ uint8_t initiator_tag; /* Initiator's transaction tag */
};
struct hardware_scb {
* of the cdb payload as seen by the chip and a DMA
* is used to pull it in.
*/
- uint8_t cdb[12];
- uint32_t cdb_ptr;
- struct status_pkt status;
- struct target_data tdata;
+ uint8_t cdb[12];
+ uint32_t cdb_ptr;
+ struct status_pkt status;
+ struct target_data tdata;
} shared_data;
/*
* A word about residuals.
* Pool of SCBs ready to be assigned
* commands to execute.
*/
- struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */
+ struct scb *scbindex[256]; /*
+ * Mapping from tag to SCB.
+ * As tag identifiers are an
+ * 8bit value, we provide space
+ * for all possible tag values.
+ * Any lookups to entries at or
+ * above AHC_SCB_MAX_ALLOC will
+ * always fail.
+ */
struct hardware_scb *hscbs; /* Array of hardware SCBs */
struct scb *scbarray; /* Array of kernel SCBs */
struct scsi_sense_data *sense; /* Per SCB sense data */
void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
int ahc_reset_channel(struct ahc_softc *ahc, char channel,
int initiate_reset);
+int ahc_abort_scbs(struct ahc_softc *ahc, int target,
+ char channel, int lun, u_int tag,
+ role_t role, uint32_t status);
void ahc_restart(struct ahc_softc *ahc);
void ahc_calc_residual(struct scb *scb);
/*************************** Utility Functions ********************************/
/*
* Aic7xxx register and scratch ram definitions.
*
- * Copyright (c) 1994-2001 Justin Gibbs.
+ * Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.31 2000/11/10 20:13:40 gibbs Exp $
*/
-VERSION = "$Id: //depot/src/aic7xxx/aic7xxx.reg#19 $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#24 $"
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
access_mode RO
mask SCSICNT 0xf0
mask OFFCNT 0x0f
+ mask U2OFFCNT 0x7f
}
/*
size 4
alias SCB_RESIDUAL_DATACNT
alias SCB_CDB_STORE
- alias SCB_TARGET_INFO
}
SCB_RESIDUAL_SGPTR {
size 4
SCB_SCSI_STATUS {
size 1
}
- SCB_CDB_STORE_PAD {
- size 3
+ SCB_TARGET_PHASES {
+ size 1
+ }
+ SCB_TARGET_DATA_DIR {
+ size 1
+ }
+ SCB_TARGET_ITAG {
+ size 1
}
SCB_DATAPTR {
size 4
SEQ_FLAGS2 {
size 1
- bit SCB_DMA 0x01
+ bit SCB_DMA 0x01
+ bit TARGET_MSG_PENDING 0x02
}
/*
* These are reserved registers in the card's scratch ram. Some of
const STATUS_BUSY 0x08
const STATUS_QUEUE_FULL 0x28
-const SCB_TARGET_PHASES 0
-const SCB_TARGET_DATA_DIR 1
-const SCB_TARGET_STATUS 2
-const SCB_INITIATOR_TAG 3
const TARGET_DATA_IN 1
/*
/*
* Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
*
- * Copyright (c) 1994-2001 Justin Gibbs.
+ * Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.seq,v 1.106 2000/11/12 05:19:46 gibbs Exp $
*/
-VERSION = "$Id: //depot/src/aic7xxx/aic7xxx.seq#33 $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#37 $"
#include "aic7xxx.reg"
#include "scsi_message.h"
} else {
mov DFDAT, DINDEX;
}
+ and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
/* Remember for disconnection decision */
test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
* < MSG_IGN_WIDE_RESIDUE.
*/
add A, -MSG_SIMPLE_Q_TAG, DINDEX;
- jnc ident_messages_done;
+ jnc ident_messages_done_msg_pending;
add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
- jc ident_messages_done;
+ jc ident_messages_done_msg_pending;
+
/* Store for host */
if ((ahc->features & AHC_CMD_CHAN) != 0) {
mov CCSCBRAM, DINDEX;
}
mov INITIATOR_TAG, DINDEX;
or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
- test SCSISIGI, ATNI jz . + 2;
- /* Initiator still wants to give us messages */
- call target_inb;
+
+ident_messages_done:
+ /* Terminate the ident list */
+ if ((ahc->features & AHC_CMD_CHAN) != 0) {
+ mvi CCSCBRAM, SCB_LIST_NULL;
+ } else {
+ mvi DFDAT, SCB_LIST_NULL;
+ }
+ or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN;
+ test SEQ_FLAGS2, TARGET_MSG_PENDING
+ jnz target_mesgout_pending;
+ test SCSISIGI, ATNI jnz target_mesgout_continue;
+ jmp target_ITloop;
+
+
+ident_messages_done_msg_pending:
+ or SEQ_FLAGS2, TARGET_MSG_PENDING;
jmp ident_messages_done;
/*
cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
test SSTAT0, SPIORDY jz .;
jmp host_target_message_loop;
-
-ident_messages_done:
- /* If ring buffer is full, return busy or queue full */
- if ((ahc->features & AHC_HS_MAILBOX) != 0) {
- and A, HOST_TQINPOS, HS_MAILBOX;
- } else {
- mov A, KERNEL_TQINPOS;
- }
- cmp TQINPOS, A jne tqinfifo_has_space;
- mvi P_STATUS|BSYO call change_phase;
- test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
- mvi STATUS_QUEUE_FULL call target_outb;
- jmp target_busfree_wait;
- mvi STATUS_BUSY call target_outb;
- jmp target_busfree_wait;
-tqinfifo_has_space:
- /* Terminate the ident list */
- if ((ahc->features & AHC_CMD_CHAN) != 0) {
- mvi CCSCBRAM, SCB_LIST_NULL;
- } else {
- mvi DFDAT, SCB_LIST_NULL;
- }
- or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN;
- test SCSISIGI, ATNI jnz target_mesgout_pending;
- jmp target_ITloop;
}
if ((ahc->flags & AHC_INITIATORROLE) != 0) {
*/
test SCB_CONTROL, TAG_ENB jz . + 3;
mvi MSG_SIMPLE_Q_TAG call target_outb;
- mov SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb;
+ mov SCB_TARGET_ITAG call target_outb;
target_synccmd:
/*
* Now determine what phases the host wants us
* to go through.
*/
- mov SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES];
+ mov SEQ_FLAGS, SCB_TARGET_PHASES;
test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
mvi P_MESGIN|BSYO call change_phase;
jmp poll_for_work;
target_cmdphase:
+ /*
+ * The target has dropped ATN (doesn't want to abort or BDR)
+ * and we believe this selection to be valid. If the ring
+ * buffer for new commands is full, return busy or queue full.
+ */
+ if ((ahc->features & AHC_HS_MAILBOX) != 0) {
+ and A, HOST_TQINPOS, HS_MAILBOX;
+ } else {
+ mov A, KERNEL_TQINPOS;
+ }
+ cmp TQINPOS, A jne tqinfifo_has_space;
+ mvi P_STATUS|BSYO call change_phase;
+ test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
+ mvi STATUS_QUEUE_FULL call target_outb;
+ jmp target_busfree_wait;
+ mvi STATUS_BUSY call target_outb;
+ jmp target_busfree_wait;
+tqinfifo_has_space:
mvi P_COMMAND|BSYO call change_phase;
call target_inb;
mov A, DINDEX;
* data direction of the DMA. Toggle it for
* target transfers.
*/
- xor LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR];
- or SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO
- call change_phase;
+ xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
+ or SCB_TARGET_DATA_DIR, BSYO call change_phase;
jmp p_data;
target_sphase:
mvi P_STATUS|BSYO call change_phase;
mvi LASTPHASE, P_STATUS;
- mov SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb;
+ mov SCB_SCSI_STATUS call target_outb;
/* XXX Watch for ATN or parity errors??? */
mvi SCSISIGO, P_MESGIN|BSYO;
/* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
and SEQ_FLAGS, ~DPHASE_PENDING;
/*
* For data-in phases, wait for any pending acks from the
- * initiator before changing phase.
+ * initiator before changing phase. We only need to
+ * send Ignore Wide Residue messages for data-in phases.
*/
test DFCNTRL, DIRECTION jz target_ITloop;
test SSTAT1, REQINIT jnz .;
+ test DATA_COUNT_ODD, 0x1 jz target_ITloop;
+ test SCSIRATE, WIDEXFER jz target_ITloop;
+ /*
+ * Issue an Ignore Wide Residue Message.
+ */
+ mvi P_MESGIN|BSYO call change_phase;
+ mvi MSG_IGN_WIDE_RESIDUE call target_outb;
+ mvi 1 call target_outb;
jmp target_ITloop;
} else {
jmp ITloop;
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: //depot/src/aic7xxx/aic7xxx_93cx6.c#8 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#10 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_93cx6.c,v 1.9 2000/11/10 20:13:41 gibbs Exp $
*/
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7xxx_93cx6.h#5 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.h#7 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_93cx6.h,v 1.8 2000/11/10 20:13:41 gibbs Exp $
*/
* Inline routines shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7xxx_inline.h#27 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#31 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.8 2000/11/12 05:19:46 gibbs Exp $
*/
ahc_intr(struct ahc_softc *ahc)
{
u_int intstat;
- u_int queuestat;
/*
* Instead of directly reading the interrupt status register,
* most cases.
*/
if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
- && (queuestat = ahc_check_cmdcmpltqueues(ahc)) != 0)
+ && (ahc_check_cmdcmpltqueues(ahc) != 0))
intstat = CMDCMPLT;
else {
intstat = ahc_inb(ahc, INTSTAT);
- queuestat = AHC_RUN_QOUTFIFO;
-#ifdef AHC_TARGET_MODE
- if ((ahc->flags & AHC_TARGETROLE) != 0)
- queuestat |= AHC_RUN_TQINFIFO;
-#endif
}
if (intstat & CMDCMPLT) {
*/
ahc_flush_device_writes(ahc);
#ifdef AHC_TARGET_MODE
- if ((queuestat & AHC_RUN_QOUTFIFO) != 0)
+ if ((ahc->flags & AHC_INITIATORROLE) != 0)
#endif
ahc_run_qoutfifo(ahc);
#ifdef AHC_TARGET_MODE
- if ((queuestat & AHC_RUN_TQINFIFO) != 0)
+ if ((ahc->flags & AHC_TARGETROLE) != 0)
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
#endif
}
/*
* Adaptec AIC7xxx device driver for Linux.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_linux.c#72 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_linux.c#79 $
*
* Copyright (c) 1994 John Aycock
* The University of Calgary Department of Computer Science.
* SCB paging, and other rework of the code.
*
* --------------------------------------------------------------------------
- * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs.
- * Copyright (c) 2000 Adaptec Inc.
+ * Copyright (c) 1994-2000 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
*---------------------------------------------------------------------------
*
*
* Form: aic7xxx=extended
* aic7xxx=no_reset
- * aic7xxx=ultra
- * aic7xxx=irq_trigger:[0,1] # 0 edge, 1 level
* aic7xxx=verbose
*
* Daniel M. Eischen, deischen@iworks.InterWorks.org, 1/23/97
*
*/
-/*
- * The next three defines are user configurable. These should be the only
- * defines a user might need to get in here and change. There are other
- * defines buried deeper in the code, but those really shouldn't need touched
- * under normal conditions.
- */
-
-#include <linux/module.h>
-
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
*/
static uint32_t aic7xxx_extended = 0;
-/*
- * The IRQ trigger method used on EISA controllers. Does not effect PCI cards.
- * -1 = Use detected settings.
- * 0 = Force Edge triggered mode.
- * 1 = Force Level triggered mode.
- */
-static int aic7xxx_irq_trigger = -1;
-
-/*
- * This variable is used to override the termination settings on a controller.
- * This should not be used under normal conditions. However, in the case
- * that a controller does not have a readable SEEPROM (so that we can't
- * read the SEEPROM settings directly) and that a controller has a buggered
- * version of the cable detection logic, this can be used to force the
- * correct termination. It is preferable to use the manual termination
- * settings in the BIOS if possible, but some motherboard controllers store
- * those settings in a format we can't read. In other cases, auto term
- * should also work, but the chipset was put together with no auto term
- * logic (common on motherboard controllers). In those cases, we have
- * 32 bits here to work with. That's good for 8 controllers/channels. The
- * bits are organized as 4 bits per channel, with scsi0 getting the lowest
- * 4 bits in the int. A 1 in a bit position indicates the termination setting
- * that corresponds to that bit should be enabled, a 0 is disabled.
- * It looks something like this:
- *
- * 0x0f = 1111-Single Ended Low Byte Termination on/off
- * ||\-Single Ended High Byte Termination on/off
- * |\-LVD Low Byte Termination on/off
- * \-LVD High Byte Termination on/off
- *
- * For non-Ultra2 controllers, the upper 2 bits are not important. So, to
- * enable both high byte and low byte termination on scsi0, I would need to
- * make sure that the override_term variable was set to 0x03 (bits 0011).
- * To make sure that all termination is enabled on an Ultra2 controller at
- * scsi2 and only high byte termination on scsi1 and high and low byte
- * termination on scsi0, I would set override_term=0xf23 (bits 1111 0010 0011)
- *
- * For the most part, users should never have to use this, that's why I
- * left it fairly cryptic instead of easy to understand. If you need it,
- * most likely someone will be telling you what your's needs to be set to.
- */
-static int aic7xxx_override_term = -1;
-
-/*
- * Certain motherboard chipset controllers tend to screw
- * up the polarity of the term enable output pin. Use this variable
- * to force the correct polarity for your system. This is a bitfield variable
- * similar to the previous one, but this one has one bit per channel instead
- * of four.
- * 0 = Force the setting to active low.
- * 1 = Force setting to active high.
- * Most Adaptec cards are active high, several motherboards are active low.
- * To force a 2940 card at SCSI 0 to active high and a motherboard 7895
- * controller at scsi1 and scsi2 to active low, and a 2910 card at scsi3
- * to active high, you would need to set stpwlev=0x9 (bits 1001).
- *
- * People shouldn't need to use this, but if you are experiencing lots of
- * SCSI timeout problems, this may help. There is one sure way to test what
- * this option needs to be. Using a boot floppy to boot the system, configure
- * your system to enable all SCSI termination (in the Adaptec SCSI BIOS) and
- * if needed then also pass a value to override_term to make sure that the
- * driver is enabling SCSI termination, then set this variable to either 0
- * or 1. When the driver boots, make sure there are *NO* SCSI cables
- * connected to your controller. If it finds and inits the controller
- * without problem, then the setting you passed to stpwlev was correct. If
- * the driver goes into a reset loop and hangs the system, then you need the
- * other setting for this variable. If neither setting lets the machine
- * boot then you have definite termination problems that may not be fixable.
- */
-static int aic7xxx_stpwlev = -1;
-
-/*
- * Set this to non-0 in order to force the driver to panic the kernel
- * and print out debugging info on a SCSI abort or reset cycle.
- */
-static int aic7xxx_panic_on_abort = 0;
-
/*
* PCI bus parity checking of the Adaptec controllers. This is somewhat
* dubious at best. To my knowledge, this option has never actually
*/
static int aic7xxx_pci_parity = 0;
-/*
- * Set this to a non-0 value to make us dump out the 32 bit instruction
- * registers on the card after completing the sequencer download. This
- * allows the actual sequencer download to be verified. It is possible
- * to use this option and still boot up and run your system. This is
- * only intended for debugging purposes.
- */
-static int aic7xxx_dump_sequencer = 0;
-
/*
* Certain newer motherboards have put new PCI based devices into the
* IO spaces that used to typically be occupied by VLB or EISA cards.
static int aic7xxx_seltime = 0x00;
/*
- * So that insmod can find the variable and make it point to something
+ * Certain devices do not perform any aging on commands. Should the
+ * device be saturated by commands in one portion of the disk, it is
+ * possible for transactions on far away sectors to never be serviced.
+ * To handle these devices, we can periodically send an ordered tag to
+ * force all outstanding transactions to be serviced prior to a new
+ * transaction.
+ */
+int aic7xxx_periodic_otag;
+
+/*
+ * Module information and settable options.
*/
#ifdef MODULE
static char *aic7xxx = NULL;
-
-MODULE_PARM(aic7xxx, "s");
-
/*
* Just in case someone uses commas to separate items on the insmod
* command line, we define a dummy buffer here to avoid having insmod
*/
static char dummy_buffer[60] = "Please don't trounce on me insmod!!\n";
+MODULE_AUTHOR("Maintainer: Justin T. Gibbs <gibbs@scsiguy.com>");
+MODULE_DESCRIPTION("Adaptec Aic77XX/78XX SCSI Host Bus Adapter driver");
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,10)
+MODULE_LICENSE("Dual BSD/GPL");
+#endif
+MODULE_PARM(aic7xxx, "s");
+MODULE_PARM_DESC(aic7xxx, "period delimited, options string.
+ verbose Enable verbose/diagnostic logging
+ no_probe Disable EISA/VLB controller probing
+ no_reset Supress initial bus resets
+ extended Enable extended geometry on all controllers
+ periodic_otag Send an ordered tagged transaction periodically
+ to prevent tag starvation. This may be
+ required by some older disk drives/RAID arrays.
+ reverse_scan Sort PCI devices highest Bus/Slot to lowest
+ tag_info:<tag_str> Set per-target tag depth
+ seltime:<int> Selection Timeout(0/256ms,1/128ms,2/64ms,3/32ms)
+
+ Sample /etc/modules.conf line:
+ Enable verbose logging
+ Disable EISA/VLB probing
+ Set tag depth on Controller 2/Target 2 to 10 tags
+ Shorten the selection timeout to 128ms from its default of 256
+
+ options aic7xxx='\"verbose.no_probe.tag_info:{{}.{}.{..10}}.seltime:1\"'
+");
#endif
static void ahc_linux_handle_scsi_status(struct ahc_softc *,
sg = (struct scatterlist *)cmd->request_buffer;
pci_unmap_sg(ahc->dev_softc, sg, cmd->use_sg,
scsi_to_pci_dma_dir(cmd->sc_data_direction));
- } else if (cmd->request_bufflen != 0)
+ } else if (cmd->request_bufflen != 0) {
+ u_int32_t high_addr;
+
+ high_addr = ahc_le32toh(scb->sg_list[0].len)
+ & AHC_SG_HIGH_ADDR_MASK;
pci_unmap_single(ahc->dev_softc,
- ahc_le32toh(scb->sg_list[0].addr),
+ ahc_le32toh(scb->sg_list[0].addr)
+ | (((dma_addr_t)high_addr) << 8),
cmd->request_bufflen,
scsi_to_pci_dma_dir(cmd->sc_data_direction));
+ }
}
static __inline int
{
struct ahc_softc *ahc;
- TAILQ_FOREACH(ahc, &ahc_tailq, links) {
- ahc_shutdown(ahc);
+ if (event == SYS_DOWN || event == SYS_HALT) {
+ TAILQ_FOREACH(ahc, &ahc_tailq, links) {
+ ahc_shutdown(ahc);
+ }
}
return (NOTIFY_OK);
}
* address). For this reason, we have to reset
* our dma mask when doing allocations.
*/
+ if(ahc->dev_softc)
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,3)
- pci_set_dma_mask(ahc->dev_softc, 0xFFFFFFFF);
+ pci_set_dma_mask(ahc->dev_softc, 0xFFFFFFFF);
#else
- ahc->dev_softc->dma_mask = 0xFFFFFFFF;
+ ahc->dev_softc->dma_mask = 0xFFFFFFFF;
#endif
*vaddr = pci_alloc_consistent(ahc->dev_softc,
dmat->maxsize, &map->bus_addr);
+ if (ahc->dev_softc)
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,3)
- pci_set_dma_mask(ahc->dev_softc, ahc->platform_data->hw_dma_mask);
+ pci_set_dma_mask(ahc->dev_softc, ahc->platform_data->hw_dma_mask);
#else
- ahc->dev_softc->dma_mask = ahc->platform_data->hw_dma_mask;
+ ahc->dev_softc->dma_mask = ahc->platform_data->hw_dma_mask;
#endif
#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0) */
/*
* At least in 2.2.14, malloc is a slab allocator so all
- * allocations are aligned. We assume, for these kernel versions
+ * allocations are aligned. We assume for these kernel versions
* that all allocations will be bellow 4Gig, physically contiguous,
* and accessable via DMA by the controller.
*/
{
char primary_channel;
- value = ahc_get_pci_bus(lahc->dev_softc)
- - ahc_get_pci_bus(rahc->dev_softc);
+ if (aic7xxx_reverse_scan != 0)
+ value = ahc_get_pci_bus(rahc->dev_softc)
+ - ahc_get_pci_bus(lahc->dev_softc);
+ else
+ value = ahc_get_pci_bus(lahc->dev_softc)
+ - ahc_get_pci_bus(rahc->dev_softc);
if (value != 0)
break;
- value = ahc_get_pci_slot(lahc->dev_softc)
- - ahc_get_pci_slot(rahc->dev_softc);
+ if (aic7xxx_reverse_scan != 0)
+ value = ahc_get_pci_slot(rahc->dev_softc)
+ - ahc_get_pci_slot(lahc->dev_softc);
+ else
+ value = ahc_get_pci_slot(lahc->dev_softc)
+ - ahc_get_pci_slot(rahc->dev_softc);
if (value != 0)
break;
/*
/*
* Handle Linux boot parameters. This routine allows for assigning a value
* to a parameter with a ':' between the parameter and the value.
- * ie. aic7xxx=unpause:0x0A,extended
+ * ie. aic7xxx=stpwlev:1,extended
*/
int
aic7xxx_setup(char *s)
} options[] = {
{ "extended", &aic7xxx_extended },
{ "no_reset", &aic7xxx_no_reset },
- { "irq_trigger", &aic7xxx_irq_trigger },
{ "verbose", &aic7xxx_verbose },
{ "reverse_scan", &aic7xxx_reverse_scan },
- { "override_term", &aic7xxx_override_term },
- { "stpwlev", &aic7xxx_stpwlev },
{ "no_probe", &aic7xxx_no_probe },
- { "panic_on_abort", &aic7xxx_panic_on_abort },
+ { "periodic_otag", &aic7xxx_periodic_otag },
{ "pci_parity", &aic7xxx_pci_parity },
- { "dump_sequencer", &aic7xxx_dump_sequencer },
{ "seltime", &aic7xxx_seltime },
{ "tag_info", NULL }
};
ahc_linux_pci_probe(template);
#endif
- aic7770_linux_probe(template);
+ if (aic7xxx_no_probe == 0)
+ aic7770_linux_probe(template);
/*
* Register with the SCSI layer all
host->this_id = ahc->our_id;
host->irq = ahc->platform_data->irq;
host->max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
- host->max_channel = (ahc->features & AHC_TWIN) ? 1 : 0;
host->max_lun = AHC_NUM_LUNS;
+ host->max_channel = (ahc->features & AHC_TWIN) ? 1 : 0;
ahc_set_unit(ahc, ahc_linux_next_unit());
sprintf(buf, "scsi%d", host->host_no);
new_name = malloc(strlen(buf) + 1, M_DEVBUF, M_NOWAIT);
dev->qfrozen++;
}
- dev->flags &= ~(AHC_DEV_Q_BASIC|AHC_DEV_Q_TAGGED);
+ dev->flags &= ~(AHC_DEV_Q_BASIC|AHC_DEV_Q_TAGGED|AHC_DEV_PERIODIC_OTAG);
if (now_queuing) {
if (!was_queuing) {
dev->maxtags = AHC_MAX_QUEUE;
dev->openings = dev->maxtags - dev->active;
}
- if (alg == AHC_QUEUE_TAGGED)
+ if (alg == AHC_QUEUE_TAGGED) {
dev->flags |= AHC_DEV_Q_TAGGED;
- else
+ if (aic7xxx_periodic_otag != 0)
+ dev->flags |= AHC_DEV_PERIODIC_OTAG;
+ } else
dev->flags |= AHC_DEV_Q_BASIC;
} else {
/* We can only have one opening */
if (tags != 0) {
device->queue_depth = tags;
ahc_set_tags(ahc, &devinfo, AHC_QUEUE_TAGGED);
- printf("scsi%d:%d:%d:%d: Tagged Queuing enabled. Depth %d\n",
- ahc->platform_data->host->host_no, device->channel,
+ printf("scsi%d:%c:%d:%d: Tagged Queuing enabled. Depth %d\n",
+ ahc->platform_data->host->host_no, device->channel + 'A',
device->id, device->lun, tags);
} else {
/*
dev->openings--;
dev->active++;
dev->commands_issued++;
- dev->commands_since_idle_or_otag++;
+ if ((dev->flags & AHC_DEV_PERIODIC_OTAG) != 0)
+ dev->commands_since_idle_or_otag++;
/*
* We only allow one untagged transaction
* are not large enough for us to pull the spi3 bits.
* In this case, we assume that a device that tells us
* they can provide inquiry data that spans the SPI3
- * bits can handle a PPR request. If the inquiry
- * request has sufficient buffer space to cover these
- * bits, we check them to see if any ppr options are
- * available.
+ * bits and says its SCSI3 can handle a PPR request.
+ * If the inquiry request has sufficient buffer space to
+ * cover these bits, we check them to see if any ppr options
+ * are available.
*/
if ((sid->additional_length + 4) >= minlen) {
if (transferred_len >= minlen
if (targ_info->curr.protocol_version > SCSI_REV_2)
targ_info->curr.transport_version = 3;
+ else
+ ppr_options = 0;
} else {
ppr_options = 0;
}
ahc->flags &= ~AHC_ALL_INTERRUPTS;
paused = TRUE;
- if (bootverbose)
- ahc_dump_card_state(ahc);
+ ahc_dump_card_state(ahc);
if ((pending_scb->flags & SCB_ACTIVE) == 0) {
printf("%s:%d:%d:%d: Command already completed\n",
* Actually re-queue this SCB in an attempt
* to select the device before it reconnects.
* In either case (selection or reselection),
- * we will now issue a the approprate message
+ * we will now issue the approprate message
* to the timed-out device.
*
* Set the MK_MESSAGE control bit indicating
if (paused)
ahc_unpause(ahc);
if (wait) {
- struct timer_list timer;
+ struct timer_list timer;
int ret;
ahc_unlock(ahc, &s);
error = ahc_linux_queue_recovery_cmd(cmd, SCB_ABORT);
if (error != 0)
- printf("aic7xxx_abort returns %d\n", error);
+ printf("aic7xxx_abort returns 0x%x\n", error);
return (error);
}
error = ahc_linux_queue_recovery_cmd(cmd, SCB_DEVICE_RESET);
if (error != 0)
- printf("aic7xxx_dev_reset returns %d\n", error);
+ printf("aic7xxx_dev_reset returns 0x%x\n", error);
return (error);
}
sectors = 32;
cylinders = disk->capacity / (heads * sectors);
- if (disk->device->channel == 0)
+ if (aic7xxx_extended != 0)
+ extended = 1;
+ else if (disk->device->channel == 0)
extended = (ahc->flags & AHC_EXTENDED_TRANS_A) != 0;
else
extended = (ahc->flags & AHC_EXTENDED_TRANS_B) != 0;
}
}
-MODULE_LICENSE("Dual BSD/GPL");
-
#if defined(MODULE) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
static Scsi_Host_Template driver_template = AIC7XXX;
Scsi_Host_Template *aic7xxx_driver_template = &driver_template;
/*
* Adaptec AIC7xxx device driver host template for Linux.
*
- * Copyright (c) 2000 Adaptec Inc.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_linux_host.h#3 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_linux_host.h#5 $
*/
#ifndef _AIC7XXX_LINUX_HOST_H_
/*
* Linux driver attachment glue for PCI based controllers.
*
- * Copyright (c) 2000, 2001 Adaptec Inc.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_linux_pci.c#23 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_linux_pci.c#27 $
*/
#include "aic7xxx_osm.h"
static int ahc_linux_pci_dev_probe(struct pci_dev *pdev,
const struct pci_device_id *ent);
+static int ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc,
+ u_long *base);
+static int ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
+ u_long *bus_addr,
+ uint8_t **maddr);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
static void ahc_linux_pci_dev_remove(struct pci_dev *pdev);
},
{ 0 }
};
+MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
struct pci_driver aic7xxx_pci_driver = {
name: "aic7xxx",
static int
ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
- char buf[80];
- struct ahc_softc *ahc;
- ahc_dev_softc_t pci;
- struct ahc_pci_identity *entry;
- char *name;
- int error;
+ char buf[80];
+ struct ahc_softc *ahc;
+ ahc_dev_softc_t pci;
+ struct ahc_pci_identity *entry;
+ char *name;
+ int error;
+
+ /*
+ * Some BIOSen report the same device multiple times.
+ */
+ TAILQ_FOREACH(ahc, &ahc_tailq, links) {
+ struct pci_dev *probed_pdev;
+
+ probed_pdev = ahc->dev_softc;
+ if (probed_pdev->bus->number == pdev->bus->number
+ && probed_pdev->devfn == pdev->devfn)
+ break;
+ }
+ if (ahc != NULL) {
+ /* Skip duplicate. */
+ return (-ENODEV);
+ }
pci = pdev;
entry = ahc_find_pci_device(pci);
&& pci_set_dma_mask(pdev, 0x7FFFFFFFFFULL) == 0) {
#else
&& ahc_linux_get_memsize() > 0x80000000) {
+
ahc->dev_softc->dma_mask =
- (bus_addr_t)(0x7FFFFFFFFFULL
- & ((1ULL << (sizeof(bus_addr_t) * 8))-1));
+ (bus_addr_t)(0x7FFFFFFFFFULL & (bus_addr_t)~0);
#endif
ahc->flags |= AHC_39BIT_ADDRESSING;
ahc->platform_data->hw_dma_mask =
- (bus_addr_t)(0x7FFFFFFFFFULL
- & ((1ULL << (sizeof(bus_addr_t) * 8))-1));
+ (bus_addr_t)(0x7FFFFFFFFFULL & (bus_addr_t)~0);
}
#endif
ahc->dev_softc = pci;
pdev = NULL;
class = PCI_CLASS_STORAGE_SCSI << 8;
while ((pdev = pci_find_class(class, pdev)) != NULL) {
- struct ahc_softc *ahc;
ahc_dev_softc_t pci;
int error;
pci = pdev;
-
- /*
- * Some BIOSen report the same device multiple times.
- */
- TAILQ_FOREACH(ahc, &ahc_tailq, links) {
- struct pci_dev *probed_pdev;
-
- probed_pdev = ahc->dev_softc;
- if (probed_pdev->bus->number == pdev->bus->number
- && probed_pdev->devfn == pdev->devfn)
- break;
- }
- if (ahc != NULL) {
- /* Skip duplicate. */
- continue;
- }
-
error = ahc_linux_pci_dev_probe(pdev, /*pci_devid*/NULL);
if (error == 0)
found++;
#endif
}
-int
-ahc_pci_map_registers(struct ahc_softc *ahc)
+static int
+ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base)
{
- uint32_t command;
- u_long base;
-#ifdef MMAPIO
- u_long start;
- u_long base_page;
- u_long base_offset;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
+ *base = pci_resource_start(ahc->dev_softc, 0);
+#else
+ *base = ahc_pci_read_config(ahc->dev_softc, PCIR_MAPS, 4);
+ *base &= PCI_BASE_ADDRESS_IO_MASK;
#endif
- uint8_t *maddr;
+ if (base == 0)
+ return (ENOMEM);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
+ if (check_region(*base, 256) != 0)
+ return (ENOMEM);
+ else
+ request_region(*base, 256, "aic7xxx");
+#else
+ if (request_region(*base, 256, "aic7xxx") == 0)
+ return (ENOMEM);
+#endif
+ return (0);
+}
- command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
- base = 0;
- maddr = NULL;
-#ifdef MMAPIO
+static int
+ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
+ u_long *bus_addr,
+ uint8_t **maddr)
+{
+ u_long start;
+ u_long base_page;
+ u_long base_offset;
+ int error;
+
+ error = 0;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
start = pci_resource_start(ahc->dev_softc, 1);
base_page = start & PAGE_MASK;
base_offset -= base_page;
#endif
if (start != 0) {
- ahc->platform_data->mem_busaddr = start;
+ *bus_addr = start;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
- if (request_mem_region(start, 0x1000, "aic7xxx") == 0) {
- printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx "
- "in use. Cannot map device.\n",
+ if (request_mem_region(start, 0x1000, "aic7xxx") == 0)
+ error = ENOMEM;
+#endif
+ if (error == 0) {
+ *maddr = ioremap_nocache(base_page, base_offset + 256);
+ if (*maddr == NULL)
+ error = ENOMEM;
+ else
+ *maddr += base_offset;
+ }
+ } else
+ error = ENOMEM;
+ return (error);
+}
+
+int
+ahc_pci_map_registers(struct ahc_softc *ahc)
+{
+ uint32_t command;
+ u_long base;
+ uint8_t *maddr;
+ int error;
+ int io_error;
+
+ /*
+ * We always reserve both our register spaces to avoid
+ * other devices claiming them.
+ */
+ command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
+ command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
+ base = 0;
+ maddr = NULL;
+#ifdef MMAPIO
+ error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
+ if (error == 0) {
+ ahc->platform_data->mem_busaddr = base;
+ ahc->tag = BUS_SPACE_MEMIO;
+ ahc->bsh.maddr = maddr;
+ ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
+ command | PCIM_CMD_MEMEN, 4);
+
+ /*
+ * Do a quick test to see if memory mapped
+ * I/O is functioning correctly.
+ */
+ if (ahc_inb(ahc, HCNTRL) == 0xFF) {
+
+ printf("aic7xxx: PCI Device %d:%d:%d "
+ "failed memory mapped test\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
- ahc_get_pci_function(ahc->dev_softc),
- start);
+ ahc_get_pci_function(ahc->dev_softc));
+ maddr = NULL;
} else
-#endif
- maddr = ioremap_nocache(base_page, base_offset + 256);
- if (maddr != NULL) {
- ahc->tag = BUS_SPACE_MEMIO;
- ahc->bsh.maddr = maddr + base_offset;
command |= PCIM_CMD_MEMEN;
- ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
- command, 4);
-
- /*
- * Do a quick test to see if memory mapped
- * I/O is functioning correctly.
- */
- if (ahc_inb(ahc, HCNTRL) == 0xFF) {
- printf("aic7xxx: PCI Device %d:%d:%d "
- "failed memory mapped test\n",
- ahc_get_pci_bus(ahc->dev_softc),
- ahc_get_pci_slot(ahc->dev_softc),
- ahc_get_pci_function(ahc->dev_softc));
- iounmap((void *)base_page);
- maddr = NULL;
- } else {
- command &= ~PCIM_CMD_PORTEN;
- ahc_pci_write_config(ahc->dev_softc,
- PCIR_COMMAND, command, 4);
- }
- }
+ } else {
+ printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx "
+ "unavailable. Cannot map device.\n",
+ ahc_get_pci_bus(ahc->dev_softc),
+ ahc_get_pci_slot(ahc->dev_softc),
+ ahc_get_pci_function(ahc->dev_softc),
+ base);
}
#endif
* complain about our ioport conflicting with
* another device if we are going to use it.
*/
+ io_error = ahc_linux_pci_reserve_io_region(ahc, &base);
if (maddr == NULL) {
- ahc->tag = BUS_SPACE_PIO;
- command &= ~(PCIM_CMD_MEMEN|PCIM_CMD_PORTEN);
- ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
- base = pci_resource_start(ahc->dev_softc, 0);
-#else
- base = ahc_pci_read_config(ahc->dev_softc, PCIR_MAPS, 4);
- base &= PCI_BASE_ADDRESS_IO_MASK;
-#endif
- if (base == 0) {
- printf("aic7xxx: PCI%d:%d:%d No mapping available. "
- "Cannot map device.\n",
- ahc_get_pci_bus(ahc->dev_softc),
- ahc_get_pci_slot(ahc->dev_softc),
- ahc_get_pci_function(ahc->dev_softc));
- return (ENXIO);
- }
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
- if (check_region(base, 256) != 0) {
-#else
- if (request_region(base, 256, "aic7xxx") == 0) {
-#endif
+ error = io_error;
+ if (error != 0) {
printf("aic7xxx: PCI%d:%d:%d IO region 0x%lx[0..255] "
- "in use. Cannot map device.\n",
+ "unavailable. Cannot map device.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc),
base);
base = 0;
- return (EBUSY);
+ } else {
+ ahc->tag = BUS_SPACE_PIO;
+ ahc->bsh.ioport = base;
+ command |= PCIM_CMD_PORTEN;
}
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
- request_region(base, 256, "aic7xxx");
-#endif
- ahc->bsh.ioport = base;
- command |= PCIM_CMD_PORTEN;
- ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
}
- return (0);
+ ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
+ return (error);
}
int
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_linux.h#65 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_linux.h#72 $
*
- * Copyright (c) 2000, 2001 Adaptec Inc.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_linux.h#65 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_linux.h#72 $
*
*/
#ifndef _AIC7XXX_LINUX_H_
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/version.h>
+#include <linux/module.h>
+#include <asm/byteorder.h>
#ifndef KERNEL_VERSION
#define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
#define ahc_le32toh(x) le32_to_cpu(x)
#define ahc_le64toh(x) le64_to_cpu(x)
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#ifndef BYTE_ORDER
+#if defined(__BIG_ENDIAN)
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+#if defined(__LITTLE_ENDIAN)
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+#endif /* BYTE_ORDER */
+
/************************* Configuration Data *********************************/
extern int aic7xxx_no_probe;
extern int aic7xxx_detect_complete;
#include <linux/smp.h>
#endif
-#define AIC7XXX_DRIVER_VERSION "6.2.1"
+#define AIC7XXX_DRIVER_VERSION "6.2.4"
/**************************** Front End Queues ********************************/
/*
AHC_DEV_TIMER_ACTIVE = 0x04, /* Our timer is active */
AHC_DEV_ON_RUN_LIST = 0x08, /* Queued to be run later */
AHC_DEV_Q_BASIC = 0x10, /* Allow basic device queuing */
- AHC_DEV_Q_TAGGED = 0x20 /* Allow full SCSI2 command queueing */
+ AHC_DEV_Q_TAGGED = 0x20, /* Allow full SCSI2 command queueing */
+ AHC_DEV_PERIODIC_OTAG = 0x40 /* Send OTAG to prevent starvation */
} ahc_dev_flags;
struct ahc_linux_target;
/*
* How many transactions have been queued
* without the device going idle. We use
- * this statistic to
+ * this statistic to determine when to issue
+ * an ordered tag to prevent transaction
+ * starvation. This statistic is only updated
+ * if the AHC_DEV_PERIODIC_OTAG flag is set
+ * on this device.
*/
u_int commands_since_idle_or_otag;
-#define AHC_OTAG_THRESH 250
+#define AHC_OTAG_THRESH 500
int lun;
struct ahc_linux_target *target;
/***************************** Low Level I/O **********************************/
-#if defined(__powerpc__) || defined(__i386__) || defined(__ia64__) || defined(__x86_64__)
+#if defined(__powerpc__) || defined(__i386__) || defined(__ia64__)
#define MMAPIO
#endif
static __inline uint8_t
ahc_inb(struct ahc_softc * ahc, long port)
{
-#ifdef MMAPIO
uint8_t x;
+#ifdef MMAPIO
if (ahc->tag == BUS_SPACE_MEMIO) {
x = readb(ahc->bsh.maddr + port);
} else {
x = inb(ahc->bsh.ioport + port);
}
- mb();
- return (x);
#else
- return (inb(ahc->bsh.ioport + port));
+ x = inb(ahc->bsh.ioport + port);
#endif
+ mb();
+ return (x);
}
static __inline void
} else {
outb(val, ahc->bsh.ioport + port);
}
- mb();
#else
outb(val, ahc->bsh.ioport + port);
#endif
+ mb();
}
static __inline void
* 3940, 2940, aic7895, aic7890, aic7880,
* aic7870, aic7860 and aic7850 SCSI controllers
*
- * Copyright (c) 1995-2000 Justin T. Gibbs
+ * Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
- * without modification, immediately at the beginning of the file.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#28 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#32 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.6 2000/11/10 20:13:41 gibbs Exp $
*/
#define DEVID_9005_TYPE(id) ((id) & 0xF)
#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
-#define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */
+#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
#define CACHESIZE 0x0000003ful /* only 5 bits */
#define LATTIME 0x0000ff00ul
+static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
+ uint16_t subvendor, uint16_t subdevice);
static int ahc_ext_scbram_present(struct ahc_softc *ahc);
static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
int pcheck, int fast, int large);
static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
static uint8_t read_brdctl(struct ahc_softc *ahc);
+static int
+ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
+ uint16_t subdevice, uint16_t subvendor)
+{
+ int result;
+
+ /* Default to invalid. */
+ result = 0;
+ if (vendor == 0x9005
+ && subvendor == 0x9005
+ && subdevice != device
+ && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
+
+ switch (SUBID_9005_TYPE(subdevice)) {
+ case SUBID_9005_TYPE_MB:
+ break;
+ case SUBID_9005_TYPE_CARD:
+ case SUBID_9005_TYPE_LCCARD:
+ /*
+ * Currently only trust Adaptec cards to
+ * get the sub device info correct.
+ */
+ if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
+ result = 1;
+ break;
+ case SUBID_9005_TYPE_RAID:
+ break;
+ default:
+ break;
+ }
+ }
+ return (result);
+}
+
struct ahc_pci_identity *
ahc_find_pci_device(ahc_dev_softc_t pci)
{
* ID as valid.
*/
if (ahc_get_pci_function(pci) > 0
- && subvendor == 0x9005
- && subdevice != device
- && SUBID_9005_TYPE_KNOWN(subdevice) != 0
+ && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
&& SUBID_9005_MFUNCENB(subdevice) == 0)
return (NULL);
/*
- * Copyright (c) 2000, 2001 Adaptec Inc.
+ * Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
* String handling code courtesy of Gerard Roudier's <groudier@club-internet.fr>
* sym driver.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/aic7xxx_proc.c#11 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_proc.c#13 $
*/
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
- * $Id: //depot/src/aic7xxx/aic7xxx.seq#33 $
- * $Id: //depot/src/aic7xxx/aic7xxx.reg#19 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#37 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#24 $
*/
#define SCSISEQ 0x00
#define SSTAT3 0x0e
#define SCSICNT 0xf0
+#define U2OFFCNT 0x7f
#define OFFCNT 0x0f
#define SCSIID_ULTRA2 0x0f
#define INITIATOR_TAG 0x56
#define SEQ_FLAGS2 0x57
+#define TARGET_MSG_PENDING 0x02
#define SCB_DMA 0x01
#define SCSICONF 0x5a
#define SCB_CDB_PTR 0xa0
#define SCB_RESIDUAL_DATACNT 0xa0
#define SCB_CDB_STORE 0xa0
-#define SCB_TARGET_INFO 0xa0
#define SCB_RESIDUAL_SGPTR 0xa4
#define SCB_SCSI_STATUS 0xa8
-#define SCB_CDB_STORE_PAD 0xa9
+#define SCB_TARGET_PHASES 0xa9
+
+#define SCB_TARGET_DATA_DIR 0xaa
+
+#define SCB_TARGET_ITAG 0xab
#define SCB_DATAPTR 0xac
#define SG_CACHE_PRE 0xfc
-#define SCB_INITIATOR_TAG 0x03
-#define SCB_TARGET_DATA_DIR 0x01
-#define SCB_TARGET_PHASES 0x00
#define MAX_OFFSET_ULTRA2 0x7f
#define MAX_OFFSET_16BIT 0x08
#define BUS_8_BIT 0x00
#define TID_SHIFT 0x04
#define SCB_DOWNLOAD_SIZE_64 0x30
#define HOST_MAILBOX_SHIFT 0x04
-#define SCB_TARGET_STATUS 0x02
#define CMD_GROUP_CODE_SHIFT 0x05
#define CCSGRAM_MAXSEGS 0x10
#define SCB_LIST_NULL 0xff
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
- * $Id: //depot/src/aic7xxx/aic7xxx.seq#33 $
- * $Id: //depot/src/aic7xxx/aic7xxx.reg#19 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#37 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#24 $
*/
static uint8_t seqprog[] = {
0xb2, 0x00, 0x00, 0x08,
0xf7, 0x11, 0x22, 0x08,
- 0x00, 0x65, 0xde, 0x59,
+ 0x00, 0x65, 0xe0, 0x59,
0xf7, 0x01, 0x02, 0x08,
0xff, 0x6a, 0x24, 0x08,
0x40, 0x00, 0x40, 0x68,
0x01, 0x4d, 0xc8, 0x30,
0x00, 0x4c, 0x12, 0x70,
0x01, 0x39, 0xa2, 0x30,
- 0x00, 0x6a, 0xa6, 0x5e,
+ 0x00, 0x6a, 0xb2, 0x5e,
0x01, 0x51, 0x20, 0x31,
0x01, 0x57, 0xae, 0x00,
0x0d, 0x6a, 0x76, 0x00,
- 0x00, 0x51, 0xf8, 0x5d,
+ 0x00, 0x51, 0x04, 0x5e,
0x01, 0x51, 0xc8, 0x30,
- 0x00, 0x39, 0xd8, 0x60,
+ 0x00, 0x39, 0xc8, 0x60,
0x00, 0xbb, 0x30, 0x70,
- 0xc1, 0x6a, 0xbe, 0x5e,
+ 0xc1, 0x6a, 0xca, 0x5e,
0x01, 0xbf, 0x72, 0x30,
0x01, 0x40, 0x7e, 0x31,
0x01, 0x90, 0x80, 0x30,
0x01, 0x4d, 0x9a, 0x18,
0xfe, 0x57, 0xae, 0x08,
0x01, 0x40, 0x20, 0x31,
- 0x00, 0x65, 0xdc, 0x58,
+ 0x00, 0x65, 0xcc, 0x58,
0x60, 0x0b, 0x40, 0x78,
0x08, 0x6a, 0x18, 0x00,
0x08, 0x11, 0x22, 0x00,
0x60, 0x0b, 0x00, 0x78,
- 0x40, 0x0b, 0x0c, 0x69,
- 0x80, 0x0b, 0xc6, 0x78,
+ 0x40, 0x0b, 0xfc, 0x68,
+ 0x80, 0x0b, 0xb6, 0x78,
0x20, 0x6a, 0x16, 0x00,
0xa4, 0x6a, 0x06, 0x00,
0x08, 0x3c, 0x78, 0x00,
0x01, 0x50, 0xc8, 0x30,
0xe0, 0x6a, 0xcc, 0x00,
- 0x48, 0x6a, 0xe2, 0x5d,
+ 0x48, 0x6a, 0xee, 0x5d,
0x01, 0x6a, 0xdc, 0x01,
0x88, 0x6a, 0xcc, 0x00,
- 0x48, 0x6a, 0xe2, 0x5d,
+ 0x48, 0x6a, 0xee, 0x5d,
0x01, 0x6a, 0x26, 0x01,
0xf0, 0x19, 0x7a, 0x08,
0x0f, 0x18, 0xc8, 0x08,
0x80, 0x3d, 0x7a, 0x00,
0x01, 0x3d, 0xd8, 0x31,
0x01, 0x3d, 0x32, 0x31,
- 0x10, 0x03, 0x56, 0x79,
- 0x00, 0x65, 0x04, 0x59,
- 0x80, 0x66, 0xa2, 0x78,
+ 0x10, 0x03, 0x46, 0x79,
+ 0x00, 0x65, 0xf4, 0x58,
+ 0x80, 0x66, 0xae, 0x78,
0x01, 0x66, 0xd8, 0x31,
0x01, 0x66, 0x32, 0x31,
- 0x40, 0x66, 0x80, 0x68,
+ 0x3f, 0x66, 0x7c, 0x08,
+ 0x40, 0x66, 0x82, 0x68,
0x01, 0x3c, 0x78, 0x00,
- 0x10, 0x03, 0xaa, 0x78,
- 0x00, 0x65, 0x04, 0x59,
+ 0x10, 0x03, 0x9e, 0x78,
+ 0x00, 0x65, 0xf4, 0x58,
0xe0, 0x66, 0xc8, 0x18,
0x00, 0x65, 0xaa, 0x50,
0xdd, 0x66, 0xc8, 0x18,
0x00, 0x65, 0xaa, 0x48,
0x01, 0x66, 0xd8, 0x31,
0x01, 0x66, 0x32, 0x31,
- 0x10, 0x03, 0x56, 0x79,
- 0x00, 0x65, 0x04, 0x59,
+ 0x10, 0x03, 0x46, 0x79,
+ 0x00, 0x65, 0xf4, 0x58,
0x01, 0x66, 0xd8, 0x31,
0x01, 0x66, 0x32, 0x31,
0x01, 0x66, 0xac, 0x30,
0x40, 0x3c, 0x78, 0x00,
- 0x10, 0x03, 0xa0, 0x78,
- 0x00, 0x65, 0x04, 0x59,
- 0x00, 0x65, 0xaa, 0x40,
- 0x61, 0x6a, 0xbe, 0x5e,
- 0x08, 0x51, 0x2e, 0x71,
- 0x02, 0x0b, 0xa6, 0x78,
- 0x00, 0x65, 0xa2, 0x40,
- 0x80, 0x86, 0xc8, 0x08,
- 0x01, 0x4f, 0xc8, 0x30,
- 0x00, 0x50, 0xbc, 0x60,
- 0xc4, 0x6a, 0x54, 0x5d,
- 0x40, 0x3c, 0xb8, 0x78,
- 0x28, 0x6a, 0x6a, 0x5d,
- 0x00, 0x65, 0x54, 0x41,
- 0x08, 0x6a, 0x6a, 0x5d,
- 0x00, 0x65, 0x54, 0x41,
0xff, 0x6a, 0xd8, 0x01,
0xff, 0x6a, 0x32, 0x01,
0x90, 0x3c, 0x78, 0x00,
- 0x10, 0x03, 0x4a, 0x69,
- 0x00, 0x65, 0x2e, 0x41,
+ 0x02, 0x57, 0x3a, 0x69,
+ 0x10, 0x03, 0x38, 0x69,
+ 0x00, 0x65, 0x1e, 0x41,
+ 0x02, 0x57, 0xae, 0x00,
+ 0x00, 0x65, 0x9e, 0x40,
+ 0x61, 0x6a, 0xca, 0x5e,
+ 0x08, 0x51, 0x1e, 0x71,
+ 0x02, 0x0b, 0xb2, 0x78,
+ 0x00, 0x65, 0xae, 0x40,
0x1a, 0x01, 0x02, 0x00,
0xf0, 0x19, 0x7a, 0x08,
0x0f, 0x0f, 0xc8, 0x08,
0x0f, 0x05, 0xc8, 0x08,
0x00, 0x3d, 0x7a, 0x00,
- 0x08, 0x1f, 0xd4, 0x78,
+ 0x08, 0x1f, 0xc4, 0x78,
0x80, 0x3d, 0x7a, 0x00,
0x20, 0x6a, 0x16, 0x00,
- 0x00, 0x65, 0xbe, 0x41,
- 0x00, 0x65, 0x98, 0x5e,
+ 0x00, 0x65, 0xc0, 0x41,
+ 0x00, 0x65, 0xa4, 0x5e,
0x00, 0x65, 0x12, 0x40,
- 0x20, 0x11, 0xe2, 0x68,
+ 0x20, 0x11, 0xd2, 0x68,
0x20, 0x6a, 0x18, 0x00,
0x20, 0x11, 0x22, 0x00,
0xf7, 0x1f, 0xca, 0x08,
- 0x80, 0xb9, 0xe8, 0x78,
+ 0x80, 0xb9, 0xd8, 0x78,
0x08, 0x65, 0xca, 0x00,
0x01, 0x65, 0x3e, 0x30,
0x01, 0xb9, 0x1e, 0x30,
0x7f, 0xb9, 0x0a, 0x08,
0x01, 0xb9, 0x0a, 0x30,
0x01, 0x54, 0xca, 0x30,
- 0x80, 0xb8, 0xf6, 0x78,
+ 0x80, 0xb8, 0xe6, 0x78,
0x80, 0x65, 0xca, 0x00,
0x01, 0x65, 0x00, 0x34,
0x01, 0x54, 0x00, 0x34,
0x1a, 0x01, 0x02, 0x00,
- 0x08, 0xb8, 0x00, 0x79,
+ 0x08, 0xb8, 0xf0, 0x78,
0x20, 0x01, 0x02, 0x00,
0x02, 0xbd, 0x08, 0x34,
0x01, 0xbd, 0x08, 0x34,
0x08, 0x01, 0x02, 0x00,
- 0x02, 0x0b, 0x06, 0x79,
+ 0x02, 0x0b, 0xf6, 0x78,
0xf7, 0x01, 0x02, 0x08,
0x01, 0x06, 0xcc, 0x34,
0xb2, 0x00, 0x00, 0x08,
0x01, 0xbf, 0x80, 0x30,
0x01, 0xb9, 0x7a, 0x30,
0x01, 0xba, 0x7c, 0x30,
- 0x00, 0x65, 0xfa, 0x58,
- 0x80, 0x0b, 0xba, 0x79,
- 0xe4, 0x6a, 0x54, 0x5d,
- 0x80, 0xba, 0x6a, 0x5d,
- 0x20, 0xb8, 0x26, 0x79,
- 0x20, 0x6a, 0x6a, 0x5d,
- 0x00, 0xa3, 0x6a, 0x5d,
- 0x01, 0xa0, 0x78, 0x30,
- 0x10, 0xb8, 0x2e, 0x79,
- 0xe4, 0x6a, 0x54, 0x5d,
- 0x00, 0x65, 0xa2, 0x40,
- 0x10, 0x03, 0x46, 0x69,
- 0x08, 0x3c, 0x62, 0x69,
- 0x04, 0x3c, 0x88, 0x69,
- 0x02, 0x3c, 0x8e, 0x69,
- 0x01, 0x3c, 0x4c, 0x79,
+ 0x00, 0x65, 0xea, 0x58,
+ 0x80, 0x0b, 0xbc, 0x79,
+ 0xe4, 0x6a, 0x60, 0x5d,
+ 0x80, 0xba, 0x76, 0x5d,
+ 0x20, 0xb8, 0x16, 0x79,
+ 0x20, 0x6a, 0x76, 0x5d,
+ 0x00, 0xab, 0x76, 0x5d,
+ 0x01, 0xa9, 0x78, 0x30,
+ 0x10, 0xb8, 0x1e, 0x79,
+ 0xe4, 0x6a, 0x60, 0x5d,
+ 0x00, 0x65, 0xae, 0x40,
+ 0x10, 0x03, 0x36, 0x69,
+ 0x08, 0x3c, 0x52, 0x69,
+ 0x04, 0x3c, 0x8a, 0x69,
+ 0x02, 0x3c, 0x90, 0x69,
+ 0x01, 0x3c, 0x3c, 0x79,
0x01, 0x6a, 0xa2, 0x30,
- 0x00, 0x65, 0x9a, 0x59,
- 0x04, 0x51, 0x3c, 0x61,
- 0x00, 0x6a, 0xa6, 0x5e,
+ 0x00, 0x65, 0x9c, 0x59,
+ 0x04, 0x51, 0x2c, 0x61,
+ 0x00, 0x6a, 0xb2, 0x5e,
0x0d, 0x6a, 0x76, 0x00,
- 0x00, 0xbb, 0xf8, 0x5d,
- 0x00, 0x65, 0x26, 0x41,
+ 0x00, 0xbb, 0x04, 0x5e,
+ 0x00, 0x65, 0x16, 0x41,
0xa4, 0x6a, 0x06, 0x00,
- 0x00, 0x65, 0x04, 0x59,
- 0x00, 0x65, 0xa2, 0x40,
- 0xe4, 0x6a, 0x54, 0x5d,
- 0x20, 0x3c, 0x52, 0x79,
- 0x02, 0x6a, 0x6a, 0x5d,
- 0x04, 0x6a, 0x6a, 0x5d,
- 0x01, 0x03, 0x54, 0x69,
+ 0x00, 0x65, 0xf4, 0x58,
+ 0x00, 0x65, 0xae, 0x40,
+ 0xe4, 0x6a, 0x60, 0x5d,
+ 0x20, 0x3c, 0x42, 0x79,
+ 0x02, 0x6a, 0x76, 0x5d,
+ 0x04, 0x6a, 0x76, 0x5d,
+ 0x01, 0x03, 0x44, 0x69,
0xf7, 0x11, 0x22, 0x08,
0xff, 0x6a, 0x24, 0x08,
0xff, 0x6a, 0x06, 0x08,
0x01, 0x6a, 0x7e, 0x00,
- 0x00, 0x65, 0x9a, 0x59,
+ 0x00, 0x65, 0x9c, 0x59,
0x00, 0x65, 0x04, 0x40,
- 0x84, 0x6a, 0x54, 0x5d,
- 0x00, 0x65, 0x04, 0x59,
+ 0x80, 0x86, 0xc8, 0x08,
+ 0x01, 0x4f, 0xc8, 0x30,
+ 0x00, 0x50, 0x64, 0x61,
+ 0xc4, 0x6a, 0x60, 0x5d,
+ 0x40, 0x3c, 0x60, 0x79,
+ 0x28, 0x6a, 0x76, 0x5d,
+ 0x00, 0x65, 0x44, 0x41,
+ 0x08, 0x6a, 0x76, 0x5d,
+ 0x00, 0x65, 0x44, 0x41,
+ 0x84, 0x6a, 0x60, 0x5d,
+ 0x00, 0x65, 0xf4, 0x58,
0x01, 0x66, 0xc8, 0x30,
0x01, 0x64, 0xd8, 0x31,
0x01, 0x64, 0x32, 0x31,
0x5b, 0x64, 0xc8, 0x28,
0x30, 0x64, 0xca, 0x18,
0x01, 0x6c, 0xc8, 0x30,
- 0xff, 0x64, 0x84, 0x79,
+ 0xff, 0x64, 0x86, 0x79,
0x08, 0x01, 0x02, 0x00,
- 0x02, 0x0b, 0x76, 0x79,
- 0x01, 0x64, 0x7c, 0x61,
+ 0x02, 0x0b, 0x78, 0x79,
+ 0x01, 0x64, 0x7e, 0x61,
0xf7, 0x01, 0x02, 0x08,
0x01, 0x06, 0xd8, 0x31,
0x01, 0x06, 0x32, 0x31,
0xff, 0x64, 0xc8, 0x18,
- 0xff, 0x64, 0x76, 0x69,
+ 0xff, 0x64, 0x78, 0x69,
0xf7, 0x3c, 0x78, 0x08,
- 0x00, 0x65, 0x2e, 0x41,
- 0x40, 0xa1, 0x7e, 0x10,
- 0x04, 0xa1, 0x54, 0x5d,
- 0x00, 0x65, 0x50, 0x42,
- 0xc4, 0x6a, 0x54, 0x5d,
+ 0x00, 0x65, 0x1e, 0x41,
+ 0x40, 0xaa, 0x7e, 0x10,
+ 0x04, 0xaa, 0x60, 0x5d,
+ 0x00, 0x65, 0x52, 0x42,
+ 0xc4, 0x6a, 0x60, 0x5d,
0xc0, 0x6a, 0x7e, 0x00,
- 0x00, 0xa2, 0x6a, 0x5d,
+ 0x00, 0xa8, 0x76, 0x5d,
0xe4, 0x6a, 0x06, 0x00,
- 0x00, 0x6a, 0x6a, 0x5d,
- 0x00, 0x65, 0x54, 0x41,
- 0x10, 0x3c, 0x9e, 0x69,
- 0x00, 0xbb, 0x74, 0x44,
+ 0x00, 0x6a, 0x76, 0x5d,
+ 0x00, 0x65, 0x44, 0x41,
+ 0x10, 0x3c, 0xa0, 0x69,
+ 0x00, 0xbb, 0x80, 0x44,
0x18, 0x6a, 0xda, 0x01,
0x01, 0x69, 0xd8, 0x31,
0x1c, 0x6a, 0xd0, 0x01,
0x09, 0xee, 0xdc, 0x01,
- 0x80, 0xee, 0xa6, 0x79,
+ 0x80, 0xee, 0xa8, 0x79,
0xff, 0x6a, 0xdc, 0x09,
0x01, 0x93, 0x26, 0x01,
0x03, 0x6a, 0x2a, 0x01,
0x01, 0x69, 0x32, 0x31,
- 0x1c, 0x6a, 0xc6, 0x5d,
+ 0x1c, 0x6a, 0xd2, 0x5d,
0x0a, 0x93, 0x26, 0x01,
- 0x00, 0x65, 0x8e, 0x5e,
+ 0x00, 0x65, 0x9a, 0x5e,
0x01, 0x50, 0xa0, 0x18,
0x02, 0x6a, 0x22, 0x05,
0x80, 0x6a, 0x74, 0x00,
0x80, 0x3c, 0x78, 0x00,
- 0x00, 0x65, 0xbe, 0x5d,
+ 0x00, 0x65, 0xca, 0x5d,
0x01, 0x3f, 0xc8, 0x30,
- 0xbf, 0x64, 0x50, 0x7a,
- 0x80, 0x64, 0x9a, 0x73,
- 0xa0, 0x64, 0xf8, 0x73,
- 0xc0, 0x64, 0xec, 0x73,
- 0xe0, 0x64, 0x28, 0x74,
- 0x01, 0x6a, 0xbe, 0x5e,
- 0x00, 0x65, 0xbe, 0x41,
+ 0xbf, 0x64, 0x52, 0x7a,
+ 0x80, 0x64, 0xa6, 0x73,
+ 0xa0, 0x64, 0x04, 0x74,
+ 0xc0, 0x64, 0xf8, 0x73,
+ 0xe0, 0x64, 0x34, 0x74,
+ 0x01, 0x6a, 0xca, 0x5e,
+ 0x00, 0x65, 0xc0, 0x41,
0xf7, 0x11, 0x22, 0x08,
0x01, 0x06, 0xd4, 0x30,
0xff, 0x6a, 0x24, 0x08,
0xf7, 0x01, 0x02, 0x08,
- 0x09, 0x0c, 0xd8, 0x79,
+ 0x09, 0x0c, 0xda, 0x79,
0x08, 0x0c, 0x04, 0x68,
- 0xb1, 0x6a, 0xbe, 0x5e,
+ 0xb1, 0x6a, 0xca, 0x5e,
0xff, 0x6a, 0x26, 0x09,
0x12, 0x01, 0x02, 0x00,
0x02, 0x6a, 0x08, 0x30,
0x00, 0xa5, 0x4a, 0x21,
0x00, 0xa6, 0x4c, 0x21,
0x00, 0xa7, 0x4e, 0x25,
- 0x08, 0xeb, 0xc2, 0x7e,
- 0x80, 0xeb, 0xf8, 0x79,
+ 0x08, 0xeb, 0xce, 0x7e,
+ 0x80, 0xeb, 0xfa, 0x79,
0xff, 0x6a, 0xd6, 0x09,
- 0x08, 0xeb, 0xfc, 0x69,
+ 0x08, 0xeb, 0xfe, 0x69,
0xff, 0x6a, 0xd4, 0x0c,
- 0x80, 0xa3, 0xc2, 0x6e,
- 0x88, 0xeb, 0x12, 0x72,
- 0x08, 0xeb, 0xc2, 0x6e,
- 0x04, 0xea, 0x16, 0xe2,
- 0x08, 0xee, 0xc2, 0x6e,
+ 0x80, 0xa3, 0xce, 0x6e,
+ 0x88, 0xeb, 0x14, 0x72,
+ 0x08, 0xeb, 0xce, 0x6e,
+ 0x04, 0xea, 0x18, 0xe2,
+ 0x08, 0xee, 0xce, 0x6e,
0x04, 0x6a, 0xd0, 0x81,
0x05, 0xa4, 0xc0, 0x89,
0x03, 0xa5, 0xc2, 0x31,
0x09, 0x6a, 0xd6, 0x05,
- 0x00, 0x65, 0xfa, 0x59,
+ 0x00, 0x65, 0xfc, 0x59,
0x06, 0xa4, 0xd4, 0x89,
- 0x80, 0x94, 0xc2, 0x7e,
+ 0x80, 0x94, 0xce, 0x7e,
0x07, 0xe9, 0x10, 0x31,
- 0x01, 0x8c, 0x1e, 0x7a,
+ 0x01, 0x8c, 0x20, 0x7a,
0x01, 0x55, 0xaa, 0x10,
0x01, 0xe9, 0x46, 0x31,
- 0x00, 0xa3, 0xa0, 0x5e,
- 0x00, 0x65, 0xec, 0x59,
+ 0x00, 0xa3, 0xac, 0x5e,
+ 0x00, 0x65, 0xee, 0x59,
0x01, 0xa4, 0xca, 0x30,
- 0x01, 0x55, 0x2a, 0x7a,
+ 0x01, 0x55, 0x2c, 0x7a,
0x04, 0x65, 0xca, 0x00,
- 0x80, 0xa3, 0x2e, 0x7a,
+ 0x80, 0xa3, 0x30, 0x7a,
0x02, 0x65, 0xca, 0x00,
0x01, 0x65, 0xf8, 0x31,
0x80, 0x93, 0x26, 0x01,
0x01, 0x8c, 0xc8, 0x30,
0x00, 0x88, 0xc8, 0x18,
0x02, 0x64, 0xc8, 0x88,
- 0xff, 0x64, 0xc2, 0x7e,
- 0xff, 0x8d, 0x44, 0x6a,
- 0xff, 0x8e, 0x44, 0x6a,
+ 0xff, 0x64, 0xce, 0x7e,
+ 0xff, 0x8d, 0x46, 0x6a,
+ 0xff, 0x8e, 0x46, 0x6a,
0x03, 0x8c, 0xd4, 0x98,
- 0x00, 0x65, 0xc2, 0x56,
+ 0x00, 0x65, 0xce, 0x56,
0x01, 0x64, 0x70, 0x30,
0xff, 0x64, 0xc8, 0x10,
0x01, 0x64, 0xc8, 0x18,
0x00, 0x8c, 0x18, 0x19,
0xff, 0x8d, 0x1a, 0x21,
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+ 0x01, 0xa4, 0x6c, 0x7c,
+ 0xff, 0xa8, 0x7c, 0x7c,
0x04, 0xb4, 0x68, 0x01,
0x01, 0x6a, 0x76, 0x00,
- 0x00, 0xbb, 0xf8, 0x5d,
- 0xff, 0xa8, 0x70, 0x7c,
- 0x71, 0x6a, 0xbe, 0x5e,
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+ 0xff, 0xa8, 0x7c, 0x7c,
+ 0x71, 0x6a, 0xca, 0x5e,
+ 0x40, 0x51, 0x7c, 0x64,
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+ 0x00, 0x65, 0xd2, 0x41,
+ 0x00, 0x65, 0xa4, 0x5e,
0x01, 0x65, 0xa2, 0x30,
0x01, 0xf8, 0xc8, 0x30,
0x01, 0x4e, 0xc8, 0x30,
- 0x00, 0x6a, 0x9c, 0xdd,
- 0x00, 0x51, 0xae, 0x5d,
+ 0x00, 0x6a, 0xa8, 0xdd,
+ 0x00, 0x51, 0xba, 0x5d,
0x01, 0x4e, 0x9c, 0x18,
0x02, 0x6a, 0x22, 0x05,
0x04, 0xb8, 0x70, 0x01,
- 0x00, 0x65, 0xba, 0x5e,
- 0x20, 0xb8, 0xd0, 0x69,
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+ 0x20, 0xb8, 0xd2, 0x69,
0x01, 0xbb, 0xa2, 0x30,
0x01, 0xba, 0x7c, 0x30,
- 0x00, 0xb9, 0xb4, 0x5c,
- 0x00, 0x65, 0xd0, 0x41,
+ 0x00, 0xb9, 0xc0, 0x5c,
+ 0x00, 0x65, 0xd2, 0x41,
0x01, 0x06, 0xd4, 0x30,
- 0x20, 0x3c, 0xbe, 0x79,
- 0x20, 0x3c, 0x50, 0x7c,
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0x01, 0xb4, 0x68, 0x01,
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0x04, 0x14, 0x58, 0x31,
0x01, 0x06, 0xd4, 0x30,
0x08, 0xa0, 0x60, 0x31,
0xac, 0x6a, 0xcc, 0x00,
- 0x14, 0x6a, 0xda, 0x5d,
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0x01, 0x06, 0xd4, 0x30,
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0xdf, 0x3c, 0x78, 0x08,
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0x4c, 0x65, 0xcc, 0x28,
0x01, 0x3e, 0x20, 0x31,
0xd0, 0x66, 0xcc, 0x18,
0xd0, 0x65, 0xca, 0x18,
0x01, 0x3e, 0x20, 0x31,
0x30, 0x65, 0xd4, 0x18,
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0xe1, 0x6a, 0x22, 0x01,
0xff, 0x6a, 0xd4, 0x08,
0x20, 0x65, 0xd4, 0x18,
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0xe1, 0x6a, 0x22, 0x01,
0xff, 0x6a, 0xd4, 0x08,
0x20, 0x65, 0xca, 0x18,
0xe0, 0x65, 0xd4, 0x18,
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0xe1, 0x6a, 0x22, 0x01,
0xff, 0x6a, 0xd4, 0x08,
0xd0, 0x65, 0xd4, 0x18,
- 0x00, 0x65, 0xe6, 0x54,
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0xe1, 0x6a, 0x22, 0x01,
0xff, 0x6a, 0xd4, 0x08,
0x01, 0x6c, 0xa2, 0x30,
- 0xff, 0x51, 0xf8, 0x74,
- 0x00, 0x51, 0x74, 0x5d,
+ 0xff, 0x51, 0x04, 0x75,
+ 0x00, 0x51, 0x80, 0x5d,
0x01, 0x51, 0x20, 0x31,
- 0x00, 0x65, 0x1a, 0x45,
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0x01, 0xba, 0xc8, 0x30,
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0x80, 0x3c, 0x78, 0x00,
0x01, 0x06, 0xd4, 0x30,
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0x01, 0x3c, 0x78, 0x00,
- 0xe0, 0x3f, 0x36, 0x65,
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0x02, 0x3c, 0x78, 0x00,
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0x01, 0x51, 0x20, 0x31,
0x04, 0x3c, 0x78, 0x00,
0x01, 0xb9, 0xc8, 0x30,
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0x08, 0x3c, 0x78, 0x00,
0x01, 0xba, 0xc8, 0x30,
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0x10, 0x3c, 0x78, 0x00,
- 0x04, 0xb8, 0x34, 0x7d,
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0xfb, 0xb8, 0x70, 0x09,
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0x01, 0x90, 0xc8, 0x30,
0xff, 0x6a, 0xa2, 0x00,
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0x01, 0x64, 0x20, 0x31,
0x80, 0x6a, 0x78, 0x00,
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- 0xff, 0x6a, 0x3a, 0x5d,
- 0x00, 0x65, 0x50, 0x44,
- 0x00, 0x65, 0x96, 0x5e,
- 0x31, 0x6a, 0xbe, 0x5e,
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+ 0x10, 0xb8, 0x5c, 0x7c,
+ 0xff, 0x6a, 0x46, 0x5d,
+ 0x00, 0x65, 0x5c, 0x44,
+ 0x00, 0x65, 0xa2, 0x5e,
+ 0x31, 0x6a, 0xca, 0x5e,
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0x10, 0x3f, 0x06, 0x00,
0x10, 0x6a, 0x06, 0x00,
0x01, 0x65, 0x74, 0x34,
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+ 0x81, 0x6a, 0xca, 0x5e,
+ 0x00, 0x65, 0x52, 0x45,
0x01, 0x06, 0xd4, 0x30,
- 0x01, 0x0c, 0x46, 0x7d,
- 0x04, 0x0c, 0x40, 0x6d,
+ 0x01, 0x0c, 0x52, 0x7d,
+ 0x04, 0x0c, 0x4c, 0x6d,
0xe0, 0x03, 0x7e, 0x08,
- 0xe0, 0x3f, 0xbe, 0x61,
+ 0xe0, 0x3f, 0xc0, 0x61,
0x01, 0x65, 0xcc, 0x30,
0x01, 0x12, 0xda, 0x34,
0x01, 0x06, 0xd4, 0x34,
- 0x01, 0x03, 0x54, 0x6d,
+ 0x01, 0x03, 0x60, 0x6d,
0x40, 0x03, 0xcc, 0x08,
0x01, 0x65, 0x06, 0x30,
0x40, 0x65, 0xc8, 0x08,
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+ 0x00, 0x66, 0x6e, 0x75,
+ 0x40, 0x65, 0x6e, 0x7d,
+ 0x00, 0x65, 0x6e, 0x5d,
0xff, 0x6a, 0xd4, 0x08,
0xff, 0x6a, 0xd4, 0x08,
0xff, 0x6a, 0xd4, 0x08,
0xff, 0x6a, 0xd4, 0x0c,
0x08, 0x01, 0x02, 0x00,
- 0x02, 0x0b, 0x6c, 0x7d,
+ 0x02, 0x0b, 0x78, 0x7d,
0x01, 0x65, 0x0c, 0x30,
- 0x02, 0x0b, 0x70, 0x7d,
+ 0x02, 0x0b, 0x7c, 0x7d,
0xf7, 0x01, 0x02, 0x0c,
0x01, 0x65, 0xc8, 0x30,
- 0xff, 0x41, 0x94, 0x75,
+ 0xff, 0x41, 0xa0, 0x75,
0x01, 0x41, 0x20, 0x31,
0xff, 0x6a, 0xa4, 0x00,
- 0x00, 0x65, 0x84, 0x45,
- 0xff, 0xbf, 0x94, 0x75,
+ 0x00, 0x65, 0x90, 0x45,
+ 0xff, 0xbf, 0xa0, 0x75,
0x01, 0x90, 0xa4, 0x30,
0x01, 0xbf, 0x20, 0x31,
- 0x00, 0xbb, 0x7e, 0x65,
- 0xff, 0x52, 0x92, 0x75,
+ 0x00, 0xbb, 0x8a, 0x65,
+ 0xff, 0x52, 0x9e, 0x75,
0x01, 0xbf, 0xcc, 0x30,
0x01, 0x90, 0xca, 0x30,
0x01, 0x52, 0x20, 0x31,
0x01, 0x65, 0x20, 0x35,
0x01, 0xbf, 0x82, 0x34,
0x01, 0x64, 0xa2, 0x30,
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+ 0x00, 0x6a, 0xb2, 0x5e,
0x0d, 0x6a, 0x76, 0x00,
- 0x00, 0x51, 0xf8, 0x45,
+ 0x00, 0x51, 0x04, 0x46,
0x01, 0x65, 0xa4, 0x30,
0xe0, 0x6a, 0xcc, 0x00,
- 0x48, 0x6a, 0xec, 0x5d,
+ 0x48, 0x6a, 0xf8, 0x5d,
0x01, 0x6a, 0xd0, 0x01,
0x01, 0x6a, 0xdc, 0x05,
0x88, 0x6a, 0xcc, 0x00,
- 0x48, 0x6a, 0xec, 0x5d,
- 0x01, 0x6a, 0xc6, 0x5d,
+ 0x48, 0x6a, 0xf8, 0x5d,
+ 0x01, 0x6a, 0xd2, 0x5d,
0x01, 0x6a, 0x26, 0x05,
0x01, 0x65, 0xd8, 0x31,
0x09, 0xee, 0xdc, 0x01,
- 0x80, 0xee, 0xb2, 0x7d,
+ 0x80, 0xee, 0xbe, 0x7d,
0xff, 0x6a, 0xdc, 0x0d,
0x01, 0x65, 0x32, 0x31,
0x0a, 0x93, 0x26, 0x01,
- 0x00, 0x65, 0x8e, 0x46,
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- 0x01, 0x0c, 0xbe, 0x7d,
- 0x04, 0x0c, 0xbc, 0x6d,
+ 0x00, 0x65, 0x9a, 0x46,
+ 0x81, 0x6a, 0xca, 0x5e,
+ 0x01, 0x0c, 0xca, 0x7d,
+ 0x04, 0x0c, 0xc8, 0x6d,
0xe0, 0x03, 0x06, 0x08,
0xe0, 0x03, 0x7e, 0x0c,
0x01, 0x65, 0x18, 0x31,
0x01, 0x6c, 0xda, 0x34,
0x3d, 0x64, 0xa4, 0x28,
0x55, 0x64, 0xc8, 0x28,
- 0x00, 0x65, 0xec, 0x45,
+ 0x00, 0x65, 0xf8, 0x45,
0x2e, 0x64, 0xa4, 0x28,
0x66, 0x64, 0xc8, 0x28,
0x00, 0x6c, 0xda, 0x18,
0x00, 0x6c, 0xda, 0x24,
0x01, 0x65, 0xc8, 0x30,
0xe0, 0x6a, 0xcc, 0x00,
- 0x44, 0x6a, 0xe8, 0x5d,
+ 0x44, 0x6a, 0xf4, 0x5d,
0x01, 0x90, 0xe2, 0x31,
- 0x04, 0x3b, 0x0c, 0x7e,
+ 0x04, 0x3b, 0x18, 0x7e,
0x30, 0x6a, 0xd0, 0x01,
0x20, 0x6a, 0xd0, 0x01,
0x1d, 0x6a, 0xdc, 0x01,
- 0xdc, 0xee, 0x08, 0x66,
- 0x00, 0x65, 0x24, 0x46,
+ 0xdc, 0xee, 0x14, 0x66,
+ 0x00, 0x65, 0x30, 0x46,
0x20, 0x6a, 0xd0, 0x01,
0x01, 0x6a, 0xdc, 0x01,
0x20, 0xa0, 0xd8, 0x31,
0x09, 0xee, 0xdc, 0x01,
- 0x80, 0xee, 0x14, 0x7e,
+ 0x80, 0xee, 0x20, 0x7e,
0x11, 0x6a, 0xdc, 0x01,
- 0x50, 0xee, 0x18, 0x66,
+ 0x50, 0xee, 0x24, 0x66,
0x20, 0x6a, 0xd0, 0x01,
0x09, 0x6a, 0xdc, 0x01,
- 0x88, 0xee, 0x1e, 0x66,
+ 0x88, 0xee, 0x2a, 0x66,
0x19, 0x6a, 0xdc, 0x01,
- 0xd8, 0xee, 0x22, 0x66,
+ 0xd8, 0xee, 0x2e, 0x66,
0xff, 0x6a, 0xdc, 0x09,
- 0x18, 0xee, 0x26, 0x6e,
+ 0x18, 0xee, 0x32, 0x6e,
0xff, 0x6a, 0xd4, 0x0c,
0x88, 0x6a, 0xcc, 0x00,
- 0x44, 0x6a, 0xe8, 0x5d,
- 0x20, 0x6a, 0xc6, 0x5d,
+ 0x44, 0x6a, 0xf4, 0x5d,
+ 0x20, 0x6a, 0xd2, 0x5d,
0x01, 0x3b, 0x26, 0x31,
- 0x04, 0x3b, 0x40, 0x6e,
+ 0x04, 0x3b, 0x4c, 0x6e,
0xa0, 0x6a, 0xca, 0x00,
0x20, 0x65, 0xc8, 0x18,
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- 0x00, 0x65, 0x38, 0x66,
+ 0x00, 0x65, 0x8a, 0x5e,
+ 0x00, 0x65, 0x44, 0x66,
0x0a, 0x93, 0x26, 0x01,
- 0x00, 0x65, 0x8e, 0x46,
+ 0x00, 0x65, 0x9a, 0x46,
0xa0, 0x6a, 0xcc, 0x00,
0xff, 0x6a, 0xc8, 0x08,
- 0x20, 0x94, 0x44, 0x6e,
- 0x10, 0x94, 0x46, 0x6e,
- 0x08, 0x94, 0x60, 0x6e,
- 0x08, 0x94, 0x60, 0x6e,
- 0x08, 0x94, 0x60, 0x6e,
+ 0x20, 0x94, 0x50, 0x6e,
+ 0x10, 0x94, 0x52, 0x6e,
+ 0x08, 0x94, 0x6c, 0x6e,
+ 0x08, 0x94, 0x6c, 0x6e,
+ 0x08, 0x94, 0x6c, 0x6e,
0xff, 0x8c, 0xc8, 0x10,
0xc1, 0x64, 0xc8, 0x18,
0xf8, 0x64, 0xc8, 0x08,
0x01, 0x99, 0xda, 0x30,
- 0x00, 0x66, 0x54, 0x66,
- 0xc0, 0x66, 0x90, 0x76,
+ 0x00, 0x66, 0x60, 0x66,
+ 0xc0, 0x66, 0x9c, 0x76,
0x60, 0x66, 0xc8, 0x18,
0x3d, 0x64, 0xc8, 0x28,
- 0x00, 0x65, 0x44, 0x46,
+ 0x00, 0x65, 0x50, 0x46,
0xf7, 0x93, 0x26, 0x09,
- 0x08, 0x93, 0x62, 0x6e,
+ 0x08, 0x93, 0x6e, 0x6e,
0x00, 0x62, 0xc4, 0x18,
- 0x00, 0x65, 0x8e, 0x5e,
- 0x00, 0x65, 0x6e, 0x5e,
- 0x00, 0x65, 0x6e, 0x5e,
- 0x00, 0x65, 0x6e, 0x5e,
+ 0x00, 0x65, 0x9a, 0x5e,
+ 0x00, 0x65, 0x7a, 0x5e,
+ 0x00, 0x65, 0x7a, 0x5e,
+ 0x00, 0x65, 0x7a, 0x5e,
0x01, 0x99, 0xda, 0x30,
0x01, 0x99, 0xda, 0x30,
0x01, 0x99, 0xda, 0x30,
0x01, 0x6c, 0x32, 0x31,
0x01, 0x6c, 0x32, 0x31,
0x01, 0x6c, 0x32, 0x35,
- 0x08, 0x94, 0x8e, 0x7e,
+ 0x08, 0x94, 0x9a, 0x7e,
0xf7, 0x93, 0x26, 0x09,
- 0x08, 0x93, 0x92, 0x6e,
+ 0x08, 0x93, 0x9e, 0x6e,
0xff, 0x6a, 0xd4, 0x0c,
- 0x04, 0xb8, 0xba, 0x6e,
+ 0x04, 0xb8, 0xc6, 0x6e,
0x01, 0x42, 0x7e, 0x31,
0xff, 0x6a, 0x76, 0x01,
0x01, 0x90, 0x84, 0x34,
0x01, 0x85, 0x0a, 0x01,
0x7f, 0x65, 0x10, 0x09,
0xfe, 0x85, 0x0a, 0x0d,
- 0xff, 0x42, 0xb6, 0x66,
- 0xff, 0x41, 0xae, 0x66,
- 0xd1, 0x6a, 0xbe, 0x5e,
+ 0xff, 0x42, 0xc2, 0x66,
+ 0xff, 0x41, 0xba, 0x66,
+ 0xd1, 0x6a, 0xca, 0x5e,
0xff, 0x6a, 0xca, 0x04,
0x01, 0x41, 0x20, 0x31,
0x01, 0xbf, 0x82, 0x30,
0x01, 0x6a, 0x76, 0x00,
- 0x00, 0xbb, 0xf8, 0x45,
+ 0x00, 0xbb, 0x04, 0x46,
0x01, 0x42, 0x20, 0x31,
0x01, 0xbf, 0x84, 0x34,
0x01, 0x41, 0x7e, 0x31,
static int
ahc_patch12_func(struct ahc_softc *ahc)
{
- return ((ahc->features & AHC_ULTRA) != 0);
+ return ((ahc->features & AHC_HS_MAILBOX) != 0);
}
static int ahc_patch11_func(struct ahc_softc *ahc);
static int
ahc_patch11_func(struct ahc_softc *ahc)
{
- return ((ahc->features & AHC_HS_MAILBOX) != 0);
+ return ((ahc->features & AHC_ULTRA) != 0);
}
static int ahc_patch10_func(struct ahc_softc *ahc);
{ ahc_patch3_func, 27, 1, 2 },
{ ahc_patch0_func, 28, 1, 1 },
{ ahc_patch6_func, 34, 1, 1 },
- { ahc_patch7_func, 37, 62, 21 },
+ { ahc_patch7_func, 37, 54, 19 },
{ ahc_patch8_func, 37, 1, 1 },
{ ahc_patch9_func, 42, 3, 2 },
{ ahc_patch0_func, 45, 3, 1 },
{ ahc_patch0_func, 56, 1, 1 },
{ ahc_patch9_func, 60, 1, 2 },
{ ahc_patch0_func, 61, 1, 1 },
- { ahc_patch9_func, 70, 1, 2 },
- { ahc_patch0_func, 71, 1, 1 },
- { ahc_patch9_func, 74, 1, 2 },
- { ahc_patch0_func, 75, 1, 1 },
- { ahc_patch11_func, 85, 1, 2 },
- { ahc_patch0_func, 86, 1, 1 },
- { ahc_patch9_func, 94, 1, 2 },
- { ahc_patch0_func, 95, 1, 1 },
- { ahc_patch8_func, 99, 9, 4 },
- { ahc_patch1_func, 101, 1, 2 },
- { ahc_patch0_func, 102, 1, 1 },
- { ahc_patch2_func, 104, 2, 1 },
- { ahc_patch2_func, 113, 4, 1 },
- { ahc_patch1_func, 117, 1, 2 },
- { ahc_patch0_func, 118, 2, 3 },
- { ahc_patch2_func, 118, 1, 2 },
- { ahc_patch0_func, 119, 1, 1 },
- { ahc_patch7_func, 120, 4, 2 },
- { ahc_patch0_func, 124, 1, 1 },
- { ahc_patch12_func, 126, 2, 1 },
- { ahc_patch1_func, 128, 1, 2 },
- { ahc_patch0_func, 129, 1, 1 },
- { ahc_patch7_func, 130, 4, 1 },
- { ahc_patch7_func, 141, 80, 9 },
- { ahc_patch4_func, 159, 1, 1 },
- { ahc_patch1_func, 172, 1, 1 },
- { ahc_patch9_func, 180, 1, 2 },
- { ahc_patch0_func, 181, 1, 1 },
- { ahc_patch9_func, 190, 1, 2 },
- { ahc_patch0_func, 191, 1, 1 },
- { ahc_patch9_func, 207, 6, 2 },
- { ahc_patch0_func, 213, 6, 1 },
- { ahc_patch8_func, 221, 18, 2 },
- { ahc_patch1_func, 234, 1, 1 },
- { ahc_patch1_func, 241, 1, 2 },
- { ahc_patch0_func, 242, 2, 2 },
- { ahc_patch12_func, 243, 1, 1 },
- { ahc_patch9_func, 251, 31, 3 },
- { ahc_patch1_func, 267, 14, 2 },
- { ahc_patch13_func, 272, 1, 1 },
- { ahc_patch14_func, 282, 14, 1 },
- { ahc_patch1_func, 298, 1, 2 },
- { ahc_patch0_func, 299, 1, 1 },
- { ahc_patch9_func, 302, 1, 1 },
- { ahc_patch13_func, 307, 1, 1 },
- { ahc_patch9_func, 308, 2, 2 },
- { ahc_patch0_func, 310, 4, 1 },
- { ahc_patch14_func, 314, 1, 1 },
- { ahc_patch15_func, 317, 2, 3 },
- { ahc_patch9_func, 317, 1, 2 },
- { ahc_patch0_func, 318, 1, 1 },
- { ahc_patch6_func, 323, 1, 2 },
- { ahc_patch0_func, 324, 1, 1 },
- { ahc_patch1_func, 328, 50, 11 },
- { ahc_patch6_func, 337, 2, 4 },
- { ahc_patch7_func, 337, 1, 1 },
- { ahc_patch8_func, 338, 1, 1 },
- { ahc_patch0_func, 339, 1, 1 },
- { ahc_patch16_func, 340, 1, 1 },
- { ahc_patch6_func, 359, 6, 3 },
- { ahc_patch16_func, 359, 5, 1 },
- { ahc_patch0_func, 365, 5, 1 },
- { ahc_patch13_func, 373, 5, 1 },
- { ahc_patch0_func, 378, 54, 17 },
- { ahc_patch14_func, 378, 1, 1 },
- { ahc_patch7_func, 380, 2, 2 },
- { ahc_patch17_func, 381, 1, 1 },
- { ahc_patch9_func, 384, 1, 1 },
- { ahc_patch18_func, 391, 1, 1 },
- { ahc_patch14_func, 396, 9, 3 },
- { ahc_patch9_func, 397, 3, 2 },
- { ahc_patch0_func, 400, 3, 1 },
- { ahc_patch9_func, 408, 6, 2 },
- { ahc_patch0_func, 414, 9, 2 },
- { ahc_patch13_func, 414, 1, 1 },
- { ahc_patch13_func, 423, 2, 1 },
- { ahc_patch14_func, 425, 1, 1 },
- { ahc_patch9_func, 427, 1, 2 },
- { ahc_patch0_func, 428, 1, 1 },
- { ahc_patch7_func, 431, 1, 1 },
+ { ahc_patch9_func, 71, 1, 2 },
+ { ahc_patch0_func, 72, 1, 1 },
+ { ahc_patch9_func, 75, 1, 2 },
+ { ahc_patch0_func, 76, 1, 1 },
+ { ahc_patch9_func, 79, 1, 2 },
+ { ahc_patch0_func, 80, 1, 1 },
+ { ahc_patch8_func, 91, 9, 4 },
+ { ahc_patch1_func, 93, 1, 2 },
+ { ahc_patch0_func, 94, 1, 1 },
+ { ahc_patch2_func, 96, 2, 1 },
+ { ahc_patch2_func, 105, 4, 1 },
+ { ahc_patch1_func, 109, 1, 2 },
+ { ahc_patch0_func, 110, 2, 3 },
+ { ahc_patch2_func, 110, 1, 2 },
+ { ahc_patch0_func, 111, 1, 1 },
+ { ahc_patch7_func, 112, 4, 2 },
+ { ahc_patch0_func, 116, 1, 1 },
+ { ahc_patch11_func, 118, 2, 1 },
+ { ahc_patch1_func, 120, 1, 2 },
+ { ahc_patch0_func, 121, 1, 1 },
+ { ahc_patch7_func, 122, 4, 1 },
+ { ahc_patch7_func, 133, 89, 11 },
+ { ahc_patch4_func, 151, 1, 1 },
+ { ahc_patch1_func, 164, 1, 1 },
+ { ahc_patch12_func, 169, 1, 2 },
+ { ahc_patch0_func, 170, 1, 1 },
+ { ahc_patch9_func, 181, 1, 2 },
+ { ahc_patch0_func, 182, 1, 1 },
+ { ahc_patch9_func, 191, 1, 2 },
+ { ahc_patch0_func, 192, 1, 1 },
+ { ahc_patch9_func, 208, 6, 2 },
+ { ahc_patch0_func, 214, 6, 1 },
+ { ahc_patch8_func, 222, 18, 2 },
+ { ahc_patch1_func, 235, 1, 1 },
+ { ahc_patch1_func, 242, 1, 2 },
+ { ahc_patch0_func, 243, 2, 2 },
+ { ahc_patch11_func, 244, 1, 1 },
+ { ahc_patch9_func, 252, 31, 3 },
+ { ahc_patch1_func, 268, 14, 2 },
+ { ahc_patch13_func, 273, 1, 1 },
+ { ahc_patch14_func, 283, 14, 1 },
+ { ahc_patch1_func, 299, 1, 2 },
+ { ahc_patch0_func, 300, 1, 1 },
+ { ahc_patch9_func, 303, 1, 1 },
+ { ahc_patch13_func, 308, 1, 1 },
+ { ahc_patch9_func, 309, 2, 2 },
+ { ahc_patch0_func, 311, 4, 1 },
+ { ahc_patch14_func, 315, 1, 1 },
+ { ahc_patch15_func, 318, 2, 3 },
+ { ahc_patch9_func, 318, 1, 2 },
+ { ahc_patch0_func, 319, 1, 1 },
+ { ahc_patch6_func, 324, 1, 2 },
+ { ahc_patch0_func, 325, 1, 1 },
+ { ahc_patch1_func, 329, 50, 11 },
+ { ahc_patch6_func, 338, 2, 4 },
+ { ahc_patch7_func, 338, 1, 1 },
+ { ahc_patch8_func, 339, 1, 1 },
+ { ahc_patch0_func, 340, 1, 1 },
+ { ahc_patch16_func, 341, 1, 1 },
+ { ahc_patch6_func, 360, 6, 3 },
+ { ahc_patch16_func, 360, 5, 1 },
+ { ahc_patch0_func, 366, 5, 1 },
+ { ahc_patch13_func, 374, 5, 1 },
+ { ahc_patch0_func, 379, 54, 17 },
+ { ahc_patch14_func, 379, 1, 1 },
+ { ahc_patch7_func, 381, 2, 2 },
+ { ahc_patch17_func, 382, 1, 1 },
+ { ahc_patch9_func, 385, 1, 1 },
+ { ahc_patch18_func, 392, 1, 1 },
+ { ahc_patch14_func, 397, 9, 3 },
+ { ahc_patch9_func, 398, 3, 2 },
+ { ahc_patch0_func, 401, 3, 1 },
+ { ahc_patch9_func, 409, 6, 2 },
+ { ahc_patch0_func, 415, 9, 2 },
+ { ahc_patch13_func, 415, 1, 1 },
+ { ahc_patch13_func, 424, 2, 1 },
+ { ahc_patch14_func, 426, 1, 1 },
+ { ahc_patch9_func, 428, 1, 2 },
+ { ahc_patch0_func, 429, 1, 1 },
{ ahc_patch7_func, 432, 1, 1 },
- { ahc_patch8_func, 433, 3, 3 },
- { ahc_patch6_func, 434, 1, 2 },
- { ahc_patch0_func, 435, 1, 1 },
- { ahc_patch9_func, 436, 1, 1 },
- { ahc_patch15_func, 437, 1, 2 },
- { ahc_patch13_func, 437, 1, 1 },
- { ahc_patch14_func, 439, 9, 4 },
- { ahc_patch9_func, 439, 1, 1 },
- { ahc_patch9_func, 446, 2, 1 },
- { ahc_patch0_func, 448, 4, 3 },
- { ahc_patch9_func, 448, 1, 2 },
- { ahc_patch0_func, 449, 3, 1 },
- { ahc_patch1_func, 453, 2, 1 },
- { ahc_patch7_func, 455, 5, 2 },
- { ahc_patch0_func, 460, 1, 1 },
- { ahc_patch8_func, 461, 109, 23 },
- { ahc_patch1_func, 463, 3, 2 },
- { ahc_patch0_func, 466, 5, 3 },
- { ahc_patch9_func, 466, 2, 2 },
- { ahc_patch0_func, 468, 3, 1 },
- { ahc_patch1_func, 473, 2, 2 },
- { ahc_patch0_func, 475, 6, 3 },
- { ahc_patch9_func, 475, 2, 2 },
- { ahc_patch0_func, 477, 3, 1 },
- { ahc_patch1_func, 483, 2, 2 },
- { ahc_patch0_func, 485, 9, 7 },
- { ahc_patch9_func, 485, 5, 6 },
- { ahc_patch19_func, 485, 1, 2 },
- { ahc_patch0_func, 486, 1, 1 },
- { ahc_patch19_func, 488, 1, 2 },
- { ahc_patch0_func, 489, 1, 1 },
- { ahc_patch0_func, 490, 4, 1 },
- { ahc_patch6_func, 494, 3, 2 },
- { ahc_patch0_func, 497, 1, 1 },
- { ahc_patch1_func, 500, 1, 1 },
- { ahc_patch6_func, 506, 1, 2 },
- { ahc_patch0_func, 507, 1, 1 },
- { ahc_patch20_func, 544, 7, 1 },
- { ahc_patch3_func, 572, 1, 2 },
- { ahc_patch0_func, 573, 1, 1 },
- { ahc_patch21_func, 576, 1, 1 },
- { ahc_patch8_func, 578, 104, 33 },
- { ahc_patch4_func, 579, 1, 1 },
- { ahc_patch1_func, 585, 2, 2 },
- { ahc_patch0_func, 587, 1, 1 },
- { ahc_patch1_func, 590, 1, 2 },
- { ahc_patch0_func, 591, 1, 1 },
- { ahc_patch9_func, 592, 3, 3 },
- { ahc_patch15_func, 593, 1, 1 },
- { ahc_patch0_func, 595, 4, 1 },
- { ahc_patch19_func, 603, 2, 2 },
- { ahc_patch0_func, 605, 1, 1 },
- { ahc_patch19_func, 609, 10, 3 },
- { ahc_patch5_func, 611, 8, 1 },
- { ahc_patch0_func, 619, 9, 2 },
- { ahc_patch5_func, 620, 8, 1 },
- { ahc_patch4_func, 630, 1, 2 },
- { ahc_patch0_func, 631, 1, 1 },
- { ahc_patch19_func, 632, 1, 2 },
- { ahc_patch0_func, 633, 3, 2 },
- { ahc_patch4_func, 635, 1, 1 },
- { ahc_patch5_func, 636, 1, 1 },
- { ahc_patch5_func, 639, 1, 1 },
- { ahc_patch5_func, 641, 1, 1 },
- { ahc_patch4_func, 643, 2, 2 },
- { ahc_patch0_func, 645, 2, 1 },
+ { ahc_patch7_func, 433, 1, 1 },
+ { ahc_patch8_func, 434, 3, 3 },
+ { ahc_patch6_func, 435, 1, 2 },
+ { ahc_patch0_func, 436, 1, 1 },
+ { ahc_patch9_func, 437, 1, 1 },
+ { ahc_patch15_func, 438, 1, 2 },
+ { ahc_patch13_func, 438, 1, 1 },
+ { ahc_patch14_func, 440, 9, 4 },
+ { ahc_patch9_func, 440, 1, 1 },
+ { ahc_patch9_func, 447, 2, 1 },
+ { ahc_patch0_func, 449, 4, 3 },
+ { ahc_patch9_func, 449, 1, 2 },
+ { ahc_patch0_func, 450, 3, 1 },
+ { ahc_patch1_func, 454, 2, 1 },
+ { ahc_patch7_func, 456, 10, 2 },
+ { ahc_patch0_func, 466, 1, 1 },
+ { ahc_patch8_func, 467, 109, 23 },
+ { ahc_patch1_func, 469, 3, 2 },
+ { ahc_patch0_func, 472, 5, 3 },
+ { ahc_patch9_func, 472, 2, 2 },
+ { ahc_patch0_func, 474, 3, 1 },
+ { ahc_patch1_func, 479, 2, 2 },
+ { ahc_patch0_func, 481, 6, 3 },
+ { ahc_patch9_func, 481, 2, 2 },
+ { ahc_patch0_func, 483, 3, 1 },
+ { ahc_patch1_func, 489, 2, 2 },
+ { ahc_patch0_func, 491, 9, 7 },
+ { ahc_patch9_func, 491, 5, 6 },
+ { ahc_patch19_func, 491, 1, 2 },
+ { ahc_patch0_func, 492, 1, 1 },
+ { ahc_patch19_func, 494, 1, 2 },
+ { ahc_patch0_func, 495, 1, 1 },
+ { ahc_patch0_func, 496, 4, 1 },
+ { ahc_patch6_func, 500, 3, 2 },
+ { ahc_patch0_func, 503, 1, 1 },
+ { ahc_patch1_func, 506, 1, 1 },
+ { ahc_patch6_func, 512, 1, 2 },
+ { ahc_patch0_func, 513, 1, 1 },
+ { ahc_patch20_func, 550, 7, 1 },
+ { ahc_patch3_func, 578, 1, 2 },
+ { ahc_patch0_func, 579, 1, 1 },
+ { ahc_patch21_func, 582, 1, 1 },
+ { ahc_patch8_func, 584, 104, 33 },
+ { ahc_patch4_func, 585, 1, 1 },
+ { ahc_patch1_func, 591, 2, 2 },
+ { ahc_patch0_func, 593, 1, 1 },
+ { ahc_patch1_func, 596, 1, 2 },
+ { ahc_patch0_func, 597, 1, 1 },
+ { ahc_patch9_func, 598, 3, 3 },
+ { ahc_patch15_func, 599, 1, 1 },
+ { ahc_patch0_func, 601, 4, 1 },
+ { ahc_patch19_func, 609, 2, 2 },
+ { ahc_patch0_func, 611, 1, 1 },
+ { ahc_patch19_func, 615, 10, 3 },
+ { ahc_patch5_func, 617, 8, 1 },
+ { ahc_patch0_func, 625, 9, 2 },
+ { ahc_patch5_func, 626, 8, 1 },
+ { ahc_patch4_func, 636, 1, 2 },
+ { ahc_patch0_func, 637, 1, 1 },
+ { ahc_patch19_func, 638, 1, 2 },
+ { ahc_patch0_func, 639, 3, 2 },
+ { ahc_patch4_func, 641, 1, 1 },
+ { ahc_patch5_func, 642, 1, 1 },
+ { ahc_patch5_func, 645, 1, 1 },
{ ahc_patch5_func, 647, 1, 1 },
- { ahc_patch5_func, 650, 1, 1 },
+ { ahc_patch4_func, 649, 2, 2 },
+ { ahc_patch0_func, 651, 2, 1 },
{ ahc_patch5_func, 653, 1, 1 },
- { ahc_patch19_func, 657, 1, 1 },
- { ahc_patch19_func, 660, 1, 1 },
- { ahc_patch4_func, 666, 1, 1 },
- { ahc_patch6_func, 669, 1, 2 },
- { ahc_patch0_func, 670, 1, 1 },
- { ahc_patch7_func, 682, 16, 1 },
- { ahc_patch4_func, 698, 20, 1 },
- { ahc_patch9_func, 719, 4, 2 },
- { ahc_patch0_func, 723, 4, 1 },
- { ahc_patch9_func, 727, 4, 2 },
- { ahc_patch0_func, 731, 3, 1 },
- { ahc_patch6_func, 737, 1, 1 },
- { ahc_patch22_func, 739, 14, 1 },
- { ahc_patch7_func, 753, 3, 1 },
- { ahc_patch9_func, 765, 24, 8 },
- { ahc_patch19_func, 769, 1, 2 },
- { ahc_patch0_func, 770, 1, 1 },
- { ahc_patch15_func, 775, 4, 2 },
- { ahc_patch0_func, 779, 7, 3 },
- { ahc_patch23_func, 779, 5, 2 },
- { ahc_patch0_func, 784, 2, 1 },
- { ahc_patch0_func, 789, 42, 3 },
- { ahc_patch18_func, 801, 18, 2 },
- { ahc_patch0_func, 819, 1, 1 },
- { ahc_patch4_func, 843, 1, 1 },
- { ahc_patch4_func, 844, 3, 2 },
- { ahc_patch0_func, 847, 1, 1 },
- { ahc_patch13_func, 848, 3, 1 },
- { ahc_patch4_func, 851, 12, 1 }
+ { ahc_patch5_func, 656, 1, 1 },
+ { ahc_patch5_func, 659, 1, 1 },
+ { ahc_patch19_func, 663, 1, 1 },
+ { ahc_patch19_func, 666, 1, 1 },
+ { ahc_patch4_func, 672, 1, 1 },
+ { ahc_patch6_func, 675, 1, 2 },
+ { ahc_patch0_func, 676, 1, 1 },
+ { ahc_patch7_func, 688, 16, 1 },
+ { ahc_patch4_func, 704, 20, 1 },
+ { ahc_patch9_func, 725, 4, 2 },
+ { ahc_patch0_func, 729, 4, 1 },
+ { ahc_patch9_func, 733, 4, 2 },
+ { ahc_patch0_func, 737, 3, 1 },
+ { ahc_patch6_func, 743, 1, 1 },
+ { ahc_patch22_func, 745, 14, 1 },
+ { ahc_patch7_func, 759, 3, 1 },
+ { ahc_patch9_func, 771, 24, 8 },
+ { ahc_patch19_func, 775, 1, 2 },
+ { ahc_patch0_func, 776, 1, 1 },
+ { ahc_patch15_func, 781, 4, 2 },
+ { ahc_patch0_func, 785, 7, 3 },
+ { ahc_patch23_func, 785, 5, 2 },
+ { ahc_patch0_func, 790, 2, 1 },
+ { ahc_patch0_func, 795, 42, 3 },
+ { ahc_patch18_func, 807, 18, 2 },
+ { ahc_patch0_func, 825, 1, 1 },
+ { ahc_patch4_func, 849, 1, 1 },
+ { ahc_patch4_func, 850, 3, 2 },
+ { ahc_patch0_func, 853, 1, 1 },
+ { ahc_patch13_func, 854, 3, 1 },
+ { ahc_patch4_func, 857, 12, 1 }
};
struct cs {
u_int16_t begin;
} critical_sections[] = {
{ 11, 18 },
{ 21, 30 },
- { 698, 714 },
- { 844, 847 },
- { 851, 857 },
- { 859, 861 },
- { 861, 863 }
+ { 704, 720 },
+ { 850, 853 },
+ { 857, 863 },
+ { 865, 867 },
+ { 867, 869 }
};
const int num_critical_sections = sizeof(critical_sections)
/ sizeof(*critical_sections);
PROG= aicasm
+.SUFFIXES= .l .y .c
+
CSRCS= aicasm.c aicasm_symbol.c
GENSRCS= aicasm_gram.c aicasm_scan.c
-DEPHDRS= aicdb.h
GENHDRS= y.tab.h aicdb.h
SRCS= ${GENSRCS} ${CSRCS}
LFLAGS= -d
endif
-.SUFFIXES= .l .y .c
-
-$(PROG): $(SRCS) $(DEPHDRS)
+$(PROG): $(SRCS) $(GENHDRS)
$(AICASM_CC) $(AICASM_CFLAGS) $(SRCS) -o $(PROG)
aicdb.h:
clean:
rm -f $(CLEANFILES) $(PROG)
+
+y.tab.h aicasm_gram.c: aicasm_gram.y
+ $(YACC) $(YFLAGS) aicasm_gram.y
+ mv y.tab.c aicasm_gram.c
+
+aicasm_scan.c: y.tab.h
/*
* Aic7xxx SCSI host adapter firmware asssembler
*
- * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998, 2000, 2001 Justin T. Gibbs.
+ * Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
- * without modification, immediately at the beginning of the file.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm.c#8 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.c#11 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm.c,v 1.29 2000/10/05 04:25:42 gibbs Exp $
*/
#include <sysexits.h>
#include <unistd.h>
+#if linux
+#include <endian.h>
+#else
+#include <machine/endian.h>
+#endif
+
#include "aicasm.h"
#include "aicasm_symbol.h"
#include "aicasm_insformat.h"
* Assembler for the sequencer program downloaded to Aic7xxx SCSI host adapters
*
* Copyright (c) 1997 Justin T. Gibbs.
+ * Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm.h#5 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.h#7 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm.h,v 1.11 2000/09/22 22:19:54 gibbs Exp $
*/
* Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
*
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
+ * Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm_gram.y#7 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_gram.y#9 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_gram.y,v 1.12 2000/10/31 18:44:32 gibbs Exp $
*/
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm_insformat.h#4 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#7 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_insformat.h,v 1.3 2000/09/22 22:19:54 gibbs Exp $
*/
-#if linux
-#include <endian.h>
-#else
-#include <machine/endian.h>
-#endif
-
struct ins_format1 {
#if BYTE_ORDER == LITTLE_ENDIAN
uint32_t immediate : 8,
/*
* Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
*
- * Copyright (c) 1997, 1998 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
+ * Copyright (c) 2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm_scan.l#5 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_scan.l#7 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_scan.l,v 1.13 2000/09/22 22:19:54 gibbs Exp $
*/
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm_symbol.c#7 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.c#9 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_symbol.c,v 1.11 2000/09/22 22:19:54 gibbs Exp $
*/
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
- * 2. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * substantially similar to the "NO WARRANTY" disclaimer below
+ * ("Disclaimer") and any redistribution must be conditioned upon
+ * including a substantially similar Disclaimer requirement for further
+ * binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: //depot/src/aic7xxx/aicasm/aicasm_symbol.h#4 $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.h#6 $
*
* $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_symbol.h,v 1.11 2000/09/22 22:19:55 gibbs Exp $
*/
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
- * GNU Public License ("GPL").
+ * GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: //depot/src/linux/drivers/scsi/aic7xxx/cam.h#10 $
+ * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/cam.h#11 $
*/
#ifndef _AIC7XXX_CAM_H
#include <asm/pgtable.h>
#include <asm/amigaints.h>
#include <asm/amigahw.h>
-#include <asm/io.h>
+
#include <asm/irq.h>
#include "scsi.h"
called = 1;
return num;
}
+
+static Scsi_Host_Template driver_template = AMIGA7XX_SCSI;
+#include "scsi_module.c"
static int dma_ports_p(struct NCR_ESP *esp);
static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
struct zorro_dev *z = NULL;
unsigned long address;
struct ESP_regs *eregs;
+ unsigned long board;
#if MKIV
#define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
#endif
if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
- unsigned long board = z->resource.start;
+ board = z->resource.start;
if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
sizeof(struct ESP_regs), "NCR53C9x")) {
/* Do some magic to figure out if the blizzard is
static int dma_ports_p(struct NCR_ESP *esp);
static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
called = 1;
return 1;
}
+
+static Scsi_Host_Template driver_template = BVME6000_SCSI;
+#include "scsi_module.c"
};
+/* The following are 16 byte commands in group 4 */
+static const char *group_4_commands[] = {
+/* 80-84 */ unknown, unknown, unknown, unknown, unknown,
+/* 85-89 */ "Memory Export In (16)", unknown, unknown, unknown,
+ "Memory Export Out (16)",
+/* 8a-8f */ unknown, unknown, unknown, unknown, unknown, unknown,
+/* 90-94 */ unknown, unknown, unknown, unknown, unknown,
+/* 95-99 */ unknown, unknown, unknown, unknown, unknown,
+/* 9a-9f */ unknown, unknown, unknown, unknown, unknown, unknown,
+};
+
+
/* The following are 12 byte commands in group 5 */
static const char *group_5_commands[] = {
/* a0-a5 */ unknown, unknown, unknown, unknown, unknown,
static const char **commands[] = {
group_0_commands, group_1_commands, group_2_commands,
- (const char **) RESERVED_GROUP, (const char **) RESERVED_GROUP,
+ (const char **) RESERVED_GROUP, group_4_commands,
group_5_commands, (const char **) VENDOR_GROUP,
(const char **) VENDOR_GROUP
};
SEST size 512 Exchanges (simultaneous I/Os) limited by module kmalloc()
max of 128k bytes contiguous.
+Ver 2.1.1 Oct 18, 2001
+ * reinitialize Cmnd->SCp.sent_command (used to identify commands as
+ passthrus) on calling scsi_done, since the scsi mid layer does not
+ use (or reinitialize) this field to prevent subsequent comands from
+ having it set incorrectly.
+
+Ver 2.1.0 Aug 27, 2001
+ * Revise driver to use new kernel 2.4.x PCI DMA API, instead of
+ virt_to_bus(). (enables driver to work w/ ia64 systems with >2Gb RAM.)
+ Rework main scatter-gather code to handle cases where SG element
+ lengths are larger than 0x7FFFF bytes and use as many scatter
+ gather pages as necessary. (Steve Cameron)
+ * Makefile changes to bring cpqfc into line w/ rest of SCSI drivers
+ (thanks to Keith Owens)
+
Ver 2.0.5 Aug 06, 2001
* Reject non-existent luns in the driver rather than letting the
hardware do it. (some HW behaves differently than others in this area.)
static void CpqTsGetSFQEntry(TACHYON * fcChip,
USHORT pi, ULONG * buffr, BOOLEAN UpdateChip);
+static void
+cpqfc_free_dma_consistent(CPQFCHBA *cpqfcHBAdata)
+{
+ // free up the primary EXCHANGES struct and Link Q
+ PTACHYON fcChip = &cpqfcHBAdata->fcChip;
+
+ if (fcChip->Exchanges != NULL)
+ pci_free_consistent(cpqfcHBAdata->PciDev, sizeof(FC_EXCHANGES),
+ fcChip->Exchanges, fcChip->exch_dma_handle);
+ fcChip->Exchanges = NULL;
+ if (cpqfcHBAdata->fcLQ != NULL)
+ pci_free_consistent(cpqfcHBAdata->PciDev, sizeof(FC_LINK_QUE),
+ cpqfcHBAdata->fcLQ, cpqfcHBAdata->fcLQ_dma_handle);
+ cpqfcHBAdata->fcLQ = NULL;
+}
// Note special requirements for Q alignment! (TL/TS UG pg. 190)
// We place critical index pointers at end of QUE elements to assist
int iStatus=0;
unsigned long ulAddr;
-
+ dma_addr_t ERQdma, IMQdma, SPQdma, SESTdma;
+ int i;
// NOTE! fcMemManager() will return system virtual addresses.
// System (kernel) virtual addresses, though non-paged, still
// Allocate primary EXCHANGES array...
+ fcChip->Exchanges = NULL;
+ cpqfcHBAdata->fcLQ = NULL;
printk("Allocating %u for %u Exchanges ",
(ULONG)sizeof(FC_EXCHANGES), TACH_MAX_XID);
- fcChip->Exchanges = kmalloc( sizeof( FC_EXCHANGES), GFP_KERNEL );
+ fcChip->Exchanges = pci_alloc_consistent(cpqfcHBAdata->PciDev,
+ sizeof(FC_EXCHANGES), &fcChip->exch_dma_handle);
printk("@ %p\n", fcChip->Exchanges);
if( fcChip->Exchanges == NULL ) // fatal error!!
{
- printk("kmalloc failure on Exchanges: fatal error\n");
+ printk("pci_alloc_consistent failure on Exchanges: fatal error\n");
return -1;
}
// zero out the entire EXCHANGE space
printk("Allocating %u for LinkQ ", (ULONG)sizeof(FC_LINK_QUE));
- cpqfcHBAdata->fcLQ = kmalloc( sizeof( FC_LINK_QUE), GFP_KERNEL );
+ cpqfcHBAdata->fcLQ = pci_alloc_consistent(cpqfcHBAdata->PciDev,
+ sizeof( FC_LINK_QUE), &cpqfcHBAdata->fcLQ_dma_handle);
printk("@ %p (%u elements)\n", cpqfcHBAdata->fcLQ, FC_LINKQ_DEPTH);
memset( cpqfcHBAdata->fcLQ, 0, sizeof( FC_LINK_QUE));
if( cpqfcHBAdata->fcLQ == NULL ) // fatal error!!
{
- printk("kmalloc failure on fc Link Que: fatal error\n");
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
+ printk("pci_alloc_consistent() failure on fc Link Que: fatal error\n");
return -1;
}
// zero out the entire EXCHANGE space
memset( cpqfcHBAdata->fcLQ, 0, sizeof( FC_LINK_QUE));
-
-
-
// Verify that basic Tach I/O registers are not NULL
-
if( !fcChip->Registers.ReMapMemBase )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("HBA base address NULL: fatal error\n");
return -1;
}
// Allocate Tach's Exchange Request Queue (each ERQ entry 32 bytes)
- fcChip->ERQ = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- sizeof( TachLiteERQ ), 32*(ERQ_LEN), 0L );
+ fcChip->ERQ = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ sizeof( TachLiteERQ ), 32*(ERQ_LEN), 0L, &ERQdma);
if( !fcChip->ERQ )
{
- printk("kmalloc/alignment failure on ERQ: fatal error\n");
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
+ printk("pci_alloc_consistent/alignment failure on ERQ: fatal error\n");
return -1;
}
fcChip->ERQ->length = ERQ_LEN-1;
- ulAddr = virt_to_bus( fcChip->ERQ);
+ ulAddr = (ULONG) ERQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! ERQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
// Allocate Tach's Inbound Message Queue (32 bytes per entry)
- fcChip->IMQ = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- sizeof( TachyonIMQ ), 32*(IMQ_LEN), 0L );
+ fcChip->IMQ = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ sizeof( TachyonIMQ ), 32*(IMQ_LEN), 0L, &IMQdma );
if( !fcChip->IMQ )
{
- printk("kmalloc/alignment failure on IMQ: fatal error\n");
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
+ printk("pci_alloc_consistent/alignment failure on IMQ: fatal error\n");
return -1;
}
fcChip->IMQ->length = IMQ_LEN-1;
- ulAddr = virt_to_bus( fcChip->IMQ);
+ ulAddr = IMQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! IMQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
// Allocate Tach's Single Frame Queue (64 bytes per entry)
- fcChip->SFQ = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- sizeof( TachLiteSFQ ), 64*(SFQ_LEN),0L );
+ fcChip->SFQ = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ sizeof( TachLiteSFQ ), 64*(SFQ_LEN),0L, &SPQdma );
if( !fcChip->SFQ )
{
- printk("kmalloc/alignment failure on SFQ: fatal error\n");
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
+ printk("pci_alloc_consistent/alignment failure on SFQ: fatal error\n");
return -1;
}
fcChip->SFQ->length = SFQ_LEN-1; // i.e. Que length [# entries -
// min. 32; max. 4096 (0xffff)]
- ulAddr = virt_to_bus( fcChip->SFQ);
+ ulAddr = SPQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! SFQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
// be on physical page (e.g. 4k) boundary.
printk("Allocating %u for TachSEST for %u Exchanges\n",
(ULONG)sizeof(TachSEST), TACH_SEST_LEN);
- fcChip->SEST = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- sizeof(TachSEST), 4, 0L );
+ fcChip->SEST = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ sizeof(TachSEST), 4, 0L, &SESTdma );
// sizeof(TachSEST), 64*TACH_SEST_LEN, 0L );
if( !fcChip->SEST )
{
- printk("kmalloc/alignment failure on SEST: fatal error\n");
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
+ printk("pci_alloc_consistent/alignment failure on SEST: fatal error\n");
return -1;
}
+ for( i=0; i < TACH_SEST_LEN; i++) // for each exchange
+ fcChip->SEST->sgPages[i] = NULL;
+
fcChip->SEST->length = TACH_SEST_LEN; // e.g. DON'T subtract one
// (TL/TS UG, pg 153)
- ulAddr = virt_to_bus( fcChip->SEST);
+ ulAddr = SESTdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! SFQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
// NOTE! write consumer index last, since the write
// causes Tachyon to process the other registers
- ulAddr = virt_to_bus( &fcChip->ERQ->consumerIndex);
+ ulAddr = ((unsigned long)&fcChip->ERQ->consumerIndex -
+ (unsigned long)fcChip->ERQ) + (unsigned long) ERQdma;
// NOTE! Tachyon DMAs to the ERQ consumer Index host
// address; must be correctly aligned
// NOTE: TachLite DMAs to the producerIndex host address
// must be correctly aligned with address bits 1-0 cleared
// Writing the BASE register clears the PI register, so write it last
- ulAddr = virt_to_bus( &fcChip->IMQ->producerIndex);
+ ulAddr = ((unsigned long)&fcChip->IMQ->producerIndex -
+ (unsigned long)fcChip->IMQ) + (unsigned long) IMQdma;
+
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! IMQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
#endif
Exchanges->fcExchange[i].status |= INITIATOR_ABORT;
- cpqfcTSCompleteExchange( fcChip, i); // abort on LDn
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, i); // abort on LDn
}
}
if( RPCset ) // SEST transaction Response frame rec'd
{
// complete the command in our driver...
- cpqfcTSCompleteExchange( fcChip, x_ID);
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev,fcChip, x_ID);
} // end "RPCset"
case 3: // allocate mem, set Tachyon Que registers
iStatus = CpqTsCreateTachLiteQues( cpqfcHBAdata, opcode2);
+ if( iStatus )
+ break;
+
// now that the Queues exist, Tach can DMA to them, so
// we can begin processing INTs
// INTEN register - enable INT (TachLite interrupt)
writeb( 0x1F, fcChip->Registers.ReMapMemBase + IINTEN);
-
- if( iStatus )
- break;
-
-
+ // Fall through
case 4: // Config Fame Manager, Init Loop Command, laser on
// L_PORT or loopback
{
CPQFCHBA *cpqfcHBAdata = (CPQFCHBA*)pHBA;
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
- USHORT i, j, iStatus=0;
+ USHORT i, iStatus=0;
void* vPtr; // mem Align manager sets this to the freed address on success
unsigned long ulPtr; // for 64-bit pointer cast (e.g. Alpa machine)
+ FC_EXCHANGES *Exchanges = fcChip->Exchanges;
+ PSGPAGES j, next;
ENTER("DestroyTachLiteQues");
{
// search out and free Pool for Extended S/G list pages
- for( i=0, j=0; i < TACH_SEST_LEN; i++, j=0) // for each exchange
+ for( i=0; i < TACH_SEST_LEN; i++) // for each exchange
{
- // It's possible that extended S/G pages were allocated and
+ // It's possible that extended S/G pages were allocated, mapped, and
// not cleared due to error conditions or O/S driver termination.
// Make sure they're all gone.
- while( fcChip->SEST->sgPages[i].PoolPage[j] &&
- (j < TL_MAX_SGPAGES))
- kfree( fcChip->SEST->sgPages[i].PoolPage[j++]);
+ if (Exchanges->fcExchange[i].Cmnd != NULL)
+ cpqfc_pci_unmap(cpqfcHBAdata->PciDev, Exchanges->fcExchange[i].Cmnd,
+ fcChip, i); // undo DMA mappings.
+ for (j=fcChip->SEST->sgPages[i] ; j != NULL ; j = next) {
+ next = j->next;
+ kfree(j);
+ }
+ fcChip->SEST->sgPages[i] = NULL;
}
ulPtr = (unsigned long)fcChip->SEST;
- vPtr = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- 0,0, (ULONG)ulPtr ); // 'free' mem
+ vPtr = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ 0,0, (ULONG)ulPtr, NULL ); // 'free' mem
fcChip->SEST = 0L; // null invalid ptr
if( !vPtr )
{
{
ulPtr = (unsigned long)fcChip->SFQ;
- vPtr = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- 0,0, (ULONG)ulPtr ); // 'free' mem
+ vPtr = fcMemManager( cpqfcHBAdata->PciDev,
+ &cpqfcHBAdata->dynamic_mem[0],
+ 0,0, (ULONG)ulPtr, NULL ); // 'free' mem
fcChip->SFQ = 0L; // null invalid ptr
if( !vPtr )
{
fcChip->IMQ->consumerIndex = 0;
ulPtr = (unsigned long)fcChip->IMQ;
- vPtr = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- 0,0, (ULONG)ulPtr ); // 'free' mem
+ vPtr = fcMemManager( cpqfcHBAdata->PciDev, &cpqfcHBAdata->dynamic_mem[0],
+ 0,0, (ULONG)ulPtr, NULL ); // 'free' mem
fcChip->IMQ = 0L; // null invalid ptr
if( !vPtr )
{
if( fcChip->ERQ ) // release memory blocks used by the queues
{
ulPtr = (unsigned long)fcChip->ERQ;
- vPtr = fcMemManager( &cpqfcHBAdata->dynamic_mem[0],
- 0,0, (ULONG)ulPtr ); // 'free' mem
+ vPtr = fcMemManager( cpqfcHBAdata->PciDev, &cpqfcHBAdata->dynamic_mem[0],
+ 0,0, (ULONG)ulPtr, NULL ); // 'free' mem
fcChip->ERQ = 0L; // null invalid ptr
if( !vPtr )
{
}
}
- // free up the primary EXCHANGES struct
- if( fcChip->Exchanges != NULL)
- {
-// printk("kfree() on Exchanges @%p\n", fcChip->Exchanges);
- kfree( fcChip->Exchanges);
- }
-
- // free up Link Q
- if( cpqfcHBAdata->fcLQ != NULL )
- {
-// printk("kfree() on LinkQ @%p\n", fcChip->fcLQ);
- kfree( cpqfcHBAdata->fcLQ);
- }
+ // free up the primary EXCHANGES struct and Link Q
+ cpqfc_free_dma_consistent(cpqfcHBAdata);
LEAVE("DestroyTachLiteQues");
/* Embedded module documentation macros - see module.h */
MODULE_AUTHOR("Compaq Computer Corporation");
-MODULE_DESCRIPTION("Driver for Compaq 64-bit/66Mhz PCI Fibre Channel HBA");
+MODULE_DESCRIPTION("Driver for Compaq 64-bit/66Mhz PCI Fibre Channel HBA v. 2.1.1");
MODULE_LICENSE("GPL");
int cpqfcTS_TargetDeviceReset( Scsi_Device *ScsiDev, unsigned int reset_flags);
while( (PciDev =
pci_find_device( PCIids[i].vendor_id, PCIids[i].device_id, PciDev) ))
{
+
+ if (pci_set_dma_mask(PciDev, CPQFCTS_DMA_MASK) != 0) {
+ printk(KERN_WARNING
+ "cpqfc: HBA cannot support required DMA mask, skipping.\n");
+ continue;
+ }
+
// NOTE: (kernel 2.2.12-32) limits allocation to 128k bytes...
printk(" scsi_register allocating %d bytes for FC HBA\n",
(ULONG)sizeof(CPQFCHBA));
// now initialize our hardware...
-
- cpqfcHBAdata->fcChip.InitializeTachyon( cpqfcHBAdata, 1,1);
+ if (cpqfcHBAdata->fcChip.InitializeTachyon( cpqfcHBAdata, 1,1)) {
+ printk(KERN_WARNING "cpqfc: initialization of HBA hardware failed.\n");
+ // FIXME: might want to do something better than nothing here.
+ }
cpqfcHBAdata->fcStatsTime = jiffies; // (for FC Statistics delta)
- case SCSI_IOCTL_FC_TARGET_ADDRESS:
+ case CPQFC_IOCTL_FC_TARGET_ADDRESS:
result =
verify_area(VERIFY_WRITE, arg, sizeof(Scsi_FCTargAddress));
if (result)
break;
- case SCSI_IOCTL_FC_TDR:
+ case CPQFC_IOCTL_FC_TDR:
result = cpqfcTS_TargetDeviceReset( ScsiDev, 0);
cpqfcTSDecodeGBICtype( &cpqfcHBA->fcChip, &buf[0]);
cpqfcTSGetLPSM( &cpqfcHBA->fcChip, &buf[ strlen(buf)]);
copy_info(&info, "%s\n", buf);
-
#define DISPLAY_WWN_INFO
#ifdef DISPLAY_WWN_INFO
}
}
#endif
+
+
+
// Unfortunately, the proc_info buffer isn't big enough
// The file "hosts.h" says not to call scsi_done from
// inside _queuecommand, so we'll do it from the heartbeat timer
+// (clarification: Turns out it's ok to call scsi_done from queuecommand
+// for cases that don't go to the hardware like scsi cmds destined
+// for LUNs we know don't exist, so this code might be simplified...)
static void QueBadTargetCmnd( CPQFCHBA *cpqfcHBAdata, Scsi_Cmnd *Cmnd)
{
printk(" cpqfcTS adapter PCI master address crossed 45-bit boundary\n");
if( IntPending & 0x2 )
printk(" cpqfcTS adapter DMA error detected\n");
- if( IntPending & 0x1 )
+ if( IntPending & 0x1 ) {
+ UCHAR IntStat;
printk(" cpqfcTS adapter PCI error detected\n");
+ IntStat = readb( cpqfcHBA->fcChip.Registers.INTSTAT.address);
+ if (IntStat & 0x4) printk("(INT)\n");
+ if (IntStat & 0x8)
+ printk("CRS: PCI master address crossed 46 bit bouandary\n");
+ if (IntStat & 0x10) printk("MRE: external memory parity error.\n");
+ }
}
}
spin_unlock_irqrestore( &io_request_lock, flags);
// we need about 8 allocations per HBA. Figuring at most 10 HBAs per server
// size the dynamic_mem array at 80.
-void* fcMemManager( ALIGNED_MEM *dynamic_mem, ULONG n_alloc, ULONG ab,
- ULONG u32_AlignedAddress)
+void* fcMemManager( struct pci_dev *pdev, ALIGNED_MEM *dynamic_mem,
+ ULONG n_alloc, ULONG ab, ULONG u32_AlignedAddress,
+ dma_addr_t *dma_handle)
{
USHORT allocBoundary=1; // compiler specific - worst case 1
// best case - replace malloc() call
if( dynamic_mem[i].AlignedAddress == u32_AlignedAddress )
{
alloc_address = dynamic_mem[i].BaseAllocated; // 'success' status
- kfree( dynamic_mem[i].BaseAllocated); // return pages to kernel
+ pci_free_consistent(pdev,dynamic_mem[i].size,
+ alloc_address,
+ dynamic_mem[i].dma_handle);
dynamic_mem[i].BaseAllocated = 0; // clear for next use
dynamic_mem[i].AlignedAddress = 0;
+ dynamic_mem[i].size = 0;
break; // quit for loop; done
}
}
}
else if( n_alloc ) // want new memory?
{
+ dma_addr_t handle;
t_alloc = n_alloc + (ab - allocBoundary); // pad bytes for alignment
-// printk("kmalloc() for Tach alignment: %ld bytes\n", t_alloc);
+// printk("pci_alloc_consistent() for Tach alignment: %ld bytes\n", t_alloc);
+// (would like to) allow thread block to free pages
alloc_address = // total bytes (NumberOfBytes)
- kmalloc( t_alloc, GFP_KERNEL); // allow thread block to free pages
-
+ pci_alloc_consistent(pdev, t_alloc, &handle);
// now mask off least sig. bits of address
if( alloc_address ) // (only if non-NULL)
{
// find place to store ptr, so we
// can free it later...
+
+ mask = (LONG)(ab - 1); // mask all low-order bits
+ mask = ~mask; // invert bits
for( i=0; i<DYNAMIC_ALLOCATIONS; i++) // look for free slot
{
if( dynamic_mem[i].BaseAllocated == 0) // take 1st available
{
dynamic_mem[i].BaseAllocated = alloc_address;// address from O/S
+ dynamic_mem[i].dma_handle = handle;
+ if (dma_handle != NULL)
+ {
+// printk("handle = %p, ab=%d, boundary = %d, mask=0x%08x\n",
+// handle, ab, allocBoundary, mask);
+ *dma_handle = (dma_addr_t)
+ ((((ULONG)handle) + (ab - allocBoundary)) & mask);
+ }
+ dynamic_mem[i].size = t_alloc;
break;
}
}
- mask = (LONG)(ab - 1); // mask all low-order bits
- mask = ~mask; // invert bits
-
ulAddress = (unsigned long)alloc_address;
ulAddress += (ab - allocBoundary); // add the alignment bytes-
char rw_flag; /* Read CDB or Write CDB */
} cpqfc_passthru_t;
-
-
-
/*
** Defines for the IOCTLS.
*/
#define CPQFCTS_SCSI_PASSTHRU _IOWR( CCPQFCTS_IOC_MAGIC,11, VENDOR_IOCTL_REQ)
+/* We would rather have equivalent generic, low-level driver agnostic
+ioctls that do what CPQFC_IOCTL_FC_TARGET_ADDRESS and
+CPQFC_IOCTL_FC_TDR 0x5388 do, but currently, we do not have them,
+consequently applications would have to know they are talking to cpqfc. */
+
+/* Used to get Fibre Channel WWN and port_id from device */
+// #define CPQFC_IOCTL_FC_TARGET_ADDRESS 0x5387
+#define CPQFC_IOCTL_FC_TARGET_ADDRESS \
+ _IOR( CCPQFCTS_IOC_MAGIC, 13, Scsi_FCTargAddress)
+
+/* Used to invoke Target Defice Reset for Fibre Channel */
+// #define CPQFC_IOCTL_FC_TDR 0x5388
+#define CPQFC_IOCTL_FC_TDR _IO( CCPQFCTS_IOC_MAGIC, 15)
#define DbgDelay(secs) { int wait_time; printk( " DbgDelay %ds ", secs); \
for( wait_time=jiffies + (secs*HZ); \
wait_time > jiffies ;) ; }
+
#define CPQFCTS_DRIVER_VER(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
+// don't forget to also change MODULE_DESCRIPTION in cpqfcTSinit.c
#define VER_MAJOR 2
-#define VER_MINOR 0
-#define VER_SUBMINOR 5
+#define VER_MINOR 1
+#define VER_SUBMINOR 1
// Macros for kernel (esp. SMP) tracing using a PCI analyzer
// (e.g. x86).
// struct is sized for largest expected cmnd (LOGIN)
} TachLiteERQ;
+// for now, just 32 bit DMA, eventually 40something, with code changes
+#define CPQFCTS_DMA_MASK ((unsigned long) (0x00000000FFFFFFFF))
+
+#define TL_MAX_SG_ELEM_LEN 0x7ffff // Max buffer length a single S/G entry
+ // may represent (a hardware limitation). The
+ // only reason to ever change this is if you
+ // want to exercise very-hard-to-reach code in
+ // cpqfcTSworker.c:build_SEST_sglist().
+
+#define TL_DANGER_SGPAGES 7 // arbitrary high water mark for # of S/G pages
+ // we must exceed to elicit a warning indicative
+ // of EXTREMELY large data transfers or
+ // EXTREME memory fragmentation.
+ // (means we just used up 2048 S/G elements,
+ // Never seen this is real life, only in
+ // testing with tricked up driver.)
-#define TL_MAX_SGPAGES 4 // arbitrary limit to # of TL Ext. S/G pages
- // stores array of allocated page blocks used
- // in extended S/G lists. Affects amount of static
- // memory consumed by driver.
#define TL_EXT_SG_PAGE_COUNT 256 // Number of Extended Scatter/Gather a/l PAIRS
// Tachyon register (IOBaseU 0x68)
// power-of-2 value ONLY! 4 min, 256 max
ULONG RSP_Len;
ULONG RSP_Addr;
ULONG Buff_Off;
+#define USES_EXTENDED_SGLIST(this_sest, x_ID) \
+ (!((this_sest)->u[ x_ID ].IWE.Buff_Off & 0x80000000))
ULONG Link;
ULONG RX_ID;
ULONG Data_Len;
ULONG GAddr3;
} TachLiteTRE;
-typedef struct
+typedef struct ext_sg_page_ptr_t *PSGPAGES;
+typedef struct ext_sg_page_ptr_t
{
- void *PoolPage[TL_MAX_SGPAGES];
-} SGPAGES, *PSGPAGES; // linked list of S/G pairs, by Exchange
-
-
+ unsigned char page[TL_EXT_SG_PAGE_BYTELEN * 2]; // 2x for alignment
+ dma_addr_t busaddr; // need the bus addresses and
+ unsigned int maplen; // lengths for later pci unmapping.
+ PSGPAGES next;
+} SGPAGES; // linked list of S/G pairs, by Exchange
typedef struct // SCSI Exchange State Table
{
TachFCHDR DataHDR[TACH_SEST_LEN]; // for SEST FCP_DATA frame hdr (no pl)
TachFCHDR_RSP RspHDR[TACH_SEST_LEN]; // space for SEST FCP_RSP frame
- SGPAGES sgPages[TACH_SEST_LEN]; // array of Pool-allocations
+ PSGPAGES sgPages[TACH_SEST_LEN]; // head of linked list of Pool-allocations
ULONG length; // Length register
ULONG base; // copy of base ptr for debug
} TachSEST;
{
void *BaseAllocated; // address as allocated from O/S;
unsigned long AlignedAddress; // aligned address (used by Tachyon DMA)
+ dma_addr_t dma_handle;
+ size_t size;
} ALIGNED_MEM;
TachLiteSFQ *SFQ; // Single Frame Queue
TachSEST *SEST; // SCSI Exchange State Table
+ dma_addr_t exch_dma_handle;
+
// these function pointers are for "generic" functions, which are
// replaced with Host Bus Adapter types at
// runtime.
// define misc functions
int cpqfcTSGetLPSM( PTACHYON fcChip, char cErrorString[]);
int cpqfcTSDecodeGBICtype( PTACHYON fcChip, char cErrorString[]);
-void* fcMemManager( ALIGNED_MEM *dyn_mem_pair, ULONG n_alloc, ULONG ab,
- ULONG ulAlignedAddress);
+void* fcMemManager( struct pci_dev *pdev,
+ ALIGNED_MEM *dyn_mem_pair, ULONG n_alloc, ULONG ab,
+ ULONG ulAlignedAddress, dma_addr_t *dma_handle);
void BigEndianSwap( UCHAR *source, UCHAR *dest, USHORT cnt);
ALIGNED_MEM dynamic_mem[DYNAMIC_ALLOCATIONS];
struct pci_dev *PciDev;
+ dma_addr_t fcLQ_dma_handle;
Scsi_Cmnd *LinkDnCmnd[CPQFCTS_REQ_QUEUE_LEN]; // collects Cmnds during LDn
// (for Acceptable targets)
LONG ExchangeID );
void cpqfcTSCompleteExchange(
+ struct pci_dev *pcidev,
PTACHYON fcChip,
ULONG exchange_ID);
void fcSestReset(
CPQFCHBA *);
-
-
-
+void cpqfc_pci_unmap(struct pci_dev *pcidev,
+ Scsi_Cmnd *cmd,
+ PTACHYON fcChip,
+ ULONG x_ID);
extern const UCHAR valid_al_pa[];
extern const int number_of_al_pa;
ULONG s_id;
} ADISC_PAYLOAD;
+struct ext_sg_entry_t {
+ __u32 len:18; /* buffer length, bits 0-17 */
+ __u32 uba:13; /* upper bus address bits 18-31 */
+ __u32 lba; /* lower bus address bits 0-31 */
+};
+
// J. McCarty's LINK.H
//
// LS_RJT Reason Codes
{
// printk(" *Terminating x_ID %Xh on %Xh* ",
// x_ID, Exchanges->fcExchange[x_ID].status);
- cpqfcTSCompleteExchange( fcChip, x_ID);
-
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, x_ID);
}
} // end of ABTS case
Done:
// Regardless of whether the Reply is valid or not, the
// the exchange is done - complete
- cpqfcTSCompleteExchange( fcChip, (fchs->ox_rx_id >>16)); // complete
+ cpqfcTSCompleteExchange(cpqfcHBAdata->PciDev, fcChip, (fchs->ox_rx_id >>16));
Quit:
return;
// Regardless of whether the Reply is valid or not, the
// the exchange is done - complete
- cpqfcTSCompleteExchange( fcChip, (fchs->ox_rx_id >>16)); // complete
+ cpqfcTSCompleteExchange(cpqfcHBAdata->PciDev, fcChip, (fchs->ox_rx_id >>16));
Quit:
return;
!(fcChip->SEST->u[ ExchangeID].IWE.Hdr_Len
& 0x80000000))
{
- cpqfcTSCompleteExchange( fcChip, ExchangeID);
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID);
}
else
{
((Exchanges->fcExchange[ ExchangeID].fchs.d_id & 0xFFFFFF) ==
(fchs->s_id & 0xFFFFFF)) )
{
- cpqfcTSCompleteExchange( fcChip, ExchangeID );
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID );
}
}
}
// already completed the exchange...
// printk("complete x_ID %Xh on ABTS RJT\n", ExchangeID);
- cpqfcTSCompleteExchange( fcChip, ExchangeID );
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID );
}
}
} // end of ABTS check
printk("completing x_ID %X on status %Xh\n",
ExchangeID, Exchanges->fcExchange[ExchangeID].status);
#endif
- cpqfcTSCompleteExchange( fcChip, ExchangeID);
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID);
}
}
else // Xchange setup failed...
Done:
}
+static void
+call_scsi_done(Scsi_Cmnd *Cmnd)
+{
+ // We have to reinitialize sent_command here, so the scsi-mid
+ // layer won't re-use the scsi command leaving it set incorrectly.
+ // (incorrectly for our purposes...it's normally unused.)
+
+ if (Cmnd->SCp.sent_command != 0) { // was it a passthru?
+ Cmnd->SCp.sent_command = 0;
+ Cmnd->result &= 0xff00ffff;
+ Cmnd->result |= (DID_PASSTHROUGH << 16); // prevents retry
+ }
+ if (Cmnd->scsi_done != NULL)
+ (*Cmnd->scsi_done)(Cmnd);
+}
+
// After successfully getting a "Process Login" (PRLI) from an
// FC port, we want to Discover the LUNs so that we know the
// addressing type (e.g., FCP-SCSI Volume Set Address, Peripheral
Cmnd->result = (DID_SOFT_ERROR << 16); // ask for retry
// printk(" BoardLockCmnd[%d] %p Complete, chnl/target/lun %d/%d/%d\n",
// i,Cmnd, Cmnd->channel, Cmnd->target, Cmnd->lun);
- if( Cmnd->scsi_done != NULL)
- (*Cmnd->scsi_done)(Cmnd);
+ call_scsi_done(Cmnd);
}
}
}
// Complete the "bad target" commands (normally only used during
// initialization, since we aren't supposed to call "scsi_done"
- // inside the queuecommand() function).
+ // inside the queuecommand() function). (this is overly contorted,
+ // scsi_done can be safely called from queuecommand for
+ // this bad target case. May want to simplify this later)
for( i=0; i< CPQFCTS_MAX_TARGET_ID; i++)
{
Scsi_Cmnd *Cmnd = cpqfcHBAdata->BadTargetCmnd[i];
cpqfcHBAdata->BadTargetCmnd[i] = NULL;
Cmnd->result = (DID_BAD_TARGET << 16);
- if( Cmnd->scsi_done != NULL)
- (*Cmnd->scsi_done)(Cmnd);
+ call_scsi_done(Cmnd);
}
else
break;
if( i >= TACH_SEST_LEN ) // Link Service Exchange
{
- cpqfcTSCompleteExchange( fcChip, i); // Don't "abort" LinkService
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, i); // Don't "abort" LinkService
}
else // SEST Exchange TO -- may post ABTS to Worker Thread Que
(Cmnd->channel == pLoggedInPort->ScsiNexus.channel) )
{
Cmnd->result = (DID_SOFT_ERROR <<16); // force retry
- if( Cmnd->scsi_done != NULL)
- (*Cmnd->scsi_done)(Cmnd);
- else
+ if( Cmnd->scsi_done == NULL)
+ {
printk("LinkDnCmnd scsi_done ptr null, port_id %Xh\n",
pLoggedInPort->port_id);
+ Cmnd->SCp.sent_command = 0;
+ }
+ else
+ call_scsi_done(Cmnd);
*SCptr = NULL; // free this slot for next use
}
}
static LONG FindFreeExchange( PTACHYON fcChip, ULONG type );
static ULONG build_SEST_sgList(
+ struct pci_dev *pcidev,
ULONG *SESTalPairStart,
Scsi_Cmnd *Cmnd,
ULONG *sgPairs,
- PSGPAGES sgPages // link list of TL Ext. S/G pages from O/S Pool
+ PSGPAGES *sgPages_head // link list of TL Ext. S/G pages from O/S Pool
);
static int build_FCP_payload( Scsi_Cmnd *Cmnd,
// assign tmp ptr (shorthand)
CMDfchs = &Exchanges->fcExchange[ *fcExchangeIndex].fchs;
-
if( Cmnd != NULL ) // (necessary for ABTS cases)
{
Exchanges->fcExchange[ *fcExchangeIndex].Cmnd = Cmnd; // Linux Scsi
pIWE->Hdr_Len |= fl; // add xmit FC frame len for data phase
- pIWE->Hdr_Addr = virt_to_bus( dataHDR );
+ pIWE->Hdr_Addr = fcChip->SEST->base +
+ ((unsigned long)&fcChip->SEST->DataHDR[*fcExchangeIndex] -
+ (unsigned long)fcChip->SEST);
+
pIWE->RSP_Len = sizeof(TachFCHDR_RSP) ; // hdr+data (recv'd RSP frame)
pIWE->RSP_Len |= (InFCHS->s_id << 8); // MS 24 bits Remote_ID
memset( &fcChip->SEST->RspHDR[ *fcExchangeIndex].pl, 0,
sizeof( FCP_STATUS_RESPONSE) ); // clear out previous status
-
- pIWE->RSP_Addr = virt_to_bus(
- &fcChip->SEST->RspHDR[ *fcExchangeIndex ]);
+
+ pIWE->RSP_Addr = fcChip->SEST->base +
+ ((unsigned long)&fcChip->SEST->RspHDR[*fcExchangeIndex] -
+ (unsigned long)fcChip->SEST);
// Do we need local or extended gather list?
// depends on size - we can handle 3 len/addr pairs
// locally.
fcp_dl = build_SEST_sgList(
+ cpqfcHBAdata->PciDev,
&pIWE->GLen1,
Cmnd, // S/G list
&sgPairs, // return # of pairs in S/G list (from "Data" descriptor)
pIRE->RSP_Len = sizeof(TachFCHDR_RSP) ; // hdr+data (recv'd RSP frame)
pIRE->RSP_Len |= (InFCHS->s_id << 8); // MS 24 bits Remote_ID
-
- pIRE->RSP_Addr = virt_to_bus(
- &fcChip->SEST->RspHDR[ *fcExchangeIndex ]);
-
+ pIRE->RSP_Addr = fcChip->SEST->base +
+ ((unsigned long)&fcChip->SEST->RspHDR[*fcExchangeIndex] -
+ (unsigned long)fcChip->SEST);
// Do we need local or extended gather list?
// depends on size - we can handle 3 len/addr pairs
// locally.
fcp_dl = build_SEST_sgList(
+ cpqfcHBAdata->PciDev,
&pIRE->SLen1,
Cmnd, // SCSI command Data desc. with S/G list
&sgPairs, // return # of pairs in S/G list (from "Data" descriptor)
// locally.
fcp_dl = build_SEST_sgList(
+ cpqfcHBAdata->PciDev,
&pTWE->SLen1,
Cmnd, // S/G list
&sgPairs, // return # of pairs in S/G list (from "Data" descriptor)
// VALid entry:Dir outbound:enable CM:enal INT:
pTRE->Hdr_Len = 0x86010020L; // data frame Len always 32 bytes
- pTRE->Hdr_Addr = virt_to_bus( dataHDR );
+ pTRE->Hdr_Addr = // bus address of dataHDR;
+ fcChip->SEST->base +
+ ((unsigned long)&fcChip->SEST->DataHDR[ *fcExchangeIndex ] -
+ (unsigned long)fcChip->SEST);
+
pTRE->RSP_Len = 64L; // hdr+data (TL assisted RSP frame)
pTRE->RSP_Len |= (InFCHS->s_id << 8); // MS 24 bits Remote_ID
- pTRE->RSP_Addr = virt_to_bus( rspHDR );
-
+ pTRE->RSP_Addr = // bus address of rspHDR
+ fcChip->SEST->base +
+ ((unsigned long)&fcChip->SEST->RspHDR[ *fcExchangeIndex ] -
+ (unsigned long)fcChip->SEST);
// Do we need local or extended gather list?
// depends on size - we can handle 3 len/addr pairs
// locally.
fcp_dl = build_SEST_sgList(
+ cpqfcHBAdata->PciDev,
&pTRE->GLen1,
Cmnd, // S/G list
&sgPairs, // return # of pairs in S/G list (from "Data" descriptor)
// len & flags according to command type above
pIRB->Req_A_SFS_Len = SfsLen; // includes IRB flags & len
- pIRB->Req_A_SFS_Addr = virt_to_bus(CMDfchs); // TL needs physical addr
- // of frame to send
+ pIRB->Req_A_SFS_Addr = // TL needs physical addr of frame to send
+ fcChip->exch_dma_handle + (unsigned long)CMDfchs -
+ (unsigned long)Exchanges;
+
pIRB->Req_A_SFS_D_ID = CMDfchs->d_id << 8; // Dest_ID must be consistent!
// Exchange is complete except for "fix-up" fields to be set
printk( "FC Error: SEST build Pool Allocation failed\n");
#endif
// return resources...
- cpqfcTSCompleteExchange( fcChip, *fcExchangeIndex); // SEST build failed
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, *fcExchangeIndex); // SEST build failed
}
}
else // no Exchanges available
}
+static dma_addr_t
+cpqfc_pci_map_sg_page(
+ struct pci_dev *pcidev,
+ ULONG *hw_paddr, // where to put phys addr for HW use
+ void *sgp_vaddr, // the virtual address of the sg page
+ dma_addr_t *umap_paddr, // where to put phys addr for unmap
+ unsigned int *maplen, // where to store sg entry length
+ int PairCount) // number of sg pairs used in the page.
+{
+ unsigned long aligned_addr = (unsigned long) sgp_vaddr;
+
+ *maplen = PairCount * 8;
+ aligned_addr += TL_EXT_SG_PAGE_BYTELEN;
+ aligned_addr &= ~(TL_EXT_SG_PAGE_BYTELEN -1);
+
+ *umap_paddr = pci_map_single(pcidev, (void *) aligned_addr,
+ *maplen, PCI_DMA_TODEVICE);
+ *hw_paddr = (ULONG) *umap_paddr;
+
+# if BITS_PER_LONG > 32
+ if( *umap_paddr >>32 ) {
+ printk("cqpfcTS:Tach SG DMA addr %p>32 bits\n",
+ (void*)umap_paddr);
+ return 0;
+ }
+# endif
+ return *umap_paddr;
+}
+
+static void
+cpqfc_undo_SEST_mappings(struct pci_dev *pcidev,
+ unsigned long contigaddr, int len, int dir,
+ struct scatterlist *sgl, int use_sg,
+ PSGPAGES *sgPages_head,
+ int allocated_pages)
+{
+ PSGPAGES i, next;
+
+ if (contigaddr != (unsigned long) NULL)
+ pci_unmap_single(pcidev, contigaddr, len, dir);
+
+ if (sgl != NULL)
+ pci_unmap_sg(pcidev, sgl, use_sg, dir);
+ for (i=*sgPages_head; i != NULL ;i = next)
+ {
+ pci_unmap_single(pcidev, i->busaddr, i->maplen,
+ scsi_to_pci_dma_dir(PCI_DMA_TODEVICE));
+ i->busaddr = (dma_addr_t) NULL;
+ i->maplen = 0L;
+ next = i->next;
+ kfree(i);
+ }
+ *sgPages_head = NULL;
+}
// This routine builds scatter/gather lists into SEST entries
// INPUTS:
//#define DBG_SEST_SGLIST 1 // for printing out S/G pairs with Ext. pages
+static int ap_hi_water = TL_DANGER_SGPAGES;
+
static ULONG build_SEST_sgList(
+ struct pci_dev *pcidev,
ULONG *SESTalPairStart, // the 3 len/address buffers in SEST
Scsi_Cmnd *Cmnd,
ULONG *sgPairs,
- PSGPAGES sgPages) // link list of TL Ext. S/G pages from O/S Pool
+ PSGPAGES *sgPages_head) // link list of TL Ext. S/G pages from O/S Pool
{
ULONG i, AllocatedPages=0; // Tach Ext. S/G page allocations
ULONG* alPair = SESTalPairStart;
- ULONG alignedPageAddress; // TL hardware alignment requirement
+ ULONG* ext_sg_page_phys_addr_place = NULL;
int PairCount;
- unsigned long ulBuff;
+ unsigned long ulBuff, contigaddr;
ULONG total_data_len=0; // (in bytes)
ULONG bytes_to_go = Cmnd->request_bufflen; // total xfer (S/G sum)
ULONG thisMappingLen;
- struct scatterlist *sgl; // S/G list (Linux format)
-
+ struct scatterlist *sgl = NULL; // S/G list (Linux format)
+ int sg_count, totalsgs;
+ dma_addr_t busaddr;
+ unsigned long thislen, offset;
+ PSGPAGES *sgpage = sgPages_head;
+ PSGPAGES prev_page = NULL;
+# define WE_HAVE_SG_LIST (sgl != (unsigned long) NULL)
+ contigaddr = (unsigned long) NULL;
if( !Cmnd->use_sg ) // no S/G list?
{
- *sgPairs = 1; // use "local" S/G pair in SEST entry
- // (for now, ignore address bits above #31)
- *alPair++ = bytes_to_go & 0x7ffff; // bits 18-0, length
- ulBuff = virt_to_bus( Cmnd->request_buffer);
-#if BITS_PER_LONG > 32
- if( ulBuff >>32 )
- {
- printk("FATAL! Tachyon DMA address %p exceeds 32 bits\n", (void*)ulBuff );
- return 0;
- }
-#endif
- *alPair = (ULONG)ulBuff;
- return bytes_to_go;
+ if (bytes_to_go <= TL_MAX_SG_ELEM_LEN)
+ {
+ *sgPairs = 1; // use "local" S/G pair in SEST entry
+ // (for now, ignore address bits above #31)
+
+ *alPair++ = bytes_to_go; // bits 18-0, length
+
+ if (bytes_to_go != 0) {
+ contigaddr = ulBuff = pci_map_single(pcidev,
+ Cmnd->request_buffer,
+ Cmnd->request_bufflen,
+ scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
+ // printk("ms %p ", ulBuff);
+ }
+ else {
+ // No data transfer, (e.g.: Test Unit Ready)
+ // printk("btg=0 ");
+ *sgPairs = 0;
+ memset(alPair, 0, sizeof(*alPair));
+ return 0;
+ }
+
+# if BITS_PER_LONG > 32
+ if( ulBuff >>32 ) {
+ printk("FATAL! Tachyon DMA address %p "
+ "exceeds 32 bits\n", (void*)ulBuff );
+ return 0;
+ }
+# endif
+ *alPair = (ULONG)ulBuff;
+ return bytes_to_go;
+ }
+ else // We have a single large (too big) contiguous buffer.
+ { // We will have to break it up. We'll use the scatter
+ // gather code way below, but use contigaddr instead
+ // of sg_dma_addr(). (this is a very rare case).
+
+ unsigned long btg;
+ contigaddr = pci_map_single(pcidev, Cmnd->request_buffer,
+ Cmnd->request_bufflen,
+ scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
+
+ // printk("contigaddr = %p, len = %d\n",
+ // (void *) contigaddr, bytes_to_go);
+ totalsgs = 0;
+ for (btg = bytes_to_go; btg > 0; ) {
+ btg -= ( btg > TL_MAX_SG_ELEM_LEN ?
+ TL_MAX_SG_ELEM_LEN : btg );
+ totalsgs++;
+ }
+ sgl = NULL;
+ *sgPairs = totalsgs;
+ }
+ }
+ else // we do have a scatter gather list
+ {
+ // [TBD - update for Linux to support > 32 bits addressing]
+ // since the format for local & extended S/G lists is different,
+ // check if S/G pairs exceeds 3.
+ // *sgPairs = Cmnd->use_sg; Nope, that's wrong.
+
+ sgl = (struct scatterlist*)Cmnd->request_buffer;
+ sg_count = pci_map_sg(pcidev, sgl, Cmnd->use_sg,
+ scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
+ // printk("sgl = %p, sg_count = %d\n", (void *) sgl, sg_count);
+ if( sg_count <= 3 ) {
+
+ // we need to be careful here that no individual mapping
+ // is too large, and if any is, that breaking it up
+ // doesn't push us over 3 sgs, or, if it does, that we
+ // handle that case. Tachyon can take 0x7FFFF bits for length,
+ // but sg structure uses "unsigned int", on the face of it,
+ // up to 0xFFFFFFFF or even more.
+
+ int i;
+ unsigned long thislen;
+
+ totalsgs = 0;
+ for (i=0;i<sg_count;i++) {
+ thislen = sg_dma_len(&sgl[i]);
+ while (thislen >= TL_MAX_SG_ELEM_LEN) {
+ totalsgs++;
+ thislen -= TL_MAX_SG_ELEM_LEN;
+ }
+ if (thislen > 0) totalsgs++;
+ }
+ *sgPairs = totalsgs;
+ } else totalsgs = 999; // as a first estimate, definitely >3,
+
+ // if (totalsgs != sg_count)
+ // printk("totalsgs = %d, sgcount=%d\n",totalsgs,sg_count);
}
-
- // [TBD - update for Linux to support > 32 bits addressing]
- // since the format for local & extended S/G lists is different,
- // check if S/G pairs exceeds 3.
- *sgPairs = Cmnd->use_sg;
- sgl = (struct scatterlist*)Cmnd->request_buffer;
-
- if( *sgPairs <= 3 ) // need "local" SEST list
+ // printk("totalsgs = %d, sgcount=%d\n", totalsgs, sg_count);
+ if( totalsgs <= 3 ) // can (must) use "local" SEST list
{
while( bytes_to_go)
{
- thisMappingLen = sgl->length; // we want them ALL on every pass
- bytes_to_go = bytes_to_go - thisMappingLen;
-
- // we have L/A pair; L = thisMappingLen, A = physicalAddress
- // load into SEST...
- total_data_len += thisMappingLen & 0x7ffff; // mask in valid bits
- // per SEST format
- *alPair = thisMappingLen & 0x7ffff; // bits 18-0, length
-// physicalAddress.HighPart <= 19; // shift to bit 19
-
- // pick up bits 44-32 of upper 64-bit address
- // and load into 31-19 LBAU (upper addr) of SEST entry
-// *alPair++ |=(ULONG)((physicalAddress.HighPart & 0xFFF8));
- // on Tachlite TS's local S/G, we can handle 13 extra address bits
- // i.e., bits 31-19 are actually bits 44-32 of physicalAddress
-
- alPair++;
-
- ulBuff = virt_to_bus( sgl->address);
-#if BITS_PER_LONG > 32
- if( ulBuff >>32 )
- {
- printk("cqpfcTS: Tach DMA address %p > 32 bits\n", (void*)ulBuff );
- return 0;
- }
-#endif
- *alPair++ = (ULONG)ulBuff; // lower 32 bits (31-0)
+ offset = 0L;
- ++sgl; // next S/G pair
-#ifdef DBG_SEST_SGLIST
- printk(" thisLen %d ", thisMappingLen);
- printk(" remain %d\n", bytes_to_go);
-#endif
+ if ( WE_HAVE_SG_LIST )
+ thisMappingLen = sg_dma_len(sgl);
+ else // or contiguous buffer?
+ thisMappingLen = bytes_to_go;
- }
- }
+ while (thisMappingLen > 0)
+ {
+ thislen = thisMappingLen > TL_MAX_SG_ELEM_LEN ?
+ TL_MAX_SG_ELEM_LEN : thisMappingLen;
+ bytes_to_go = bytes_to_go - thislen;
+ // we have L/A pair; L = thislen, A = physicalAddress
+ // load into SEST...
+ total_data_len += thislen;
+ *alPair = thislen; // bits 18-0, length
+ alPair++;
+ if ( WE_HAVE_SG_LIST )
+ ulBuff = sg_dma_address(sgl) + offset;
+ else
+ ulBuff = contigaddr + offset;
+
+ offset += thislen;
+
+# if BITS_PER_LONG > 32
+ if( ulBuff >>32 ) {
+ printk("cqpfcTS: 2Tach DMA address %p > 32 bits\n",
+ (void*)ulBuff );
+ printk("%s = %p, offset = %ld\n",
+ WE_HAVE_SG_LIST ? "ulBuff" : "contigaddr",
+ WE_HAVE_SG_LIST ? (void *) ulBuff : (void *) contigaddr,
+ offset);
+ return 0;
+ }
+# endif
+ *alPair++ = (ULONG)ulBuff; // lower 32 bits (31-0)
+ thisMappingLen -= thislen;
+ }
+
+ if ( WE_HAVE_SG_LIST ) ++sgl; // next S/G pair
+ else if (bytes_to_go != 0) printk("BTG not zero!\n");
+
+# ifdef DBG_SEST_SGLIST
+ printk("L=%d ", thisMappingLen);
+ printk("btg=%d ", bytes_to_go);
+# endif
+
+ }
+ // printk("i:%d\n", *sgPairs);
+ }
else // more than 3 pairs requires Extended S/G page (Pool Allocation)
{
// clear out SEST DWORDs (local S/G addr) C-F (A-B set in following logic)
-
-
-
for( i=2; i<6; i++)
alPair[i] = 0;
PairCount = TL_EXT_SG_PAGE_COUNT; // forces initial page allocation
-
+ totalsgs = 0;
while( bytes_to_go )
{
-
-
- // Per SEST format, we can support 524287 byte lenghts per
+ // Per SEST format, we can support 524287 byte lengths per
// S/G pair. Typical user buffers are 4k, and very rarely
// exceed 12k due to fragmentation of physical memory pages.
// However, on certain O/S system (not "user") buffers (on platforms
- // with huge memories like 256Meg), it's possible to exceed this
- // length in a single S/G address/len mapping.
- //
- // Check for Tachyon length boundary
- //
- if( sgl->length > 0x7ffff )
- {
- // never ask for more than we can handle
- thisMappingLen = sgl->length & 0x7ffff;
- }
- else
- thisMappingLen = sgl->length;
-
-
+ // with huge memories), it's possible to exceed this
+ // length in a single S/G address/len mapping, so we have to handle
+ // that.
- // should we load into "this" extended S/G page, or allocate
- // new page?
+ offset = 0L;
+ if ( WE_HAVE_SG_LIST )
+ thisMappingLen = sg_dma_len(sgl);
+ else
+ thisMappingLen = bytes_to_go;
- if( PairCount >= TL_EXT_SG_PAGE_COUNT )
+ while (thisMappingLen > 0)
{
- // have we exceeded the max possible extended pages?
- if( AllocatedPages >= TL_MAX_SGPAGES)
- {
- printk("Error: aborted loop on %d Ext. S/G page allocations\n",
- AllocatedPages);
-
- total_data_len = 0; // failure!! Ext. S/G is All-or-none affair
- break; // failed
- }
-
- // Allocate the TL Extended S/G list page from O/S pool. We have
- // to allocated twice what we want to ensure required TL alignment
- // (Tachlite TL/TS User Man. Rev 6.0, p 168)
- // We store the original allocated PVOID so we can free later
-
- sgPages->PoolPage[ AllocatedPages] =
- kmalloc( TL_EXT_SG_PAGE_BYTELEN*2,GFP_ATOMIC); // double for alignment
-
-
- if( !sgPages->PoolPage[ AllocatedPages] ) // Allocation failed?
- {
-
- printk("Error: Allocation failed @ %d S/G page allocations\n",
- AllocatedPages);
-
- total_data_len = 0; // failure!! Ext. S/G is All-or-none affair
- break; // give up
- }
- // clear out memory we just allocated
- memset( sgPages->PoolPage[AllocatedPages], 0,
- TL_EXT_SG_PAGE_BYTELEN*2);
-
+ thislen = thisMappingLen > TL_MAX_SG_ELEM_LEN ?
+ TL_MAX_SG_ELEM_LEN : thisMappingLen;
+ // printk("%d/%d/%d\n", thislen, thisMappingLen, bytes_to_go);
- // align the memory - TL requires sizeof() Ext. S/G page alignment.
- // We doubled the actual required size so we could mask off LSBs
- // to get desired offset
-
- ulBuff = virt_to_bus( sgPages->PoolPage[AllocatedPages]);
+ // should we load into "this" extended S/G page, or allocate
+ // new page?
-#if BITS_PER_LONG > 32
- if( ulBuff >>32 )
- {
- printk("cqpfcTS: Tach ext. S/G DMA address %p > 32 bits\n",
- (void*)ulBuff );
- return 0;
- }
-#endif
-
- ulBuff += TL_EXT_SG_PAGE_BYTELEN; // ensures we pass align. boundary
- ulBuff &= (0xFFFFFFFF - (TL_EXT_SG_PAGE_BYTELEN -1) );// mask off LSBs
-
- alignedPageAddress = (ULONG)ulBuff;
-#ifdef DBG_SEST_SGLIST
- printk("new PoolPage: %p, alignedPageAddress %lXh\n",
- sgPages->PoolPage[AllocatedPages], ulBuff);
-#endif
+ if( PairCount >= TL_EXT_SG_PAGE_COUNT )
+ {
+ // Now, we have to map the previous page, (triggering buffer bounce)
+ // The first time thru the loop, there won't be a previous page.
+ if (prev_page != NULL) // is there a prev page?
+ {
+ // this code is normally kind of hard to trigger,
+ // you have to use up more than 256 scatter gather
+ // elements to get here. Cranking down TL_MAX_SG_ELEM_LEN
+ // to an absurdly low value (128 bytes or so) to artificially
+ // break i/o's into a zillion pieces is how I tested it.
+ busaddr = cpqfc_pci_map_sg_page(pcidev,
+ ext_sg_page_phys_addr_place,
+ prev_page->page,
+ &prev_page->busaddr,
+ &prev_page->maplen,
+ PairCount);
+ }
+ // Allocate the TL Extended S/G list page. We have
+ // to allocate twice what we want to ensure required TL alignment
+ // (Tachlite TL/TS User Man. Rev 6.0, p 168)
+ // We store the original allocated PVOID so we can free later
+ *sgpage = kmalloc( sizeof(SGPAGES), GFP_ATOMIC);
+ if ( ! *sgpage )
+ {
+ printk("cpqfc: Allocation failed @ %d S/G page allocations\n",
+ AllocatedPages);
+ total_data_len = 0; // failure!! Ext. S/G is All-or-none affair
+ // unmap the previous mappings, if any.
- // set pointer, in SEST if first Ext. S/G page, or in last pair
- // of linked Ext. S/G pages...
- // (Only 32-bit PVOIDs, so just load lower 32 bits)
- // NOTE: the Len field must be '0' if this is the first Ext. S/G
- // pointer in SEST, and not 0 otherwise.
- if( alPair == SESTalPairStart) // initial Ext. S/G list?
- *alPair = 0;
- else // not the SEST entry... Len must be non-0, so
- // arbitrarily set it to number bytes remaining
- *alPair = ( bytes_to_go & 0x7ffff);
-
-#ifdef DBG_SEST_SGLIST
- printk("PairCount %d @%p even %Xh, ",
- PairCount, alPair, *alPair);
-#endif
- alPair++; // next DWORD
+ cpqfc_undo_SEST_mappings(pcidev, contigaddr,
+ Cmnd->request_bufflen,
+ scsi_to_pci_dma_dir(Cmnd->sc_data_direction),
+ sgl, Cmnd->use_sg, sgPages_head, AllocatedPages+1);
- *alPair = alignedPageAddress; // TL needs 32-bit physical
-#ifdef DBG_SEST_SGLIST
- printk("odd %Xh\n", *alPair);
-#endif
-
- // now reset the pointer to the ACTUAL (Extended) S/G page
- // which will accept the Len/ PhysicalAddress pairs
- alPair = bus_to_virt(alignedPageAddress);
-
- AllocatedPages++;
- PairCount = 1; // starting new Ext. S/G page
- } // end of new TL Ext. S/G page allocation
+ // FIXME: testing shows that if we get here,
+ // it's bad news. (this has been this way for a long
+ // time though, AFAIK. Not that that excuses it.)
+ return 0; // give up (and probably hang the system)
+ }
+ // clear out memory we just allocated
+ memset( (*sgpage)->page,0,TL_EXT_SG_PAGE_BYTELEN*2);
+ (*sgpage)->next = NULL;
+ (*sgpage)->busaddr = (dma_addr_t) NULL;
+ (*sgpage)->maplen = 0L;
- *alPair = thisMappingLen; // bits 18-0, length (range check above)
-
-
-// physicalAddress.HighPart <= 19; // shift to bit 19
-
- // pick up bits 44-32 of upper 64-bit address
- // and load into 31-19 LBAU (upper addr) of SEST entry
-// *alPair |=(ULONG)((physicalAddress.HighPart & 0xFFF8));
+ // align the memory - TL requires sizeof() Ext. S/G page alignment.
+ // We doubled the actual required size so we could mask off LSBs
+ // to get desired offset
+
+ ulBuff = (unsigned long) (*sgpage)->page;
+ ulBuff += TL_EXT_SG_PAGE_BYTELEN;
+ ulBuff &= ~(TL_EXT_SG_PAGE_BYTELEN -1);
+
+ // set pointer, in SEST if first Ext. S/G page, or in last pair
+ // of linked Ext. S/G pages... (Only 32-bit PVOIDs, so just
+ // load lower 32 bits)
+ // NOTE: the Len field must be '0' if this is the first Ext. S/G
+ // pointer in SEST, and not 0 otherwise (we know thislen != 0).
+
+ *alPair = (alPair != SESTalPairStart) ? thislen : 0;
+
+# ifdef DBG_SEST_SGLIST
+ printk("PairCount %d @%p even %Xh, ",
+ PairCount, alPair, *alPair);
+# endif
+
+ // Save the place where we need to store the physical
+ // address of this scatter gather page which we get when we map it
+ // (and mapping we can do only after we fill it in.)
+ alPair++; // next DWORD, will contain phys addr of the ext page
+ ext_sg_page_phys_addr_place = alPair;
+
+ // Now, set alPair = the virtual addr of the (Extended) S/G page
+ // which will accept the Len/ PhysicalAddress pairs
+ alPair = (ULONG *) ulBuff;
+
+ AllocatedPages++;
+ if (AllocatedPages >= ap_hi_water)
+ {
+ // This message should rarely, if ever, come out.
+ // Previously (cpqfc version <= 2.0.5) the driver would
+ // just puke if more than 4 SG pages were used, and nobody
+ // ever complained about that. This only comes out if
+ // more than 8 pages are used.
+
+ printk(KERN_WARNING
+ "cpqfc: Possible danger. %d scatter gather pages used.\n"
+ "cpqfc: detected seemingly extreme memory "
+ "fragmentation or huge data transfers.\n",
+ AllocatedPages);
+ ap_hi_water = AllocatedPages+1;
+ }
+
+ PairCount = 1; // starting new Ext. S/G page
+ prev_page = (*sgpage); // remember this page, for next time thru
+ sgpage = &((*sgpage)->next);
+ } // end of new TL Ext. S/G page allocation
+ *alPair = thislen; // bits 18-0, length (range check above)
-#ifdef DBG_SEST_SGLIST
- printk("PairCount %d @%p, even %Xh, ",
- PairCount, alPair, *alPair);
-#endif
+# ifdef DBG_SEST_SGLIST
+ printk("PairCount %d @%p, even %Xh, ", PairCount, alPair, *alPair);
+# endif
- alPair++; // next DWORD
- // on Tachlite TS's local S/G, we can handle 13 extra address bits
- // i.e., bits 31-19 are actually bits 44-32 of physicalAddress
+ alPair++; // next DWORD, physical address
+ if ( WE_HAVE_SG_LIST )
+ ulBuff = sg_dma_address(sgl) + offset;
+ else
+ ulBuff = contigaddr + offset;
+ offset += thislen;
- ulBuff = virt_to_bus( sgl->address);
-#if BITS_PER_LONG > 32
- if( ulBuff >>32 )
- {
- printk("cqpfcTS: Tach DMA address %p > 32 bits\n", (void*)ulBuff );
- return 0;
- }
-#endif
- *alPair = (ULONG)ulBuff; // lower 32 bits (31-0)
+# if BITS_PER_LONG > 32
+ if( ulBuff >>32 )
+ {
+ printk("cqpfcTS: 1Tach DMA address %p > 32 bits\n", (void*)ulBuff );
+ printk("%s = %p, offset = %ld\n",
+ WE_HAVE_SG_LIST ? "ulBuff" : "contigaddr",
+ WE_HAVE_SG_LIST ? (void *) ulBuff : (void *) contigaddr,
+ offset);
+ return 0;
+ }
+# endif
+ *alPair = (ULONG) ulBuff; // lower 32 bits (31-0)
-#ifdef DBG_SEST_SGLIST
- printk("odd %Xh\n", *alPair);
-#endif
- alPair++; // next DWORD
+# ifdef DBG_SEST_SGLIST
+ printk("odd %Xh\n", *alPair);
+# endif
+ alPair++; // next DWORD, next address/length pair
-
- PairCount++; // next Length/Address pair
- bytes_to_go -= thisMappingLen;
- total_data_len += thisMappingLen;
- sgl++; // next S/G pair
- }
+ PairCount++; // next Length/Address pair
+
+ // if (PairCount > pc_hi_water)
+ // {
+ // printk("pc hi = %d ", PairCount);
+ // pc_hi_water = PairCount;
+ // }
+ bytes_to_go -= thislen;
+ total_data_len += thislen;
+ thisMappingLen -= thislen;
+ totalsgs++;
+ } // while (thisMappingLen > 0)
+ if ( WE_HAVE_SG_LIST ) sgl++; // next S/G pair
+ } // while (bytes_to_go)
+
+ // printk("Totalsgs=%d\n", totalsgs);
+ *sgPairs = totalsgs;
+
+ // PCI map (and bounce) the last (and usually only) extended SG page
+ busaddr = cpqfc_pci_map_sg_page(pcidev,
+ ext_sg_page_phys_addr_place,
+ prev_page->page,
+ &prev_page->busaddr,
+ &prev_page->maplen,
+ PairCount);
}
return total_data_len;
}
if( CompleteExchange || // flag from Reply frames
pExchange->status ) // typically, can get FRAME_TO
{
- cpqfcTSCompleteExchange( fcChip, ExchangeID);
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID);
}
}
if( CompleteExchange ) // by Type of exchange (e.g. end-of-xchng)
{
- cpqfcTSCompleteExchange( fcChip, ExchangeID);
+ cpqfcTSCompleteExchange( cpqfcHBAdata->PciDev, fcChip, ExchangeID);
}
else
return i;
}
+static void
+cpqfc_pci_unmap_extended_sg(struct pci_dev *pcidev,
+ PTACHYON fcChip,
+ ULONG x_ID)
+{
+ // Unmaps the memory regions used to hold the scatter gather lists
+
+ PSGPAGES i;
+ // Were there any such regions needing unmapping?
+ if (! USES_EXTENDED_SGLIST(fcChip->SEST, x_ID))
+ return; // No such regions, we're outta here.
+ // for each extended scatter gather region needing unmapping...
+ for (i=fcChip->SEST->sgPages[x_ID] ; i != NULL ; i = i->next)
+ pci_unmap_single(pcidev, i->busaddr, i->maplen,
+ scsi_to_pci_dma_dir(PCI_DMA_TODEVICE));
+}
+// Called also from cpqfcTScontrol.o, so can't be static
+void
+cpqfc_pci_unmap(struct pci_dev *pcidev,
+ Scsi_Cmnd *cmd,
+ PTACHYON fcChip,
+ ULONG x_ID)
+{
+ // Undo the DMA mappings
+ if (cmd->use_sg) { // Used scatter gather list for data buffer?
+ cpqfc_pci_unmap_extended_sg(pcidev, fcChip, x_ID);
+ pci_unmap_sg(pcidev, cmd->buffer, cmd->use_sg,
+ scsi_to_pci_dma_dir(cmd->sc_data_direction));
+ // printk("umsg %d\n", cmd->use_sg);
+ }
+ else if (cmd->request_bufflen) {
+ // printk("ums %p ", fcChip->SEST->u[ x_ID ].IWE.GAddr1);
+ pci_unmap_single(pcidev, fcChip->SEST->u[ x_ID ].IWE.GAddr1,
+ cmd->request_bufflen,
+ scsi_to_pci_dma_dir(cmd->sc_data_direction));
+ }
+}
// We call this routine to free an Exchange for any reason:
// completed successfully, completed with error, aborted, etc.
//scompleteexchange
void cpqfcTSCompleteExchange(
+ struct pci_dev *pcidev,
PTACHYON fcChip,
ULONG x_ID)
{
FC_EXCHANGES *Exchanges = fcChip->Exchanges;
+ int already_unmapped = 0;
if( x_ID < TACH_SEST_LEN ) // SEST-based (or LinkServ for FCP exchange)
{
// case for. Need code maintenance! Return "ERROR"
else
{
- printk("DEFAULT result %Xh, x_ID %Xh, Cmnd %p\n",
+ unsigned int stat = Exchanges->fcExchange[ x_ID ].status;
+ printk("DEFAULT result %Xh, x_ID %Xh, Cmnd %p",
Exchanges->fcExchange[ x_ID ].status, x_ID,
Exchanges->fcExchange[ x_ID ].Cmnd);
+
+ if (stat & INVALID_ARGS) printk(" INVALID_ARGS ");
+ if (stat & LNKDWN_OSLS) printk(" LNKDWN_OSLS ");
+ if (stat & LNKDWN_LASER) printk(" LNKDWN_LASER ");
+ if (stat & OUTQUE_FULL) printk(" OUTQUE_FULL ");
+ if (stat & DRIVERQ_FULL) printk(" DRIVERQ_FULL ");
+ if (stat & SEST_FULL) printk(" SEST_FULL ");
+ if (stat & BAD_ALPA) printk(" BAD_ALPA ");
+ if (stat & OVERFLOW) printk(" OVERFLOW ");
+ if (stat & COUNT_ERROR) printk(" COUNT_ERROR ");
+ if (stat & LINKFAIL_RX) printk(" LINKFAIL_RX ");
+ if (stat & ABORTSEQ_NOTIFY) printk(" ABORTSEQ_NOTIFY ");
+ if (stat & LINKFAIL_TX) printk(" LINKFAIL_TX ");
+ if (stat & HOSTPROG_ERR) printk(" HOSTPROG_ERR ");
+ if (stat & FRAME_TO) printk(" FRAME_TO ");
+ if (stat & INV_ENTRY) printk(" INV_ENTRY ");
+ if (stat & SESTPROG_ERR) printk(" SESTPROG_ERR ");
+ if (stat & OUTBOUND_TIMEOUT) printk(" OUTBOUND_TIMEOUT ");
+ if (stat & INITIATOR_ABORT) printk(" INITIATOR_ABORT ");
+ if (stat & MEMPOOL_FAIL) printk(" MEMPOOL_FAIL ");
+ if (stat & FC2_TIMEOUT) printk(" FC2_TIMEOUT ");
+ if (stat & TARGET_ABORT) printk(" TARGET_ABORT ");
+ if (stat & EXCHANGE_QUEUED) printk(" EXCHANGE_QUEUED ");
+ if (stat & PORTID_CHANGED) printk(" PORTID_CHANGED ");
+ if (stat & DEVICE_REMOVED) printk(" DEVICE_REMOVED ");
+ if (stat & SFQ_FRAME) printk(" SFQ_FRAME ");
+ printk("\n");
+
Exchanges->fcExchange[ x_ID ].Cmnd->result = (DID_ERROR <<16);
}
}
cpqfcTSCheckandSnoopFCP( fcChip, x_ID); // (will set ->result)
}
+ cpqfc_pci_unmap(pcidev, Exchanges->fcExchange[x_ID].Cmnd,
+ fcChip, x_ID); // undo DMA mappings.
+ already_unmapped = 1;
+
// OK, we've set the Scsi "->result" field, so proceed with calling
// Linux Scsi "done" (if not NULL), and free any kernel memory we
// may have allocated for the exchange.
if( Exchanges->fcExchange[ x_ID ].Cmnd->result != (DID_ABORT<<16) )
{
PCI_TRACE(0xAC)
- (*Exchanges->fcExchange[ x_ID ].Cmnd->scsi_done)
- (Exchanges->fcExchange[ x_ID ].Cmnd);
+ call_scsi_done(Exchanges->fcExchange[ x_ID ].Cmnd);
}
else
{
-
+ Exchanges->fcExchange[ x_ID ].Cmnd->SCp.sent_command = 0;
// printk(" not calling scsi_done on x_ID %Xh, Cmnd %p\n",
// x_ID, Exchanges->fcExchange[ x_ID ].Cmnd);
}
}
else{
+ Exchanges->fcExchange[ x_ID ].Cmnd->SCp.sent_command = 0;
printk(" x_ID %Xh, type %Xh, Cdb0 %Xh\n", x_ID,
Exchanges->fcExchange[ x_ID ].type,
Exchanges->fcExchange[ x_ID ].Cmnd->cmnd[0]);
// Now, clean up non-Scsi_Cmnd items...
CleanUpSestResources:
-
+
+ if (!already_unmapped)
+ cpqfc_pci_unmap(pcidev, Exchanges->fcExchange[x_ID].Cmnd,
+ fcChip, x_ID); // undo DMA mappings.
+
// Was an Extended Scatter/Gather page allocated? We know
// this by checking DWORD 4, bit 31 ("LOC") of SEST entry
if( !(fcChip->SEST->u[ x_ID ].IWE.Buff_Off & 0x80000000))
{
- int i = 0;
+ PSGPAGES p, next;
// extended S/G list was used -- Free the allocated ext. S/G pages
-
- while( fcChip->SEST->sgPages[x_ID].PoolPage[i] &&
- (i < TL_MAX_SGPAGES) )
- {
- kfree( fcChip->SEST->sgPages[x_ID].PoolPage[i]);
- fcChip->SEST->sgPages[x_ID].PoolPage[i] = NULL;
- i++;
+ for (p = fcChip->SEST->sgPages[x_ID]; p != NULL; p = next) {
+ next = p->next;
+ kfree(p);
}
+ fcChip->SEST->sgPages[x_ID] = NULL;
}
Exchanges->fcExchange[ x_ID ].Cmnd = NULL;
* the hardware register!
*/
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
static int dma_ports_p(struct NCR_ESP *esp);
static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
#define DTC_address(reg) (base + DTC_5380_OFFSET + reg)
#define dbNCR5380_read(reg) \
- (rval=readb(DTC_address(reg)), \
+ (rval=isa_readb(DTC_address(reg)), \
(((unsigned char) printk("DTC : read register %d at addr %08x is: %02x\n"\
, (reg), (int)DTC_address(reg), rval)), rval ) )
#define dbNCR5380_write(reg, value) do { \
printk("DTC : write %02x to register %d at address %08x\n", \
(value), (reg), (int)DTC_address(reg)); \
- writeb(value, DTC_address(reg));} while(0)
+ isa_writeb(value, DTC_address(reg));} while(0)
#if !(DTCDEBUG & DTCDEBUG_TRANSFER)
-#define NCR5380_read(reg) (readb(DTC_address(reg)))
-#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
+#define NCR5380_read(reg) (isa_readb(DTC_address(reg)))
+#define NCR5380_write(reg, value) (isa_writeb(value, DTC_address(reg)))
#else
-#define NCR5380_read(reg) (readb(DTC_address(reg)))
+#define NCR5380_read(reg) (isa_readb(DTC_address(reg)))
#define xNCR5380_read(reg) \
(((unsigned char) printk("DTC : read register %d at address %08x\n"\
- , (reg), DTC_address(reg))), readb(DTC_address(reg)))
+ , (reg), DTC_address(reg))), isa_readb(DTC_address(reg)))
#define NCR5380_write(reg, value) do { \
printk("DTC : write %02x to register %d at address %08x\n", \
(value), (reg), (int)DTC_address(reg)); \
- writeb(value, DTC_address(reg));} while(0)
+ isa_writeb(value, DTC_address(reg));} while(0)
#endif
#define NCR5380_intr dtc_intr
#include <linux/zorro.h>
#include <asm/irq.h>
-#include <asm/io.h>
+
#include <asm/amigaints.h>
#include <asm/amigahw.h>
* the hardware register!
*/
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
Scsi_Device sdev;
#endif
char cmnd[MAX_COMMAND_SIZE];
- memset(cmnd, 0xff, 12);
+ memset(cmnd, 0xff, MAX_COMMAND_SIZE);
TRACE2(("gdth_flush() hanum %d\n",hanum));
ha = HADATA(gdth_ctr_tab[hanum]);
#ifndef __alpha__
/* controller reset */
- memset(cmnd, 0xff, 12);
+ memset(cmnd, 0xff, MAX_COMMAND_SIZE);
#if LINUX_VERSION_CODE >= 0x020322
sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
scp = scsi_allocate_device(sdev, 1, FALSE);
unsigned int epc;
struct zorro_dev *z = NULL;
unsigned int default_dma_xfer_mask;
+ wd33c93_regs regs;
#ifdef CHECK_WD33C93
volatile unsigned char *sasr_3393, *scmd_3393;
unsigned char save_sasr;
/*
* Check for 14MHz SCSI clock
*/
- if (epc & GVP_SCSICLKMASK)
- wd33c93_init(instance, (wd33c93_regs *)&(DMA(instance)->SASR),
- dma_setup, dma_stop, WD33C93_FS_8_10);
- else
- wd33c93_init(instance, (wd33c93_regs *)&(DMA(instance)->SASR),
- dma_setup, dma_stop, WD33C93_FS_12_15);
+ regs.SASR = &(DMA(instance)->SASR);
+ regs.SCMD = &(DMA(instance)->SCMD);
+ wd33c93_init(instance, regs, dma_setup, dma_stop,
+ (epc & GVP_SCSICLKMASK) ? WD33C93_FS_8_10
+ : WD33C93_FS_12_15);
if (num_gvp11++ == 0) {
first_instance = instance;
static void dma_led_on(struct NCR_ESP *);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are trasfered to the ESP chip
* via PIO.
static int esp_dafb_dma_irq_p(struct NCR_ESP * espdev);
static int esp_iosb_dma_irq_p(struct NCR_ESP * espdev);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are transferred to the ESP chip
* via PIO.
* 53c9x via PIO.
*/
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/*
* We keep the structure that is used to access the registers on the 53c9x
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
- * Version : v1.17a (July 13, 2001)
+ * Version : v1.18 (Oct 11, 2001)
*
- * Description: Linux device driver for AMI MegaRAID controller
+ * Description: Linux device driver for LSI Logic MegaRAID controller
*
* Supported controllers: MegaRAID 418, 428, 438, 466, 762, 467, 471, 490
* 493.
* our current formula working to calculate logical drive number, return
* failure for LUN > 7
*
+ *
+ * Version 1.17b
+ * Mon Jul 30 19:24:02 EDT 2001 - AM
+ *
+ * Added support for random deletion of logical drives
+ *
+ * Version 1.17c
+ * Tue Sep 25 09:37:49 EDT 2001 - Atul Mukker <atulm@lsil.com>
+ *
+ * With single and dual channel controllers, some virtaul channels are
+ * displayed negative.
+ *
* Version 1.17a-ac
* Mon Aug 6 14:59:29 BST 2001 - "Michael Johnson" <johnsom@home.com>
*
* Make the HP print formatting and check for buggy firmware runtime not
* ifdef dependant.
*
+ *
+ * Version 1.17d
+ * Thu Oct 11 10:48:45 EDT 2001 - Atul Mukker <atulm@lsil.com>
+ *
+ * Driver 1.17c oops when loaded without controller.
+ *
+ * Special case for "use_sg == 1" removed while building the scatter gather
+ * list.
+ *
+ * Version 1.18
+ * Thu Oct 11 15:02:53 EDT 2001 - Atul Mukker <atulm@lsil.com>
+ *
+ * References to AMI have been changed to LSI Logic.
+ *
+ *
* BUGS:
* Some older 2.1 kernels (eg. 2.1.90) have a bug in pci.c that
* fails to detect the controller as a pci device on the system.
* queue task is a simple api without irq forms
*/
-MODULE_AUTHOR ("American Megatrends Inc.");
-MODULE_DESCRIPTION ("AMI MegaRAID driver");
-MODULE_LICENSE("GPL");
-
+MODULE_AUTHOR ("LSI Logic Corporation");
+MODULE_DESCRIPTION ("LSI Logic MegaRAID driver");
+MODULE_LICENSE ("GPL");
#define DRIVER_LOCK_T
#define DRIVER_LOCK_INIT(p)
#define DRIVER_LOCK(p)
#define DRIVER_UNLOCK(p)
-#define IO_LOCK_T unsigned long io_flags = 0;
+#define IO_LOCK_T unsigned long io_flags = 0
#define IO_LOCK spin_lock_irqsave(&io_request_lock,io_flags);
#define IO_UNLOCK spin_unlock_irqrestore(&io_request_lock,io_flags);
*/
static char kernel_version[] = UTS_RELEASE;
-MODULE_AUTHOR ("American Megatrends Inc.");
-MODULE_DESCRIPTION ("AMI MegaRAID driver");
+MODULE_AUTHOR ("LSI Logic Corporation");
+MODULE_DESCRIPTION ("LSI Logic MegaRAID driver");
#define DRIVER_LOCK_T
#define DRIVER_LOCK_INIT(p)
#define DRIVER_LOCK(p)
#define DRIVER_UNLOCK(p)
-#define IO_LOCK_T unsigned long io_flags = 0;
+#define IO_LOCK_T unsigned long io_flags = 0
#define IO_LOCK spin_lock_irqsave(&io_request_lock,io_flags);
#define IO_UNLOCK spin_unlock_irqrestore(&io_request_lock,io_flags);
static struct mcontroller mcontroller[MAX_CONTROLLERS];
/* The current driver version */
-static u32 driver_ver = 117;
+static u32 driver_ver = 114;
/* major number used by the device for character interface */
static int major;
panic(KERN_ERR "megaraid:Problem...!\n");
}
+ islogical = ( (SCpnt->channel >= megaCfg->productInfo.SCSIChanPresent) &&
+ (SCpnt->channel <= megaCfg->host->max_channel) );
+#if 0
islogical = (SCpnt->channel == megaCfg->host->max_channel);
+#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
/* Special Case to handle PassThrough->XferAddrress > 4GB */
mega_ext_passthru *epthru;
long seg;
char islogical;
- char lun = SCpnt->lun;
+ int lun = SCpnt->lun;
+ int max_lun;
if ((SCpnt->cmnd[0] == MEGADEVIOC))
return megadev_doioctl (megaCfg, SCpnt);
}
#endif
+ islogical = ( (SCpnt->channel >= megaCfg->productInfo.SCSIChanPresent) &&
+ (SCpnt->channel <= megaCfg->host->max_channel) );
+#if 0
islogical = (IS_RAID_CH(SCpnt->channel) && /* virtual ch is raid - AM */
(SCpnt->channel == megaCfg->host->max_channel));
+#endif
if ( ! megaCfg->support_ext_cdb ) {
if (!islogical && lun != 0) {
return NULL;
}
- /*
- * Return error for LUN > 7. The way we calculate logical drive number
- * requires it to be so.
- */
- if( lun > 7 ) {
- SCpnt->result = (DID_BAD_TARGET << 16);
- callDone (SCpnt);
- return NULL;
- }
-
if (islogical) {
- lun = (SCpnt->target * 8) + lun;
+ /* have just LUN 0 for each target on virtual channels */
+ if( SCpnt->lun != 0 ) {
+ SCpnt->result = (DID_BAD_TARGET << 16);
+ callDone (SCpnt);
+ return NULL;
+ }
+
+ lun = mega_get_lun(megaCfg, SCpnt);
- if(lun >= megaCfg->numldrv ) {
+ max_lun = (megaCfg->flag & BOARD_40LD) ?
+ FC_MAX_LOGICAL_DRIVES : MAX_LOGICAL_DRIVES;
+
+ /*
+ * max_lun increases by 0x80 if some logical drive was deleted.
+ */
+ if(megaCfg->read_ldidmap) {
+ max_lun += 0x80;
+ }
+
+ if( lun > max_lun ) {
SCpnt->result = (DID_BAD_TARGET << 16);
callDone (SCpnt);
return NULL;
}
}
}
+ } else {
+ if ( lun > 7) {
+ /* Do not support lun >7 for physically accessed devices */
+ SCpnt->result = (DID_BAD_TARGET << 16);
+ callDone (SCpnt);
+ return NULL;
+ }
}
/*-----------------------------------------------------
*
return NULL;
}
+static int
+mega_get_lun(mega_host_config *this_hba, Scsi_Cmnd *sc)
+{
+ int tgt;
+ int lun;
+ int virt_chan;
+
+ tgt = sc->target;
+
+ if ( tgt > 7 ) tgt--; /* we do not get inquires for tgt 7 */
+
+ virt_chan = sc->channel - this_hba->productInfo.SCSIChanPresent;
+ lun = (virt_chan * 15) + tgt;
+
+ /*
+ * If "delete logical drive" feature is enabled on this controller.
+ * Do only if at least one delete logical drive operation was done.
+ *
+ * Also, after logical drive deletion, instead of logical drive number,
+ * the value returned should be 0x80+logical drive id.
+ *
+ * These is valid only for IO commands.
+ */
+
+ if( this_hba->support_random_del && this_hba->read_ldidmap ) {
+ switch(sc->cmnd[0]) {
+ case READ_6: /* fall through */
+ case WRITE_6: /* fall through */
+ case READ_10: /* fall through */
+ case WRITE_10:
+ lun += 0x80;
+ }
+ }
+
+ return lun;
+}
+
+
static mega_passthru *
mega_prepare_passthru(mega_host_config *megacfg, mega_scb *scb, Scsi_Cmnd *sc)
{
*--------------------------------------------------------------------*/
static void megaraid_isr (int irq, void *devp, struct pt_regs *regs)
{
- IO_LOCK_T
+ IO_LOCK_T;
mega_host_config * megaCfg;
u_char byte, idx, sIdx, tmpBox[MAILBOX_SIZE];
u32 dword = 0;
}
sgList = (struct scatterlist *) scb->SCpnt->request_buffer;
-
+#if 0
if (scb->SCpnt->use_sg == 1) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
return 0;
}
-
+#endif
/* Copy Scatter-Gather list info into controller structure */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
sgcnt = pci_map_sg (megaCfg->dev,
mboxData[2] = NC_SUBOP_PRODUCT_INFO; /* i.e. 0x0E */
if ((retval = megaIssueCmd (megaCfg, mboxData, NULL, 0)) != 0)
- printk ("ami:Product_info cmd failed with error: %d\n",
+ printk ("megaraid: Product_info cmd failed with error: %d\n",
retval);
pci_unmap_single (megaCfg->dev,
PCI_DMA_FROMDEVICE);
}
- megaCfg->host->max_channel = megaCfg->productInfo.SCSIChanPresent;
+ /*
+ * kernel scans the channels from 0 to <= max_channel
+ */
+ megaCfg->host->max_channel =
+ megaCfg->productInfo.SCSIChanPresent + NVIRT_CHAN -1;
+
megaCfg->host->max_id = 16; /* max targets per channel */
/*(megaCfg->flag & BOARD_40LD)?FC_MAX_TARGETS_PER_CHANNEL:MAX_TARGET+1; */
+#if 0
megaCfg->host->max_lun = /* max lun */
- (megaCfg->
- flag & BOARD_40LD) ? FC_MAX_LOGICAL_DRIVES : MAX_LOGICAL_DRIVES;
+ (megaCfg->flag & BOARD_40LD) ?
+ FC_MAX_LOGICAL_DRIVES : MAX_LOGICAL_DRIVES;
+#endif
+ megaCfg->host->max_lun = 7; /* Upto 7 luns for non disk devices */
+
megaCfg->host->cmd_per_lun = MAX_CMD_PER_LUN;
megaCfg->numldrv = enquiry3Pnt->numLDrv;
}
#endif
- /* use HP firmware and bios version encoding */
-if (megaCfg->productInfo.subSystemVendorID == HP_SUBSYS_ID) {
- sprintf (megaCfg->fwVer, "%c%d%d.%d%d",
- megaCfg->productInfo.FwVer[2],
- megaCfg->productInfo.FwVer[1] >> 8,
- megaCfg->productInfo.FwVer[1] & 0x0f,
- megaCfg->productInfo.FwVer[2] >> 8,
- megaCfg->productInfo.FwVer[2] & 0x0f);
- sprintf (megaCfg->biosVer, "%c%d%d.%d%d",
- megaCfg->productInfo.BiosVer[2],
- megaCfg->productInfo.BiosVer[1] >> 8,
- megaCfg->productInfo.BiosVer[1] & 0x0f,
- megaCfg->productInfo.BiosVer[2] >> 8,
- megaCfg->productInfo.BiosVer[2] & 0x0f);
-} else {
- memcpy (megaCfg->fwVer, (char *) megaCfg->productInfo.FwVer, 4);
- megaCfg->fwVer[4] = 0;
-
- memcpy (megaCfg->biosVer, (char *) megaCfg->productInfo.BiosVer, 4);
- megaCfg->biosVer[4] = 0;
-}
+ /* use HP firmware and bios version encoding */
+ if (megaCfg->productInfo.subSystemVendorID == HP_SUBSYS_ID) {
+ sprintf (megaCfg->fwVer, "%c%d%d.%d%d",
+ megaCfg->productInfo.FwVer[2],
+ megaCfg->productInfo.FwVer[1] >> 8,
+ megaCfg->productInfo.FwVer[1] & 0x0f,
+ megaCfg->productInfo.FwVer[0] >> 8,
+ megaCfg->productInfo.FwVer[0] & 0x0f);
+ sprintf (megaCfg->biosVer, "%c%d%d.%d%d",
+ megaCfg->productInfo.BiosVer[2],
+ megaCfg->productInfo.BiosVer[1] >> 8,
+ megaCfg->productInfo.BiosVer[1] & 0x0f,
+ megaCfg->productInfo.BiosVer[0] >> 8,
+ megaCfg->productInfo.BiosVer[0] & 0x0f);
+ } else {
+ memcpy (megaCfg->fwVer, (char *) megaCfg->productInfo.FwVer, 4);
+ megaCfg->fwVer[4] = 0;
+
+ memcpy (megaCfg->biosVer, (char *) megaCfg->productInfo.BiosVer, 4);
+ megaCfg->biosVer[4] = 0;
+ }
megaCfg->support_ext_cdb = mega_support_ext_cdb(megaCfg);
printk (KERN_NOTICE "megaraid: [%s:%s] detected %d logical drives" M_RD_CRLFSTR,
u32 magic64;
#endif
- int i;
+ int i;
#ifdef __LP64__
u64 megaBase;
if (!host)
goto err_unmap;
-#if 0
/*
* Comment the following initialization if you know 'max_sectors' is
* not defined for this kernel.
* greatly increases the IO performance - AM
*/
host->max_sectors = 1024;
-#endif
scsi_set_pci_device(host, pdev);
megaCfg = (mega_host_config *) host->hostdata;
megaCfg->lock_pend = SPIN_LOCK_UNLOCKED;
megaCfg->lock_scsicmd = SPIN_LOCK_UNLOCKED;
megaCfg->flag = flag;
+ megaCfg->int_qh = NULL;
+ megaCfg->int_qt = NULL;
+ megaCfg->int_qlen = 0;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
megaCfg->dev = pdev;
* Find out which channel is raid and which is scsi
*/
mega_enum_raid_scsi(megaCfg);
- for( i = 0; i < megaCfg->host->max_channel; i++ ) {
+ for( i = 0; i < megaCfg->productInfo.SCSIChanPresent; i++ ) {
if(IS_RAID_CH(i))
printk(KERN_NOTICE"megaraid: channel[%d] is raid.\n", i+1);
else
mega_hbas[numCtlrs].hostdata_addr = megaCfg;
+ /*
+ * Do we support random deletion and addition of logical drives
+ */
+ megaCfg->read_ldidmap = 0; /* set it after first logdrv delete cmd */
+ megaCfg->support_random_del = mega_support_random_del(megaCfg);
+
/* Initialize SCBs */
if (mega_init_scb (megaCfg)) {
pci_free_consistent (megaCfg->dev,
skip_id = (skip_id > 15) ? -1 : skip_id;
}
- printk (KERN_NOTICE "megaraid: " MEGARAID_VERSION M_RD_CRLFSTR);
+ printk (KERN_NOTICE "megaraid: " MEGARAID_VERSION);
memset (mega_hbas, 0, sizeof (mega_hbas));
{
mega_mailbox *mboxp;
unsigned char mbox[16];
+ int i;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
dma_addr_t dma_handle;
if( megaIssueCmd(megacfg, mbox, NULL, 0) == 0 ) {
mega_ch_class = *((char *)megacfg->mega_buffer);
- /* logical drives channel is RAID */
- mega_ch_class |= (0x01 << megacfg->host->max_channel);
+ for( i = 0; i < NVIRT_CHAN; i++ ) {
+ /* logical drives channel is RAID */
+ mega_ch_class |= (0x01 << (megacfg->productInfo.SCSIChanPresent+i));
+ }
}
else {
mega_ch_class = 0xFF;
megaCfg = (mega_host_config *) pSHost->hostdata;
sprintf (buffer,
- "AMI MegaRAID %s %d commands %d targs %d chans %d luns",
+ "LSI Logic MegaRAID %s %d commands %d targs %d chans %d luns",
megaCfg->fwVer, megaCfg->productInfo.MaxConcCmds,
megaCfg->host->max_id, megaCfg->host->max_channel,
megaCfg->host->max_lun);
DRIVER_LOCK (megaCfg);
if (!(megaCfg->flag & (1L << SCpnt->channel))) {
- if (SCpnt->channel < SCpnt->host->max_channel)
+ if (SCpnt->channel < megaCfg->productInfo.SCSIChanPresent)
printk ( KERN_NOTICE
- "scsi%d: scanning channel %c for devices.\n",
- megaCfg->host->host_no, SCpnt->channel + '1');
+ "scsi%d: scanning channel %d for devices.\n",
+ megaCfg->host->host_no, SCpnt->channel);
else
printk ( KERN_NOTICE
- "scsi%d: scanning virtual channel for logical drives.\n",
- megaCfg->host->host_no);
+ "scsi%d: scanning virtual channel %d for logical drives.\n",
+ megaCfg->host->host_no,
+ SCpnt->channel-megaCfg->productInfo.SCSIChanPresent+1);
megaCfg->flag |= (1L << SCpnt->channel);
}
megaCfg->flag |= IN_QUEUE;
/* Allocate and build a SCB request */
if ((pScb = mega_build_cmd (megaCfg, SCpnt)) != NULL) {
- /*build SCpnt for M_RD_IOCTL_CMD_NEW cmd in mega_ioctl() */
- /* Add SCB to the head of the pending queue */
- /* Add SCB to the head of the pending queue */
- if (megaCfg->qPendingH == NULL) {
- megaCfg->qPendingH = megaCfg->qPendingT = pScb;
- } else {
- megaCfg->qPendingT->next = pScb;
- megaCfg->qPendingT = pScb;
- }
- megaCfg->qPendingT->next = NULL;
- megaCfg->qPcnt++;
- if (mega_runpendq (megaCfg) == -1) {
- DRIVER_UNLOCK (megaCfg);
- return 0;
+ /*
+ * Check if the HBA is in quiescent state, e.g., during a delete
+ * logical drive opertion. If it is, queue the commands in the
+ * internal queue until the delete operation is complete.
+ */
+ if( ! megaCfg->quiescent ) {
+ /* Add SCB to the head of the pending queue */
+ if (megaCfg->qPendingH == NULL) {
+ megaCfg->qPendingH = megaCfg->qPendingT = pScb;
+ } else {
+ megaCfg->qPendingT->next = pScb;
+ megaCfg->qPendingT = pScb;
+ }
+ megaCfg->qPendingT->next = NULL;
+ megaCfg->qPcnt++;
+
+ if (mega_runpendq (megaCfg) == -1) {
+ DRIVER_UNLOCK (megaCfg);
+ return 0;
+ }
+ }
+ else {
+ /* Add SCB to the internal queue */
+ if (megaCfg->int_qh == NULL) {
+ megaCfg->int_qh = megaCfg->int_qt = pScb;
+ } else {
+ megaCfg->int_qt->next = pScb;
+ megaCfg->int_qt = pScb;
+ }
+ megaCfg->int_qt->next = NULL;
+ megaCfg->int_qlen++;
}
if (pScb->SCpnt->cmnd[0] == M_RD_IOCTL_CMD_NEW) {
return -1;
if( *(unsigned short *)(bh->b_data + 510) == 0xAA55 ) {
+
for( largest_cyl = -1, p = (struct partition *)(0x1BE + bh->b_data),
i = 0; i < 4; ++i, ++p) {
}
}
}
+
if (largest) {
heads = largest->end_head + 1;
sectors = largest->end_sector & 0x3f;
break;
case M_RD_IOCTL_CMD_NEW:
+
+ /*
+ * Deletion of logical drives is only handled in 0x80 commands
+ */
+ if( ioc.mbox[0] == FC_DEL_LOGDRV && ioc.mbox[2] == OP_DEL_LOGDRV ) {
+ return -EINVAL;
+ }
+
/* which adapter? */
adapno = ioc.ui.fcs.adapno;
}
if(shpnt == NULL) return -ENODEV;
+ /*
+ * ioctls for deleting logical drives is a special case, so check
+ * for it first
+ */
+ if( ioc.mbox[0] == FC_DEL_LOGDRV && ioc.mbox[2] == OP_DEL_LOGDRV ) {
+
+ if( !megacfg->support_random_del ) {
+ printk("megaraid: logdrv delete on non supporting f/w.\n");
+ return -EINVAL;
+ }
+
+ uioc = (struct uioctl_t *)arg;
+
+ ret = mega_del_logdrv(megacfg, ioc.mbox[3]);
+
+ put_user(1, &uioc->mbox[16]); /* numstatus */
+ put_user(ret, &uioc->mbox[17]); /* status */
+
+ /* if deletion failed, let the user know by failing ioctl */
+ return ret;
+ }
+
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
scsicmd = (Scsi_Cmnd *)kmalloc(sizeof(Scsi_Cmnd), GFP_KERNEL|GFP_DMA);
#else
put_user (scsicmd->result, &uioc->pthru.scsistatus);
} else {
put_user (1, &uioc->mbox[16]); /* numstatus */
- /* status */
- put_user (scsicmd->result, &uioc->mbox[17]);
+ put_user (scsicmd->result, &uioc->mbox[17]); /* status */
}
if (kvaddr) {
}
+/*
+ * Find out if this controller supports random deletion and addition of
+ * logical drives
+ */
+static int
+mega_support_random_del(mega_host_config *this_hba)
+{
+ mega_mailbox *mboxpnt;
+ unsigned char mbox[16];
+ int ret;
+
+ mboxpnt = (mega_mailbox *)mbox;
+
+ memset(mbox, 0, sizeof(mbox));
+
+ /*
+ * issue command
+ */
+ mbox[0] = FC_DEL_LOGDRV;
+ mbox[2] = OP_SUP_DEL_LOGDRV;
+
+ ret = megaIssueCmd(this_hba, mbox, NULL, 0);
+
+ return !ret;
+}
+
+static int
+mega_del_logdrv(mega_host_config *this_hba, int logdrv)
+{
+ int rval;
+ IO_LOCK_T;
+ DECLARE_WAIT_QUEUE_HEAD(wq);
+ mega_scb *scbp;
+
+ /*
+ * Stop sending commands to the controller, queue them internally.
+ * When deletion is complete, ISR will flush the queue.
+ */
+ IO_LOCK;
+ this_hba->quiescent = 1;
+ IO_UNLOCK;
+
+ while( this_hba->qPcnt ) {
+ sleep_on_timeout( &wq, 1*HZ ); /* sleep for 1s */
+ }
+ rval = mega_do_del_logdrv(this_hba, logdrv);
+
+ IO_LOCK;
+ /*
+ * Attach the internal queue to the pending queue
+ */
+ if( this_hba->qPendingH == NULL ) {
+ /*
+ * If pending queue head is null, make internal queue as
+ * pending queue
+ */
+ this_hba->qPendingH = this_hba->int_qh;
+ this_hba->qPendingT = this_hba->int_qt;
+ this_hba->qPcnt = this_hba->int_qlen;
+ }
+ else {
+ /*
+ * Append pending queue to internal queue
+ */
+ if( this_hba->int_qt ) {
+ this_hba->int_qt->next = this_hba->qPendingH;
+
+ this_hba->qPendingH = this_hba->int_qh;
+ this_hba->qPcnt += this_hba->int_qlen;
+ }
+ }
+
+ this_hba->int_qh = this_hba->int_qt = NULL;
+ this_hba->int_qlen = 0;
+
+ /*
+ * If delete operation was successful, add 0x80 to the logical drive
+ * ids for commands in the pending queue.
+ */
+ if( this_hba->read_ldidmap) {
+ for( scbp = this_hba->qPendingH; scbp; scbp = scbp->next ) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ if( scbp->pthru->logdrv < 0x80 )
+ scbp->pthru->logdrv += 0x80;
+#else
+ if( scbp->pthru.logdrv < 0x80 )
+ scbp->pthru.logdrv += 0x80;
+#endif
+ }
+ }
+ this_hba->quiescent = 0;
+
+ IO_UNLOCK;
+
+ return rval;
+}
+
+
+static int
+mega_do_del_logdrv(mega_host_config *this_hba, int logdrv)
+{
+ mega_mailbox *mboxpnt;
+ unsigned char mbox[16];
+ int rval;
+
+ mboxpnt = (mega_mailbox *)mbox;
+
+ memset(mbox, 0, sizeof(mbox));
+
+ mbox[0] = FC_DEL_LOGDRV;
+ mbox[2] = OP_DEL_LOGDRV;
+ mbox[3] = logdrv;
+
+ rval = megaIssueCmd(this_hba, mbox, NULL, 0);
+
+ /* log this event */
+ if( rval != 0 ) {
+ printk("megaraid: Attempt to delete logical drive %d failed.",
+ logdrv);
+ return rval;
+ }
+
+ printk("megaraid: logical drive %d deleted.\n", logdrv);
+
+ /*
+ * After deleting first logical drive, the logical drives must be
+ * addressed by adding 0x80 to the logical drive id.
+ */
+ this_hba->read_ldidmap = 1;
+
+ return rval;
+}
+
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0)
void *
dma_alloc_consistent(void *dev, size_t size, dma_addr_t *dma_addr)
#include <linux/version.h>
#endif
+/*
+ * For state flag. Do not use LSB(8 bits) which are
+ * reserved for storing info about channels.
+ */
#define IN_ISR 0x80000000L
#define IN_ABORT 0x40000000L
#define IN_RESET 0x20000000L
#define IN_QUEUE 0x10000000L
-
#define BOARD_QUARTZ 0x08000000L
#define BOARD_40LD 0x04000000L
#define BOARD_64BIT 0x02000000L
#define M_RD_IOCTL_CMD_NEW 0x81
#define M_RD_DRIVER_IOCTL_INTERFACE 0x82
-#define MEGARAID_VERSION "v1.17a (Release Date: Fri Jul 13 18:44:01 EDT 2001)"
+#define MEGARAID_VERSION "v1.18 (Release Date: Thu Oct 11 15:02:53 EDT 2001\n)"
#define MEGARAID_IOCTL_VERSION 114
int support_ext_cdb;
int boot_ldrv_enabled;
int boot_ldrv;
+
+ int support_random_del; /* Do we support random deletion of logdrvs */
+ int read_ldidmap; /* set after logical drive deltion. The logical
+ drive number must be read from the map */
+ int quiescent; /* a stage reached when delete logical drive needs to
+ be done. Stop sending requests to the hba till
+ delete operation is completed */
+
+ mega_scb *int_qh; /* commands are queued in the internal queue */
+ mega_scb *int_qt; /* while the hba is quiescent */
+ int int_qlen;
} mega_host_config;
typedef struct _driver_info {
};
#pragma pack()
+#define NVIRT_CHAN 4 /* # of virtual channels to represent 60 logical
+ drives */
+
+/*
+ * Command for random deletion of logical drives
+ */
+#define FC_DEL_LOGDRV 0xA4 /* f/w command */
+#define OP_SUP_DEL_LOGDRV 0x2A /* is feature supported */
+#define OP_GET_LDID_MAP 0x18 /* get logdrv id and logdrv number map */
+#define OP_DEL_LOGDRV 0x1C /* delete logical drive */
/*================================================================
*
static void mega_enum_raid_scsi(mega_host_config *);
static int mega_partsize(Disk *, kdev_t, int *);
static void mega_get_boot_ldrv(mega_host_config *);
+static int mega_get_lun(mega_host_config *, Scsi_Cmnd *);
+static int mega_support_random_del(mega_host_config *);
+static int mega_del_logdrv(mega_host_config *, int);
+static int mega_do_del_logdrv(mega_host_config *, int);
#endif
int mvme147_detect(Scsi_Host_Template *tpnt)
{
static unsigned char called = 0;
+ wd33c93_regs regs;
if (!MACH_IS_MVME147 || called)
return 0;
tpnt->proc_info = &wd33c93_proc_info;
mvme147_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata));
+ if (!mvme147_host)
+ goto err_out;
+
mvme147_host->base = 0xfffe4000;
mvme147_host->irq = MVME147_IRQ_SCSI_PORT;
- wd33c93_init(mvme147_host, (wd33c93_regs *)0xfffe4000,
- dma_setup, dma_stop, WD33C93_FS_8_10);
-
- request_irq(MVME147_IRQ_SCSI_PORT, mvme147_intr, 0, "MVME147 SCSI PORT", mvme147_intr);
- request_irq(MVME147_IRQ_SCSI_DMA, mvme147_intr, 0, "MVME147 SCSI DMA", mvme147_intr);
+ regs.SASR = (volatile unsigned char *)0xfffe4000;
+ regs.SCMD = (volatile unsigned char *)0xfffe4001;
+ wd33c93_init(mvme147_host, regs, dma_setup, dma_stop, WD33C93_FS_8_10);
+
+ if (request_irq(MVME147_IRQ_SCSI_PORT, mvme147_intr, 0, "MVME147 SCSI PORT", mvme147_intr))
+ goto err_unregister;
+ if (request_irq(MVME147_IRQ_SCSI_DMA, mvme147_intr, 0, "MVME147 SCSI DMA", mvme147_intr))
+ goto err_free_irq;
#if 0 /* Disabled; causes problems booting */
m147_pcc->scsi_interrupt = 0x10; /* Assert SCSI bus reset */
udelay(100);
m147_pcc->dma_intr = 0x89; /* Ack and enable ints */
return 1;
+
+ err_free_irq:
+ free_irq(MVME147_IRQ_SCSI_PORT, mvme147_intr);
+ err_unregister:
+ wd33c93_release();
+ scsi_unregister(mvme147_host);
+ err_out:
+ return 0;
}
#define HOSTS_C
called = 1;
return 1;
}
+
+static Scsi_Host_Template driver_template = MVME16x_SCSI;
+#include "scsi_module.c"
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/pgtable.h>
-#include <asm/io.h>
+
#include "scsi.h"
#include "hosts.h"
static struct NCR_ESP *current_esp;
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are trasfered to the ESP chip
* via PIO.
int i,k;
k = 0;
i = jiffies + WATCHDOG;
- while ( i > jiffies && !qabort && !((k = inb(qbase + 4)) & 0xe0))
+ while ( i > jiffies && !qabort && !((k = inb(qbase + 4)) & 0xe0)) {
barrier();
+ cpu_relax();
+ }
if (i <= jiffies)
return (DID_TIME_OUT);
if (qabort)
i = inb(qbase + 5); /* should be bus service */
while (!qabort && ((i & 0x20) != 0x20)) {
barrier();
+ cpu_relax();
i |= inb(qbase + 5);
}
rtrc(0)
cmd->scsi_done = done;
/* wait for the last command's interrupt to finish */
- while (qlcmd != NULL)
+ while (qlcmd != NULL) {
barrier();
+ cpu_relax();
+ }
ql_icmd(cmd);
return 0;
}
outw(HCCR_CLEAR_RISC_INTR, host->io_port + HOST_HCCR);
isp2x00_enable_irqs(host);
/* wait for the loop to come up */
- for (wait_time = jiffies + 10 * HZ; wait_time > jiffies && hostdata->adapter_state == AS_LOOP_DOWN;)
+ for (wait_time = jiffies + 10 * HZ; wait_time > jiffies && hostdata->adapter_state == AS_LOOP_DOWN;) {
barrier();
-
+ cpu_relax();
+ }
if (hostdata->adapter_state == AS_LOOP_DOWN) {
printk("qlogicfc%d : link is not up\n", hostdata->host_id);
}
some time before recognizing it is attached to a fabric */
#if ISP2x00_FABRIC
- for (wait_time = jiffies + 5 * HZ; wait_time > jiffies;)
+ for (wait_time = jiffies + 5 * HZ; wait_time > jiffies;) {
barrier();
+ cpu_relax();
+ }
#endif
LEAVE("isp2x00_detect");
outw(HCCR_BIOS_DISABLE, host->io_port + HOST_HCCR);
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && inw(host->io_port + HOST_HCCR) == RISC_BUSY)
+ while (--loop_count && inw(host->io_port + HOST_HCCR) == RISC_BUSY) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk("qlogicfc%d : reset_hardware loop timeout\n", hostdata->host_id);
return 1;
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && inw(host->io_port + HOST_HCCR) & 0x0080)
+ while (--loop_count && inw(host->io_port + HOST_HCCR) & 0x0080) {
barrier();
+ cpu_relax();
+ }
if (!loop_count) {
printk("qlogicfc%d : mbox_command loop timeout #1\n", hostdata->host_id);
param[0] = 0x4006;
while (1) {
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && !(inw(host->io_port + PCI_INTER_STS) & 0x08)) {
+ while (--loop_count && !(inw(host->io_port + PCI_INTER_STS) & 0x08)) {
barrier();
+ cpu_relax();
}
if (!loop_count) {
loop_count = DEFAULT_LOOP_COUNT;
while (--loop_count && inw(host->io_port + MBOX0) == 0x04) {
barrier();
+ cpu_relax();
}
if (!loop_count)
printk("qlogicfc%d : mbox_command loop timeout #3\n", hostdata->host_id);
isp_outw(HCCR_BIOS_DISABLE, host, HOST_HCCR);
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY)
+ while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk("qlogicisp: reset_hardware loop timeout\n");
return 1;
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080)
+ while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk("qlogicisp: mbox_command loop timeout #1\n");
isp_outw(HCCR_SET_HOST_INTR, host, HOST_HCCR);
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04))
+ while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04)) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk("qlogicisp: mbox_command loop timeout #2\n");
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && isp_inw(host, MBOX0) == 0x04)
+ while (--loop_count && isp_inw(host, MBOX0) == 0x04) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk("qlogicisp: mbox_command loop timeout #3\n");
/* Wait for host IRQ bit to clear. */
loop_count = DEFAULT_LOOP_COUNT;
- while (--loop_count && (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_HIRQ))
+ while (--loop_count && (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_HIRQ)) {
barrier();
+ cpu_relax();
+ }
if (!loop_count)
printk(KERN_EMERG "qlogicpti: mbox_command loop timeout #1\n");
}
count++;
sgpnt[count - 1].address = bh->b_data;
+ sgpnt[count - 1].page = NULL;
sgpnt[count - 1].length += bh->b_size;
if (!dma_host) {
SCpnt->request_bufflen += bh->b_size;
static struct block_device_operations sd_fops =
{
+ owner: THIS_MODULE,
open: sd_open,
release: sd_release,
ioctl: sd_ioctl,
return 1;
}
-static int sr_dev_open(struct inode *inode, struct file *file)
-{
- int err;
- MOD_INC_USE_COUNT;
- err = cdrom_open(inode, file);
- if (err)
- MOD_DEC_USE_COUNT;
- return err;
-}
-
-static int sr_dev_release(struct inode *inode, struct file *file)
-{
- int err = cdrom_release(inode, file);
- MOD_DEC_USE_COUNT;
- return err;
-}
-
struct block_device_operations sr_bdops =
{
- open: sr_dev_open,
- release: sr_dev_release,
+ owner: THIS_MODULE,
+ open: cdrom_open,
+ release: cdrom_release,
ioctl: cdrom_ioctl,
check_media_change: cdrom_media_changed,
};
static volatile int main_running = 0;
static struct tq_struct NCR5380_tqueue = {
- NULL, /* next */
- 0, /* sync */
- (void (*)(void*))NCR5380_main, /* routine, must have (void *) arg... */
- NULL /* data */
+// NULL, /* next */
+ sync: 0, /* sync */
+ routine: (void (*)(void*))NCR5380_main, /* routine, must have (void *) arg... */
+ data: NULL /* data */
};
static __inline__ void queue_main(void)
HOSTNO, NCR5380_read(BUS_AND_STATUS_REG),
NCR5380_read(STATUS_REG));
- if((sun3scsi_dma_finish())) {
+ if((sun3scsi_dma_finish(hostdata->connected->request.cmd))) {
printk("scsi%d: overrun in UDC counter -- not prepared to deal with this!\n", HOSTNO);
printk("please e-mail sammy@oh.verio.com with a description of how this\n");
printk("error was produced.\n");
#include <asm/sun3ints.h>
#include <asm/dvma.h>
+#include <asm/idprom.h>
+#include <asm/machines.h>
+
/* dma on! */
#define REAL_DMA
#define AFTER_RESET_DELAY (HZ/2)
/* ms to wait after hitting dma regs */
-#define SUN3_DMA_DELAY 5
+#define SUN3_DMA_DELAY 10
/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
#define SUN3_DVMA_BUFSIZE 0xe000
static volatile struct sun3_dma_regs *dregs;
static unsigned char *dmabuf = NULL; /* dma memory buffer */
static struct sun3_udc_regs *udc_regs = NULL;
-static void *sun3_dma_orig_addr = NULL;
+static unsigned char *sun3_dma_orig_addr = NULL;
static unsigned long sun3_dma_orig_count = 0;
static int sun3_dma_active = 0;
+static unsigned long last_residual = 0;
/*
* NCR 5380 register access functions
static int called = 0;
struct Scsi_Host *instance;
+ /* check that this machine has an onboard 5380 */
+ switch(idprom->id_machtype) {
+ case SM_SUN3|SM_3_50:
+ case SM_SUN3|SM_3_60:
+ break;
+
+ default:
+ return 0;
+ }
+
if(called)
return 0;
sun3_scsi_regp = (unsigned char *)ioaddr;
dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);
- if((dmabuf = sun3_dvma_malloc(SUN3_DVMA_BUFSIZE)) == NULL) {
+ if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)))
+ == NULL) {
printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
return 0;
}
-
- if((udc_regs = sun3_dvma_malloc(sizeof(struct sun3_udc_regs)))
- == NULL) {
+#ifdef OLDDMA
+ if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) {
printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
return 0;
}
-
+#endif
#ifdef SUPPORT_TAGS
if (setup_use_tagged_queuing < 0)
setup_use_tagged_queuing = DEFAULT_USE_TAGGED_QUEUING;
/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag)
{
+#ifdef OLDDMA
if(write_flag)
memcpy(dmabuf, data, count);
else {
sun3_dma_orig_addr = data;
sun3_dma_orig_count = count;
}
+#else
+ void *addr;
+// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf);
+ addr = (void *)dvma_map((unsigned long) data, count);
+ sun3_dma_orig_addr = addr;
+ sun3_dma_orig_count = count;
+#endif
dregs->fifo_count = 0;
sun3_udc_write(UDC_RESET, UDC_CSR);
}
/* setup udc */
- udc_regs->addr_hi = ((sun3_dvma_vtop(dmabuf) & 0xff0000) >> 8);
- udc_regs->addr_lo = (sun3_dvma_vtop(dmabuf) & 0xffff);
+#ifdef OLDDMA
+ udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8);
+ udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff);
+#else
+ udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
+ udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
+#endif
udc_regs->count = count/2; /* count in words */
udc_regs->mode_hi = UDC_MODE_HIWORD;
if(write_flag) {
}
/* announce location of regs block */
- sun3_udc_write(((sun3_dvma_vtop(udc_regs) & 0xff0000) >> 8),
+ sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
UDC_CHN_HI);
- sun3_udc_write((sun3_dvma_vtop(udc_regs) & 0xffff), UDC_CHN_LO);
+ sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
/* set dma master on */
sun3_udc_write(0xd, UDC_MODE);
}
-static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
+static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance)
{
unsigned short resid;
return (unsigned long) resid;
}
+static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
+{
+ return last_residual;
+}
+
static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted, Scsi_Cmnd *cmd,
int write_flag)
{
}
/* clean up after our dma is done */
-static int sun3scsi_dma_finish(void)
+static int sun3scsi_dma_finish(int write_flag)
{
unsigned short count;
+ unsigned short fifo;
int ret = 0;
- count = sun3scsi_dma_residual(default_instance);
-
sun3_dma_active = 0;
+ // check to empty the fifo on a read
+ if(!write_flag) {
+ int tmo = 200000; /* 2 sec */
+
+ while(1) {
+ if(dregs->csr & CSR_FIFO_EMPTY)
+ break;
+
+ if(--tmo <= 0)
+ return 1;
+
+ udelay(10);
+ }
+ }
+
+
+ count = sun3scsi_dma_count(default_instance);
+#ifdef OLDDMA
+
/* if we've finished a read, copy out the data we read */
if(sun3_dma_orig_addr) {
/* check for residual bytes after dma end */
sun3_dma_orig_addr = NULL;
}
-
+#else
+
+ fifo = dregs->fifo_count;
+ last_residual = fifo;
+
+ /* empty bytes from the fifo which didn't make it */
+ if((!write_flag) && (count - fifo) == 2) {
+ unsigned short data;
+ unsigned char *vaddr;
+
+ data = dregs->fifo_data;
+ vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
+
+ vaddr += (sun3_dma_orig_count - fifo);
+
+ vaddr[-2] = (data & 0xff00) >> 8;
+ vaddr[-1] = (data & 0xff);
+ }
+
+ dvma_unmap(sun3_dma_orig_addr);
+#endif
sun3_udc_write(UDC_RESET, UDC_CSR);
-
+ dregs->fifo_count = 0;
dregs->csr &= ~CSR_SEND;
/* reset fifo */
#include "sun3x_esp.h"
#include <asm/sun3x.h>
#include <asm/dvma.h>
+#include <asm/irq.h>
extern struct NCR_ESP *espchain;
static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
static void dma_drain(struct NCR_ESP *esp);
+static void dma_invalidate(struct NCR_ESP *esp);
static void dma_dump_state(struct NCR_ESP *esp);
static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length);
static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length);
static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
static void dma_advance_sg (Scsi_Cmnd *sp);
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
/* This is where all commands are put
* before they are trasfered to the ESP chip
* via PIO.
/* Optional functions */
esp->dma_barrier = &dma_barrier;
+ esp->dma_invalidate = &dma_invalidate;
esp->dma_drain = &dma_drain;
- esp->dma_irq_entry = &dma_ints_off;
- esp->dma_irq_exit = &dma_ints_on;
+ esp->dma_irq_entry = 0;
+ esp->dma_irq_exit = 0;
esp->dma_led_on = 0;
esp->dma_led_off = 0;
esp->dma_poll = &dma_poll;
esp->eregs = (struct ESP_regs *)(SUN3X_ESP_BASE);
esp->dregs = (void *)SUN3X_ESP_DMA;
- esp->esp_command = (volatile unsigned char *)cmd_buffer;
- esp->esp_command_dvma = dvma_alloc(virt_to_phys(cmd_buffer),
- sizeof (cmd_buffer));
+#if 0
+ esp->esp_command = (volatile unsigned char *)cmd_buffer;
+ esp->esp_command_dvma = dvma_map((unsigned long)cmd_buffer,
+ sizeof (cmd_buffer));
+#else
+ esp->esp_command = (volatile unsigned char *)dvma_malloc(DVMA_PAGE_SIZE);
+ esp->esp_command_dvma = dvma_vtob((unsigned long)esp->esp_command);
+#endif
esp->irq = 2;
if (request_irq(esp->irq, esp_intr, SA_INTERRUPT,
esp_initialize(esp);
+ /* for reasons beyond my knowledge (and which should likely be fixed)
+ sync mode doesn't work on a 3/80 at 5mhz. but it does at 4. */
+ esp->sync_defp = 0x3f;
+
printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps,
esps_in_use);
esps_running = esps_in_use;
return esps_in_use;
}
+static void dma_do_drain(struct NCR_ESP *esp)
+{
+ struct sparc_dma_registers *dregs =
+ (struct sparc_dma_registers *) esp->dregs;
+
+ int count = 500000;
+
+ while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0))
+ udelay(1);
+
+ if(!count) {
+ printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ }
+
+ dregs->cond_reg |= DMA_FIFO_STDRAIN;
+
+ count = 500000;
+
+ while((dregs->cond_reg & DMA_FIFO_ISDRAIN) && (--count > 0))
+ udelay(1);
+
+ if(!count) {
+ printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ }
+
+}
+
static void dma_barrier(struct NCR_ESP *esp)
{
- struct sparc_dma_registers *dregs =
- (struct sparc_dma_registers *) esp->dregs;
-
- while(dregs->cond_reg & DMA_PEND_READ)
- udelay(1);
- dregs->cond_reg &= ~(DMA_ENABLE);
+ struct sparc_dma_registers *dregs =
+ (struct sparc_dma_registers *) esp->dregs;
+ int count = 500000;
+
+ while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0))
+ udelay(1);
+
+ if(!count) {
+ printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ }
+
+ dregs->cond_reg &= ~(DMA_ENABLE);
}
/* This uses various DMA csr fields and the fifo flags count value to
static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
{
- __u32 base, end, sz;
-
- base = ((__u32)sp->SCp.ptr);
- base &= (0x1000000 - 1);
- end = (base + sp->SCp.this_residual);
- if(end > 0x1000000)
- end = 0x1000000;
- sz = (end - base);
- return sz;
+ return sp->SCp.this_residual;
}
static void dma_drain(struct NCR_ESP *esp)
{
struct sparc_dma_registers *dregs =
(struct sparc_dma_registers *) esp->dregs;
+ int count = 500000;
if(dregs->cond_reg & DMA_FIFO_ISDRAIN) {
dregs->cond_reg |= DMA_FIFO_STDRAIN;
- while(dregs->cond_reg & DMA_FIFO_ISDRAIN)
+ while((dregs->cond_reg & DMA_FIFO_ISDRAIN) && (--count > 0))
udelay(1);
+ if(!count) {
+ printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ }
+
}
}
+static void dma_invalidate(struct NCR_ESP *esp)
+{
+ struct sparc_dma_registers *dregs =
+ (struct sparc_dma_registers *) esp->dregs;
+
+ __u32 tmp;
+ int count = 500000;
+
+ while(((tmp = dregs->cond_reg) & DMA_PEND_READ) && (--count > 0))
+ udelay(1);
+
+ if(!count) {
+ printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ }
+
+ dregs->cond_reg = tmp | DMA_FIFO_INV;
+ dregs->cond_reg &= ~DMA_FIFO_INV;
+
+}
+
static void dma_dump_state(struct NCR_ESP *esp)
{
struct sparc_dma_registers *dregs =
(struct sparc_dma_registers *) esp->dregs;
- ESPLOG(("esp%d: dma -- cond_reg<%08lx> addr<%p>\n",
+ ESPLOG(("esp%d: dma -- cond_reg<%08lx> addr<%08lx>\n",
esp->esp_id, dregs->cond_reg, dregs->st_addr));
}
struct sparc_dma_registers *dregs =
(struct sparc_dma_registers *) esp->dregs;
- dregs->cond_reg |= (DMA_ST_WRITE | DMA_ENABLE);
dregs->st_addr = vaddress;
+ dregs->cond_reg |= (DMA_ST_WRITE | DMA_ENABLE);
}
static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length)
(struct sparc_dma_registers *) esp->dregs;
/* Set up the DMA counters */
- dregs->cond_reg = ((dregs->cond_reg & ~(DMA_ST_WRITE)) | DMA_ENABLE);
+
dregs->st_addr = vaddress;
+ dregs->cond_reg = ((dregs->cond_reg & ~(DMA_ST_WRITE)) | DMA_ENABLE);
}
static void dma_ints_off(struct NCR_ESP *esp)
static void dma_poll(struct NCR_ESP *esp, unsigned char *vaddr)
{
- dma_drain(esp);
+ int count = 50;
+ dma_do_drain(esp);
/* Wait till the first bits settle. */
- while(vaddr[0] == 0xff)
+ while((*(volatile unsigned char *)vaddr == 0xff) && (--count > 0))
udelay(1);
+
+ if(!count) {
+// printk("%s:%d timeout expire (data %02x)\n", __FILE__, __LINE__,
+// esp_read(esp->eregs->esp_fdata));
+ //mach_halt();
+ vaddr[0] = esp_read(esp->eregs->esp_fdata);
+ vaddr[1] = esp_read(esp->eregs->esp_fdata);
+ }
+
}
static int dma_ports_p(struct NCR_ESP *esp)
(struct sparc_dma_registers *) esp->dregs;
unsigned long nreg = dregs->cond_reg;
+// printk("dma_setup %c addr %08x cnt %08x\n",
+// write ? 'W' : 'R', addr, count);
+
+ dma_do_drain(esp);
+
if(write)
nreg |= DMA_ST_WRITE;
- else
+ else {
nreg &= ~(DMA_ST_WRITE);
+ }
+
nreg |= DMA_ENABLE;
dregs->cond_reg = nreg;
dregs->st_addr = addr;
static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
{
- sp->SCp.have_data_in = dvma_alloc(virt_to_phys(sp->SCp.buffer),
+ sp->SCp.have_data_in = dvma_map((unsigned long)sp->SCp.buffer,
sp->SCp.this_residual);
sp->SCp.ptr = (char *)((unsigned long)sp->SCp.have_data_in);
}
struct mmu_sglist *sg = (struct mmu_sglist *) sp->SCp.buffer;
while (sz >= 0) {
- sg[sz].dvma_addr = dvma_alloc(virt_to_phys(sg[sz].addr), sg[sz].len);
+ sg[sz].dvma_addr = dvma_map((unsigned long)sg[sz].addr, sg[sz].len);
sz--;
}
sp->SCp.ptr=(char *)((unsigned long)sp->SCp.buffer->dvma_address);
static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
{
- dvma_free(sp->SCp.have_data_in, sp->request_bufflen);
+ dvma_unmap(sp->SCp.have_data_in);
}
static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
struct mmu_sglist *sg = (struct mmu_sglist *)sp->buffer;
while(sz >= 0) {
- dvma_free(sg[sz].dvma_addr,sg[sz].len);
+ dvma_unmap(sg[sz].dvma_addr);
sz--;
}
}
* the driver sets host->wish_block = TRUE for all ISA boards.
*/
+#include <linux/module.h>
#include <linux/version.h>
#ifndef LinuxVersionCode
#define MAX_INT_PARAM 10
-#if defined(MODULE)
-#include <linux/module.h>
-
MODULE_PARM(boot_options, "s");
MODULE_PARM(io_port, "1-" __MODULE_STRING(MAX_INT_PARAM) "i");
MODULE_PARM(linked_comm, "i");
MODULE_PARM(ext_tran, "i");
MODULE_AUTHOR("Dario Ballabio");
-#endif
-
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/kernel.h>
-static inline uchar read_wd33c93(wd33c93_regs *regp,uchar reg_num)
+static inline uchar read_wd33c93(const wd33c93_regs regs, uchar reg_num)
{
- regp->SASR = reg_num;
+ *regs.SASR = reg_num;
mb();
- return(regp->SCMD);
+ return(*regs.SCMD);
}
-#define READ_AUX_STAT() (regp->SASR)
+#define READ_AUX_STAT() (*regs.SASR)
-static inline void write_wd33c93(wd33c93_regs *regp,uchar reg_num, uchar value)
+static inline void write_wd33c93(const wd33c93_regs regs, uchar reg_num,
+ uchar value)
{
- regp->SASR = reg_num;
+ *regs.SASR = reg_num;
mb();
- regp->SCMD = value;
+ *regs.SCMD = value;
mb();
}
-static inline void write_wd33c93_cmd(wd33c93_regs *regp, uchar cmd)
+static inline void write_wd33c93_cmd(const wd33c93_regs regs, uchar cmd)
{
- regp->SASR = WD_COMMAND;
+ *regs.SASR = WD_COMMAND;
mb();
- regp->SCMD = cmd;
+ *regs.SCMD = cmd;
mb();
}
-static inline uchar read_1_byte(wd33c93_regs *regp)
+static inline uchar read_1_byte(const wd33c93_regs regs)
{
uchar asr;
uchar x = 0;
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
- write_wd33c93_cmd(regp, WD_CMD_TRANS_INFO|0x80);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
+ write_wd33c93_cmd(regs, WD_CMD_TRANS_INFO|0x80);
do {
asr = READ_AUX_STAT();
if (asr & ASR_DBR)
- x = read_wd33c93(regp, WD_DATA);
+ x = read_wd33c93(regs, WD_DATA);
} while (!(asr & ASR_INT));
return x;
}
-static void write_wd33c93_count(wd33c93_regs *regp,unsigned long value)
+static void write_wd33c93_count(const wd33c93_regs regs, unsigned long value)
{
- regp->SASR = WD_TRANSFER_COUNT_MSB;
+ *regs.SASR = WD_TRANSFER_COUNT_MSB;
mb();
- regp->SCMD = value >> 16;
- regp->SCMD = value >> 8;
- regp->SCMD = value;
+ *regs.SCMD = value >> 16;
+ *regs.SCMD = value >> 8;
+ *regs.SCMD = value;
mb();
}
-static unsigned long read_wd33c93_count(wd33c93_regs *regp)
+static unsigned long read_wd33c93_count(const wd33c93_regs regs)
{
unsigned long value;
- regp->SASR = WD_TRANSFER_COUNT_MSB;
+ *regs.SASR = WD_TRANSFER_COUNT_MSB;
mb();
- value = regp->SCMD << 16;
- value |= regp->SCMD << 8;
- value |= regp->SCMD;
+ value = *regs.SCMD << 16;
+ value |= *regs.SCMD << 8;
+ value |= *regs.SCMD;
mb();
return value;
}
*/
static void wd33c93_execute (struct Scsi_Host *instance)
{
-struct WD33C93_hostdata *hostdata;
-wd33c93_regs *regp;
+struct WD33C93_hostdata *hostdata = (struct WD33C93_hostdata *)instance->hostdata;
+const wd33c93_regs regs = hostdata->regs;
Scsi_Cmnd *cmd, *prev;
int i;
- hostdata = (struct WD33C93_hostdata *)instance->hostdata;
- regp = hostdata->regp;
-
DB(DB_EXECUTE,printk("EX("))
if (hostdata->selecting || hostdata->connected) {
*/
if (is_dir_out(cmd))
- write_wd33c93(regp, WD_DESTINATION_ID, cmd->target);
+ write_wd33c93(regs, WD_DESTINATION_ID, cmd->target);
else
- write_wd33c93(regp, WD_DESTINATION_ID, cmd->target | DSTID_DPD);
+ write_wd33c93(regs, WD_DESTINATION_ID, cmd->target | DSTID_DPD);
/* Now we need to figure out whether or not this command is a good
* candidate for disconnect/reselect. We guess to the best of our
no:
- write_wd33c93(regp, WD_SOURCE_ID, ((cmd->SCp.phase)?SRCID_ER:0));
+ write_wd33c93(regs, WD_SOURCE_ID, ((cmd->SCp.phase)?SRCID_ER:0));
- write_wd33c93(regp, WD_TARGET_LUN, cmd->lun);
- write_wd33c93(regp,WD_SYNCHRONOUS_TRANSFER,hostdata->sync_xfer[cmd->target]);
+ write_wd33c93(regs, WD_TARGET_LUN, cmd->lun);
+ write_wd33c93(regs, WD_SYNCHRONOUS_TRANSFER,hostdata->sync_xfer[cmd->target]);
hostdata->busy[cmd->target] |= (1 << cmd->lun);
if ((hostdata->level2 == L2_NONE) ||
if (hostdata->sync_stat[cmd->target] == SS_UNSET)
hostdata->sync_stat[cmd->target] = SS_FIRST;
hostdata->state = S_SELECTING;
- write_wd33c93_count(regp,0); /* guarantee a DATA_PHASE interrupt */
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN);
+ write_wd33c93_count(regs, 0); /* guarantee a DATA_PHASE interrupt */
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN);
}
else {
*/
hostdata->connected = cmd;
- write_wd33c93(regp, WD_COMMAND_PHASE, 0);
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0);
/* copy command_descriptor_block into WD chip
* (take advantage of auto-incrementing)
*/
- regp->SASR = WD_CDB_1;
+ *regs.SASR = WD_CDB_1;
for (i=0; i<cmd->cmd_len; i++)
- regp->SCMD = cmd->cmnd[i];
+ *regs.SCMD = cmd->cmnd[i];
/* The wd33c93 only knows about Group 0, 1, and 5 commands when
* it's doing a 'select-and-transfer'. To be safe, we write the
* way there won't be problems with vendor-unique, audio, etc.
*/
- write_wd33c93(regp, WD_OWN_ID, cmd->cmd_len);
+ write_wd33c93(regs, WD_OWN_ID, cmd->cmd_len);
/* When doing a non-disconnect command with DMA, we can save
* ourselves a DATA phase interrupt later by setting everything
if ((cmd->SCp.phase == 0) && (hostdata->no_dma == 0)) {
if (hostdata->dma_setup(cmd,
(is_dir_out(cmd))?DATA_OUT_DIR:DATA_IN_DIR))
- write_wd33c93_count(regp,0); /* guarantee a DATA_PHASE interrupt */
+ write_wd33c93_count(regs, 0); /* guarantee a DATA_PHASE interrupt */
else {
- write_wd33c93_count(regp, cmd->SCp.this_residual);
- write_wd33c93(regp,WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_DMA);
+ write_wd33c93_count(regs, cmd->SCp.this_residual);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_DMA);
hostdata->dma = D_DMA_RUNNING;
}
}
else
- write_wd33c93_count(regp,0); /* guarantee a DATA_PHASE interrupt */
+ write_wd33c93_count(regs, 0); /* guarantee a DATA_PHASE interrupt */
hostdata->state = S_RUNNING_LEVEL2;
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
}
/*
-static void transfer_pio(wd33c93_regs *regp, uchar *buf, int cnt,
- int data_in_dir, struct WD33C93_hostdata *hostdata)
+static void transfer_pio(const wd33c93_regs regs, uchar *buf, int cnt,
+ int data_in_dir, struct WD33C93_hostdata *hostdata)
{
uchar asr;
DB(DB_TRANSFER,printk("(%p,%d,%s:",buf,cnt,data_in_dir?"in":"out"))
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
- write_wd33c93_count(regp,cnt);
- write_wd33c93_cmd(regp, WD_CMD_TRANS_INFO);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
+ write_wd33c93_count(regs, cnt);
+ write_wd33c93_cmd(regs, WD_CMD_TRANS_INFO);
if (data_in_dir) {
do {
asr = READ_AUX_STAT();
if (asr & ASR_DBR)
- *buf++ = read_wd33c93(regp, WD_DATA);
+ *buf++ = read_wd33c93(regs, WD_DATA);
} while (!(asr & ASR_INT));
}
else {
do {
asr = READ_AUX_STAT();
if (asr & ASR_DBR)
- write_wd33c93(regp, WD_DATA, *buf++);
+ write_wd33c93(regs, WD_DATA, *buf++);
} while (!(asr & ASR_INT));
}
-static void transfer_bytes(wd33c93_regs *regp, Scsi_Cmnd *cmd, int data_in_dir)
+static void transfer_bytes(const wd33c93_regs regs, Scsi_Cmnd *cmd,
+ int data_in_dir)
{
struct WD33C93_hostdata *hostdata;
unsigned long length;
cmd->SCp.ptr = cmd->SCp.buffer->address;
}
- write_wd33c93(regp,WD_SYNCHRONOUS_TRANSFER,hostdata->sync_xfer[cmd->target]);
+ write_wd33c93(regs, WD_SYNCHRONOUS_TRANSFER,hostdata->sync_xfer[cmd->target]);
/* 'hostdata->no_dma' is TRUE if we don't even want to try DMA.
* Update 'this_residual' and 'ptr' after 'transfer_pio()' returns.
#ifdef PROC_STATISTICS
hostdata->pio_cnt++;
#endif
- transfer_pio(regp, (uchar *)cmd->SCp.ptr, cmd->SCp.this_residual,
+ transfer_pio(regs, (uchar *)cmd->SCp.ptr, cmd->SCp.this_residual,
data_in_dir, hostdata);
length = cmd->SCp.this_residual;
- cmd->SCp.this_residual = read_wd33c93_count(regp);
+ cmd->SCp.this_residual = read_wd33c93_count(regs);
cmd->SCp.ptr += (length - cmd->SCp.this_residual);
}
#ifdef PROC_STATISTICS
hostdata->dma_cnt++;
#endif
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_DMA);
- write_wd33c93_count(regp,cmd->SCp.this_residual);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_DMA);
+ write_wd33c93_count(regs, cmd->SCp.this_residual);
if ((hostdata->level2 >= L2_DATA) ||
(hostdata->level2 == L2_BASIC && cmd->SCp.phase == 0)) {
- write_wd33c93(regp, WD_COMMAND_PHASE, 0x45);
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0x45);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
hostdata->state = S_RUNNING_LEVEL2;
}
else
- write_wd33c93_cmd(regp, WD_CMD_TRANS_INFO);
+ write_wd33c93_cmd(regs, WD_CMD_TRANS_INFO);
hostdata->dma = D_DMA_RUNNING;
}
void wd33c93_intr (struct Scsi_Host *instance)
{
-struct WD33C93_hostdata *hostdata;
+struct WD33C93_hostdata *hostdata = (struct WD33C93_hostdata *)instance->hostdata;
+const wd33c93_regs regs = hostdata->regs;
Scsi_Cmnd *patch, *cmd;
-wd33c93_regs *regp;
uchar asr, sr, phs, id, lun, *ucp, msg;
unsigned long length, flags;
- hostdata = (struct WD33C93_hostdata *)instance->hostdata;
- regp = hostdata->regp;
-
asr = READ_AUX_STAT();
if (!(asr & ASR_INT) || (asr & ASR_BSY))
return;
#endif
cmd = (Scsi_Cmnd *)hostdata->connected; /* assume we're connected */
- sr = read_wd33c93(regp, WD_SCSI_STATUS); /* clear the interrupt */
- phs = read_wd33c93(regp, WD_COMMAND_PHASE);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS); /* clear the interrupt */
+ phs = read_wd33c93(regs, WD_COMMAND_PHASE);
DB(DB_INTR,printk("{%02x:%02x-",asr,sr))
hostdata->dma_stop(cmd->host, cmd, 1);
hostdata->dma = D_DMA_OFF;
length = cmd->SCp.this_residual;
- cmd->SCp.this_residual = read_wd33c93_count(regp);
+ cmd->SCp.this_residual = read_wd33c93_count(regs);
cmd->SCp.ptr += (length - cmd->SCp.this_residual);
DB(DB_TRANSFER,printk("%p/%d]",cmd->SCp.ptr,cmd->SCp.this_residual))
}
case CSR_UNEXP |PHS_DATA_IN:
case CSR_SRV_REQ |PHS_DATA_IN:
DB(DB_INTR,printk("IN-%d.%d",cmd->SCp.this_residual,cmd->SCp.buffers_residual))
- transfer_bytes(regp, cmd, DATA_IN_DIR);
+ transfer_bytes(regs, cmd, DATA_IN_DIR);
if (hostdata->state != S_RUNNING_LEVEL2)
hostdata->state = S_CONNECTED;
break;
case CSR_UNEXP |PHS_DATA_OUT:
case CSR_SRV_REQ |PHS_DATA_OUT:
DB(DB_INTR,printk("OUT-%d.%d",cmd->SCp.this_residual,cmd->SCp.buffers_residual))
- transfer_bytes(regp, cmd, DATA_OUT_DIR);
+ transfer_bytes(regs, cmd, DATA_OUT_DIR);
if (hostdata->state != S_RUNNING_LEVEL2)
hostdata->state = S_CONNECTED;
break;
case CSR_UNEXP |PHS_COMMAND:
case CSR_SRV_REQ |PHS_COMMAND:
DB(DB_INTR,printk("CMND-%02x,%ld",cmd->cmnd[0],cmd->pid))
- transfer_pio(regp, cmd->cmnd, cmd->cmd_len, DATA_OUT_DIR, hostdata);
+ transfer_pio(regs, cmd->cmnd, cmd->cmd_len, DATA_OUT_DIR, hostdata);
hostdata->state = S_CONNECTED;
break;
case CSR_SRV_REQ |PHS_STATUS:
DB(DB_INTR,printk("STATUS="))
- cmd->SCp.Status = read_1_byte(regp);
+ cmd->SCp.Status = read_1_byte(regs);
DB(DB_INTR,printk("%02x",cmd->SCp.Status))
if (hostdata->level2 >= L2_BASIC) {
- sr = read_wd33c93(regp, WD_SCSI_STATUS); /* clear interrupt */
+ sr = read_wd33c93(regs, WD_SCSI_STATUS); /* clear interrupt */
hostdata->state = S_RUNNING_LEVEL2;
- write_wd33c93(regp, WD_COMMAND_PHASE, 0x50);
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0x50);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
}
else {
hostdata->state = S_CONNECTED;
case CSR_SRV_REQ |PHS_MESS_IN:
DB(DB_INTR,printk("MSG_IN="))
- msg = read_1_byte(regp);
- sr = read_wd33c93(regp, WD_SCSI_STATUS); /* clear interrupt */
+ msg = read_1_byte(regs);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS); /* clear interrupt */
hostdata->incoming_msg[hostdata->incoming_ptr] = msg;
if (hostdata->incoming_msg[0] == EXTENDED_MESSAGE)
case COMMAND_COMPLETE:
DB(DB_INTR,printk("CCMP-%ld",cmd->pid))
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_PRE_CMP_DISC;
break;
case SAVE_POINTERS:
DB(DB_INTR,printk("SDP"))
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
break;
case RESTORE_POINTERS:
DB(DB_INTR,printk("RDP"))
if (hostdata->level2 >= L2_BASIC) {
- write_wd33c93(regp, WD_COMMAND_PHASE, 0x45);
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0x45);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
hostdata->state = S_RUNNING_LEVEL2;
}
else {
- write_wd33c93_cmd(regp, WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
}
break;
case DISCONNECT:
DB(DB_INTR,printk("DIS"))
cmd->device->disconnect = 1;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_PRE_TMP_DISC;
break;
#endif
if (hostdata->sync_stat[cmd->target] == SS_WAITING)
hostdata->sync_stat[cmd->target] = SS_SET;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
break;
* specifically ask for sync transfers, we won't do any.
*/
- write_wd33c93_cmd(regp,WD_CMD_ASSERT_ATN); /* want MESS_OUT */
+ write_wd33c93_cmd(regs, WD_CMD_ASSERT_ATN); /* want MESS_OUT */
hostdata->outgoing_msg[0] = EXTENDED_MESSAGE;
hostdata->outgoing_msg[1] = 3;
hostdata->outgoing_msg[2] = EXTENDED_SDTR;
printk("sync_xfer=%02x",hostdata->sync_xfer[cmd->target]);
#endif
hostdata->sync_stat[cmd->target] = SS_SET;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
break;
case EXTENDED_WDTR:
- write_wd33c93_cmd(regp,WD_CMD_ASSERT_ATN); /* want MESS_OUT */
+ write_wd33c93_cmd(regs, WD_CMD_ASSERT_ATN); /* want MESS_OUT */
printk("sending WDTR ");
hostdata->outgoing_msg[0] = EXTENDED_MESSAGE;
hostdata->outgoing_msg[1] = 2;
hostdata->outgoing_msg[2] = EXTENDED_WDTR;
hostdata->outgoing_msg[3] = 0; /* 8 bit transfer width */
hostdata->outgoing_len = 4;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
break;
default:
- write_wd33c93_cmd(regp,WD_CMD_ASSERT_ATN); /* want MESS_OUT */
+ write_wd33c93_cmd(regs, WD_CMD_ASSERT_ATN); /* want MESS_OUT */
printk("Rejecting Unknown Extended Message(%02x). ",ucp[2]);
hostdata->outgoing_msg[0] = MESSAGE_REJECT;
hostdata->outgoing_len = 1;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
break;
}
else {
hostdata->incoming_ptr++;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
}
break;
default:
printk("Rejecting Unknown Message(%02x) ",msg);
- write_wd33c93_cmd(regp,WD_CMD_ASSERT_ATN); /* want MESS_OUT */
+ write_wd33c93_cmd(regs, WD_CMD_ASSERT_ATN); /* want MESS_OUT */
hostdata->outgoing_msg[0] = MESSAGE_REJECT;
hostdata->outgoing_len = 1;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
hostdata->state = S_CONNECTED;
}
restore_flags(flags);
* have been turned off for the command that just completed.
*/
- write_wd33c93(regp,WD_SOURCE_ID, SRCID_ER);
+ write_wd33c93(regs, WD_SOURCE_ID, SRCID_ER);
if (phs == 0x60) {
DB(DB_INTR,printk("SX-DONE-%ld",cmd->pid))
cmd->SCp.Message = COMMAND_COMPLETE;
- lun = read_wd33c93(regp, WD_TARGET_LUN);
+ lun = read_wd33c93(regs, WD_TARGET_LUN);
DB(DB_INTR,printk(":%d.%d",cmd->SCp.Status,lun))
hostdata->connected = NULL;
hostdata->busy[cmd->target] &= ~(1 << cmd->lun);
case CSR_SDP:
DB(DB_INTR,printk("SDP"))
hostdata->state = S_RUNNING_LEVEL2;
- write_wd33c93(regp, WD_COMMAND_PHASE, 0x41);
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0x41);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
break;
hostdata->outgoing_len = 1;
hostdata->outgoing_msg[0] = NOP;
}
- transfer_pio(regp, hostdata->outgoing_msg, hostdata->outgoing_len,
+ transfer_pio(regs, hostdata->outgoing_msg, hostdata->outgoing_len,
DATA_OUT_DIR, hostdata);
DB(DB_INTR,printk("%02x",hostdata->outgoing_msg[0]))
hostdata->outgoing_len = 0;
* have been turned off for the command that just completed.
*/
- write_wd33c93(regp,WD_SOURCE_ID, SRCID_ER);
+ write_wd33c93(regs, WD_SOURCE_ID, SRCID_ER);
if (cmd == NULL) {
printk(" - Already disconnected! ");
hostdata->state = S_UNCONNECTED;
* have been turned off for the command that just completed.
*/
- write_wd33c93(regp,WD_SOURCE_ID, SRCID_ER);
+ write_wd33c93(regs, WD_SOURCE_ID, SRCID_ER);
DB(DB_INTR,printk("DISC-%ld",cmd->pid))
if (cmd == NULL) {
printk(" - Already disconnected! ");
/* OK - find out which device reselected us. */
- id = read_wd33c93(regp, WD_SOURCE_ID);
+ id = read_wd33c93(regs, WD_SOURCE_ID);
id &= SRCID_MASK;
/* and extract the lun from the ID message. (Note that we don't
*/
if (sr == CSR_RESEL_AM) {
- lun = read_wd33c93(regp, WD_DATA);
+ lun = read_wd33c93(regs, WD_DATA);
if (hostdata->level2 < L2_RESELECT)
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
lun &= 7;
}
else {
}
else {
/* Verify this is a change to MSG_IN and read the message */
- sr = read_wd33c93(regp, WD_SCSI_STATUS);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS);
if (sr == (CSR_ABORT | PHS_MESS_IN) ||
sr == (CSR_UNEXP | PHS_MESS_IN) ||
sr == (CSR_SRV_REQ | PHS_MESS_IN)) {
/* Got MSG_IN, grab target LUN */
- lun = read_1_byte(regp);
+ lun = read_1_byte(regs);
/* Now we expect a 'paused with ACK asserted' int.. */
asr = READ_AUX_STAT();
if (!(asr & ASR_INT)) {
printk("wd33c93: No int after LUN on RESEL (%02x)\n",
asr);
}
- sr = read_wd33c93(regp, WD_SCSI_STATUS);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS);
if (sr != CSR_MSGIN)
printk("wd33c93: Not paused with ACK on RESEL (%02x)\n",
sr);
lun &= 7;
- write_wd33c93_cmd(regp,WD_CMD_NEGATE_ACK);
+ write_wd33c93_cmd(regs, WD_CMD_NEGATE_ACK);
}
else {
printk("wd33c93: Not MSG_IN on reselect (%02x)\n", sr);
*/
if (is_dir_out(cmd))
- write_wd33c93(regp, WD_DESTINATION_ID, cmd->target);
+ write_wd33c93(regs, WD_DESTINATION_ID, cmd->target);
else
- write_wd33c93(regp, WD_DESTINATION_ID, cmd->target | DSTID_DPD);
+ write_wd33c93(regs, WD_DESTINATION_ID, cmd->target | DSTID_DPD);
if (hostdata->level2 >= L2_RESELECT) {
- write_wd33c93_count(regp, 0); /* we want a DATA_PHASE interrupt */
- write_wd33c93(regp, WD_COMMAND_PHASE, 0x45);
- write_wd33c93_cmd(regp, WD_CMD_SEL_ATN_XFER);
+ write_wd33c93_count(regs, 0); /* we want a DATA_PHASE interrupt */
+ write_wd33c93(regs, WD_COMMAND_PHASE, 0x45);
+ write_wd33c93_cmd(regs, WD_CMD_SEL_ATN_XFER);
hostdata->state = S_RUNNING_LEVEL2;
}
else
static void reset_wd33c93(struct Scsi_Host *instance)
{
-struct WD33C93_hostdata *hostdata;
-wd33c93_regs *regp;
+struct WD33C93_hostdata *hostdata = (struct WD33C93_hostdata *)instance->hostdata;
+const wd33c93_regs regs = hostdata->regs;
uchar sr;
- hostdata = (struct WD33C93_hostdata *)instance->hostdata;
- regp = hostdata->regp;
-
- write_wd33c93(regp, WD_OWN_ID, OWNID_EAF | OWNID_RAF |
+ write_wd33c93(regs, WD_OWN_ID, OWNID_EAF | OWNID_RAF |
instance->this_id | hostdata->clock_freq);
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
- write_wd33c93(regp, WD_SYNCHRONOUS_TRANSFER,
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
+ write_wd33c93(regs, WD_SYNCHRONOUS_TRANSFER,
calc_sync_xfer(hostdata->default_sx_per/4,DEFAULT_SX_OFF));
- write_wd33c93(regp, WD_COMMAND, WD_CMD_RESET);
+ write_wd33c93(regs, WD_COMMAND, WD_CMD_RESET);
#ifdef CONFIG_MVME147_SCSI
udelay(25); /* The old wd33c93 on MVME147 needs this, at least */
#endif
while (!(READ_AUX_STAT() & ASR_INT))
;
- sr = read_wd33c93(regp, WD_SCSI_STATUS);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS);
- hostdata->microcode = read_wd33c93(regp, WD_CDB_1);
+ hostdata->microcode = read_wd33c93(regs, WD_CDB_1);
if (sr == 0x00)
hostdata->chip = C_WD33C93;
else if (sr == 0x01) {
- write_wd33c93(regp, WD_QUEUE_TAG, 0xa5); /* any random number */
- sr = read_wd33c93(regp, WD_QUEUE_TAG);
+ write_wd33c93(regs, WD_QUEUE_TAG, 0xa5); /* any random number */
+ sr = read_wd33c93(regs, WD_QUEUE_TAG);
if (sr == 0xa5) {
hostdata->chip = C_WD33C93B;
- write_wd33c93(regp, WD_QUEUE_TAG, 0);
+ write_wd33c93(regs, WD_QUEUE_TAG, 0);
}
else
hostdata->chip = C_WD33C93A;
else
hostdata->chip = C_UNKNOWN_CHIP;
- write_wd33c93(regp, WD_TIMEOUT_PERIOD, TIMEOUT_PERIOD_VALUE);
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
+ write_wd33c93(regs, WD_TIMEOUT_PERIOD, TIMEOUT_PERIOD_VALUE);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
}
{
struct Scsi_Host *instance;
struct WD33C93_hostdata *hostdata;
-wd33c93_regs *regp;
+wd33c93_regs regs;
Scsi_Cmnd *tmp, *prev;
disable_irq(cmd->host->irq);
instance = cmd->host;
hostdata = (struct WD33C93_hostdata *)instance->hostdata;
- regp = hostdata->regp;
+ regs = hostdata->regs;
/*
* Case 1 : If the command hasn't been issued yet, we simply remove it
}
printk("sending wd33c93 ABORT command - ");
- write_wd33c93(regp, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
- write_wd33c93_cmd(regp, WD_CMD_ABORT);
+ write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
+ write_wd33c93_cmd(regs, WD_CMD_ABORT);
/* Now we have to attempt to flush out the FIFO... */
do {
asr = READ_AUX_STAT();
if (asr & ASR_DBR)
- read_wd33c93(regp, WD_DATA);
+ read_wd33c93(regs, WD_DATA);
} while (!(asr & ASR_INT) && timeout-- > 0);
- sr = read_wd33c93(regp, WD_SCSI_STATUS);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS);
printk("asr=%02x, sr=%02x, %ld bytes un-transferred (timeout=%ld) - ",
- asr, sr, read_wd33c93_count(regp), timeout);
+ asr, sr, read_wd33c93_count(regs), timeout);
/*
* Abort command processed.
*/
printk("sending wd33c93 DISCONNECT command - ");
- write_wd33c93_cmd(regp, WD_CMD_DISCONNECT);
+ write_wd33c93_cmd(regs, WD_CMD_DISCONNECT);
timeout = 1000000;
asr = READ_AUX_STAT();
while ((asr & ASR_CIP) && timeout-- > 0)
asr = READ_AUX_STAT();
- sr = read_wd33c93(regp, WD_SCSI_STATUS);
+ sr = read_wd33c93(regs, WD_SCSI_STATUS);
printk("asr=%02x, sr=%02x.",asr,sr);
hostdata->busy[cmd->target] &= ~(1 << cmd->lun);
-void wd33c93_init (struct Scsi_Host *instance, wd33c93_regs *regs,
- dma_setup_t setup, dma_stop_t stop, int clock_freq)
+void wd33c93_init(struct Scsi_Host *instance, const wd33c93_regs regs,
+ dma_setup_t setup, dma_stop_t stop, int clock_freq)
{
struct WD33C93_hostdata *hostdata;
int i;
hostdata = (struct WD33C93_hostdata *)instance->hostdata;
- hostdata->regp = regs;
+ hostdata->regs = regs;
hostdata->clock_freq = clock_freq;
hostdata->dma_setup = setup;
hostdata->dma_stop = stop;
#ifdef MODULE
int init_module(void) { return 0; }
void cleanup_module(void) {}
+#endif
void wd33c93_release(void)
{
-MOD_DEC_USE_COUNT;
+ MOD_DEC_USE_COUNT;
}
-#endif
/* This is what the 3393 chip looks like to us */
typedef struct {
- volatile unsigned char SASR;
-#if !defined(CONFIG_MVME147_SCSI)
- char pad;
-#endif
-#ifdef CONFIG_SGI_IP22
- char pad2,pad3;
-#endif
- volatile unsigned char SCMD;
+ volatile unsigned char *SASR;
+ volatile unsigned char *SCMD;
} wd33c93_regs;
struct WD33C93_hostdata {
struct Scsi_Host *next;
- wd33c93_regs *regp;
+ wd33c93_regs regs;
uchar clock_freq;
uchar chip; /* what kind of wd33c93? */
uchar microcode; /* microcode rev */
#define PR_STOP 1<<7
-void wd33c93_init (struct Scsi_Host *instance, wd33c93_regs *regs,
+void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
dma_setup_t setup, dma_stop_t stop, int clock_freq);
int wd33c93_abort (Scsi_Cmnd *cmd);
int wd33c93_queuecommand (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
module_init(dmasound_atari_init);
module_exit(dmasound_atari_cleanup);
+MODULE_LICENSE("GPL");
module_init(dmasound_awacs_init);
module_exit(dmasound_awacs_cleanup);
+MODULE_LICENSE("GPL");
MODULE_PARM(writeBufSize, "i");
MODULE_PARM(numReadBufs, "i");
MODULE_PARM(readBufSize, "i");
+MODULE_LICENSE("GPL");
#ifdef MODULE
static int sq_unit = -1;
module_init(dmasound_paula_init);
module_exit(dmasound_paula_cleanup);
+MODULE_LICENSE("GPL");
module_init(dmasound_q40_init);
module_exit(dmasound_q40_cleanup);
+MODULE_LICENSE("GPL");
#include <linux/soundcard.h>
#include <linux/ac97_codec.h>
#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <asm/io.h>
#include "efxmgr.h"
#include "passthrough.h"
MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
+#ifdef CONFIG_PM
+#define PM_SUSPENDED(card) (card->pm_suspended)
+#else
+#define PM_SUSPENDED(card) (0)
+#endif
+
/* "software" or virtual channel, an instance of opened /dev/dsp */
struct i810_state {
unsigned int magic;
/* virtual channel number */
int virt;
+#ifdef CONFIG_PM
+ unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
+#endif
struct dmabuf {
/* wave sample stuff */
unsigned int rate;
/* PCI device stuff */
struct pci_dev * pci_dev;
u16 pci_id;
-
+#ifdef CONFIG_PM
+ u16 pm_suspended;
+ u32 pm_save_state[64/sizeof(u32)];
+ int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
+#endif
/* soundcore stuff */
int dev_audio;
if(!(state->card->ac97_features & 4)) {
#ifdef DEBUG
- printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
+ printk(KERN_WARNING "i810_audio: S/PDIF transmitter not available.\n");
#endif
state->card->ac97_status &= ~SPDIF_ON;
} else {
if(!(state->card->ac97_features&0x0001))
{
dmabuf->rate = clocking;
+#ifdef DEBUG
+ printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n",
+ rate,clocking);
+#endif
return clocking;
}
if(new_rate != rate) {
dmabuf->rate = (new_rate * 48000)/clocking;
- rate = new_rate;
}
#ifdef DEBUG
- printk("i810_audio: called i810_set_dac_rate : rate = %d/%d\n", dmabuf->rate, rate);
+ printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
#endif
+ rate = new_rate;
return dmabuf->rate;
}
for (;;) {
/* It seems that we have to set the current state to TASK_INTERRUPTIBLE
every time to make the process really go to sleep */
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
spin_lock_irqsave(&state->card->lock, flags);
i810_update_ptr(state);
if (nonblock) {
remove_wait_queue(&dmabuf->wait, &wait);
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
return -EBUSY;
}
stop_dac(state);
synchronize_irq();
remove_wait_queue(&dmabuf->wait, &wait);
- current->state = TASK_RUNNING;
+ set_current_state(TASK_RUNNING);
if (signal_pending(current))
return -ERESTARTSYS;
spin_unlock(&card->lock);
}
-/* in this loop, dmabuf.count signifies the amount of data that is waiting to be copied to
- the user's buffer. it is filled by the dma machine and drained by this loop. */
+/* in this loop, dmabuf.count signifies the amount of data that is
+ waiting to be copied to the user's buffer. It is filled by the dma
+ machine and drained by this loop. */
+
static ssize_t i810_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
{
struct i810_state *state = (struct i810_state *)file->private_data;
+ struct i810_card *card=state ? state->card : 0;
struct dmabuf *dmabuf = &state->dmabuf;
ssize_t ret;
unsigned long flags;
unsigned int swptr;
int cnt;
+ DECLARE_WAITQUEUE(waita, current);
#ifdef DEBUG2
printk("i810_audio: i810_read called, count = %d\n", count);
return -ENODEV;
if (!dmabuf->read_channel) {
dmabuf->ready = 0;
- dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
+ dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
if (!dmabuf->read_channel) {
return -EBUSY;
}
dmabuf->trigger &= ~PCM_ENABLE_OUTPUT;
ret = 0;
+ add_wait_queue(&dmabuf->wait, &waita);
while (count > 0) {
- spin_lock_irqsave(&state->card->lock, flags);
+ spin_lock_irqsave(&card->lock, flags);
+ if (PM_SUSPENDED(card)) {
+ spin_unlock_irqrestore(&card->lock, flags);
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule();
+ if (signal_pending(current)) {
+ if (!ret) ret = -EAGAIN;
+ break;
+ }
+ continue;
+ }
swptr = dmabuf->swptr;
if (dmabuf->count > dmabuf->dmasize) {
dmabuf->count = dmabuf->dmasize;
// this is to make the copy_to_user simpler below
if(cnt > (dmabuf->dmasize - swptr))
cnt = dmabuf->dmasize - swptr;
- spin_unlock_irqrestore(&state->card->lock, flags);
+ spin_unlock_irqrestore(&card->lock, flags);
if (cnt > count)
cnt = count;
if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
if (!ret) ret = -EFAULT;
- return ret;
+ goto done;
}
swptr = (swptr + cnt) % dmabuf->dmasize;
- spin_lock_irqsave(&state->card->lock, flags);
+ spin_lock_irqsave(&card->lock, flags);
+
+ if (PM_SUSPENDED(card)) {
+ spin_unlock_irqrestore(&card->lock, flags);
+ continue;
+ }
dmabuf->swptr = swptr;
dmabuf->count -= cnt;
- spin_unlock_irqrestore(&state->card->lock, flags);
+ spin_unlock_irqrestore(&card->lock, flags);
count -= cnt;
buffer += cnt;
i810_update_lvi(state,1);
if(!(dmabuf->enable & ADC_RUNNING))
start_adc(state);
+ done:
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&dmabuf->wait, &waita);
+
return ret;
}
static ssize_t i810_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
{
struct i810_state *state = (struct i810_state *)file->private_data;
+ struct i810_card *card=state ? state->card : 0;
struct dmabuf *dmabuf = &state->dmabuf;
ssize_t ret;
unsigned long flags;
unsigned int swptr = 0;
int cnt, x;
+ DECLARE_WAITQUEUE(waita, current);
#ifdef DEBUG2
printk("i810_audio: i810_write called, count = %d\n", count);
return -ENODEV;
if (!dmabuf->write_channel) {
dmabuf->ready = 0;
- dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
+ dmabuf->write_channel = card->alloc_pcm_channel(card);
if(!dmabuf->write_channel)
return -EBUSY;
}
dmabuf->trigger &= ~PCM_ENABLE_INPUT;
ret = 0;
+ add_wait_queue(&dmabuf->wait, &waita);
while (count > 0) {
spin_lock_irqsave(&state->card->lock, flags);
+ if (PM_SUSPENDED(card)) {
+ spin_unlock_irqrestore(&card->lock, flags);
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule();
+ if (signal_pending(current)) {
+ if (!ret) ret = -EAGAIN;
+ break;
+ }
+ continue;
+ }
+
swptr = dmabuf->swptr;
if (dmabuf->count < 0) {
dmabuf->count = 0;
i810_update_lvi(state,0);
if (file->f_flags & O_NONBLOCK) {
if (!ret) ret = -EAGAIN;
- return ret;
+ goto ret;
}
/* Not strictly correct but works */
tmo = (dmabuf->dmasize * HZ) / (dmabuf->rate * 4);
}
if (signal_pending(current)) {
if (!ret) ret = -ERESTARTSYS;
- return ret;
+ goto ret;
}
continue;
}
if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
if (!ret) ret = -EFAULT;
- return ret;
+ goto ret;
}
swptr = (swptr + cnt) % dmabuf->dmasize;
spin_lock_irqsave(&state->card->lock, flags);
+ if (PM_SUSPENDED(card)) {
+ spin_unlock_irqrestore(&card->lock, flags);
+ continue;
+ }
+
dmabuf->swptr = swptr;
dmabuf->count += cnt;
- spin_unlock_irqrestore(&state->card->lock, flags);
count -= cnt;
buffer += cnt;
ret += cnt;
+ spin_unlock_irqrestore(&state->card->lock, flags);
}
if (swptr % dmabuf->fragsize) {
x = dmabuf->fragsize - (swptr % dmabuf->fragsize);
i810_update_lvi(state,0);
if (!dmabuf->enable && dmabuf->count >= dmabuf->userfragsize)
start_dac(state);
+ ret:
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&dmabuf->wait, &waita);
return ret;
}
open: i810_open_mixdev,
};
-/* AC97 codec initialisation. */
-static int __init i810_ac97_init(struct i810_card *card)
+/* AC97 codec initialisation. These small functions exist so we don't
+ duplicate code between module init and apm resume */
+
+static inline int i810_ac97_exists(struct i810_card *card,int ac97_number)
{
- int num_ac97 = 0;
- int total_channels = 0;
- struct ac97_codec *codec;
- u16 eid;
- int i=0;
- u32 reg;
+ u32 reg = inl(card->iobase + GLOB_STA);
+ return (reg & (0x100 << ac97_number));
+}
- reg = inl(card->iobase + GLOB_CNT);
+static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
+{
+ i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
+ i810_ac97_set(codec,AC97_EXTENDED_STATUS,
+ i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
+ return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
+}
+
+
+static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
+{
+ /* Returns 0 on failure */
+ int i;
+
+ if (ac97_probe_codec(codec) == 0) return 0;
+
+ /* power it all up */
+ i810_ac97_set(codec, AC97_POWER_CONTROL,
+ i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
+ /* wait for analog ready */
+ for (i=10;
+ i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf);
+ i--)
+ {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ/20);
+ }
+ return i;
+}
+
+/* if I knew what this did, I'd give it a better name */
+static int i810_ac97_random_init_stuff(struct i810_card *card)
+{
+ u32 reg = inl(card->iobase + GLOB_CNT);
+ int i;
+
if((reg&2)==0) /* Cold required */
reg|=2;
else
reg&=~8; /* ACLink on */
outl(reg , card->iobase + GLOB_CNT);
- while(i<10)
+ for(i=0;i<10;i++)
{
if((inl(card->iobase+GLOB_CNT)&4)==0)
break;
- current->state = TASK_UNINTERRUPTIBLE;
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ/20);
- i++;
}
if(i==10)
{
return 0;
}
- current->state = TASK_UNINTERRUPTIBLE;
- schedule_timeout(HZ/5);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ/2);
+ reg = inl(card->iobase + GLOB_STA);
+ inw(card->ac97base);
+ return 1;
+}
+
+static int __init i810_ac97_init(struct i810_card *card)
+{
+ int num_ac97 = 0;
+ int total_channels = 0;
+ struct ac97_codec *codec;
+ u16 eid;
+ u32 reg;
+
+ if(!i810_ac97_random_init_stuff(card)) return 0;
/* Number of channels supported */
/* What about the codec? Just because the ICH supports */
/* check the ready status before probing. So we chk */
/* What do we do if it's not ready? Wait and try */
/* again, or abort? */
- reg = inl(card->iobase + GLOB_STA);
- if (!(reg & (0x100 << num_ac97))) {
+ if (!i810_ac97_exists(card,num_ac97)) {
if(num_ac97 == 0)
printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
+ card->ac97_codec[num_ac97] = 0;
break; /* I think this works, if not ready stop */
}
codec->codec_read = i810_ac97_get;
codec->codec_write = i810_ac97_set;
- if (ac97_probe_codec(codec) == 0)
- break;
-
- /* power up everything, modify this when implementing power saving */
- i810_ac97_set(codec, AC97_POWER_CONTROL,
- i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
- /* wait for analog ready */
- for (i=10;
- i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf);
- i--)
- {
- current->state = TASK_UNINTERRUPTIBLE;
- schedule_timeout(HZ/20);
+ if(!i810_ac97_probe_and_powerup(card,codec)) {
+ printk("i810_audio: timed out waiting for codec %d analog ready", num_ac97);
+ break; /* it didn't work */
}
-
/* Store state information about S/PDIF transmitter */
card->ac97_status = 0;
-
+
/* Don't attempt to get eid until powerup is complete */
eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
else
{
- /* Enable variable rate mode */
- i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
- i810_ac97_set(codec,AC97_EXTENDED_STATUS,
- i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
-
- if(!(i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1))
- {
+ if(!i810_ac97_enable_variable_rate(codec)) {
printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
card->ac97_features&=~1;
- }
+ }
}
/* Determine how many channels the codec(s) support */
card->irq = pci_dev->irq;
card->next = devs;
card->magic = I810_CARD_MAGIC;
+#ifdef CONFIG_PM
+ card->pm_suspended=0;
+#endif
spin_lock_init(&card->lock);
devs = card;
kfree(card);
}
+#ifdef CONFIG_PM
+static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state)
+{
+ struct i810_card *card = dev->driver_data;
+ struct i810_state *state;
+ unsigned long flags;
+ struct dmabuf *dmabuf;
+ int i,num_ac97;
+#ifdef DEBUG
+ printk("i810_audio: i810_pm_suspend called\n");
+#endif
+ if(!card) return 0;
+ spin_lock_irqsave(&card->lock, flags);
+ card->pm_suspended=1;
+ for(i=0;i<NR_HW_CH;i++) {
+ state = card->states[i];
+ if(!state) continue;
+ /* this happens only if there are open files */
+ dmabuf = &state->dmabuf;
+ if(dmabuf->enable & DAC_RUNNING ||
+ (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
+ state->pm_saved_dac_rate=dmabuf->rate;
+ stop_dac(state);
+ } else {
+ state->pm_saved_dac_rate=0;
+ }
+ if(dmabuf->enable & ADC_RUNNING) {
+ state->pm_saved_adc_rate=dmabuf->rate;
+ stop_adc(state);
+ } else {
+ state->pm_saved_adc_rate=0;
+ }
+ dmabuf->ready = 0;
+ dmabuf->swptr = dmabuf->hwptr = 0;
+ dmabuf->count = dmabuf->total_bytes = 0;
+ }
+
+ spin_unlock_irqrestore(&card->lock, flags);
+
+ /* save mixer settings */
+ for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
+ struct ac97_codec *codec = card->ac97_codec[num_ac97];
+ if(!codec) continue;
+ for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
+ if((supported_mixer(codec,i)) &&
+ (codec->read_mixer)) {
+ card->pm_saved_mixer_settings[i][num_ac97]=
+ codec->read_mixer(codec,i);
+ }
+ }
+ }
+ pci_save_state(dev,card->pm_save_state); /* XXX do we need this? */
+ pci_disable_device(dev); /* disable busmastering */
+ pci_set_power_state(dev,3); /* Zzz. */
+
+ return 0;
+}
+
+
+static int i810_pm_resume(struct pci_dev *dev)
+{
+ int num_ac97,i=0;
+ struct i810_card *card=(struct i810_card *)dev->driver_data;
+ pci_enable_device(dev);
+ pci_restore_state (dev,card->pm_save_state);
+
+ /* observation of a toshiba portege 3440ct suggests that the
+ hardware has to be more or less completely reinitialized from
+ scratch after an apm suspend. Works For Me. -dan */
+
+ i810_ac97_random_init_stuff(card);
+
+ for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
+ struct ac97_codec *codec = card->ac97_codec[num_ac97];
+ /* check they haven't stolen the hardware while we were
+ away */
+ if(!i810_ac97_exists(card,num_ac97)) {
+ if(num_ac97) continue;
+ else BUG();
+ }
+ if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
+
+ if((card->ac97_features&0x0001)) {
+ /* at probe time we found we could do variable
+ rates, but APM suspend has made it forget
+ its magical powers */
+ if(!i810_ac97_enable_variable_rate(codec)) BUG();
+ }
+ /* we lost our mixer settings, so restore them */
+ for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
+ if(supported_mixer(codec,i)){
+ int val=card->
+ pm_saved_mixer_settings[i][num_ac97];
+ codec->mixer_state[i]=val;
+ codec->write_mixer(codec,i,
+ (val & 0xff) ,
+ ((val >> 8) & 0xff) );
+ }
+ }
+ }
+
+ /* we need to restore the sample rate from whatever it was */
+ for(i=0;i<NR_HW_CH;i++) {
+ struct i810_state * state=card->states[i];
+ if(state) {
+ if(state->pm_saved_adc_rate)
+ i810_set_adc_rate(state,state->pm_saved_adc_rate);
+ if(state->pm_saved_dac_rate)
+ i810_set_dac_rate(state,state->pm_saved_dac_rate);
+ }
+ }
+
+
+ card->pm_suspended = 0;
+
+ /* any processes that were reading/writing during the suspend
+ probably ended up here */
+ for(i=0;i<NR_HW_CH;i++) {
+ struct i810_state *state = card->states[i];
+ if(state) wake_up(&state->dmabuf.wait);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_PM */
MODULE_AUTHOR("");
MODULE_DESCRIPTION("Intel 810 audio support");
id_table: i810_pci_tbl,
probe: i810_probe,
remove: i810_remove,
+#ifdef CONFIG_PM
+ suspend: i810_pm_suspend,
+ resume: i810_pm_resume,
+#endif /* CONFIG_PM */
};
module_init(i810_init_module);
module_exit(i810_cleanup_module);
+
+/*
+Local Variables:
+c-basic-offset: 8
+End:
+*/
MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
MODULE_DESCRIPTION("IT8172 AudioPCI97 Driver");
+MODULE_LICENSE("GPL");
/* --------------------------------------------------------------------- */
MODULE_AUTHOR("Monta Vista Software, jsun@mvista.com or jsun@junsun.net");
MODULE_DESCRIPTION("NEC Vrc5477 audio (AC97) Driver");
+MODULE_LICENSE("GPL");
/* --------------------------------------------------------------------- */
extern void jsun_scan_pci_bus(void);
#include <linux/soundcard.h>
#include <linux/pci.h>
#include <linux/smp_lock.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
#include <asm/dma.h>
#include <linux/init.h>
#include <linux/poll.h>
*speedp = speed1;
retval = 1;
} else {
- *divp = div2;
+ /* *divp = div2; */
+ *divp = 0x80 | div2;
*speedp = speed2;
retval = 2;
}
/*
* The 0x80 is important for the first audio channel
*/
- div = 0x80 | ess_calc_div (795500, 128, speedp, &diff);
+ if (devc->submodel == SUBMDL_ES1888) {
+ div = 0x80 | ess_calc_div (795500, 256, speedp, &diff);
+ } else {
+ div = 0x80 | ess_calc_div (795500, 128, speedp, &diff);
+ }
} else if(devc->caps & SB_CAP_ES18XX_RATE) {
- ess_calc_best_speed(ES18XX_CLOCK1, 128, ES18XX_CLOCK2, 256,
+ if (devc->submodel == SUBMDL_ES1888) {
+ ess_calc_best_speed(397700, 128, 795500, 256,
&div, speedp);
+ } else {
+ ess_calc_best_speed(ES18XX_CLOCK1, 128, ES18XX_CLOCK2, 256,
+ &div, speedp);
+ }
} else {
if (*speedp > 22000) {
div = 0x80 | ess_calc_div (ES1688_CLOCK1, 256, speedp, &diff);
if ((hwrpb->sys_type) == 201) {
printk(KERN_INFO "trident: Running on Alpha system type Nautilus\n");
ac97_data = ali_ac97_get(card, 0, AC97_POWER_CONTROL);
- ali_ac97_set(card, 0, AC97_POWER_CONTROL, ac97_data |
+ ali_ac97_set(card, 0, AC97_POWER_CONTROL, ac97_data | ALI_EAPD_POWER_DOWN);
}
}
#endif
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
-#include <linux/smp.h>
#include <linux/spinlock.h>
+#include <linux/bitops.h>
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
#include <asm/system.h>
#include "sound_config.h"
#include "waveartist.h"
-#ifndef _ISA_DMA
-#define _ISA_DMA(x) (x)
-#endif
-#ifndef _ISA_IRQ
-#define _ISA_IRQ(x) (x)
+#ifdef CONFIG_ARM
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
#endif
-#define POSSIBLE_RECORDING_DEVICES (SOUND_MASK_LINE |\
- SOUND_MASK_MIC |\
- SOUND_MASK_LINE1)
+#ifndef NO_DMA
+#define NO_DMA 255
+#endif
#define SUPPORTED_MIXER_DEVICES (SOUND_MASK_SYNTH |\
SOUND_MASK_PCM |\
0x0000, /* Treble */
0x2323, /* Synth (FM) */
0x4b4b, /* PCM */
- 0x0000, /* PC Speaker */
+ 0x6464, /* PC Speaker */
0x0000, /* Ext Line */
0x0000, /* Mic */
0x0000, /* CD */
- 0x0000, /* Recording monitor */
+ 0x6464, /* Recording monitor */
0x0000, /* SB PCM (ALT PCM) */
0x0000, /* Recording level */
- 0x0000, /* Input gain */
- 0x0000, /* Output gain */
+ 0x6464, /* Input gain */
+ 0x6464, /* Output gain */
0x0000, /* Line1 (Aux1) */
0x0000, /* Line2 (Aux2) */
0x0000, /* Line3 (Aux3) */
0x0000, /* Digital2 */
0x0000, /* Digital3 */
0x0000, /* Phone In */
- 0x0000, /* Phone Out */
+ 0x6464, /* Phone Out */
0x0000, /* Video */
0x0000, /* Radio */
0x0000 /* Monitor */
int dev_no;
/* Mixer parameters */
+ const struct waveartist_mixer_info *mix;
+
unsigned short *levels; /* cache of volume settings */
int recmask; /* currently enabled recording device! */
- int supported_devices; /* SUPPORTED_MIXER_DEVICES */
- int rec_devices; /* POSSIBLE_RECORDING_DEVICES */
#ifdef CONFIG_ARCH_NETWINDER
signed int slider_vol; /* hardware slider volume */
#endif
} wavnc_info;
+/*
+ * This is the implementation specific mixer information.
+ */
+struct waveartist_mixer_info {
+ unsigned int supported_devs; /* Supported devices */
+ unsigned int recording_devs; /* Recordable devies */
+ unsigned int stereo_devs; /* Stereo devices */
+
+ unsigned int (*select_input)(wavnc_info *, unsigned int,
+ unsigned char *, unsigned char *);
+ int (*decode_mixer)(wavnc_info *, int,
+ unsigned char, unsigned char);
+ int (*get_mixer)(wavnc_info *, int);
+};
+
typedef struct wavnc_port_info {
int open_mode;
int speed;
static wavnc_info adev_info[MAX_AUDIO_DEV];
static spinlock_t waveartist_lock = SPIN_LOCK_UNLOCKED;
-#ifndef machine_is_netwinder
+#ifndef CONFIG_ARCH_NETWINDER
#define machine_is_netwinder() 0
-#endif
-
+#else
static struct timer_list vnc_timer;
-static void vnc_configure_mixer(wavnc_info *devc);
+static void vnc_configure_mixer(wavnc_info *devc, unsigned int input_mask);
static int vnc_private_ioctl(int dev, unsigned int cmd, caddr_t arg);
static void vnc_slider_tick(unsigned long data);
+#endif
static inline void
waveartist_set_ctlr(struct address_info *hw, unsigned char clear, unsigned char set)
unsigned int timeout = timeout_ms * 10 * HZ / 100;
do {
- current->state = TASK_INTERRUPTIBLE;
+ set_current_state(TASK_INTERRUPTIBLE);
timeout = schedule_timeout(timeout);
} while (timeout);
}
static struct audio_driver waveartist_audio_driver = {
- owner: THIS_MODULE,
- open: waveartist_open,
- close: waveartist_close,
- output_block: waveartist_output_block,
- start_input: waveartist_start_input,
- ioctl: waveartist_ioctl,
+ owner: THIS_MODULE,
+ open: waveartist_open,
+ close: waveartist_close,
+ output_block: waveartist_output_block,
+ start_input: waveartist_start_input,
+ ioctl: waveartist_ioctl,
prepare_for_input: waveartist_prepare_for_input,
prepare_for_output: waveartist_prepare_for_output,
- halt_io: waveartist_halt,
- halt_input: waveartist_halt_input,
- halt_output: waveartist_halt_output,
- trigger: waveartist_trigger,
- set_speed: waveartist_set_speed,
- set_bits: waveartist_set_bits,
- set_channels: waveartist_set_channels
+ halt_io: waveartist_halt,
+ halt_input: waveartist_halt_input,
+ halt_output: waveartist_halt_output,
+ trigger: waveartist_trigger,
+ set_speed: waveartist_set_speed,
+ set_bits: waveartist_set_bits,
+ set_channels: waveartist_set_channels
};
/* -------------------------------------------------------------------------
* Mixer stuff
*/
+struct mix_ent {
+ unsigned char reg_l;
+ unsigned char reg_r;
+ unsigned char shift;
+ unsigned char max;
+};
+
+static const struct mix_ent mix_devs[SOUND_MIXER_NRDEVICES] = {
+ { 2, 6, 1, 7 }, /* SOUND_MIXER_VOLUME */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_BASS */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_TREBLE */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_SYNTH */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_PCM */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_SPEAKER */
+ { 0, 4, 6, 31 }, /* SOUND_MIXER_LINE */
+ { 2, 6, 4, 3 }, /* SOUND_MIXER_MIC */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_CD */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_IMIX */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_ALTPCM */
+#if 0
+ { 3, 7, 0, 10 }, /* SOUND_MIXER_RECLEV */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_IGAIN */
+#else
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_RECLEV */
+ { 3, 7, 0, 7 }, /* SOUND_MIXER_IGAIN */
+#endif
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_OGAIN */
+ { 0, 4, 1, 31 }, /* SOUND_MIXER_LINE1 */
+ { 1, 5, 6, 31 }, /* SOUND_MIXER_LINE2 */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_LINE3 */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_DIGITAL1 */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_DIGITAL2 */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_DIGITAL3 */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_PHONEIN */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_PHONEOUT */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_VIDEO */
+ { 0, 0, 0, 0 }, /* SOUND_MIXER_RADIO */
+ { 0, 0, 0, 0 } /* SOUND_MIXER_MONITOR */
+};
+
static void
waveartist_mixer_update(wavnc_info *devc, int whichDev)
{
- unsigned int mask, reg_l, reg_r;
unsigned int lev_left, lev_right;
- unsigned int vals[3];
lev_left = devc->levels[whichDev] & 0xff;
lev_right = devc->levels[whichDev] >> 8;
+ if (lev_left > 100)
+ lev_left = 100;
+ if (lev_right > 100)
+ lev_right = 100;
+
#define SCALE(lev,max) ((lev) * (max) / 100)
if (machine_is_netwinder() && whichDev == SOUND_MIXER_PHONEOUT)
whichDev = SOUND_MIXER_VOLUME;
- switch(whichDev) {
- case SOUND_MIXER_VOLUME:
- mask = 0x000e;
- reg_l = 0x200;
- reg_r = 0x600;
- lev_left = SCALE(lev_left, 7) << 1;
- lev_right = SCALE(lev_right, 7) << 1;
- break;
+ if (mix_devs[whichDev].reg_l || mix_devs[whichDev].reg_r) {
+ const struct mix_ent *mix = mix_devs + whichDev;
+ unsigned int mask, left, right;
+
+ mask = mix->max << mix->shift;
+ lev_left = SCALE(lev_left, mix->max) << mix->shift;
+ lev_right = SCALE(lev_right, mix->max) << mix->shift;
+
+ /* read left setting */
+ left = waveartist_cmd1_r(devc, WACMD_GET_LEVEL |
+ mix->reg_l << 8);
+
+ /* read right setting */
+ right = waveartist_cmd1_r(devc, WACMD_GET_LEVEL |
+ mix->reg_r << 8);
+
+ left = (left & ~mask) | (lev_left & mask);
+ right = (right & ~mask) | (lev_right & mask);
+
+ /* write left,right back */
+ waveartist_cmd3(devc, WACMD_SET_MIXER, left, right);
+ } else {
+ switch(whichDev) {
+ case SOUND_MIXER_PCM:
+ waveartist_cmd3(devc, WACMD_SET_LEVEL,
+ SCALE(lev_left, 32767),
+ SCALE(lev_right, 32767));
+ break;
- case SOUND_MIXER_LINE:
- if ((devc->recmask & SOUND_MASK_LINE) == 0)
- return;
- mask = 0x07c0;
- reg_l = 0x000;
- reg_r = 0x400;
- lev_left = SCALE(lev_left, 31) << 6;
- lev_right = SCALE(lev_right, 31) << 6;
- break;
+ case SOUND_MIXER_SYNTH:
+ waveartist_cmd3(devc, 0x0100 | WACMD_SET_LEVEL,
+ SCALE(lev_left, 32767),
+ SCALE(lev_right, 32767));
+ break;
+ }
+ }
+}
- case SOUND_MIXER_MIC:
- if ((devc->recmask & SOUND_MASK_MIC) == 0)
- return;
- mask = 0x0030;
- reg_l = 0x200;
- reg_r = 0x600;
- lev_left = SCALE(lev_left, 3) << 4;
- lev_right = SCALE(lev_right, 3) << 4;
- break;
+/*
+ * Set the ADC MUX to the specified values. We do NOT do any
+ * checking of the values passed, since we assume that the
+ * relevant *_select_input function has done that for us.
+ */
+static void
+waveartist_set_adc_mux(wavnc_info *devc, char left_dev, char right_dev)
+{
+ unsigned int reg_08, reg_09;
- case SOUND_MIXER_RECLEV:
- mask = 0x000f;
- reg_l = 0x300;
- reg_r = 0x700;
- lev_left = SCALE(lev_left, 10);
- lev_right = SCALE(lev_right, 10);
- break;
+ reg_08 = waveartist_cmd1_r(devc, WACMD_GET_LEVEL | 0x0800);
+ reg_09 = waveartist_cmd1_r(devc, WACMD_GET_LEVEL | 0x0900);
- case SOUND_MIXER_LINE1:
- if ((devc->recmask & SOUND_MASK_LINE1) == 0)
- return;
- mask = 0x003e;
- reg_l = 0x000;
- reg_r = 0x400;
- lev_left = SCALE(lev_left, 31) << 1;
- lev_right = SCALE(lev_right, 31) << 1;
- break;
+ reg_08 = (reg_08 & ~0x3f) | right_dev << 3 | left_dev;
- case SOUND_MIXER_PCM:
- waveartist_cmd3(devc, WACMD_SET_LEVEL,
- SCALE(lev_left, 32767),
- SCALE(lev_right, 32767));
- return;
+ waveartist_cmd3(devc, WACMD_SET_MIXER, reg_08, reg_09);
+}
+
+/*
+ * Decode a recording mask into a mixer selection as follows:
+ *
+ * OSS Source WA Source Actual source
+ * SOUND_MASK_IMIX Mixer Mixer output (same as AD1848)
+ * SOUND_MASK_LINE Line Line in
+ * SOUND_MASK_LINE1 Aux 1 Aux 1 in
+ * SOUND_MASK_LINE2 Aux 2 Aux 2 in
+ * SOUND_MASK_MIC Mic Microphone
+ */
+static unsigned int
+waveartist_select_input(wavnc_info *devc, unsigned int recmask,
+ unsigned char *dev_l, unsigned char *dev_r)
+{
+ unsigned int recdev = ADC_MUX_NONE;
+
+ if (recmask & SOUND_MASK_IMIX) {
+ recmask = SOUND_MASK_IMIX;
+ recdev = ADC_MUX_MIXER;
+ } else if (recmask & SOUND_MASK_LINE2) {
+ recmask = SOUND_MASK_LINE2;
+ recdev = ADC_MUX_AUX2;
+ } else if (recmask & SOUND_MASK_LINE1) {
+ recmask = SOUND_MASK_LINE1;
+ recdev = ADC_MUX_AUX1;
+ } else if (recmask & SOUND_MASK_LINE) {
+ recmask = SOUND_MASK_LINE;
+ recdev = ADC_MUX_LINE;
+ } else if (recmask & SOUND_MASK_MIC) {
+ recmask = SOUND_MASK_MIC;
+ recdev = ADC_MUX_MIC;
+ }
+ *dev_l = *dev_r = recdev;
+
+ return recmask;
+}
+
+static int
+waveartist_decode_mixer(wavnc_info *devc, int dev, unsigned char lev_l,
+ unsigned char lev_r)
+{
+ switch (dev) {
+ case SOUND_MIXER_VOLUME:
case SOUND_MIXER_SYNTH:
- waveartist_cmd3(devc, 0x0100 | WACMD_SET_LEVEL,
- SCALE(lev_left, 32767),
- SCALE(lev_right, 32767));
- return;
+ case SOUND_MIXER_PCM:
+ case SOUND_MIXER_LINE:
+ case SOUND_MIXER_MIC:
+ case SOUND_MIXER_IGAIN:
+ case SOUND_MIXER_LINE1:
+ case SOUND_MIXER_LINE2:
+ devc->levels[dev] = lev_l | lev_r << 8;
+ break;
+
+ case SOUND_MIXER_IMIX:
+ break;
default:
- return;
+ dev = -EINVAL;
+ break;
}
- /* read left setting */
- vals[0] = reg_l + WACMD_GET_LEVEL;
- waveartist_cmd(devc, 1, vals, 1, vals + 1);
-
- /* read right setting */
- vals[0] = reg_r + 0x30;
- waveartist_cmd(devc, 1, vals, 1, vals + 2);
-
- vals[1] = (vals[1] & ~mask) | (lev_left & mask);
- vals[2] = (vals[2] & ~mask) | (lev_right & mask);
+ return dev;
+}
- /* write left,right back */
- vals[0] = WACMD_SET_MIXER;
- waveartist_cmd(devc, 3, vals, 0, NULL);
+static int waveartist_get_mixer(wavnc_info *devc, int dev)
+{
+ return devc->levels[dev];
}
+static const struct waveartist_mixer_info waveartist_mixer = {
+ supported_devs: SUPPORTED_MIXER_DEVICES | SOUND_MASK_IGAIN,
+ recording_devs: SOUND_MASK_LINE | SOUND_MASK_MIC |
+ SOUND_MASK_LINE1 | SOUND_MASK_LINE2 |
+ SOUND_MASK_IMIX,
+ stereo_devs: (SUPPORTED_MIXER_DEVICES | SOUND_MASK_IGAIN) & ~
+ (SOUND_MASK_SPEAKER | SOUND_MASK_IMIX),
+ select_input: waveartist_select_input,
+ decode_mixer: waveartist_decode_mixer,
+ get_mixer: waveartist_get_mixer,
+};
+
static void
-waveartist_select_input(wavnc_info *devc, unsigned int input)
+waveartist_set_recmask(wavnc_info *devc, unsigned int recmask)
{
- unsigned int vals[3];
+ unsigned char dev_l, dev_r;
- /*
- * Get reg 9
- */
- vals[0] = 0x0830;
- waveartist_cmd(devc, 1, vals, 1, vals + 1);
+ recmask &= devc->mix->recording_devs;
/*
- * Get reg 10, only so that we can write it back.
+ * If more than one recording device selected,
+ * disable the device that is currently in use.
*/
- vals[0] = 0x0930;
- waveartist_cmd(devc, 1, vals, 1, vals + 2);
-
- if (debug_flg & DEBUG_MIXER)
- printk("RECSRC: old left: 0x%04X, old right: 0x%04X.\n",
- vals[1] & 0x07, (vals[1] >> 3) & 0x07);
+ if (hweight32(recmask) > 1)
+ recmask &= ~devc->recmask;
/*
- * kill current left/right mux input select
+ * Translate the recording device mask into
+ * the ADC multiplexer settings.
*/
- vals[1] &= ~0x03F;
+ devc->recmask = devc->mix->select_input(devc, recmask,
+ &dev_l, &dev_r);
- switch (input) {
- case SOUND_MASK_MIC:
- /*
- * right=mic, left=mic
- */
- vals[1] |= 0x002D;
- break;
-
- case SOUND_MASK_LINE1:
- /*
- * right=none, left=Aux1;
- */
- vals[1] |= 0x0004;
- break;
+ waveartist_set_adc_mux(devc, dev_l, dev_r);
+}
- case SOUND_MASK_LINE:
- /*
- * right=Line, left=Line;
- */
- vals[1] |= 0x0012;
- break;
- }
+static int
+waveartist_set_mixer(wavnc_info *devc, int dev, unsigned int level)
+{
+ unsigned int lev_left = level & 0x00ff;
+ unsigned int lev_right = (level & 0xff00) >> 8;
- if (debug_flg & DEBUG_MIXER)
- printk("RECSRC %d: left=0x%04X, right=0x%04X.\n", input,
- vals[1] & 0x07, (vals[1] >> 3) & 0x07);
+ if (lev_left > 100)
+ lev_left = 100;
+ if (lev_right > 100)
+ lev_right = 100;
/*
- * and finally - write the reg pair back....
+ * Mono devices have their right volume forced to their
+ * left volume. (from ALSA driver OSS emulation).
*/
- vals[0] = WACMD_SET_MIXER;
+ if (!(devc->mix->stereo_devs & (1 << dev)))
+ lev_right = lev_left;
- waveartist_cmd(devc, 3, vals, 0, NULL);
+ dev = devc->mix->decode_mixer(devc, dev, lev_left, lev_right);
+
+ if (dev >= 0)
+ waveartist_mixer_update(devc, dev);
+
+ return dev < 0 ? dev : 0;
}
static int
-waveartist_mixer_set(wavnc_info *devc, int whichDev, unsigned int level)
+waveartist_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
{
- unsigned int lev_left = level & 0x007f;
- unsigned int lev_right = (level & 0x7f00) >> 8;
- int left, right, devmask;
-
- left = level & 0x7f;
- right = (level & 0x7f00) >> 8;
-
- if (debug_flg & DEBUG_MIXER)
- printk("wa_mixer_set(dev=%d, level=%X)\n",
- whichDev, level);
-
- switch (whichDev) {
- case SOUND_MIXER_VOLUME: /* master volume (0-7) */
- case SOUND_MIXER_LINE: /* external line (0-31) */
- case SOUND_MIXER_MIC: /* mono mic (0-3) */
- case SOUND_MIXER_RECLEV: /* recording level (0-7) */
- case SOUND_MIXER_LINE1: /* mono external aux1 (0-31) */
- case SOUND_MIXER_PCM: /* Waveartist PCM (0-32767) */
- case SOUND_MIXER_SYNTH: /* internal synth (0-31) */
- case SOUND_MIXER_IMIX: /* recording feedback */
- devc->levels[whichDev] = lev_left | lev_right << 8;
- waveartist_mixer_update(devc, whichDev);
- break;
+ wavnc_info *devc = (wavnc_info *)audio_devs[dev]->devc;
+ int ret = 0, val, nr;
- /* Select recording input source
+ /*
+ * All SOUND_MIXER_* ioctls use type 'M'
*/
- case SOUND_MIXER_RECSRC:
- devmask = level & devc->rec_devices;
+ if (((cmd >> 8) & 255) != 'M')
+ return -ENOIOCTLCMD;
#ifdef CONFIG_ARCH_NETWINDER
- if (machine_is_netwinder())
- vnc_configure_mixer(devc);
+ if (machine_is_netwinder()) {
+ ret = vnc_private_ioctl(dev, cmd, arg);
+ if (ret != -ENOIOCTLCMD)
+ return ret;
else
+ ret = 0;
+ }
#endif
- {
- waveartist_select_input(devc, level);
- /*
- * if record monitoring is on, make sure the bit is set
- */
- if (devc->levels[SOUND_MIXER_IMIX])
- waveartist_mixer_update(devc, SOUND_MIXER_IMIX);
+ nr = cmd & 0xff;
+
+ if (_SIOC_DIR(cmd) & _SIOC_WRITE) {
+ if (get_user(val, (int *)arg))
+ return -EFAULT;
+
+ switch (nr) {
+ case SOUND_MIXER_RECSRC:
+ waveartist_set_recmask(devc, val);
+ break;
+
+ default:
+ ret = -EINVAL;
+ if (nr < SOUND_MIXER_NRDEVICES &&
+ devc->mix->supported_devs & (1 << nr))
+ ret = waveartist_set_mixer(devc, nr, val);
}
+ }
- /*
- * do not save in "levels", return current setting
- */
- return devc->recmask;
+ if (ret == 0 && _SIOC_DIR(cmd) & _SIOC_READ) {
+ ret = -EINVAL;
- default:
- return -EINVAL;
+ switch (nr) {
+ case SOUND_MIXER_RECSRC:
+ ret = devc->recmask;
+ break;
+
+ case SOUND_MIXER_DEVMASK:
+ ret = devc->mix->supported_devs;
+ break;
+
+ case SOUND_MIXER_STEREODEVS:
+ ret = devc->mix->stereo_devs;
+ break;
+
+ case SOUND_MIXER_RECMASK:
+ ret = devc->mix->recording_devs;
+ break;
+
+ case SOUND_MIXER_CAPS:
+ ret = SOUND_CAP_EXCL_INPUT;
+ break;
+
+ default:
+ if (nr < SOUND_MIXER_NRDEVICES)
+ ret = devc->mix->get_mixer(devc, nr);
+ break;
+ }
+
+ if (ret >= 0)
+ ret = put_user(ret, (int *)arg) ? -EFAULT : 0;
}
- return devc->levels[whichDev];
+ return ret;
}
+static struct mixer_operations waveartist_mixer_operations =
+{
+ owner: THIS_MODULE,
+ id: "WaveArtist",
+ name: "WaveArtist",
+ ioctl: waveartist_mixer_ioctl
+};
+
static void
waveartist_mixer_reset(wavnc_info *devc)
{
waveartist_cmd3(devc, WACMD_SET_MIXER, 0x9800, 0xa836);
/*
- * set mixer input select to none, RX filter gains 0 db
+ * set mixer input select to none, RX filter gains 0 dB
*/
waveartist_cmd3(devc, WACMD_SET_MIXER, 0x4c00, 0x8c00);
/* set default input device = internal mic
* current recording device = none
*/
- devc->recmask = 0;
+ waveartist_set_recmask(devc, 0);
for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
waveartist_mixer_update(devc, i);
-
- devc->supported_devices = SUPPORTED_MIXER_DEVICES;
- devc->rec_devices = POSSIBLE_RECORDING_DEVICES;
-
- if (machine_is_netwinder()) {
- devc->supported_devices |= SOUND_MASK_PHONEIN | SOUND_MASK_PHONEOUT;
- devc->rec_devices |= SOUND_MASK_PHONEIN;
- }
-}
-
-static int
-waveartist_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
-{
- wavnc_info *devc = (wavnc_info *)audio_devs[dev]->devc;
- int ret;
-
-#ifdef CONFIG_ARCH_NETWINDER
- if (machine_is_netwinder()) {
- ret = vnc_private_ioctl(dev, cmd, arg);
- if (ret != -ENOIOCTLCMD)
- return ret;
- }
-#endif
-
- if (((cmd >> 8) & 0xff) == 'M') {
- if (_SIOC_DIR(cmd) & _SIOC_WRITE) {
- int val;
-
- if (get_user(val, (int *)arg))
- return -EFAULT;
-
- return waveartist_mixer_set(devc, cmd & 0xff, val);
- } else {
- /*
- * Return parameters
- */
- switch (cmd & 0xff) {
- case SOUND_MIXER_RECSRC:
- ret = devc->recmask;
- break;
-
- case SOUND_MIXER_DEVMASK:
- ret = devc->supported_devices;
- break;
-
- case SOUND_MIXER_STEREODEVS:
- ret = devc->supported_devices &
- ~(SOUND_MASK_SPEAKER|SOUND_MASK_IMIX);
- break;
-
- case SOUND_MIXER_RECMASK:
- ret = devc->rec_devices;
- break;
-
- case SOUND_MIXER_CAPS:
- ret = SOUND_CAP_EXCL_INPUT;
- break;
-
- default:
- if ((cmd & 0xff) < SOUND_MIXER_NRDEVICES)
- ret = devc->levels[cmd & 0xff];
- else
- return -EINVAL;
- }
-
- return put_user(ret, (int *)arg) ? -EFAULT : 0;
- }
- }
-
- return -ENOIOCTLCMD;
}
-static struct mixer_operations waveartist_mixer_operations =
-{
- owner: THIS_MODULE,
- id: "WaveArtist",
- name: "WaveArtist NetWinder",
- ioctl: waveartist_mixer_ioctl
-};
-
static int __init waveartist_init(wavnc_info *devc)
{
wavnc_port_info *portc;
return 0;
}
- if (hw_config->irq > _ISA_IRQ(15) || hw_config->irq < _ISA_IRQ(0)) {
+ if (hw_config->irq > 15 || hw_config->irq < 0) {
printk(KERN_WARNING "WaveArtist: Bad IRQ %d\n",
hw_config->irq);
return 0;
}
- if (hw_config->dma != _ISA_DMA(3)) {
+ if (hw_config->dma != 3) {
printk(KERN_WARNING "WaveArtist: Bad DMA %d\n",
hw_config->dma);
return 0;
return 1;
}
-static void __init attach_waveartist(struct address_info *hw)
+static void __init
+attach_waveartist(struct address_info *hw, const struct waveartist_mixer_info *mix)
{
wavnc_info *devc = &adev_info[nr_waveartist_devs];
request_region(hw->io_base, 15, devc->hw.name);
+ devc->mix = mix;
devc->dev_no = waveartist_init(devc);
if (devc->dev_no < 0)
vnc_timer.data = nr_waveartist_devs;
add_timer(&vnc_timer);
- vnc_configure_mixer(devc);
+ vnc_configure_mixer(devc, 0);
+
+ devc->no_autoselect = 1;
}
#endif
nr_waveartist_devs += 1;
"to unload\n");
}
+#ifdef CONFIG_ARCH_NETWINDER
+
/*
* Rebel.com Netwinder specifics...
*/
+#include <asm/hardware/dec21285.h>
+
#define VNC_TIMER_PERIOD (HZ/4) //check slider 4 times/sec
#define MIXER_PRIVATE3_RESET 0x53570000
extern spinlock_t gpio_lock;
static inline void
-vnc_update_spkr_mute(wavnc_info *devc)
+vnc_mute_spkr(wavnc_info *devc)
{
unsigned long flags;
}
static void
-vnc_mute_lout(wavnc_info *devc, int mute)
+vnc_mute_lout(wavnc_info *devc)
{
+ unsigned int left, right;
+
+ left = waveartist_cmd1_r(devc, WACMD_GET_LEVEL);
+ right = waveartist_cmd1_r(devc, WACMD_GET_LEVEL | 0x400);
+
+ if (devc->line_mute_state) {
+ left &= ~1;
+ right &= ~1;
+ } else {
+ left |= 1;
+ right |= 1;
+ }
+ waveartist_cmd3(devc, WACMD_SET_MIXER, left, right);
+
}
static int
return old_slider_volume;
}
-static void
-vnc_configure_mixer(wavnc_info *devc)
+/*
+ * Decode a recording mask into a mixer selection on the NetWinder
+ * as follows:
+ *
+ * OSS Source WA Source Actual source
+ * SOUND_MASK_IMIX Mixer Mixer output (same as AD1848)
+ * SOUND_MASK_LINE Line Line in
+ * SOUND_MASK_LINE1 Left Mic Handset
+ * SOUND_MASK_PHONEIN Left Aux Telephone microphone
+ * SOUND_MASK_MIC Right Mic Builtin microphone
+ */
+static unsigned int
+netwinder_select_input(wavnc_info *devc, unsigned int recmask,
+ unsigned char *dev_l, unsigned char *dev_r)
{
- u_int vals[3];
-
- if (!devc->no_autoselect) {
- if (devc->handset_detect) {
- devc->recmask = SOUND_MASK_LINE1;
- devc->spkr_mute_state = devc->line_mute_state = 1;
- } else if (devc->telephone_detect) {
- devc->recmask = SOUND_MASK_PHONEIN;
- devc->spkr_mute_state = devc->line_mute_state = 1;
- } else {
- /* unless someone has asked for LINE-IN,
- * we default to MIC
- */
- if ((devc->recmask & SOUND_MASK_LINE) == 0)
- devc->recmask = SOUND_MASK_MIC;
- devc->spkr_mute_state = devc->line_mute_state = 0;
- }
- vnc_update_spkr_mute(devc);
- vnc_mute_lout(devc, devc->spkr_mute_state);
+ unsigned int recdev_l = ADC_MUX_NONE, recdev_r = ADC_MUX_NONE;
+
+ if (recmask & SOUND_MASK_IMIX) {
+ recmask = SOUND_MASK_IMIX;
+ recdev_l = ADC_MUX_MIXER;
+ recdev_r = ADC_MUX_MIXER;
+ } else if (recmask & SOUND_MASK_LINE) {
+ recmask = SOUND_MASK_LINE;
+ recdev_l = ADC_MUX_LINE;
+ recdev_r = ADC_MUX_LINE;
+ } else if (recmask & SOUND_MASK_LINE1) {
+ recmask = SOUND_MASK_LINE1;
+ waveartist_cmd1(devc, WACMD_SET_MONO); /* left */
+ recdev_l = ADC_MUX_MIC;
+ recdev_r = ADC_MUX_NONE;
+ } else if (recmask & SOUND_MASK_PHONEIN) {
+ recmask = SOUND_MASK_PHONEIN;
+ waveartist_cmd1(devc, WACMD_SET_MONO); /* left */
+ recdev_l = ADC_MUX_AUX1;
+ recdev_r = ADC_MUX_NONE;
+ } else if (recmask & SOUND_MASK_MIC) {
+ recmask = SOUND_MASK_MIC;
+ waveartist_cmd1(devc, WACMD_SET_MONO | 0x100); /* right */
+ recdev_l = ADC_MUX_NONE;
+ recdev_r = ADC_MUX_MIC;
}
- /* Ok. At this point, we have done the autoswitch logic, or we
- * have had a command from an ioctl. We have a valid devc->recmask.
- * Now we have to connect up the hardware to reflect the recmask.
- */
- vals[1] = waveartist_cmd1_r(devc, WACMD_GET_LEVEL | 0x800);
- vals[2] = waveartist_cmd1_r(devc, WACMD_GET_LEVEL | 0x900);
+ *dev_l = recdev_l;
+ *dev_r = recdev_r;
- vals[1] &= ~0x3f;
+ return recmask;
+}
- switch(devc->recmask) {
- case SOUND_MASK_MIC: /* builtin mic */
- waveartist_cmd1(devc, WACMD_SET_MONO | 0x100); /* right */
- vals[1] |= 0x28;
+static int
+netwinder_decode_mixer(wavnc_info *devc, int dev, unsigned char lev_l,
+ unsigned char lev_r)
+{
+ switch (dev) {
+ case SOUND_MIXER_VOLUME:
+ case SOUND_MIXER_SYNTH:
+ case SOUND_MIXER_PCM:
+ case SOUND_MIXER_LINE:
+ case SOUND_MIXER_IGAIN:
+ devc->levels[dev] = lev_l | lev_r << 8;
+ break;
+
+ case SOUND_MIXER_MIC: /* right mic only */
+ devc->levels[SOUND_MIXER_MIC] &= 0xff;
+ devc->levels[SOUND_MIXER_MIC] |= lev_l << 8;
+ break;
+
+ case SOUND_MIXER_LINE1: /* left mic only */
+ devc->levels[SOUND_MIXER_MIC] &= 0xff00;
+ devc->levels[SOUND_MIXER_MIC] |= lev_l;
+ dev = SOUND_MIXER_MIC;
+ break;
+
+ case SOUND_MIXER_PHONEIN: /* left aux only */
+ devc->levels[SOUND_MIXER_LINE1] = lev_l;
+ dev = SOUND_MIXER_LINE1;
+ break;
+
+ case SOUND_MIXER_IMIX:
+ case SOUND_MIXER_PHONEOUT:
+ break;
+
+ default:
+ dev = -EINVAL;
+ break;
+ }
+ return dev;
+}
+
+static int netwinder_get_mixer(wavnc_info *devc, int dev)
+{
+ int levels;
+
+ switch (dev) {
+ case SOUND_MIXER_VOLUME:
+ case SOUND_MIXER_SYNTH:
+ case SOUND_MIXER_PCM:
+ case SOUND_MIXER_LINE:
+ case SOUND_MIXER_IGAIN:
+ levels = devc->levels[dev];
break;
- case SOUND_MASK_LINE1: /* out handset */
- waveartist_cmd1(devc, WACMD_SET_MONO); /* left */
- vals[1] |= 0x05;
+ case SOUND_MIXER_MIC: /* builtin mic: right mic only */
+ levels = devc->levels[SOUND_MIXER_MIC] >> 8;
+ levels |= levels << 8;
break;
- case SOUND_MASK_PHONEIN: /* our telephone mic */
- waveartist_cmd1(devc, WACMD_SET_MONO); /* left */
- vals[1] |= 0x04;
+ case SOUND_MIXER_LINE1: /* handset mic: left mic only */
+ levels = devc->levels[SOUND_MIXER_MIC] & 0xff;
+ levels |= levels << 8;
break;
- case SOUND_MASK_LINE: /* stereo line in */
- vals[1] |= 12;
+ case SOUND_MIXER_PHONEIN: /* phone mic: left aux1 only */
+ levels = devc->levels[SOUND_MIXER_LINE1] & 0xff;
+ levels |= levels << 8;
break;
default:
- return;
+ levels = 0;
}
- vals[0] = WACMD_SET_MIXER;
- waveartist_cmd(devc, 3, vals, 0, NULL);
+ return levels;
+}
+
+/*
+ * Waveartist specific mixer information.
+ */
+static const struct waveartist_mixer_info netwinder_mixer = {
+ supported_devs: SOUND_MASK_VOLUME | SOUND_MASK_SYNTH |
+ SOUND_MASK_PCM | SOUND_MASK_SPEAKER |
+ SOUND_MASK_LINE | SOUND_MASK_MIC |
+ SOUND_MASK_IMIX | SOUND_MASK_LINE1 |
+ SOUND_MASK_PHONEIN | SOUND_MASK_PHONEOUT|
+ SOUND_MASK_IGAIN,
+
+ recording_devs: SOUND_MASK_LINE | SOUND_MASK_MIC |
+ SOUND_MASK_IMIX | SOUND_MASK_LINE1 |
+ SOUND_MASK_PHONEIN,
+
+ stereo_devs: SOUND_MASK_VOLUME | SOUND_MASK_SYNTH |
+ SOUND_MASK_PCM | SOUND_MASK_LINE |
+ SOUND_MASK_IMIX | SOUND_MASK_IGAIN,
+
+ select_input: netwinder_select_input,
+ decode_mixer: netwinder_decode_mixer,
+ get_mixer: netwinder_get_mixer,
+};
+
+static void
+vnc_configure_mixer(wavnc_info *devc, unsigned int recmask)
+{
+ if (!devc->no_autoselect) {
+ if (devc->handset_detect) {
+ recmask = SOUND_MASK_LINE1;
+ devc->spkr_mute_state = devc->line_mute_state = 1;
+ } else if (devc->telephone_detect) {
+ recmask = SOUND_MASK_PHONEIN;
+ devc->spkr_mute_state = devc->line_mute_state = 1;
+ } else {
+ /* unless someone has asked for LINE-IN,
+ * we default to MIC
+ */
+ if ((devc->recmask & SOUND_MASK_LINE) == 0)
+ devc->recmask = SOUND_MASK_MIC;
+ devc->spkr_mute_state = devc->line_mute_state = 0;
+ }
+ vnc_mute_spkr(devc);
+ vnc_mute_lout(devc);
- waveartist_mixer_update(devc, SOUND_MIXER_IMIX);
+ if (recmask != devc->recmask)
+ waveartist_set_recmask(devc, recmask);
+ }
}
static int
/*
* read the "buttons" state.
- * Bit 4 = handset present,
- * Bit 5 = offhook
+ * Bit 4 = 0 means handset present
+ * Bit 5 = 1 means phone offhook
*/
- temp = inb(0x201) & 0x30;
+ temp = inb(0x201);
old_hs = devc->handset_detect;
old_td = devc->telephone_detect;
if (!devc->no_autoselect &&
(old_hs != devc->handset_detect ||
old_td != devc->telephone_detect))
- vnc_configure_mixer(devc);
+ vnc_configure_mixer(devc, devc->recmask);
slider_volume = vnc_volume_slider(devc);
if (slider_volume != temp && devc->use_slider) {
devc->slider_vol = slider_volume;
- waveartist_mixer_set(devc, SOUND_MIXER_VOLUME,
+ waveartist_set_mixer(devc, SOUND_MIXER_VOLUME,
slider_volume | slider_volume << 8);
return 1;
devc->line_mute_state = (val & VNC_MUTE_LINE_OUT) ? 1 : 0;
if (prev_spkr_mute != devc->spkr_mute_state)
- vnc_update_spkr_mute(devc);
+ vnc_mute_spkr(devc);
if (prev_line_mute != devc->line_mute_state)
- vnc_mute_lout(devc, devc->line_mute_state);
+ vnc_mute_lout(devc);
if (prev_auto_state != devc->no_autoselect)
- vnc_configure_mixer(devc);
+ vnc_configure_mixer(devc, devc->recmask);
return 0;
}
return put_user(val, (int *)arg) ? -EFAULT : 0;
}
- if (((cmd >> 8) & 0xff) == 'M') {
- if (_SIOC_DIR(cmd) & _SIOC_WRITE) {
- /*
- * special case for master volume: if we
- * received this call - switch from hw
- * volume control to a software volume
- * control, till the hw volume is modified
- * to signal that user wants to be back in
- * hardware...
- */
- if ((cmd & 0xff) == SOUND_MIXER_VOLUME)
- devc->use_slider = 0;
- } else if ((cmd & 0xff) == SOUND_MIXER_STEREODEVS) {
- val = devc->supported_devices &
- ~(SOUND_MASK_IMIX |
- SOUND_MASK_MIC |
- SOUND_MASK_LINE1 |
- SOUND_MASK_PHONEIN |
- SOUND_MASK_PHONEOUT);
- return put_user(val, (int *)arg) ? -EFAULT : 0;
+ if (_SIOC_DIR(cmd) & _SIOC_WRITE) {
+ /*
+ * special case for master volume: if we
+ * received this call - switch from hw
+ * volume control to a software volume
+ * control, till the hw volume is modified
+ * to signal that user wants to be back in
+ * hardware...
+ */
+ if ((cmd & 0xff) == SOUND_MIXER_VOLUME)
+ devc->use_slider = 0;
+
+ /* speaker output */
+ if ((cmd & 0xff) == SOUND_MIXER_SPEAKER) {
+ unsigned int val, l, r;
+
+ if (get_user(val, (int *)arg))
+ return -EFAULT;
+
+ l = val & 0x7f;
+ r = (val & 0x7f00) >> 8;
+ val = (l + r) / 2;
+ devc->levels[SOUND_MIXER_SPEAKER] = val | (val << 8);
+ devc->spkr_mute_state = (val <= 50);
+ vnc_mute_spkr(devc);
+ return 0;
}
}
return -ENOIOCTLCMD;
}
+#endif
+
static struct address_info cfg;
static int attached;
static int __initdata dma2 = 0;
-MODULE_PARM(io, "i"); /* IO base */
-MODULE_PARM(irq, "i"); /* IRQ */
-MODULE_PARM(dma, "i"); /* DMA */
-MODULE_PARM(dma2, "i"); /* DMA2 */
-
static int __init init_waveartist(void)
{
+ const struct waveartist_mixer_info *mix;
+
if (!io && machine_is_netwinder()) {
/*
* The NetWinder WaveArtist is at a fixed address.
dma2 = 7;
}
+ mix = &waveartist_mixer;
+#ifdef CONFIG_ARCH_NETWINDER
+ if (machine_is_netwinder())
+ mix = &netwinder_mixer;
+#endif
+
cfg.io_base = io;
cfg.irq = irq;
cfg.dma = dma;
if (!probe_waveartist(&cfg))
return -ENODEV;
- attach_waveartist(&cfg);
+ attach_waveartist(&cfg, mix);
attached = 1;
return 0;
}
__setup("waveartist=", setup_waveartist);
#endif
+
+MODULE_DESCRIPTION("Rockwell WaveArtist RWA-010 sound driver");
+MODULE_PARM(io, "i"); /* IO base */
+MODULE_PARM(irq, "i"); /* IRQ */
+MODULE_PARM(dma, "i"); /* DMA */
+MODULE_PARM(dma2, "i"); /* DMA2 */
+MODULE_LICENSE("GPL");
#define WACMD_RST_MIXER 0x33
#define WACMD_SET_MONO 0x34
+/*
+ * Definitions for left/right recording input mux
+ */
+#define ADC_MUX_NONE 0
+#define ADC_MUX_MIXER 1
+#define ADC_MUX_LINE 2
+#define ADC_MUX_AUX2 3
+#define ADC_MUX_AUX1 4
+#define ADC_MUX_MIC 5
+
+/*
+ * Definitions for mixer gain settings
+ */
+#define MIX_GAIN_LINE 0 /* line in */
+#define MIX_GAIN_AUX1 1 /* aux1 */
+#define MIX_GAIN_AUX2 2 /* aux2 */
+#define MIX_GAIN_XMIC 3 /* crossover mic */
+#define MIX_GAIN_MIC 4 /* normal mic */
+#define MIX_GAIN_PREMIC 5 /* preamp mic */
+#define MIX_GAIN_OUT 6 /* output */
+#define MIX_GAIN_MONO 7 /* mono in */
+
int wa_sendcmd(unsigned int cmd);
int wa_writecmd(unsigned int cmd, unsigned int arg);
#ifdef PERFMON_STATS
#define ixj_perfmon(x) ((x)++)
#else
-#deifne ixj_perfmon(x) do {} while(0);
+#define ixj_perfmon(x) do {} while(0);
#endif
static int ixj_convert_loaded;
fbcon-iplan2p8.o fbcon-vga-planes.o fbcon-cfb16.o \
fbcon-cfb2.o fbcon-cfb24.o fbcon-cfb32.o fbcon-cfb4.o \
fbcon-cfb8.o fbcon-mac.o fbcon-mfb.o \
- cyber2000fb.o fbcon-hga.o
+ cyber2000fb.o sa1100fb.o fbcon-hga.o
# Each configuration option enables a list of files.
* ATI Mach64 CT/VT/GT/LT Cursor Support
*/
-#include <linux/malloc.h>
+#include <linux/slab.h>
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/init.h>
#ifdef CONFIG_AMIGA
#include <asm/amigahw.h>
#endif
+#ifdef CONFIG_ALL_PPC
+#include <asm/processor.h>
+#define isPReP (_machine == _MACH_prep)
+#else
+#define isPReP 0
+#endif
#include <video/fbcon.h>
#include <video/fbcon-mfb.h>
case 16:
_par->line_length = _par->var.xres_virtual * 2;
_par->visual = FB_VISUAL_DIRECTCOLOR;
-#ifdef CONFIG_PREP
- _par->var.red.offset = 2;
- _par->var.green.offset = -3;
- _par->var.blue.offset = 8;
-#else
- _par->var.red.offset = 10;
- _par->var.green.offset = 5;
- _par->var.blue.offset = 0;
-#endif
+ if(isPReP) {
+ _par->var.red.offset = 2;
+ _par->var.green.offset = -3;
+ _par->var.blue.offset = 8;
+ } else {
+ _par->var.red.offset = 10;
+ _par->var.green.offset = 5;
+ _par->var.blue.offset = 0;
+ }
_par->var.red.length = 5;
_par->var.green.length = 5;
_par->var.blue.length = 5;
case 24:
_par->line_length = _par->var.xres_virtual * 3;
_par->visual = FB_VISUAL_DIRECTCOLOR;
-#ifdef CONFIG_PREP
- _par->var.red.offset = 8;
- _par->var.green.offset = 16;
- _par->var.blue.offset = 24;
-#else
- _par->var.red.offset = 16;
- _par->var.green.offset = 8;
- _par->var.blue.offset = 0;
-#endif
+ if(isPReP) {
+ _par->var.red.offset = 8;
+ _par->var.green.offset = 16;
+ _par->var.blue.offset = 24;
+ } else {
+ _par->var.red.offset = 16;
+ _par->var.green.offset = 8;
+ _par->var.blue.offset = 0;
+ }
_par->var.red.length = 8;
_par->var.green.length = 8;
_par->var.blue.length = 8;
case 32:
_par->line_length = _par->var.xres_virtual * 4;
_par->visual = FB_VISUAL_DIRECTCOLOR;
-#ifdef CONFIG_PREP
- _par->var.red.offset = 8;
- _par->var.green.offset = 16;
- _par->var.blue.offset = 24;
-#else
- _par->var.red.offset = 16;
- _par->var.green.offset = 8;
- _par->var.blue.offset = 0;
-#endif
+ if(isPReP) {
+ _par->var.red.offset = 8;
+ _par->var.green.offset = 16;
+ _par->var.blue.offset = 24;
+ } else {
+ _par->var.red.offset = 16;
+ _par->var.green.offset = 8;
+ _par->var.blue.offset = 0;
+ }
_par->var.red.length = 8;
_par->var.green.length = 8;
_par->var.blue.length = 8;
#ifdef FBCON_HAS_CFB16
case 16:
assert (regno < 16);
-#ifdef CONFIG_PREP
- fb_info->fbcon_cmap.cfb16[regno] =
- ((red & 0xf800) >> 9) |
- ((green & 0xf800) >> 14) |
- ((green & 0xf800) << 2) |
- ((blue & 0xf800) >> 3);
-#else
- fb_info->fbcon_cmap.cfb16[regno] =
- ((red & 0xf800) >> 1) |
- ((green & 0xf800) >> 6) |
- ((blue & 0xf800) >> 11);
-#endif
+ if(isPReP) {
+ fb_info->fbcon_cmap.cfb16[regno] =
+ ((red & 0xf800) >> 9) |
+ ((green & 0xf800) >> 14) |
+ ((green & 0xf800) << 2) |
+ ((blue & 0xf800) >> 3);
+ } else {
+ fb_info->fbcon_cmap.cfb16[regno] =
+ ((red & 0xf800) >> 1) |
+ ((green & 0xf800) >> 6) |
+ ((blue & 0xf800) >> 11);
+ }
#endif /* FBCON_HAS_CFB16 */
#ifdef FBCON_HAS_CFB24
#ifdef FBCON_HAS_CFB32
case 32:
assert (regno < 16);
-#ifdef CONFIG_PREP
- fb_info->fbcon_cmap.cfb32[regno] =
- ((red & 0xff00)) |
- ((green & 0xff00) << 8) |
- ((blue & 0xff00) << 16);
-#else
- fb_info->fbcon_cmap.cfb32[regno] =
- ((red & 0xff00) << 8) |
- ((green & 0xff00)) |
- ((blue & 0xff00) >> 8);
-#endif
+ if(isPReP) {
+ fb_info->fbcon_cmap.cfb32[regno] =
+ ((red & 0xff00)) |
+ ((green & 0xff00) << 8) |
+ ((blue & 0xff00) << 16);
+ } else {
+ fb_info->fbcon_cmap.cfb32[regno] =
+ ((red & 0xff00) << 8) |
+ ((green & 0xff00)) |
+ ((blue & 0xff00) >> 8);
+ }
break;
#endif /* FBCON_HAS_CFB32 */
default:
-#ifdef CONFIG_PREP
+#ifdef CONFIG_ALL_PPC
#define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
#define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
static void __init get_prep_addrs (unsigned long *display, unsigned long *registers)
DPRINTK ("EXIT\n");
}
-#endif /* CONFIG_PREP */
+#endif /* CONFIG_ALL_PPC */
info->pdev = pdev;
-#ifdef CONFIG_PREP
- /* Xbh does this, though 0 seems to be the init value */
- pcibios_write_config_dword (0, pdev->devfn, PCI_BASE_ADDRESS_0, 0x00000000);
-#endif
+ if(isPReP) {
+ /* Xbh does this, though 0 seems to be the init value */
+ pcibios_write_config_dword (0, pdev->devfn, PCI_BASE_ADDRESS_0,
+ 0x00000000);
-#ifdef CONFIG_PREP
- get_prep_addrs (&board_addr, &info->fbregs_phys);
-#else /* CONFIG_PREP */
- DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
- get_pci_addrs (pdev, &board_addr, &info->fbregs_phys);
-#endif /* CONFIG_PREP */
+#ifdef CONFIG_ALL_PPC
+ get_prep_addrs (&board_addr, &info->fbregs_phys);
+#endif
+ } else {
+ DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
+ get_pci_addrs (pdev, &board_addr, &info->fbregs_phys);
+ }
DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, info->fbregs_phys);
-#ifdef CONFIG_PREP
- /* PReP dies if we ioremap the IO registers, but it works w/out... */
- info->regs = (char *) info->fbregs_phys;
-#else
- info->regs = 0; /* FIXME: this forces VGA. alternatives? */
-#endif
+ if(isPReP) {
+ /* PReP dies if we ioremap the IO registers, but it works w/out... */
+ info->regs = (char *) info->fbregs_phys;
+ } else
+ info->regs = 0; /* FIXME: this forces VGA. alternatives? */
if (*btype == BT_GD5480) {
board_size = 32 * MB_;
MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@mandrakesoft.com>");
MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
+MODULE_LICENSE("GPL");
static void __exit clgenfb_exit (void)
{
* bestclock() - determine closest possible clock lower(?) than the
* desired pixel clock
**************************************************************************/
-#define abs(x) ((x)<0 ? -(x) : (x))
static void bestclock (long freq, long *best, long *nom,
long *den, long *div, long maxfreq)
{
{ 0, }
};
-MODULE_DEVICE_TABLE(pci, cyberpro_pci_table);
-
static struct pci_driver cyberpro_driver = {
name: "CyberPro",
probe: cyberpro_probe,
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
+MODULE_DEVICE_TABLE(pci,cyberpro_pci_table);
MODULE_LICENSE("GPL");
#define PCI_DEVICE_ID_RADEON_QE 0x5145
#define PCI_DEVICE_ID_RADEON_QF 0x5146
#define PCI_DEVICE_ID_RADEON_QG 0x5147
-#define PCI_DEVICE_ID_RADEON_VE 0x5159
+#define PCI_DEVICE_ID_RADEON_QY 0x5159
+#define PCI_DEVICE_ID_RADEON_QZ 0x515a
+#define PCI_DEVICE_ID_RADEON_LW 0x4c57
+#define PCI_DEVICE_ID_RADEON_LY 0x4c59
+#define PCI_DEVICE_ID_RADEON_LZ 0x4c5a
+#define PCI_DEVICE_ID_RADEON_QL 0x514c
+#define PCI_DEVICE_ID_RADEON_QW 0x5157
#define RADEON_REGSIZE 0x4000
#define SC_BOTTOM_RIGHT 0x16F0
#define SRC_SC_BOTTOM_RIGHT 0x16F4
#define RB2D_DSTCACHE_CTLSTAT 0x342C
+#define LVDS_GEN_CNTL 0x02d0
+#define LVDS_PLL_CNTL 0x02d4
+#define TMDS_CRC 0x02a0
+
+#define RADEON_BASE_CODE 0x0f0b
+#define RADEON_BIOS_0_SCRATCH 0x0010
+#define RADEON_BIOS_1_SCRATCH 0x0014
+#define RADEON_BIOS_2_SCRATCH 0x0018
+#define RADEON_BIOS_3_SCRATCH 0x001c
+#define RADEON_BIOS_4_SCRATCH 0x0020
+#define RADEON_BIOS_5_SCRATCH 0x0024
+#define RADEON_BIOS_6_SCRATCH 0x0028
+#define RADEON_BIOS_7_SCRATCH 0x002c
#define CLK_PIN_CNTL 0x0001
#define CRTC_HSYNC_DIS (1 << 8)
#define CRTC_VSYNC_DIS (1 << 9)
#define CRTC_DISPLAY_DIS (1 << 10)
+#define CRTC_CRT_ON (1 << 15)
/* DSTCACHE_CTLSTAT bit constants */
/* CRTC_GEN_CNTL bit constants */
#define CRTC_DBL_SCAN_EN 0x00000001
#define CRTC_CUR_EN 0x00010000
+#define CRTC_INTERLACE_EN (1 << 1)
#define CRTC_EXT_DISP_EN (1 << 24)
#define CRTC_EN (1 << 25)
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
#define CUR_LOCK 0x80000000
+
+/* FP bit constants */
+#define FP_CRTC_H_TOTAL_MASK 0x000003ff
+#define FP_CRTC_H_DISP_MASK 0x01ff0000
+#define FP_CRTC_V_TOTAL_MASK 0x00000fff
+#define FP_CRTC_V_DISP_MASK 0x0fff0000
+#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
+#define FP_H_SYNC_WID_MASK 0x003f0000
+#define FP_V_SYNC_STRT_MASK 0x00000fff
+#define FP_V_SYNC_WID_MASK 0x001f0000
+#define FP_CRTC_H_TOTAL_SHIFT 0x00000000
+#define FP_CRTC_H_DISP_SHIFT 0x00000010
+#define FP_CRTC_V_TOTAL_SHIFT 0x00000000
+#define FP_CRTC_V_DISP_SHIFT 0x00000010
+#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
+#define FP_H_SYNC_WID_SHIFT 0x00000010
+#define FP_V_SYNC_STRT_SHIFT 0x00000000
+#define FP_V_SYNC_WID_SHIFT 0x00000010
+
+/* FP_GEN_CNTL bit constants */
+#define FP_FPON (1 << 0)
+#define FP_TMDS_EN (1 << 2)
+#define FP_EN_TMDS (1 << 7)
+#define FP_DETECT_SENSE (1 << 8)
+#define FP_SEL_CRTC2 (1 << 13)
+#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
+#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
+#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
+#define FP_CRTC_USE_SHADOW_VEND (1 << 18)
+#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
+#define FP_DFP_SYNC_SEL (1 << 21)
+#define FP_CRTC_LOCK_8DOT (1 << 22)
+#define FP_CRT_SYNC_SEL (1 << 23)
+#define FP_USE_SHADOW_EN (1 << 24)
+#define FP_CRT_SYNC_ALT (1 << 26)
+
+/* LVDS_GEN_CNTL bit constants */
+#define LVDS_ON (1 << 0)
+#define LVDS_DISPLAY_DIS (1 << 1)
+#define LVDS_PANEL_TYPE (1 << 2)
+#define LVDS_PANEL_FORMAT (1 << 3)
+#define LVDS_EN (1 << 7)
+#define LVDS_DIGON (1 << 18)
+#define LVDS_BLON (1 << 19)
+#define LVDS_SEL_CRTC2 (1 << 23)
+
+/* LVDS_PLL_CNTL bit constatns */
+#define HSYNC_DELAY_SHIFT 0x1c
+#define HSYNC_DELAY_MASK (0xf << 0x1c)
+
+/* FP_HORZ_STRETCH bit constants */
+#define HORZ_STRETCH_RATIO_MASK 0xffff
+#define HORZ_STRETCH_RATIO_MAX 4096
+#define HORZ_PANEL_SIZE (0x1ff << 16)
+#define HORZ_PANEL_SHIFT 16
+#define HORZ_STRETCH_PIXREP (0 << 25)
+#define HORZ_STRETCH_BLEND (1 << 26)
+#define HORZ_STRETCH_ENABLE (1 << 25)
+#define HORZ_AUTO_RATIO (1 << 27)
+#define HORZ_FP_LOOP_STRETCH (0x7 << 28)
+#define HORZ_AUTO_RATIO_INC (1 << 31)
+
+
+/* FP_VERT_STRETCH bit constants */
+#define VERT_STRETCH_RATIO_MASK 0xfff
+#define VERT_STRETCH_RATIO_MAX 4096
+#define VERT_PANEL_SIZE (0xfff << 12)
+#define VERT_PANEL_SHIFT 12
+#define VERT_STRETCH_LINREP (0 << 26)
+#define VERT_STRETCH_BLEND (1 << 26)
+#define VERT_STRETCH_ENABLE (1 << 25)
+#define VERT_AUTO_RATIO_EN (1 << 27)
+#define VERT_FP_LOOP_STRETCH (0x7 << 28)
+#define VERT_STRETCH_RESERVED 0xf1000000
+
/* DAC_CNTL bit constants */
#define DAC_8BIT_EN 0x00000100
#define DAC_4BPP_PIX_ORDER 0x00000200
#define SOFT_RESET_RB (1 << 6)
#define SOFT_RESET_HDP (1 << 7)
+/* SURFACE_CNTL bit consants */
+#define SURF_TRANSLATION_DIS (1 << 8)
+#define NONSURF_AP0_SWP_16BPP (1 << 20)
+#define NONSURF_AP0_SWP_32BPP (1 << 21)
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
* 2001-02-19 mode bug fixes, 0.0.7
* 2001-07-05 fixed scrolling issues, engine initialization,
* and minor mode tweaking, 0.0.9
- *
- * 2001-09-07 Radeon VE support
+ * 2001-09-07 Radeon VE support, Nick Kurshev
+ * blanking, pan_display, and cmap fixes, 0.1.0
+ * 2001-10-10 Radeon 7500 and 8500 support, and experimental
+ * flat panel support, 0.1.1
*
* Special thanks to ATI DevRel team for their hardware donations.
*
*/
-#define RADEON_VERSION "0.0.10"
+#define RADEON_VERSION "0.1.1"
#include <linux/config.h>
#include <linux/pci.h>
#include <asm/io.h>
+#if defined(__powerpc__)
+#include <asm/prom.h>
+#endif
#include <video/fbcon.h>
#include <video/fbcon-cfb8.h>
RADEON_QE,
RADEON_QF,
RADEON_QG,
- RADEON_VE
+ RADEON_QY,
+ RADEON_QZ,
+ RADEON_QL,
+ RADEON_QW,
+ RADEON_LW,
+ RADEON_LY,
+ RADEON_LZ
+};
+
+
+enum radeon_montype
+{
+ MT_NONE,
+ MT_CRT, /* CRT */
+ MT_LCD, /* LCD */
+ MT_DFP, /* DVI */
+ MT_CTV, /* composite TV */
+ MT_STV /* S-Video out */
};
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
- { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_VE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_VE},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
struct radeon_regs {
+ /* CRTC regs */
u32 crtc_h_total_disp;
u32 crtc_h_sync_strt_wid;
u32 crtc_v_total_disp;
u32 crtc_v_sync_strt_wid;
u32 crtc_pitch;
+ u32 crtc_gen_cntl;
+ u32 crtc_ext_cntl;
+ u32 dac_cntl;
+
u32 flags;
u32 pix_clock;
int xres, yres;
int bpp;
- u32 crtc_gen_cntl;
- u32 crtc_ext_cntl;
- u32 dac_cntl;
+
+ /* DDA regs */
u32 dda_config;
u32 dda_on_off;
+
+ /* PLL regs */
u32 ppll_div_3;
u32 ppll_ref_div;
+
+ /* Flat panel regs */
+ u32 fp_crtc_h_total_disp;
+ u32 fp_crtc_v_total_disp;
+ u32 fp_gen_cntl;
+ u32 fp_h_sync_strt_wid;
+ u32 fp_horz_stretch;
+ u32 fp_panel_cntl;
+ u32 fp_v_sync_strt_wid;
+ u32 fp_vert_stretch;
+ u32 lvds_gen_cntl;
+ u32 lvds_pll_cntl;
+ u32 tmds_crc;
+
+#if defined(__BIG_ENDIAN)
+ u32 surface_cntl;
+#endif
};
struct radeon_regs state;
struct radeon_regs init_state;
- char name[10];
+ char name[17];
char ram_type[12];
u32 mmio_base_phys;
int pitch, bpp, depth;
int xres, yres, pixclock;
+ int hasCRTC2;
+ int crtDisp_type;
+ int dviDisp_type;
+
+ int panel_xres, panel_yres;
+ int hOver_plus, hSync_width, hblank;
+ int vOver_plus, vSync_width, vblank;
+
u32 dp_gui_master_cntl;
struct pll_info pll;
struct ram_info ram;
+ u32 hack_crtc_ext_cntl;
+ u32 hack_crtc_v_sync_strt_wid;
+
#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
union {
#if defined(FBCON_HAS_CFB16)
u_int16_t cfb16[16];
#endif
+#if defined(FBCON_HAS_CFB24)
+ u_int32_t cfb24[16];
+#endif
#if defined(FBCON_HAS_CFB32)
u_int32_t cfb32[16];
#endif
#define INPLL(addr) _INPLL(rinfo, addr)
+#define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
+ (rinfo->dviDisp_type != MT_STV) && \
+ (rinfo->dviDisp_type != MT_CTV) ? \
+ rinfo->dviDisp_type : rinfo->crtDisp_type)
+
+static char *GET_MON_NAME(int type)
+{
+ char *pret = NULL;
+
+ switch (type) {
+ case MT_NONE:
+ pret = "no";
+ break;
+ case MT_CRT:
+ pret = "CRT";
+ break;
+ case MT_DFP:
+ pret = "DFP";
+ break;
+ case MT_LCD:
+ pret = "LCD";
+ break;
+ case MT_CTV:
+ pret = "CTV";
+ break;
+ case MT_STV:
+ pret = "STV";
+ break;
+ }
+
+ return pret;
+}
+
/*
* 2D engine routines
static char fontname[40] __initdata;
static char *mode_option __initdata;
static char noaccel __initdata = 0;
+static char panel_yres __initdata = 0;
#ifdef FBCON_HAS_CFB8
static struct display_switch fbcon_radeon8;
struct fb_info *info);
static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info);
-static void radeon_set_dispsw (struct radeonfb_info *rinfo);
+static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
static void radeon_save_state (struct radeonfb_info *rinfo,
struct radeon_regs *save);
static void radeon_engine_init (struct radeonfb_info *rinfo);
static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
static char *radeon_find_rom(struct radeonfb_info *rinfo);
static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
+static void radeon_get_moninfo (struct radeonfb_info *rinfo);
+static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
+static int radeon_read_OF (struct radeonfb_info *rinfo);
+#if defined(__powerpc__)
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
+#endif
static struct fb_ops radeon_fb_ops = {
fb_get_fix: radeonfb_get_fix,
memcpy(fontname, this_opt + 5, i);
} else if (!strncmp(this_opt, "noaccel", 7)) {
noaccel = 1;
- }
- else mode_option = this_opt;
+ } else if (!strncmp(this_opt, "panel_yres:", 11)) {
+ panel_yres = simple_strtoul((this_opt+11), NULL, 0);
+ } else
+ mode_option = this_opt;
}
return 0;
int i, j;
char *bios_seg = NULL;
+ RTRACE("radeonfb_pci_register BEGIN\n");
+
rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
if (!rinfo) {
printk ("radeonfb: could not allocate memory\n");
memset (rinfo, 0, sizeof (struct radeonfb_info));
+ rinfo->pdev = pdev;
+
/* enable device */
{
int err;
return -ENODEV;
}
+ rinfo->chipset = pdev->device;
+
/* chipset */
switch (pdev->device) {
case PCI_DEVICE_ID_RADEON_QD:
case PCI_DEVICE_ID_RADEON_QG:
strcpy(rinfo->name, "Radeon QG ");
break;
- case PCI_DEVICE_ID_RADEON_VE:
- strcpy(rinfo->name, "Radeon VE ");
+ case PCI_DEVICE_ID_RADEON_QY:
+ strcpy(rinfo->name, "Radeon QY VE ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_QZ:
+ strcpy(rinfo->name, "Radeon QZ VE ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_QW:
+ strcpy(rinfo->name, "Radeon 7500 QW ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_QL:
+ strcpy(rinfo->name, "Radeon 8500 QL ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_LW:
+ strcpy(rinfo->name, "Radeon M7 LW ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_LY:
+ strcpy(rinfo->name, "Radeon M6 LY ");
+ rinfo->hasCRTC2 = 1;
+ break;
+ case PCI_DEVICE_ID_RADEON_LZ:
+ strcpy(rinfo->name, "Radeon M6 LZ ");
+ rinfo->hasCRTC2 = 1;
break;
default:
return -ENODEV;
bios_seg = radeon_find_rom(rinfo);
radeon_get_pllinfo(rinfo, bios_seg);
- printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
- rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
-
RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
+ radeon_get_moninfo(rinfo);
+ if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
+ (rinfo->crtDisp_type == MT_DFP)) {
+ if (!radeon_get_dfpinfo(rinfo)) {
+ iounmap ((void*)rinfo->mmio_base);
+ release_mem_region (rinfo->mmio_base_phys,
+ pci_resource_len(pdev, 2));
+ release_mem_region (rinfo->fb_base_phys,
+ pci_resource_len(pdev, 0));
+ kfree (rinfo);
+ return -ENODEV;
+ }
+ }
+
rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
rinfo->video_ram);
if (!rinfo->fb_base) {
radeon_engine_init (rinfo);
}
- printk ("radeonfb: ATI %s %d MB\n",rinfo->name,
+ printk ("radeonfb: ATI %s %s %d MB\n", rinfo->name, rinfo->ram_type,
(rinfo->video_ram/(1024*1024)));
+ if (rinfo->hasCRTC2) {
+ printk("radeonfb: DVI port %s monitor connected\n",
+ GET_MON_NAME(rinfo->dviDisp_type));
+ printk("radeonfb: CRT port %s monitor connected\n",
+ GET_MON_NAME(rinfo->crtDisp_type));
+ } else {
+ printk("radeonfb: CRT port %s monitor connected\n",
+ GET_MON_NAME(rinfo->crtDisp_type));
+ }
+
+ RTRACE("radeonfb_pci_register END\n");
+
return 0;
}
static char *radeon_find_rom(struct radeonfb_info *rinfo)
-{
+{
+#if defined(__i386__)
u32 segstart;
char *rom_base;
char *rom;
int stage;
- int i;
+ int i,j;
char aty_rom_sig[] = "761295520";
- char radeon_sig[] = "RG6";
-
-#if defined(__i386__)
- for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
+ char *radeon_sig[] = {
+ "RG6",
+ "RADEON"
+ };
+
+ for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
+
stage = 1;
-
+
rom_base = (char *)ioremap(segstart, 0x1000);
-
+
if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
stage = 2;
-
- if (stage != 2) {
+
+ if (stage != 2) {
iounmap(rom_base);
continue;
}
-
+
rom = rom_base;
-
+
for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
if (aty_rom_sig[0] == *rom)
if (strncmp(aty_rom_sig, rom,
strlen(aty_rom_sig)) == 0)
stage = 3;
rom++;
- }
+ }
if (stage != 3) {
iounmap(rom_base);
- continue;
+ continue;
}
rom = rom_base;
-
+
for (i = 0; (i < 512) && (stage != 4); i++) {
- if (radeon_sig[0] == *rom)
- if (strncmp(radeon_sig, rom,
- strlen(radeon_sig)) == 0)
- stage = 4;
+ for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
+ if (radeon_sig[j][0] == *rom)
+ if (strncmp(radeon_sig[j], rom,
+ strlen(radeon_sig[j])) == 0) {
+ stage = 4;
+ break;
+ }
+ }
rom++;
- }
+ }
if (stage != 4) {
iounmap(rom_base);
continue;
- }
+ }
return rom_base;
}
-#endif
+#endif
return NULL;
}
+
static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
{
void *bios_header;
rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
rinfo->pll.ppll_min = pll.PCLK_min_freq;
rinfo->pll.ppll_max = pll.PCLK_max_freq;
+
+ printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
+ rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
} else {
+#if defined(__powerpc__)
+ if (radeon_read_OF(rinfo)) {
+ unsigned int tmp, Nx, M, ref_div, xclk;
+
+ tmp = INPLL(M_SPLL_REF_FB_DIV);
+ ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
+
+ Nx = (tmp & 0xff00) >> 8;
+ M = (tmp & 0xff);
+ xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
+ (2 * M)));
+
+ rinfo->pll.xclk = xclk;
+ rinfo->pll.ref_div = ref_div;
+ rinfo->pll.ppll_min = 12000;
+ rinfo->pll.ppll_max = 35000;
+
+ printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
+ rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
+
+ return;
+ }
+#endif
/* no BIOS or BIOS not found, use defaults */
+ switch (rinfo->chipset) {
+ case PCI_DEVICE_ID_RADEON_QW:
+ rinfo->pll.ppll_max = 35000;
+ rinfo->pll.ppll_min = 12000;
+ rinfo->pll.xclk = 23000;
+ rinfo->pll.ref_div = 12;
+ rinfo->pll.ref_clk = 2700;
+ break;
+ case PCI_DEVICE_ID_RADEON_QL:
+ rinfo->pll.ppll_max = 35000;
+ rinfo->pll.ppll_min = 12000;
+ rinfo->pll.xclk = 27500;
+ rinfo->pll.ref_div = 12;
+ rinfo->pll.ref_clk = 2700;
+ break;
+ case PCI_DEVICE_ID_RADEON_QD:
+ case PCI_DEVICE_ID_RADEON_QE:
+ case PCI_DEVICE_ID_RADEON_QF:
+ case PCI_DEVICE_ID_RADEON_QG:
+ default:
+ rinfo->pll.ppll_max = 35000;
+ rinfo->pll.ppll_min = 12000;
+ rinfo->pll.xclk = 16600;
+ rinfo->pll.ref_div = 67;
+ rinfo->pll.ref_clk = 2700;
+ break;
+ }
- rinfo->pll.ppll_max = 35000;
- rinfo->pll.ppll_min = 12000;
- rinfo->pll.xclk = 16600;
- rinfo->pll.ref_div = 67;
- rinfo->pll.ref_clk = 2700;
+ printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
+ rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
}
}
+
+static void radeon_get_moninfo (struct radeonfb_info *rinfo)
+{
+ unsigned int tmp;
+
+ tmp = INREG(RADEON_BIOS_4_SCRATCH);
+
+ if (rinfo->hasCRTC2) {
+ /* primary DVI port */
+ if (tmp & 0x08)
+ rinfo->dviDisp_type = MT_DFP;
+ else if (tmp & 0x4)
+ rinfo->dviDisp_type = MT_LCD;
+ else if (tmp & 0x200)
+ rinfo->dviDisp_type = MT_CRT;
+ else if (tmp & 0x10)
+ rinfo->dviDisp_type = MT_CTV;
+ else if (tmp & 0x20)
+ rinfo->dviDisp_type = MT_STV;
+
+ /* secondary CRT port */
+ if (tmp & 0x2)
+ rinfo->crtDisp_type = MT_CRT;
+ else if (tmp & 0x800)
+ rinfo->crtDisp_type = MT_DFP;
+ else if (tmp & 0x400)
+ rinfo->crtDisp_type = MT_LCD;
+ else if (tmp & 0x1000)
+ rinfo->crtDisp_type = MT_CTV;
+ else if (tmp & 0x2000)
+ rinfo->crtDisp_type = MT_STV;
+ } else {
+ rinfo->dviDisp_type = MT_NONE;
+
+ tmp = INREG(FP_GEN_CNTL);
+
+ if (tmp & FP_EN_TMDS)
+ rinfo->crtDisp_type = MT_DFP;
+ else
+ rinfo->crtDisp_type = MT_CRT;
+ }
+}
+
+
+static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
+{
+ unsigned int tmp;
+ unsigned short a, b;
+
+ if (panel_yres) {
+ rinfo->panel_yres = panel_yres;
+ } else {
+ tmp = INREG(FP_VERT_STRETCH);
+ tmp &= 0x00fff000;
+ rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
+ }
+
+ switch (rinfo->panel_yres) {
+ case 480:
+ rinfo->panel_xres = 640;
+ break;
+ case 600:
+ rinfo->panel_xres = 800;
+ break;
+ case 786:
+ rinfo->panel_xres = 1024;
+ break;
+ case 1024:
+ rinfo->panel_xres = 1280;
+ break;
+ case 1050:
+ rinfo->panel_xres = 1400;
+ break;
+ case 1200:
+ rinfo->panel_xres = 1600;
+ break;
+ default:
+ printk("radeonfb: Failed to detect DFP panel size\n");
+ return 0;
+ }
+
+ printk("radeonfb: detected DFP panel size: %dx%d\n",
+ rinfo->panel_xres, rinfo->panel_yres);
+
+ tmp = INREG(FP_CRTC_H_TOTAL_DISP);
+ a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
+ b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
+ rinfo->hblank = (a - b + 1) * 8;
+
+ tmp = INREG(FP_H_SYNC_STRT_WID);
+ rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
+ FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
+ rinfo->hOver_plus *= 8;
+ rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
+ FP_H_SYNC_WID_SHIFT);
+ rinfo->hSync_width *= 8;
+ tmp = INREG(FP_CRTC_V_TOTAL_DISP);
+ a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
+ b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
+ rinfo->vblank = a - b /* + 24 */ ;
+
+ tmp = INREG(FP_V_SYNC_STRT_WID);
+ rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
+ - b + 1;
+ rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
+ FP_V_SYNC_WID_SHIFT);
+
+ return 1;
+}
+
+
+#if defined(__powerpc__)
+static int radeon_read_OF (struct radeonfb_info *rinfo)
+{
+ struct device_node *dp;
+ unsigned int *xtal;
+
+ dp = pci_device_to_OF_node(rinfo->pdev);
+
+ xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
+
+ rinfo->pll.ref_clk = *xtal / 10;
+
+ if (*xtal)
+ return 1;
+ else
+ return 0;
+}
+#endif
+
+
static void radeon_engine_init (struct radeonfb_info *rinfo)
{
u32 temp;
disp->var = radeonfb_default_var;
info->disp = disp;
- radeon_set_dispsw (rinfo);
+ radeon_set_dispsw (rinfo, disp);
if (noaccel)
disp->scrollmode = SCROLL_YREDRAW;
-static void radeon_set_dispsw (struct radeonfb_info *rinfo)
-{
- struct display *disp = &rinfo->disp;
- int accel;
+static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
- accel = disp->var.accel_flags & FB_ACCELF_TEXT;
-
+{
+ int accel;
+
+ accel = disp->var.accel_flags & FB_ACCELF_TEXT;
+
disp->dispsw_data = NULL;
-
- disp->screen_base = (char*)rinfo->fb_base;
+
+ disp->screen_base = (char*)rinfo->fb_base;
disp->type = FB_TYPE_PACKED_PIXELS;
disp->type_aux = 0;
disp->ypanstep = 1;
disp->ywrapstep = 0;
disp->can_soft_blank = 1;
- disp->inverse = 0;
+ disp->inverse = 0;
- rinfo->depth = disp->var.bits_per_pixel;
+ rinfo->depth = disp->var.bits_per_pixel;
switch (disp->var.bits_per_pixel) {
#ifdef FBCON_HAS_CFB8
case 8:
- disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
- disp->visual = FB_VISUAL_PSEUDOCOLOR;
- disp->line_length = disp->var.xres_virtual;
+ disp->dispsw = &fbcon_cfb8;
+ disp->visual = FB_VISUAL_PSEUDOCOLOR;
+ disp->line_length = disp->var.xres_virtual;
break;
-#endif
+#endif
#ifdef FBCON_HAS_CFB16
case 16:
disp->dispsw = &fbcon_cfb16;
disp->dispsw_data = &rinfo->con_cmap.cfb16;
- disp->visual = FB_VISUAL_DIRECTCOLOR;
- disp->line_length = disp->var.xres_virtual * 2;
+ disp->visual = FB_VISUAL_DIRECTCOLOR;
+ disp->line_length = disp->var.xres_virtual * 2;
+ break;
+#endif
+#ifdef FBCON_HAS_CFB32
+ case 24:
+ disp->dispsw = &fbcon_cfb24;
+ disp->dispsw_data = &rinfo->con_cmap.cfb24;
+ disp->visual = FB_VISUAL_DIRECTCOLOR;
+ disp->line_length = disp->var.xres_virtual * 4;
break;
#endif
#ifdef FBCON_HAS_CFB32
case 32:
disp->dispsw = &fbcon_cfb32;
disp->dispsw_data = &rinfo->con_cmap.cfb32;
- disp->visual = FB_VISUAL_DIRECTCOLOR;
- disp->line_length = disp->var.xres_virtual * 4;
- break;
+ disp->visual = FB_VISUAL_DIRECTCOLOR;
+ disp->line_length = disp->var.xres_virtual * 4;
+ break;
#endif
default:
printk ("radeonfb: setting fbcon_dummy renderer\n");
disp->dispsw = &fbcon_dummy;
}
-
+
return;
}
+
+
+
+static void do_install_cmap(int con, struct fb_info *info)
+{
+ struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
+
+ if (con != rinfo->currcon)
+ return;
+
+ if (fb_display[con].cmap.len)
+ fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
+ else {
+ int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
+ fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
+ }
+}
+
+static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
+ struct fb_var_screeninfo *var,
+ struct fb_var_screeninfo *v,
+ int nom, int den)
+{
+ static struct {
+ int xres, yres;
+ } modes[] = {
+ {1600, 1280},
+ {1280, 1024},
+ {1024, 768},
+ {800, 600},
+ {640, 480},
+ {-1, -1}
+ };
+ int i;
+
+ /* use highest possible virtual resolution */
+ if (v->xres_virtual == -1 && v->yres_virtual == -1) {
+ printk("radeonfb: using max availabe virtual resolution\n");
+ for (i=0; modes[i].xres != -1; i++) {
+ if (modes[i].xres * nom / den * modes[i].yres <
+ rinfo->video_ram / 2)
+ break;
+ }
+ if (modes[i].xres == -1) {
+ printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
+ return -EINVAL;
+ }
+ v->xres_virtual = modes[i].xres;
+ v->yres_virtual = modes[i].yres;
+
+ printk("radeonfb: virtual resolution set to max of %dx%d\n",
+ v->xres_virtual, v->yres_virtual);
+ } else if (v->xres_virtual == -1) {
+ v->xres_virtual = (rinfo->video_ram * den /
+ (nom * v->yres_virtual * 2)) & ~15;
+ } else if (v->yres_virtual == -1) {
+ v->xres_virtual = (v->xres_virtual + 15) & ~15;
+ v->yres_virtual = rinfo->video_ram * den /
+ (nom * v->xres_virtual *2);
+ } else {
+ if (v->xres_virtual * nom / den * v->yres_virtual >
+ rinfo->video_ram) {
+ return -EINVAL;
+ }
+ }
+
+ if (v->xres_virtual * nom / den >= 8192) {
+ v->xres_virtual = 8192 * den / nom - 16;
+ }
+
+ if (v->xres_virtual < v->xres)
+ return -EINVAL;
+
+ if (v->yres_virtual < v->yres)
+ return -EINVAL;
+
+ return 0;
+}
+
+
/*
* fb ops
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
struct display *disp;
struct fb_var_screeninfo v;
- int nom, den, i, accel;
+ int nom, den, accel;
unsigned chgvar = 0;
- static struct {
- int xres, yres;
- } modes[] = {
- {
- 1600, 1280}, {
- 1280, 1024}, {
- 1024, 768}, {
- 800, 600}, {
- 640, 480}, {
- -1, -1}
- };
-
+
disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
- accel = var->accel_flags & FB_ACCELF_TEXT;
-
+ accel = var->accel_flags & FB_ACCELF_TEXT;
+
if (con >= 0) {
chgvar = ((disp->var.xres != var->xres) ||
(disp->var.yres != var->yres) ||
(disp->var.xres_virtual != var->xres_virtual) ||
(disp->var.yres_virtual != var->yres_virtual) ||
+ (disp->var.bits_per_pixel != var->bits_per_pixel) ||
memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
}
-
+
memcpy (&v, var, sizeof (v));
-
+
switch (v.bits_per_pixel) {
#ifdef FBCON_HAS_CFB8
case 8:
- v.bits_per_pixel = 8;
- disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
nom = den = 1;
disp->line_length = v.xres_virtual;
- disp->visual = FB_VISUAL_PSEUDOCOLOR;
+ disp->visual = FB_VISUAL_PSEUDOCOLOR;
v.red.offset = v.green.offset = v.blue.offset = 0;
v.red.length = v.green.length = v.blue.length = 8;
+ v.transp.offset = v.transp.length = 0;
break;
#endif
-
+
#ifdef FBCON_HAS_CFB16
case 16:
- v.bits_per_pixel = 16;
- disp->dispsw = &fbcon_cfb16;
- disp->dispsw_data = &rinfo->con_cmap.cfb16;
nom = 2;
den = 1;
disp->line_length = v.xres_virtual * 2;
v.red.offset = 11;
v.green.offset = 5;
v.blue.offset = 0;
- v.red.length = 5;
- v.green.length = 6;
- v.blue.length = 5;
+ v.red.length = 5;
+ v.green.length = 6;
+ v.blue.length = 5;
+ v.transp.offset = v.transp.length = 0;
+ break;
+#endif
+
+#ifdef FBCON_HAS_CFB24
+ case 24:
+ nom = 4;
+ den = 1;
+ disp->line_length = v.xres_virtual * 3;
+ disp->visual = FB_VISUAL_DIRECTCOLOR;
+ v.red.offset = 16;
+ v.green.offset = 8;
+ v.blue.offset = 0;
+ v.red.length = v.blue.length = v.green.length = 8;
+ v.transp.offset = v.transp.length = 0;
break;
#endif
-
-#ifdef FBCON_HAS_CFB32
+#ifdef FBCON_HAS_CFB32
case 32:
- v.bits_per_pixel = 32;
- disp->dispsw = &fbcon_cfb32;
- disp->dispsw_data = rinfo->con_cmap.cfb32;
nom = 4;
den = 1;
disp->line_length = v.xres_virtual * 4;
- disp->visual = FB_VISUAL_DIRECTCOLOR;
+ disp->visual = FB_VISUAL_DIRECTCOLOR;
v.red.offset = 16;
v.green.offset = 8;
- v.blue.offset = 0;
+ v.blue.offset = 0;
v.red.length = v.blue.length = v.green.length = 8;
+ v.transp.offset = 24;
+ v.transp.length = 8;
break;
#endif
default:
return -EINVAL;
}
- if (v.xres * nom / den * v.yres > (rinfo->video_ram)) {
- printk ("radeonfb: mode %dx%dx%d rejected, not enough video ram\n",
- var->xres, var->yres, var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (v.xres_virtual == -1 && v.yres_virtual == -1) {
- printk ("radeonfb: using maximum available virtual resolution\n");
- for (i = 0; modes[i].xres != -1; i++) {
- if (modes[i].xres * nom / den * modes[i].yres < (rinfo->video_ram/2))
- break;
- }
- if (modes[i].xres == -1) {
- printk ("radeonfb: could not find a virtual res\n");
- return -EINVAL;
- }
- v.xres_virtual = modes[i].xres;
- v.yres_virtual = modes[i].yres;
+ if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
+ return -EINVAL;
- printk ("radeonfb: virtual resolution set to maximum of %dx%d\n",
- v.xres_virtual, v.yres_virtual);
- }
-
if (v.xoffset < 0)
v.xoffset = 0;
if (v.yoffset < 0)
v.yoffset = 0;
-
+
if (v.xoffset > v.xres_virtual - v.xres)
v.xoffset = v.xres_virtual - v.xres - 1;
if (v.yoffset > v.yres_virtual - v.yres)
v.yoffset = v.yres_virtual - v.yres - 1;
-
+
v.red.msb_right = v.green.msb_right = v.blue.msb_right =
v.transp.offset = v.transp.length =
v.transp.msb_right = 0;
case FB_ACTIVATE_NXTOPEN:
case FB_ACTIVATE_NOW:
break;
- default:
+ default:
return -EINVAL;
}
-
- disp->type = FB_TYPE_PACKED_PIXELS;
-
+
memcpy (&disp->var, &v, sizeof (v));
+
+ if (chgvar) {
+ radeon_set_dispsw(rinfo, disp);
- radeon_load_video_mode (rinfo, &v);
-
- if (chgvar && info && info->changevar)
- info->changevar (con);
+ if (noaccel)
+ disp->scrollmode = SCROLL_YREDRAW;
+ else
+ disp->scrollmode = 0;
+
+ if (info && info->changevar)
+ info->changevar(con);
+ }
+
+ radeon_load_video_mode (rinfo, &v);
+
+ do_install_cmap(con, info);
return 0;
}
struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
- struct display *disp;
- unsigned int base;
-
- disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
-
- if (var->xoffset > (var->xres_virtual - var->xres))
- return -EINVAL;
- if (var->yoffset > (var->yres_virtual - var->yres))
+ u32 offset, xoffset, yoffset;
+
+ xoffset = (var->xoffset + 7) & ~7;
+ yoffset = var->yoffset;
+
+ if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
+ var->yres_virtual))
return -EINVAL;
-
- if (var->vmode & FB_VMODE_YWRAP) {
- if (var->yoffset < 0 ||
- var->yoffset >= disp->var.yres_virtual ||
- var->xoffset )
- return -EINVAL;
- } else {
- if (var->xoffset + disp->var.xres > disp->var.xres_virtual ||
- var->yoffset + disp->var.yres > disp->var.yres_virtual)
- return -EINVAL;
- }
-
- base = var->yoffset * disp->line_length + var->xoffset;
-
- disp->var.xoffset = var->xoffset;
- disp->var.yoffset = var->yoffset;
-
- if (var->vmode & FB_VMODE_YWRAP)
- disp->var.vmode |= FB_VMODE_YWRAP;
- else
- disp->var.vmode &= ~FB_VMODE_YWRAP;
+
+ offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
+
+ OUTREG(CRTC_OFFSET, offset);
return 0;
}
-
static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg, int con, struct fb_info *info)
{
}
-
static int radeonfb_switch (int con, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
struct display *disp;
struct fb_cmap *cmap;
- int switchcon = 0;
+ int switchcon = 0;
disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
-
+
if (rinfo->currcon >= 0) {
cmap = &(rinfo->currcon_display->cmap);
if (cmap->len)
fb_get_cmap (cmap, 1, radeon_getcolreg, info);
- }
-
- if ((disp->var.xres != rinfo->xres) ||
- (disp->var.yres != rinfo->yres) ||
- (disp->var.pixclock != rinfo->pixclock) ||
- (disp->var.bits_per_pixel != rinfo->depth))
- switchcon = 1;
+ }
+
+ if ((disp->var.xres != rinfo->xres) ||
+ (disp->var.yres != rinfo->yres) ||
+ (disp->var.pixclock != rinfo->pixclock) ||
+ (disp->var.bits_per_pixel != rinfo->depth))
+ switchcon = 1;
+
+ if (switchcon) {
+ rinfo->currcon = con;
+ rinfo->currcon_display = disp;
+ disp->var.activate = FB_ACTIVATE_NOW;
+
+ radeonfb_set_var (&disp->var, con, info);
+ radeon_set_dispsw (rinfo, disp);
+ do_install_cmap(con, info);
+ }
- if (switchcon) {
- rinfo->currcon = con;
- rinfo->currcon_display = disp;
- disp->var.activate = FB_ACTIVATE_NOW;
+ /* XXX absurd hack for X to restore console */
+ {
+ OUTREGP(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl,
+ CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
+ OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
+ }
- radeonfb_set_var (&disp->var, con, info);
- radeon_set_dispsw (rinfo);
- }
-
return 0;
}
static void radeonfb_blank (int blank, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
- u8 mode = 0;
-
- switch (blank) {
- case 0:
- /* unblank */
- mode = 0;
- break;
- case 1:
- /* blank */
- mode = ((INREG8(CRTC_EXT_CNTL + 1) & 3) | 4);
- break;
- case 2:
- case 3:
- case 4:
- mode = blank | 4;
- break;
- }
-
- OUTREG8(CRTC_EXT_CNTL + 1, mode);
+ u32 val = INREG(CRTC_EXT_CNTL);
+
+ /* reset it */
+ val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
+ CRTC_VSYNC_DIS);
+
+ switch (blank) {
+ case VESA_NO_BLANKING:
+ break;
+ case VESA_VSYNC_SUSPEND:
+ val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
+ break;
+ case VESA_HSYNC_SUSPEND:
+ val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
+ break;
+ case VESA_POWERDOWN:
+ val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
+ CRTC_HSYNC_DIS);
+ break;
+ }
+
+ OUTREG(CRTC_EXT_CNTL, val);
}
case 8:
rc = 256;
break;
- case 16:
- rc = 64;
- break;
default:
rc = 32;
break;
unsigned blue, unsigned transp, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
- u32 pindex, col;
+ u32 pindex;
if (regno > 255)
return 1;
rinfo->palette[regno].green = green;
rinfo->palette[regno].blue = blue;
- /* init gamma for hicolor */
- if ((rinfo->depth > 8) && (regno == 0)) {
- int i;
- u32 tmp;
-
- for (i=0; i<255; i++) {
- OUTREG(PALETTE_INDEX, i);
- tmp = (i << 16) | (i << 8) | i;
- radeon_fifo_wait(32);
- OUTREG(PALETTE_DATA, tmp);
- }
- }
-
- /* default */
- pindex = regno;
- col = (red << 16) | (green << 8) | blue;
-
- if (rinfo->depth == 16) {
- pindex = regno << 3;
-
- if ((rinfo->depth == 16) && (regno >= 32)) {
- pindex -= 252;
+ /* init gamma for hicolor */
+ if ((rinfo->depth > 8) && (regno == 0)) {
+ int i;
+
+ for (i=0; i<255; i++) {
+ OUTREG(PALETTE_INDEX, i);
+ OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
+ }
+ }
+
+ /* default */
+ pindex = regno;
+
+ /* XXX actually bpp, fixme */
+ if (rinfo->depth == 16)
+ pindex = regno * 8;
+
+ if (rinfo->depth == 16) {
+ OUTREG(PALETTE_INDEX, pindex/2);
+ OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
+ (green << 8) | (rinfo->palette[regno/2].blue));
+ green = rinfo->palette[regno/2].green;
+ }
+
+ if ((rinfo->depth == 8) || (regno < 32)) {
+ OUTREG(PALETTE_INDEX, pindex);
+ OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
+ }
- col = (rinfo->palette[regno >> 1].red << 16) |
- (green << 8) |
- (rinfo->palette[regno >> 1].blue);
- } else {
- col = (red << 16) | (green << 8) | blue;
- }
- }
-
- OUTREG8(PALETTE_INDEX, pindex);
- radeon_fifo_wait(32);
- OUTREG(PALETTE_DATA, col);
#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
if (regno < 32) {
switch (rinfo->depth) {
#ifdef FBCON_HAS_CFB16
case 16:
- rinfo->con_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
+ rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
regno;
break;
#endif
+#ifdef FBCON_HAS_CFB24
+ case 24:
+ rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
+ break;
+#endif
#ifdef FBCON_HAS_CFB32
case 32: {
u32 i;
static void radeon_save_state (struct radeonfb_info *rinfo,
struct radeon_regs *save)
{
+ /* CRTC regs */
save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
save->dac_cntl = INREG(DAC_CNTL);
save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
save->crtc_pitch = INREG(CRTC_PITCH);
+#if defined(__BIG_ENDIAN)
+ save->surface_cntl = INREG(SURFACE_CNTL);
+#endif
+
+ /* FP regs */
+ save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
+ save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
+ save->fp_gen_cntl = INREG(FP_GEN_CNTL);
+ save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
+ save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
+ save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
+ save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
+ save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
+ save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
+ save->tmds_crc = INREG(TMDS_CRC);
}
int hTotal, vTotal, hSyncStart, hSyncEnd,
hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
+ u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
u32 dotClock = 1000000000 / mode->pixclock,
sync, h_sync_pol, v_sync_pol;
int freq = dotClock / 10; /* x 100 */
int useable_precision, roff, ron;
int min_bits, format = 0;
int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
+ int primary_mon = PRIMARY_MONITOR(rinfo);
rinfo->xres = mode->xres;
rinfo->yres = mode->yres;
vSyncEnd = vSyncStart + mode->vsync_len;
vTotal = vSyncEnd + mode->upper_margin;
+ if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
+ if (rinfo->panel_xres < mode->xres)
+ rinfo->xres = mode->xres = rinfo->panel_xres;
+ if (rinfo->panel_yres < mode->yres)
+ rinfo->yres = mode->yres = rinfo->panel_yres;
+
+ hTotal = mode->xres + rinfo->hblank + mode->left_margin;
+ hSyncStart = mode->xres + rinfo->hOver_plus + mode->right_margin;
+ hSyncEnd = hSyncStart + rinfo->hOver_plus + mode->hsync_len;
+
+ vTotal = mode->yres + rinfo->vblank + mode->upper_margin;
+ vSyncStart = mode->yres + rinfo->vOver_plus + mode->lower_margin;
+ vSyncEnd = vSyncStart + rinfo->vSync_width + mode->vsync_len;
+ }
+
sync = mode->sync;
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
break;
}
- hsync_fudge = hsync_adj_tab[format-1];
+ if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
+ hsync_fudge = hsync_fudge_fp[format-1];
+ else
+ hsync_fudge = hsync_adj_tab[format-1];
+
hsync_start = hSyncStart - 8 + hsync_fudge;
newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
(format << 8);
- newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
+ if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
+ newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
+ newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
+ CRTC_INTERLACE_EN);
+ } else {
+ newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
+ CRTC_CRT_ON;
+ }
- newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
+ newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
DAC_8BIT_EN;
newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0xffff) |
(vsync_wid << 16) | (v_sync_pol << 23));
newmode.crtc_pitch = (mode->xres >> 3);
+ newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
+
+#if defined(__BIG_ENDIAN)
+ newmode.surface_cntl = SURF_TRANSLATION_DIS;
+ switch (mode->bits_per_pixel) {
+ case 16:
+ newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
+ break;
+ case 24:
+ case 32:
+ newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
+ break;
+ }
+#endif
rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
& ~(0x3f)) / 64;
rinfo->bpp = mode->bits_per_pixel;
+ rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
+ rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
+
if (freq > rinfo->pll.ppll_max)
freq = rinfo->pll.ppll_max;
if (freq*12 < rinfo->pll.ppll_min)
(rinfo->ram.rloop << 20));
newmode.dda_on_off = (ron << 16) | roff;
+ if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
+ int hRatio, vRatio;
+
+ if ((rinfo->panel_xres == 0) || (rinfo->panel_yres == 0)) {
+ hRatio = vRatio = 1;
+ } else {
+ if (mode->xres > rinfo->panel_xres)
+ mode->xres = rinfo->panel_xres;
+ if (mode->yres > rinfo->panel_yres)
+ mode->yres = rinfo->panel_yres;
+
+ hRatio = mode->xres / rinfo->panel_xres;
+ vRatio = mode->yres / rinfo->panel_yres;
+ }
+
+ if (hRatio == 1) {
+ newmode.fp_horz_stretch =
+ rinfo->init_state.fp_horz_stretch;
+ newmode.fp_horz_stretch &= ~(HORZ_STRETCH_BLEND |
+ HORZ_STRETCH_ENABLE);
+ } else {
+ newmode.fp_horz_stretch =
+ ((((unsigned long)(hRatio * HORZ_STRETCH_RATIO_MAX +
+ (int)0.5)) & HORZ_STRETCH_RATIO_MASK)) |
+ (rinfo->init_state.fp_horz_stretch &
+ (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
+ HORZ_AUTO_RATIO_INC));
+ newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
+ HORZ_STRETCH_ENABLE);
+ }
+ newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
+
+ if (vRatio == 1) {
+ newmode.fp_vert_stretch =
+ rinfo->init_state.fp_vert_stretch;
+ newmode.fp_vert_stretch &= ~(VERT_STRETCH_BLEND |
+ VERT_STRETCH_ENABLE);
+ } else {
+ newmode.fp_vert_stretch =
+ ((((unsigned long)(vRatio * VERT_STRETCH_RATIO_MAX +
+ (int)0.5)) & VERT_STRETCH_RATIO_MASK)) |
+ (rinfo->init_state.fp_vert_stretch &
+ (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED));
+ newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
+ VERT_STRETCH_ENABLE);
+ }
+ newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
+
+ newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
+ ~(FP_SEL_CRTC2 |
+ FP_RMX_HVSYNC_CONTROL_EN |
+ FP_DFP_SYNC_SEL |
+ FP_CRT_SYNC_SEL |
+ FP_CRTC_LOCK_8DOT |
+ FP_USE_SHADOW_EN |
+ FP_CRTC_USE_SHADOW_VEND |
+ FP_CRT_SYNC_ALT));
+ newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
+ FP_CRTC_DONT_SHADOW_HEND);
+
+ newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
+ newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
+ newmode.tmds_crc = rinfo->init_state.tmds_crc;
+
+ newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
+
+ if (primary_mon == MT_LCD) {
+ newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
+ newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
+ } else {
+ /* DFP */
+ newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
+ }
+
+ newmode.fp_crtc_h_total_disp =
+ rinfo->init_state.fp_crtc_h_total_disp;
+ newmode.fp_crtc_v_total_disp =
+ rinfo->init_state.fp_crtc_v_total_disp;
+ newmode.fp_h_sync_strt_wid =
+ rinfo->init_state.fp_h_sync_strt_wid;
+ newmode.fp_v_sync_strt_wid =
+ rinfo->init_state.fp_v_sync_strt_wid;
+ }
+
/* do it! */
radeon_write_mode (rinfo, &newmode);
}
-
static void radeon_write_mode (struct radeonfb_info *rinfo,
struct radeon_regs *mode)
{
int i;
+ int primary_mon = PRIMARY_MONITOR(rinfo);
/* blank screen */
OUTREG8(CRTC_EXT_CNTL + 1, 4);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, 0);
OUTREG(CRTC_PITCH, mode->crtc_pitch);
+#if 1
+ printk("CRTC_H_TOTAL_DISP = 0x%x, H_SYNC = 0x%x\n",
+ mode->crtc_h_total_disp, mode->crtc_h_sync_strt_wid);
+ printk("CRTC_V_TOTAL_DISP = 0x%x, V_SYNC = 0x%x\n",
+ mode->crtc_v_total_disp, mode->crtc_v_sync_strt_wid);
+ printk("PPLL_DIV_3 = 0x%x, PPLL_REF_DIV = 0x%x\n",
+ mode->ppll_div_3, mode->ppll_ref_div);
+ printk("DDA_CONFIG = 0x%x, DDA_ON_OFF = 0x%x\n",
+ mode->dda_config, mode->dda_on_off);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ OUTREG(SURFACE_CNTL, mode->surface_cntl);
+#endif
while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
PPLL_DIV_SEL_MASK) {
OUTREG(DDA_CONFIG, mode->dda_config);
OUTREG(DDA_ON_OFF, mode->dda_on_off);
+ if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
+ OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
+ OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
+ OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
+ OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
+ OUTREG(TMDS_CRC, mode->tmds_crc);
+ OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
+ OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
+ OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
+
+ if (primary_mon == MT_LCD) {
+ unsigned int tmp = INREG(LVDS_GEN_CNTL);
+
+ if ((tmp & (LVDS_ON | LVDS_BLON)) ==
+ (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)))
+ OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
+ } else {
+ /* DVI */
+ if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
+ udelay(1000);
+ OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
+ } else {
+ OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
+ LVDS_BLON);
+ udelay(1000);
+ OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
+ }
+ }
+ }
+
/* unblank screen */
OUTREG8(CRTC_EXT_CNTL + 1, 0);
static struct display_switch fbcon_radeon8 = {
setup: fbcon_cfb8_setup,
bmove: fbcon_radeon_bmove,
- clear: fbcon_cfb8_clear,
+ clear: fbcon_radeon_clear,
putc: fbcon_cfb8_putc,
putcs: fbcon_cfb8_putcs,
revc: fbcon_cfb8_revc,
* - We don't limit the CPU clock rate nor the mode selection
* according to the available SDRAM bandwidth.
*
+ * Other notes:
+ * - Linear grayscale palettes and the kernel.
+ * Such code does not belong in the kernel. The kernel frame buffer
+ * drivers do not expect a linear colourmap, but a colourmap based on
+ * the VT100 standard mapping.
+ *
+ * If your _userspace_ requires a linear colourmap, then the setup of
+ * such a colourmap belongs _in userspace_, not in the kernel. Code
+ * to set the colourmap correctly from user space has been sent to
+ * David Neuer. It's around 8 lines of C code, plus another 4 to
+ * detect if we are using grayscale.
*
* Code Status:
* 1999/04/01:
*
* 2001/07/27: <rmk@arm.linux.org.uk>
* - Halve YRES on dual scan LCDs.
+ *
+ * 2001/08/22: <rmk@arm.linux.org.uk>
+ * - Add b/w iPAQ pixclock value.
+ *
+ * 2001/10/12: <rmk@arm.linux.org.uk>
+ * - Add patch 681/1 and clean up stork definitions.
*/
#include <linux/config.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/uaccess.h>
+#include <asm/arch/assabet.h>
#include <video/fbcon.h>
#include <video/fbcon-mfb.h>
/*
* These machines are good machines!
*/
- if (machine_is_assabet() || machine_is_bitsy())
+ if (machine_is_assabet() || machine_is_h3600())
return;
/*
LCCR3_PixRsEdg + LCCR3_VrtSnchH +
LCCR3_HorSnchH + LCCR3_ACBsCntOff + LCCR3_ACBsDiv(2);
}
-#ifdef CONFIG_SA1100_CERF
- if (machine_is_cerf()) {
- DPRINTK("Configuring Cerf LCD\n");
-#if defined (CONFIG_CERF_LCD_72_A)
- shadow.lccr0 =
- LCCR0_LEN + LCCR0_Color + LCCR0_Dual +
- LCCR0_LDM + LCCR0_BAM + LCCR0_ERM + LCCR0_Pas +
- LCCR0_LtlEnd + LCCR0_DMADel(0);
- shadow.lccr1 =
- LCCR1_DisWdth(var->xres) + LCCR1_HorSnchWdth(5) +
- LCCR1_BegLnDel(61) + LCCR1_EndLnDel(9);
- shadow.lccr2 =
- LCCR2_DisHght(var->yres / 2) + LCCR2_VrtSnchWdth(1) +
- LCCR2_BegFrmDel(3) + LCCR2_EndFrmDel(0);
- shadow.lccr3 =
- LCCR3_OutEnH + LCCR3_PixRsEdg + LCCR3_VrtSnchH +
- LCCR3_HorSnchH + LCCR3_ACBsCntOff +
- LCCR3_ACBsDiv(2) + LCCR3_PixClkDiv(38);
-#elif defined (CONFIG_CERF_LCD_57_A)
- shadow.lccr0 =
- LCCR0_LEN + LCCR0_Color + LCCR0_Sngl +
- LCCR0_LDM + LCCR0_BAM + LCCR0_ERM + LCCR0_Pas +
- LCCR0_LtlEnd + LCCR0_DMADel(0);
- shadow.lccr1 =
- LCCR1_DisWdth(var->xres) + LCCR1_HorSnchWdth(5) +
- LCCR1_BegLnDel(61) + LCCR1_EndLnDel(9);
- shadow.lccr2 =
- LCCR2_DisHght(var->yres) + LCCR2_VrtSnchWdth(1) +
- LCCR2_BegFrmDel(3) + LCCR2_EndFrmDel(0);
- shadow.lccr3 =
- LCCR3_OutEnH + LCCR3_PixRsEdg + LCCR3_VrtSnchH +
- LCCR3_HorSnchH + LCCR3_ACBsCntOff +
- LCCR3_ACBsDiv(2) + LCCR3_PixClkDiv(38);
-#elif defined (CONFIG_CERF_LCD_38_A)
- shadow.lccr0 =
- LCCR0_LEN + LCCR0_Color + LCCR0_Sngl +
- LCCR0_LDM + LCCR0_BAM + LCCR0_ERM + LCCR0_Pas +
- LCCR0_LtlEnd + LCCR0_DMADel(0);
- shadow.lccr1 =
- LCCR1_DisWdth(var->xres) + LCCR1_HorSnchWdth(5) +
- LCCR1_BegLnDel(61) + LCCR1_EndLnDel(9);
- shadow.lccr2 =
- LCCR2_DisHght(var->yres) + LCCR2_VrtSnchWdth(1) +
- LCCR2_BegFrmDel(3) + LCCR2_EndFrmDel(0);
- shadow.lccr3 =
- LCCR3_OutEnH + LCCR3_PixRsEdg + LCCR3_VrtSnchH +
- LCCR3_HorSnchH + LCCR3_ACBsCntOff +
- LCCR3_ACBsDiv(2) + LCCR3_PixClkDiv(38);
-#else
-#error "Must have a CerfBoard LCD form factor selected"
-#endif
- }
-#endif
if (machine_is_lart()) {
DPRINTK("Configuring LART LCD\n");
#if defined LART_GREY_LCD
};
#ifdef CONFIG_SA1100_ASSABET
-static struct sa1100fb_mach_info assabet_info __initdata = {
-#ifdef ASSABET_PAL_VIDEO
+#ifndef ASSABET_PAL_VIDEO
+/*
+ * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
+ * takes an RGB666 signal, but we provide it with an RGB565 signal
+ * instead (def_rgb_16).
+ */
+static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
+ pixclock: 171521, bpp: 16,
+ xres: 320, yres: 240,
+
+ hsync_len: 5, vsync_len: 1,
+ left_margin: 61, upper_margin: 3,
+ right_margin: 9, lower_margin: 0,
+
+ sync: FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+ lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+ lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
+};
+#else
+static struct sa1100fb_mach_info pal_info __initdata = {
pixclock: 67797, bpp: 16,
xres: 640, yres: 512,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
-#else
- pixclock: 171521, bpp: 16,
- xres: 320, yres: 240,
-
- hsync_len: 5, vsync_len: 1,
- left_margin: 61, upper_margin: 3,
- right_margin: 9, lower_margin: 0,
-
- sync: FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
-#endif
};
#endif
+#endif
-#ifdef CONFIG_SA1100_BITSY
-static struct sa1100fb_mach_info bitsy_info __initdata = {
+#ifdef CONFIG_SA1100_H3600
+static struct sa1100fb_mach_info h3600_info __initdata = {
#ifdef CONFIG_IPAQ_H3100
- pixclock: 0, bpp: 4,
+ pixclock: 407766, bpp: 4,
xres: 320, yres: 240,
hsync_len: 26, vsync_len: 41,
lccr0: LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
-#error FIXME
- /*
- * Sorry, this should have read:
- * FIXME: please get rid of the PCD and PixClkDiv definitions
- * in favour of pixclock. --rmk
- */
#else
- pixclock: 5722222, bpp: 16,
+ pixclock: 174757, bpp: 16,
xres: 320, yres: 240,
hsync_len: 3, vsync_len: 3,
#endif
};
-static struct sa1100fb_rgb bitsy_rgb_16 = {
+static struct sa1100fb_rgb h3600_rgb_16 = {
red: { offset: 12, length: 4, },
green: { offset: 7, length: 4, },
blue: { offset: 1, length: 4, },
#ifdef CONFIG_SA1100_CERF
static struct sa1100fb_mach_info cerf_info __initdata = {
- pixclock: 171521, bpp: 8,
#if defined(CONFIG_CERF_LCD_72_A)
+ pixclock: 171521, bpp: 8,
xres: 640, yres: 480,
lccr0: LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
LCCR3_PixClkDiv(38),
#elif defined(CONFIG_CERF_LCD_57_A)
+ pixclock: 171521, bpp: 8,
xres: 320, yres: 240,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
LCCR3_PixClkDiv(38),
#elif defined(CONFIG_CERF_LCD_38_A)
+ pixclock: 171521, bpp: 8,
xres: 240, yres: 320,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Pas,
- lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
+ lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(56) |
+ LCCR3_PixClkDiv(38),
+#elif defined(CONFIG_CERF_LCD_38_B)
+ pixclock: 171521, bpp: 4,
+ xres: 320, yres: 240,
+ lccr0: LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
+ lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(56) |
LCCR3_PixClkDiv(38),
#else
#error "Must have a CerfBoard LCD form factor selected"
sync: FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};
+
+#if 0
+static struct sa1100fb_rgb cerf_rgb_16 = {
+ red: { offset: 8, length: 4, },
+ green: { offset: 4, length: 4, },
+ blue: { offset: 0, length: 4, },
+ transp: { offset: 0, length: 0, },
+};
+#endif
#endif
#ifdef CONFIG_SA1100_FREEBIRD
#ifdef CONFIG_SA1100_GRAPHICSCLIENT
static struct sa1100fb_mach_info graphicsclient_info __initdata = {
- pixclock: 0, bpp: 8,
+ pixclock: 53500, bpp: 8,
xres: 640, yres: 480,
hsync_len: 9, vsync_len: 9,
sync: 0,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2) |
- LCCR3_PixClkDiv(10),
+ lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
};
#endif
};
#endif
+#ifdef CONFIG_SA1100_STORK
+#if STORK_TFT /* ie the NEC TFT */
+/*
+ * pixclock is ps per clock. say 72Hz, 800x600 clocks => (1/72)/(800*600)
+ * = 28935 and a bit
+ * NB likely to be increased to ease bus timings wrt pcmcia interface
+ */
+static struct sa1100fb_mach_info stork_tft_info __initdata = {
+ pixclock: 28935, bpp: 16,
+ xres: 640, yres: 480,
+
+ hsync_len: 64, vsync_len: 2,
+ left_margin: 48, upper_margin: 12,
+ right_margin: 48, lower_margin: 31,
+
+ sync: 0,
+
+ lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+ lccr3: LCCR3_OutEnH | LCCR3_PixRsEdg,
+};
+
+static struct sa1100fb_rgb stork_tft_rgb_16 = {
+ red: { offset: 11, length: 5, },
+ green: { offset: 5, length: 6, },
+ blue: { offset: 0, length: 5, },
+ transp: { offset: 0, length: 0, },
+};
+
+#else /* Kyocera DSTN */
+
+static struct sa1100fb_mach_info stork_dstn_info __initdata = {
+ pixclock: 0, bpp: 16,
+ xres: 640, yres: 480,
+
+ hsync_len: 2, vsync_len: 2,
+ left_margin: 2, upper_margin: 0,
+ right_margin: 2, lower_margin: 0,
+
+ sync: FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT ,
+
+ lccr0: LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
+#error Fixme
+ lccr3: 0xff00 |
+ 0x18 /* ought to be 0x14 but DMA isn't up to that as yet */
+};
+
+static struct sa1100fb_rgb stork_dstn_rgb_16 = {
+ red: { offset: 8, length: 4, },
+ green: { offset: 4, length: 4, },
+ blue: { offset: 0, length: 4, },
+ transp: { offset: 0, length: 0, },
+};
+#endif
+#endif
+
#ifdef CONFIG_SA1100_XP860
static struct sa1100fb_mach_info xp860_info __initdata = {
pixclock: 0, bpp: 8,
};
#endif
+
+
static struct sa1100fb_mach_info * __init
sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
{
/*
* R G B T
* default {11,5}, { 5,6}, { 0,5}, { 0,0}
- * bitsy {12,4}, { 7,4}, { 1,4}, { 0,0}
+ * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
* freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
*/
#ifdef CONFIG_SA1100_ASSABET
if (machine_is_assabet()) {
- inf = &assabet_info;
+#ifndef ASSABET_PAL_VIDEO
+ inf = &lq039q2ds54_info;
+#else
+ inf = &pal_info;
+#endif
}
#endif
-#ifdef CONFIG_SA1100_BITSY
- if (machine_is_bitsy()) {
- inf = &bitsy_info;
- fbi->rgb[RGB_16] = &bitsy_rgb_16;
+#ifdef CONFIG_SA1100_H3600
+ if (machine_is_h3600()) {
+ inf = &h3600_info;
+ fbi->rgb[RGB_16] = &h3600_rgb_16;
}
#endif
#ifdef CONFIG_SA1100_BRUTUS
if (machine_is_xp860()) {
inf = &xp860_info;
}
+#endif
+#ifdef CONFIG_SA1100_STORK
+ if (machine_is_stork()) {
+#if STORK_TFT
+ inf = &stork_tft_info;
+ fbi->rgb[RGB_16] = &stork_tft_rgb_16;
+#else
+ inf = &stork_dstn_info;
+ fbi->rgb[RGB_16] = &stork_dstn_rgb_16;
+#endif
+ }
#endif
return inf;
}
break;
}
- printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz",
+#ifdef CONFIG_CPU_FREQ
+ printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
sa1100fb_display_dma_period(var),
cpufreq_get(smp_processor_id()));
+#endif
return ret;
}
static inline void sa1100fb_set_truecolor(u_int is_true_color)
{
DPRINTK("true_color = %d\n", is_true_color);
-#ifdef CONFIG_SA1100_ASSABET
+
if (machine_is_assabet()) {
#if 1
// phase 4 or newer Assabet's
if (is_true_color)
- BCR_set(BCR_LCD_12RGB);
+ ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
else
- BCR_clear(BCR_LCD_12RGB);
+ ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
#else
// older Assabet's
if (is_true_color)
- BCR_clear(BCR_LCD_12RGB);
+ ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
else
- BCR_set(BCR_LCD_12RGB);
+ ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
#endif
}
-#endif
}
static void
/*
* sa1100fb_activate_var():
* Configures LCD Controller based on entries in var parameter. Settings are
- * only written to the controller if changes were made.
+ * only written to the controller if changes were made.
*/
static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
{
*/
if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
(LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
- (DBAR1 != (Address) fbi->dbar1) || (DBAR2 != (Address) fbi->dbar2))
+ (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
sa1100fb_schedule_task(fbi, C_REENABLE);
return 0;
if (machine_is_omnimeter())
LEDBacklightOn();
#endif
-#ifdef CONFIG_SA1100_BITSY
- /* what rmk said --dneuer */
-#endif
}
/*
if (machine_is_omnimeter())
LEDBacklightOff();
#endif
-#ifdef CONFIG_SA1100_BITSY
- /* what rmk said --dneuer */
-#endif
}
static void sa1100fb_power_up_lcd(struct sa1100fb_info *fbi)
{
DPRINTK("LCD power on\n");
-#if defined(CONFIG_SA1100_ASSABET) && !defined(ASSABET_PAL_VIDEO)
+#ifndef ASSABET_PAL_VIDEO
if (machine_is_assabet())
- BCR_set(BCR_LCD_ON);
+ ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
#endif
#ifdef CONFIG_SA1100_HUW_WEBPANEL
if (machine_is_huw_webpanel())
if (machine_is_omnimeter())
LCDPowerOn();
#endif
-#ifdef CONFIG_SA1100_BITSY
- if (machine_is_bitsy()) {
- set_bitsy_egpio(EGPIO_BITSY_LCD_ON |
- EGPIO_BITSY_LCD_PCI |
- EGPIO_BITSY_LCD_5V_ON |
- EGPIO_BITSY_LVDD_ON);
+#ifdef CONFIG_SA1100_H3600
+ if (machine_is_h3600()) {
+ set_h3600_egpio(EGPIO_H3600_LCD_ON |
+ EGPIO_H3600_LCD_PCI |
+ EGPIO_H3600_LCD_5V_ON |
+ EGPIO_H3600_LVDD_ON);
}
#endif
+#ifdef CONFIG_SA1100_STORK
+ if (machine_is_stork()) {
+ storkSetLCDCPLD(0, 1);
+ storkSetLatchA(STORK_LCD_BACKLIGHT_INVERTER_ON);
+ }
+#endif
}
static void sa1100fb_power_down_lcd(struct sa1100fb_info *fbi)
{
DPRINTK("LCD power off\n");
-#if defined(CONFIG_SA1100_ASSABET) && !defined(ASSABET_PAL_VIDEO)
+#ifndef ASSABET_PAL_VIDEO
if (machine_is_assabet())
- BCR_clear(BCR_LCD_ON);
+ ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
#endif
#ifdef CONFIG_SA1100_HUW_WEBPANEL
// dont forget to set the control lines to zero (?)
if (machine_is_huw_webpanel())
BCR_set(BCR_TFT_NPWR);
#endif
-#ifdef CONFIG_SA1100_BITSY
- if (machine_is_bitsy()) {
- clr_bitsy_egpio(EGPIO_BITSY_LCD_ON |
- EGPIO_BITSY_LCD_PCI |
- EGPIO_BITSY_LCD_5V_ON |
- EGPIO_BITSY_LVDD_ON);
+#ifdef CONFIG_SA1100_H3600
+ if (machine_is_h3600()) {
+ clr_h3600_egpio(EGPIO_H3600_LCD_ON |
+ EGPIO_H3600_LCD_PCI |
+ EGPIO_H3600_LCD_5V_ON |
+ EGPIO_H3600_LVDD_ON);
+ }
+#endif
+#ifdef CONFIG_SA1100_STORK
+ if (machine_is_stork()) {
+ storkSetLCDCPLD(0, 0);
+ storkClearLatchA(STORK_LCD_BACKLIGHT_INVERTER_ON);
}
#endif
}
GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
}
#endif
-#ifdef CONFIG_SA1100_CERF
-#error Please contact <rmk@arm.linux.org.uk> about this
if (machine_is_cerf()) {
/* GPIO15 is used as a bypass for 3.8" displays */
mask |= GPIO_GPIO15;
-
+#ifdef CONFIG_SA1100_CERF
+#warning Read Me Now!
+#endif
+#if 0 /* if this causes you problems, mail <rmk@arm.linux.org.uk> please. */
+ /*
+ * This was enabled for the 72_A version only, which is a _color_
+ * _dual_ LCD. Now look at the generic test above, and calculate
+ * the mask value for a colour dual display...
+ *
+ * I therefore conclude that the code below is redundant, and will
+ * be killed at the start of November 2001.
+ */
/* FIXME: why is this? The Cerf's display doesn't seem
* to be dual scan or active. I just leave it here,
* but in my opinion this is definitively wrong.
/* color {dual/single} passive */
mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
- }
#endif
+ }
if (mask) {
GPDR |= mask;
LCCR2 = fbi->reg_lccr2;
LCCR1 = fbi->reg_lccr1;
LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
- DBAR1 = (Address) fbi->dbar1;
- DBAR2 = (Address) fbi->dbar2;
+ DBAR1 = fbi->dbar1;
+ DBAR2 = fbi->dbar2;
LCCR0 |= LCCR0_LEN;
#ifdef CONFIG_SA1100_GRAPHICSCLIENT
/*
* Ok, calculate its DMA period
*/
- period = sa1100fb_display_dma_period(get_con_var(fbi, i));
+ period = sa1100fb_display_dma_period(get_con_var(&fbi->fb, i));
if (period < min_period)
min_period = period;
}
ret = request_irq(IRQ_LCD, sa1100fb_handle_irq, SA_INTERRUPT,
fbi->fb.fix.id, fbi);
if (ret) {
- printk(KERN_ERR "sa1100fb: failed in request_irq: %d\n", ret);
+ printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
goto failed;
}
-#if defined(CONFIG_SA1100_ASSABET) && defined(ASSABET_PAL_VIDEO)
+#ifdef ASSABET_PAL_VIDEO
if (machine_is_assabet())
- BCR_clear(BCR_LCD_ON);
+ ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
#endif
#ifdef CONFIG_SA1100_FREEBIRD
return 0;
}
+MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
MODULE_LICENSE("GPL");
/* Shadows for LCD controller registers */
struct sa1100fb_lcd_reg {
- Word lccr0;
- Word lccr1;
- Word lccr2;
- Word lccr3;
+ unsigned long lccr0;
+ unsigned long lccr1;
+ unsigned long lccr2;
+ unsigned long lccr3;
};
#define RGB_8 (0)
#include <linux/fs.h>
#include <asm/io.h>
-#include <asm/mtrr.h>
#include <video/fbcon.h>
#include <video/fbcon-cfb8.h>
*/
static rwlock_t adfs_map_lock;
+#define GET_FRAG_ID(_map,_start,_idmask) \
+ ({ \
+ unsigned long _v2, _frag; \
+ unsigned int _tmp; \
+ _tmp = _start >> 5; \
+ _frag = le32_to_cpu(_map[_tmp]); \
+ _v2 = le32_to_cpu(_map[_tmp + 1]); \
+ _tmp = start & 31; \
+ _frag = (_frag >> _tmp) | (_v2 << (32 - _tmp)); \
+ _frag & _idmask; \
+ })
+
/*
* return the map bit offset of the fragment frag_id in
* the zone dm.
do {
unsigned long frag;
- /*
- * get fragment id
- */
- {
- unsigned long v2;
- unsigned int tmp;
-
- tmp = start >> 5;
-
- frag = le32_to_cpu(map[tmp]);
- v2 = le32_to_cpu(map[tmp + 1]);
-
- tmp = start & 31;
-
- frag = (frag >> tmp) | (v2 << (32 - tmp));
-
- frag &= idmask;
- }
-
+ frag = GET_FRAG_ID(map, start, idmask);
mapptr = start + idlen;
/*
/*
* get fragment id
*/
- {
- unsigned long v2;
- unsigned int tmp;
-
- tmp = start >> 5;
-
- frag = le32_to_cpu(map[tmp]);
- v2 = le32_to_cpu(map[tmp + 1]);
-
- tmp = start & 31;
-
- frag = (frag >> tmp) | (v2 << (32 - tmp));
-
- frag &= idmask;
- }
+ frag = GET_FRAG_ID(map, start, idmask);
/*
* If the freelink is null, then no free fragments
/*
* get fragment id
*/
- {
- unsigned long v2;
- unsigned int tmp;
-
- tmp = start >> 5;
-
- frag = le32_to_cpu(map[tmp]);
- v2 = le32_to_cpu(map[tmp + 1]);
-
- tmp = start & 31;
-
- frag = (frag >> tmp) | (v2 << (32 - tmp));
-
- frag &= idmask;
- }
-
+ frag = GET_FRAG_ID(map, start, idmask);
mapptr = start + idlen;
/*
va_end(args);
printk(KERN_CRIT "ADFS-fs error (device %s)%s%s: %s\n",
- kdevname(sb->s_dev), function ? ": " : "",
+ bdevname(sb->s_dev), function ? ": " : "",
function ? function : "", error_buf);
}
if (adfs_checkbblk(b_data)) {
if (!silent)
printk("VFS: Can't find an adfs filesystem on dev "
- "%s.\n", kdevname(dev));
+ "%s.\n", bdevname(dev));
goto error_free_bh;
}
if (adfs_checkdiscrecord(dr)) {
if (!silent)
printk("VPS: Can't find an adfs filesystem on dev "
- "%s.\n", kdevname(dev));
+ "%s.\n", bdevname(dev));
goto error_free_bh;
}
if (sb->s_blocksize != bh->b_size) {
if (!silent)
printk(KERN_ERR "VFS: Unsupported blocksize on dev "
- "%s.\n", kdevname(dev));
+ "%s.\n", bdevname(dev));
goto error_free_bh;
}
bdev->bd_op = get_blkfops(MAJOR(dev));
if (bdev->bd_op) {
ret = 0;
+ if (bdev->bd_op->owner)
+ __MOD_INC_USE_COUNT(bdev->bd_op->owner);
if (bdev->bd_op->open)
ret = bdev->bd_op->open(inode, file);
if (!ret) {
bdev->bd_openers++;
bdev->bd_inode->i_size = blkdev_size(dev);
bdev->bd_inode->i_blkbits = blksize_bits(block_size(dev));
- } else if (!bdev->bd_openers)
- bdev->bd_op = NULL;
+ } else {
+ if (bdev->bd_op->owner)
+ __MOD_DEC_USE_COUNT(bdev->bd_op->owner);
+ if (!bdev->bd_openers)
+ bdev->bd_op = NULL;
+ }
}
unlock_kernel();
up(&bdev->bd_sem);
kill_bdev(bdev);
if (bdev->bd_op->release)
ret = bdev->bd_op->release(bd_inode, NULL);
+ if (bdev->bd_op->owner)
+ __MOD_DEC_USE_COUNT(bdev->bd_op->owner);
if (!bdev->bd_openers)
bdev->bd_op = NULL;
unlock_kernel();
O_TARGET := cramfs.o
-obj-y := inode.o uncompress.o inflate/zlib.o
+obj-y := inode.o uncompress.o
obj-m := $(O_TARGET)
-include $(TOPDIR)/Rules.make
+CFLAGS_uncompress.o := -I $(TOPDIR)/fs/inflate_fs
-inflate/zlib.o:
- make -C inflate
+include $(TOPDIR)/Rules.make
+++ /dev/null
-#
-# inflate/Makefile
-#
-#
-# NOTE NOTE NOTE!
-#
-# This code is basically a bastardized version of the zlib
-# library uncompression. It avoids dynamic allocations at
-# all cost, and is cut down in other ways too, to make it
-# simpler and more specialized. If you want to get the real
-# thing, don't look here.
-#
-# The simplifications mean that this version of the library
-# (unlike the real lib) is completely single-threaded, and
-# you cannot do multiple uncompressions at a time. You can
-# ONLY use it to uncompress a single block, with both the
-# source and the destination completely in memory. In SMP
-# environments, the uncompression has to be protected by
-# some lock to guarantee single-threaded access to the static
-# data structures used for inflation.
-#
-# You have been warned.
-#
-# (The upsides of the simplification is that you can't get in
-# any nasty situations wrt memory management, and that the
-# uncompression can be done without blocking on allocation).
-#
-
-O_TARGET := zlib.o
-
-obj-y := adler32.o infblock.o infcodes.o inffast.o inflate.o \
- inftrees.o infutil.o uncompr.o
-
-include $(TOPDIR)/Rules.make
+++ /dev/null
-/* adler32.c -- compute the Adler-32 checksum of a data stream
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* @(#) $Id$ */
-
-#include "zlib.h"
-
-#define BASE 65521L /* largest prime smaller than 65536 */
-#define NMAX 5552
-/* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
-
-#define DO1(buf,i) {s1 += buf[i]; s2 += s1;}
-#define DO2(buf,i) DO1(buf,i); DO1(buf,i+1);
-#define DO4(buf,i) DO2(buf,i); DO2(buf,i+2);
-#define DO8(buf,i) DO4(buf,i); DO4(buf,i+4);
-#define DO16(buf) DO8(buf,0); DO8(buf,8);
-
-/* ========================================================================= */
-uLong ZEXPORT cramfs_adler32(adler, buf, len)
- uLong adler;
- const Bytef *buf;
- uInt len;
-{
- unsigned long s1 = adler & 0xffff;
- unsigned long s2 = (adler >> 16) & 0xffff;
- int k;
-
- if (buf == Z_NULL) return 1L;
-
- while (len > 0) {
- k = len < NMAX ? len : NMAX;
- len -= k;
- while (k >= 16) {
- DO16(buf);
- buf += 16;
- k -= 16;
- }
- if (k != 0) do {
- s1 += *buf++;
- s2 += s1;
- } while (--k);
- s1 %= BASE;
- s2 %= BASE;
- }
- return (s2 << 16) | s1;
-}
+++ /dev/null
-/* infblock.c -- interpret and process block types to last block
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "infblock.h"
-#include "inftrees.h"
-#include "infcodes.h"
-#include "infutil.h"
-
-struct inflate_codes_state {int dummy;}; /* for buggy compilers */
-
-/* simplify the use of the inflate_huft type with some defines */
-#define exop word.what.Exop
-#define bits word.what.Bits
-
-/* Table for deflate from PKZIP's appnote.txt. */
-local const uInt border[] = { /* Order of the bit length code lengths */
- 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15};
-
-/*
- Notes beyond the 1.93a appnote.txt:
-
- 1. Distance pointers never point before the beginning of the output
- stream.
- 2. Distance pointers can point back across blocks, up to 32k away.
- 3. There is an implied maximum of 7 bits for the bit length table and
- 15 bits for the actual data.
- 4. If only one code exists, then it is encoded using one bit. (Zero
- would be more efficient, but perhaps a little confusing.) If two
- codes exist, they are coded using one bit each (0 and 1).
- 5. There is no way of sending zero distance codes--a dummy must be
- sent if there are none. (History: a pre 2.0 version of PKZIP would
- store blocks with no distance codes, but this was discovered to be
- too harsh a criterion.) Valid only for 1.93a. 2.04c does allow
- zero distance codes, which is sent as one code of zero bits in
- length.
- 6. There are up to 286 literal/length codes. Code 256 represents the
- end-of-block. Note however that the static length tree defines
- 288 codes just to fill out the Huffman codes. Codes 286 and 287
- cannot be used though, since there is no length base or extra bits
- defined for them. Similarily, there are up to 30 distance codes.
- However, static trees define 32 codes (all 5 bits) to fill out the
- Huffman codes, but the last two had better not show up in the data.
- 7. Unzip can check dynamic Huffman blocks for complete code sets.
- The exception is that a single code would not be complete (see #4).
- 8. The five bits following the block type is really the number of
- literal codes sent minus 257.
- 9. Length codes 8,16,16 are interpreted as 13 length codes of 8 bits
- (1+6+6). Therefore, to output three times the length, you output
- three codes (1+1+1), whereas to output four times the same length,
- you only need two codes (1+3). Hmm.
- 10. In the tree reconstruction algorithm, Code = Code + Increment
- only if BitLength(i) is not zero. (Pretty obvious.)
- 11. Correction: 4 Bits: # of Bit Length codes - 4 (4 - 19)
- 12. Note: length code 284 can represent 227-258, but length code 285
- really is 258. The last length deserves its own, short code
- since it gets used a lot in very redundant files. The length
- 258 is special since 258 - 3 (the min match length) is 255.
- 13. The literal/length and distance code bit lengths are read as a
- single stream of lengths. It is possible (and advantageous) for
- a repeat code (16, 17, or 18) to go across the boundary between
- the two sets of lengths.
- */
-
-
-void cramfs_inflate_blocks_reset(s, z, c)
-inflate_blocks_statef *s;
-z_streamp z;
-uLongf *c;
-{
- if (c != Z_NULL)
- *c = s->check;
- if (s->mode == CODES)
- cramfs_inflate_codes_free(s->sub.decode.codes, z);
- s->mode = TYPE;
- s->bitk = 0;
- s->bitb = 0;
- s->read = s->write = s->window;
- if (s->checkfn != Z_NULL)
- z->adler = s->check = (*s->checkfn)(0L, (const Bytef *)Z_NULL, 0);
-}
-
-
-inflate_blocks_statef *cramfs_inflate_blocks_new(z, c, w)
-z_streamp z;
-check_func c;
-uInt w;
-{
- inflate_blocks_statef *s;
- static struct inflate_blocks_state working_blocks_state;
- static inflate_huft working_hufts[MANY];
- static unsigned char working_window[1 << MAX_WBITS];
-
- s = &working_blocks_state;
- s->hufts = working_hufts;
- s->window = working_window;
- s->end = s->window + w;
- s->checkfn = c;
- s->mode = TYPE;
- cramfs_inflate_blocks_reset(s, z, Z_NULL);
- return s;
-}
-
-
-int cramfs_inflate_blocks(s, z, r)
-inflate_blocks_statef *s;
-z_streamp z;
-int r;
-{
- uInt t; /* temporary storage */
- uLong b; /* bit buffer */
- uInt k; /* bits in bit buffer */
- Bytef *p; /* input data pointer */
- uInt n; /* bytes available there */
- Bytef *q; /* output window write pointer */
- uInt m; /* bytes to end of window or read pointer */
-
- /* copy input/output information to locals (UPDATE macro restores) */
- LOAD
-
- /* process input based on current state */
- while (1) switch (s->mode)
- {
- case TYPE:
- NEEDBITS(3)
- t = (uInt)b & 7;
- s->last = t & 1;
- switch (t >> 1)
- {
- case 0: /* stored */
- DUMPBITS(3)
- t = k & 7; /* go to byte boundary */
- DUMPBITS(t)
- s->mode = LENS; /* get length of stored block */
- break;
- case 1: /* fixed */
- {
- uInt bl, bd;
- inflate_huft *tl, *td;
-
- cramfs_inflate_trees_fixed(&bl, &bd, &tl, &td, z);
- s->sub.decode.codes = cramfs_inflate_codes_new(bl, bd, tl, td, z);
- if (s->sub.decode.codes == Z_NULL)
- {
- r = Z_MEM_ERROR;
- LEAVE
- }
- }
- DUMPBITS(3)
- s->mode = CODES;
- break;
- case 2: /* dynamic */
- DUMPBITS(3)
- s->mode = TABLE;
- break;
- case 3: /* illegal */
- DUMPBITS(3)
- s->mode = BAD;
- z->msg = (char*)"invalid block type";
- r = Z_DATA_ERROR;
- LEAVE
- }
- break;
- case LENS:
- NEEDBITS(32)
- if ((((~b) >> 16) & 0xffff) != (b & 0xffff))
- {
- s->mode = BAD;
- z->msg = (char*)"invalid stored block lengths";
- r = Z_DATA_ERROR;
- LEAVE
- }
- s->sub.left = (uInt)b & 0xffff;
- b = k = 0; /* dump bits */
- s->mode = s->sub.left ? STORED : (s->last ? DRY : TYPE);
- break;
- case STORED:
- if (n == 0)
- LEAVE
- NEEDOUT
- t = s->sub.left;
- if (t > n) t = n;
- if (t > m) t = m;
- memcpy(q, p, t);
- p += t; n -= t;
- q += t; m -= t;
- if ((s->sub.left -= t) != 0)
- break;
- s->mode = s->last ? DRY : TYPE;
- break;
- case TABLE:
- NEEDBITS(14)
- s->sub.trees.table = t = (uInt)b & 0x3fff;
-#ifndef PKZIP_BUG_WORKAROUND
- if ((t & 0x1f) > 29 || ((t >> 5) & 0x1f) > 29)
- {
- s->mode = BAD;
- z->msg = (char*)"too many length or distance symbols";
- r = Z_DATA_ERROR;
- LEAVE
- }
-#endif
- {
- static unsigned int working_blens [258 + 0x1f + 0x1f];
- s->sub.trees.blens = working_blens;
- }
- DUMPBITS(14)
- s->sub.trees.index = 0;
- s->mode = BTREE;
- case BTREE:
- while (s->sub.trees.index < 4 + (s->sub.trees.table >> 10))
- {
- NEEDBITS(3)
- s->sub.trees.blens[border[s->sub.trees.index++]] = (uInt)b & 7;
- DUMPBITS(3)
- }
- while (s->sub.trees.index < 19)
- s->sub.trees.blens[border[s->sub.trees.index++]] = 0;
- s->sub.trees.bb = 7;
- t = cramfs_inflate_trees_bits(s->sub.trees.blens, &s->sub.trees.bb,
- &s->sub.trees.tb, s->hufts, z);
- if (t != Z_OK)
- {
- r = t;
- if (r == Z_DATA_ERROR)
- s->mode = BAD;
- LEAVE
- }
- s->sub.trees.index = 0;
- s->mode = DTREE;
- case DTREE:
- while (t = s->sub.trees.table,
- s->sub.trees.index < 258 + (t & 0x1f) + ((t >> 5) & 0x1f))
- {
- inflate_huft *h;
- uInt i, j, c;
-
- t = s->sub.trees.bb;
- NEEDBITS(t)
- h = s->sub.trees.tb + ((uInt)b & cramfs_inflate_mask[t]);
- t = h->bits;
- c = h->base;
- if (c < 16)
- {
- DUMPBITS(t)
- s->sub.trees.blens[s->sub.trees.index++] = c;
- }
- else /* c == 16..18 */
- {
- i = c == 18 ? 7 : c - 14;
- j = c == 18 ? 11 : 3;
- NEEDBITS(t + i)
- DUMPBITS(t)
- j += (uInt)b & cramfs_inflate_mask[i];
- DUMPBITS(i)
- i = s->sub.trees.index;
- t = s->sub.trees.table;
- if (i + j > 258 + (t & 0x1f) + ((t >> 5) & 0x1f) ||
- (c == 16 && i < 1))
- {
- s->mode = BAD;
- z->msg = (char*)"invalid bit length repeat";
- r = Z_DATA_ERROR;
- LEAVE
- }
- c = c == 16 ? s->sub.trees.blens[i - 1] : 0;
- do {
- s->sub.trees.blens[i++] = c;
- } while (--j);
- s->sub.trees.index = i;
- }
- }
- s->sub.trees.tb = Z_NULL;
- {
- uInt bl, bd;
- inflate_huft *tl, *td;
- inflate_codes_statef *c;
-
- bl = 9; /* must be <= 9 for lookahead assumptions */
- bd = 6; /* must be <= 9 for lookahead assumptions */
- t = s->sub.trees.table;
- t = cramfs_inflate_trees_dynamic(257 + (t & 0x1f), 1 + ((t >> 5) & 0x1f),
- s->sub.trees.blens, &bl, &bd, &tl, &td,
- s->hufts, z);
- if (t != Z_OK)
- {
- if (t == (uInt)Z_DATA_ERROR)
- s->mode = BAD;
- r = t;
- LEAVE
- }
- if ((c = cramfs_inflate_codes_new(bl, bd, tl, td, z)) == Z_NULL)
- {
- r = Z_MEM_ERROR;
- LEAVE
- }
- s->sub.decode.codes = c;
- }
- s->mode = CODES;
- case CODES:
- UPDATE
- if ((r = cramfs_inflate_codes(s, z, r)) != Z_STREAM_END)
- return cramfs_inflate_flush(s, z, r);
- r = Z_OK;
- cramfs_inflate_codes_free(s->sub.decode.codes, z);
- LOAD
- if (!s->last)
- {
- s->mode = TYPE;
- break;
- }
- s->mode = DRY;
- case DRY:
- FLUSH
- if (s->read != s->write)
- LEAVE
- s->mode = DONE;
- case DONE:
- r = Z_STREAM_END;
- LEAVE
- case BAD:
- r = Z_DATA_ERROR;
- LEAVE
- default:
- r = Z_STREAM_ERROR;
- LEAVE
- }
-}
-
-
-int cramfs_inflate_blocks_free(s, z)
-inflate_blocks_statef *s;
-z_streamp z;
-{
- cramfs_inflate_blocks_reset(s, z, Z_NULL);
- return Z_OK;
-}
-
-
-void cramfs_inflate_set_dictionary(s, d, n)
-inflate_blocks_statef *s;
-const Bytef *d;
-uInt n;
-{
- memcpy(s->window, d, n);
- s->read = s->write = s->window + n;
-}
-
-
-/* Returns true if inflate is currently at the end of a block generated
- * by Z_SYNC_FLUSH or Z_FULL_FLUSH.
- * IN assertion: s != Z_NULL
- */
-int inflate_blocks_sync_point(s)
-inflate_blocks_statef *s;
-{
- return s->mode == LENS;
-}
+++ /dev/null
-/* infblock.h -- header to use infblock.c
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-struct inflate_blocks_state;
-typedef struct inflate_blocks_state FAR inflate_blocks_statef;
-
-extern inflate_blocks_statef * cramfs_inflate_blocks_new OF((
- z_streamp z,
- check_func c, /* check function */
- uInt w)); /* window size */
-
-extern int cramfs_inflate_blocks OF((
- inflate_blocks_statef *,
- z_streamp ,
- int)); /* initial return code */
-
-extern void cramfs_inflate_blocks_reset OF((
- inflate_blocks_statef *,
- z_streamp ,
- uLongf *)); /* check value on output */
-
-extern int cramfs_inflate_blocks_free OF((
- inflate_blocks_statef *,
- z_streamp));
-
-extern void cramfs_inflate_set_dictionary OF((
- inflate_blocks_statef *s,
- const Bytef *d, /* dictionary */
- uInt n)); /* dictionary length */
-
-extern int inflate_blocks_sync_point OF((
- inflate_blocks_statef *s));
+++ /dev/null
-/* infcodes.c -- process literals and length/distance pairs
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "inftrees.h"
-#include "infblock.h"
-#include "infcodes.h"
-#include "infutil.h"
-#include "inffast.h"
-
-/* simplify the use of the inflate_huft type with some defines */
-#define exop word.what.Exop
-#define bits word.what.Bits
-
-typedef enum { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */
- START, /* x: set up for LEN */
- LEN, /* i: get length/literal/eob next */
- LENEXT, /* i: getting length extra (have base) */
- DIST, /* i: get distance next */
- DISTEXT, /* i: getting distance extra */
- COPY, /* o: copying bytes in window, waiting for space */
- LIT, /* o: got literal, waiting for output space */
- WASH, /* o: got eob, possibly still output waiting */
- END, /* x: got eob and all data flushed */
- BADCODE} /* x: got error */
-inflate_codes_mode;
-
-/* inflate codes private state */
-struct inflate_codes_state {
-
- /* mode */
- inflate_codes_mode mode; /* current inflate_codes mode */
-
- /* mode dependent information */
- uInt len;
- union {
- struct {
- inflate_huft *tree; /* pointer into tree */
- uInt need; /* bits needed */
- } code; /* if LEN or DIST, where in tree */
- uInt lit; /* if LIT, literal */
- struct {
- uInt get; /* bits to get for extra */
- uInt dist; /* distance back to copy from */
- } copy; /* if EXT or COPY, where and how much */
- } sub; /* submode */
-
- /* mode independent information */
- Byte lbits; /* ltree bits decoded per branch */
- Byte dbits; /* dtree bits decoder per branch */
- inflate_huft *ltree; /* literal/length/eob tree */
- inflate_huft *dtree; /* distance tree */
-
-};
-
-
-inflate_codes_statef *cramfs_inflate_codes_new(bl, bd, tl, td, z)
-uInt bl, bd;
-inflate_huft *tl;
-inflate_huft *td; /* need separate declaration for Borland C++ */
-z_streamp z;
-{
- inflate_codes_statef *c;
- static inflate_codes_statef memory_allocation;
-
- c = &memory_allocation;
- {
- c->mode = START;
- c->lbits = (Byte)bl;
- c->dbits = (Byte)bd;
- c->ltree = tl;
- c->dtree = td;
- }
- return c;
-}
-
-
-int cramfs_inflate_codes(s, z, r)
-inflate_blocks_statef *s;
-z_streamp z;
-int r;
-{
- uInt j; /* temporary storage */
- inflate_huft *t; /* temporary pointer */
- uInt e; /* extra bits or operation */
- uLong b; /* bit buffer */
- uInt k; /* bits in bit buffer */
- Bytef *p; /* input data pointer */
- uInt n; /* bytes available there */
- Bytef *q; /* output window write pointer */
- uInt m; /* bytes to end of window or read pointer */
- Bytef *f; /* pointer to copy strings from */
- inflate_codes_statef *c = s->sub.decode.codes; /* codes state */
-
- /* copy input/output information to locals (UPDATE macro restores) */
- LOAD
-
- /* process input and output based on current state */
- while (1) switch (c->mode)
- { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */
- case START: /* x: set up for LEN */
-#ifndef SLOW
- if (m >= 258 && n >= 10)
- {
- UPDATE
- r = cramfs_inflate_fast(c->lbits, c->dbits, c->ltree, c->dtree, s, z);
- LOAD
- if (r != Z_OK)
- {
- c->mode = r == Z_STREAM_END ? WASH : BADCODE;
- break;
- }
- }
-#endif /* !SLOW */
- c->sub.code.need = c->lbits;
- c->sub.code.tree = c->ltree;
- c->mode = LEN;
- case LEN: /* i: get length/literal/eob next */
- j = c->sub.code.need;
- NEEDBITS(j)
- t = c->sub.code.tree + ((uInt)b & cramfs_inflate_mask[j]);
- DUMPBITS(t->bits)
- e = (uInt)(t->exop);
- if (e == 0) /* literal */
- {
- c->sub.lit = t->base;
- c->mode = LIT;
- break;
- }
- if (e & 16) /* length */
- {
- c->sub.copy.get = e & 15;
- c->len = t->base;
- c->mode = LENEXT;
- break;
- }
- if ((e & 64) == 0) /* next table */
- {
- c->sub.code.need = e;
- c->sub.code.tree = t + t->base;
- break;
- }
- if (e & 32) /* end of block */
- {
- c->mode = WASH;
- break;
- }
- c->mode = BADCODE; /* invalid code */
- z->msg = (char*)"invalid literal/length code";
- r = Z_DATA_ERROR;
- LEAVE
- case LENEXT: /* i: getting length extra (have base) */
- j = c->sub.copy.get;
- NEEDBITS(j)
- c->len += (uInt)b & cramfs_inflate_mask[j];
- DUMPBITS(j)
- c->sub.code.need = c->dbits;
- c->sub.code.tree = c->dtree;
- c->mode = DIST;
- case DIST: /* i: get distance next */
- j = c->sub.code.need;
- NEEDBITS(j)
- t = c->sub.code.tree + ((uInt)b & cramfs_inflate_mask[j]);
- DUMPBITS(t->bits)
- e = (uInt)(t->exop);
- if (e & 16) /* distance */
- {
- c->sub.copy.get = e & 15;
- c->sub.copy.dist = t->base;
- c->mode = DISTEXT;
- break;
- }
- if ((e & 64) == 0) /* next table */
- {
- c->sub.code.need = e;
- c->sub.code.tree = t + t->base;
- break;
- }
- c->mode = BADCODE; /* invalid code */
- z->msg = (char*)"invalid distance code";
- r = Z_DATA_ERROR;
- LEAVE
- case DISTEXT: /* i: getting distance extra */
- j = c->sub.copy.get;
- NEEDBITS(j)
- c->sub.copy.dist += (uInt)b & cramfs_inflate_mask[j];
- DUMPBITS(j)
- c->mode = COPY;
- case COPY: /* o: copying bytes in window, waiting for space */
-#ifndef __TURBOC__ /* Turbo C bug for following expression */
- f = (uInt)(q - s->window) < c->sub.copy.dist ?
- s->end - (c->sub.copy.dist - (q - s->window)) :
- q - c->sub.copy.dist;
-#else
- f = q - c->sub.copy.dist;
- if ((uInt)(q - s->window) < c->sub.copy.dist)
- f = s->end - (c->sub.copy.dist - (uInt)(q - s->window));
-#endif
- while (c->len)
- {
- NEEDOUT
- OUTBYTE(*f++)
- if (f == s->end)
- f = s->window;
- c->len--;
- }
- c->mode = START;
- break;
- case LIT: /* o: got literal, waiting for output space */
- NEEDOUT
- OUTBYTE(c->sub.lit)
- c->mode = START;
- break;
- case WASH: /* o: got eob, possibly more output */
- if (k > 7) /* return unused byte, if any */
- {
- k -= 8;
- n++;
- p--; /* can always return one */
- }
- FLUSH
- if (s->read != s->write)
- LEAVE
- c->mode = END;
- case END:
- r = Z_STREAM_END;
- LEAVE
- case BADCODE: /* x: got error */
- r = Z_DATA_ERROR;
- LEAVE
- default:
- r = Z_STREAM_ERROR;
- LEAVE
- }
-#ifdef NEED_DUMMY_RETURN
- return Z_STREAM_ERROR; /* Some dumb compilers complain without this */
-#endif
-}
-
-
-void cramfs_inflate_codes_free(c, z)
-inflate_codes_statef *c;
-z_streamp z;
-{
-}
+++ /dev/null
-/* infcodes.h -- header to use infcodes.c
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-struct inflate_codes_state;
-typedef struct inflate_codes_state FAR inflate_codes_statef;
-
-extern inflate_codes_statef *cramfs_inflate_codes_new OF((
- uInt, uInt,
- inflate_huft *, inflate_huft *,
- z_streamp ));
-
-extern int cramfs_inflate_codes OF((
- inflate_blocks_statef *,
- z_streamp ,
- int));
-
-extern void cramfs_inflate_codes_free OF((
- inflate_codes_statef *,
- z_streamp ));
-
+++ /dev/null
-/* inffast.c -- process literals and length/distance pairs fast
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "inftrees.h"
-#include "infblock.h"
-#include "infcodes.h"
-#include "infutil.h"
-#include "inffast.h"
-
-struct inflate_codes_state {int dummy;}; /* for buggy compilers */
-
-/* simplify the use of the inflate_huft type with some defines */
-#define exop word.what.Exop
-#define bits word.what.Bits
-
-/* macros for bit input with no checking and for returning unused bytes */
-#define GRABBITS(j) {while(k<(j)){b|=((uLong)NEXTBYTE)<<k;k+=8;}}
-#define UNGRAB {c=z->avail_in-n;c=(k>>3)<c?k>>3:c;n+=c;p-=c;k-=c<<3;}
-
-/* Called with number of bytes left to write in window at least 258
- (the maximum string length) and number of input bytes available
- at least ten. The ten bytes are six bytes for the longest length/
- distance pair plus four bytes for overloading the bit buffer. */
-
-int cramfs_inflate_fast(bl, bd, tl, td, s, z)
-uInt bl, bd;
-inflate_huft *tl;
-inflate_huft *td; /* need separate declaration for Borland C++ */
-inflate_blocks_statef *s;
-z_streamp z;
-{
- inflate_huft *t; /* temporary pointer */
- uInt e; /* extra bits or operation */
- uLong b; /* bit buffer */
- uInt k; /* bits in bit buffer */
- Bytef *p; /* input data pointer */
- uInt n; /* bytes available there */
- Bytef *q; /* output window write pointer */
- uInt m; /* bytes to end of window or read pointer */
- uInt ml; /* mask for literal/length tree */
- uInt md; /* mask for distance tree */
- uInt c; /* bytes to copy */
- uInt d; /* distance back to copy from */
- Bytef *r; /* copy source pointer */
-
- /* load input, output, bit values */
- LOAD
-
- /* initialize masks */
- ml = cramfs_inflate_mask[bl];
- md = cramfs_inflate_mask[bd];
-
- /* do until not enough input or output space for fast loop */
- do { /* assume called with m >= 258 && n >= 10 */
- /* get literal/length code */
- GRABBITS(20) /* max bits for literal/length code */
- if ((e = (t = tl + ((uInt)b & ml))->exop) == 0)
- {
- DUMPBITS(t->bits)
- *q++ = (Byte)t->base;
- m--;
- continue;
- }
- do {
- DUMPBITS(t->bits)
- if (e & 16)
- {
- /* get extra bits for length */
- e &= 15;
- c = t->base + ((uInt)b & cramfs_inflate_mask[e]);
- DUMPBITS(e)
-
- /* decode distance base of block to copy */
- GRABBITS(15); /* max bits for distance code */
- e = (t = td + ((uInt)b & md))->exop;
- do {
- DUMPBITS(t->bits)
- if (e & 16)
- {
- /* get extra bits to add to distance base */
- e &= 15;
- GRABBITS(e) /* get extra bits (up to 13) */
- d = t->base + ((uInt)b & cramfs_inflate_mask[e]);
- DUMPBITS(e)
-
- /* do the copy */
- m -= c;
- if ((uInt)(q - s->window) >= d) /* offset before dest */
- { /* just copy */
- r = q - d;
- *q++ = *r++; c--; /* minimum count is three, */
- *q++ = *r++; c--; /* so unroll loop a little */
- }
- else /* else offset after destination */
- {
- e = d - (uInt)(q - s->window); /* bytes from offset to end */
- r = s->end - e; /* pointer to offset */
- if (c > e) /* if source crosses, */
- {
- c -= e; /* copy to end of window */
- do {
- *q++ = *r++;
- } while (--e);
- r = s->window; /* copy rest from start of window */
- }
- }
- do { /* copy all or what's left */
- *q++ = *r++;
- } while (--c);
- break;
- }
- else if ((e & 64) == 0)
- {
- t += t->base;
- e = (t += ((uInt)b & cramfs_inflate_mask[e]))->exop;
- }
- else
- {
- z->msg = (char*)"invalid distance code";
- UNGRAB
- UPDATE
- return Z_DATA_ERROR;
- }
- } while (1);
- break;
- }
- if ((e & 64) == 0)
- {
- t += t->base;
- if ((e = (t += ((uInt)b & cramfs_inflate_mask[e]))->exop) == 0)
- {
- DUMPBITS(t->bits)
- *q++ = (Byte)t->base;
- m--;
- break;
- }
- }
- else if (e & 32)
- {
- UNGRAB
- UPDATE
- return Z_STREAM_END;
- }
- else
- {
- z->msg = (char*)"invalid literal/length code";
- UNGRAB
- UPDATE
- return Z_DATA_ERROR;
- }
- } while (1);
- } while (m >= 258 && n >= 10);
-
- /* not enough input or output--restore pointers and return */
- UNGRAB
- UPDATE
- return Z_OK;
-}
+++ /dev/null
-/* inffast.h -- header to use inffast.c
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-extern int cramfs_inflate_fast OF((
- uInt,
- uInt,
- inflate_huft *,
- inflate_huft *,
- inflate_blocks_statef *,
- z_streamp ));
+++ /dev/null
-/* inffixed.h -- table for decoding fixed codes
- * Generated automatically by the maketree.c program
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-local uInt fixed_bl = 9;
-local uInt fixed_bd = 5;
-local inflate_huft fixed_tl[] = {
- {{{96,7}},256}, {{{0,8}},80}, {{{0,8}},16}, {{{84,8}},115},
- {{{82,7}},31}, {{{0,8}},112}, {{{0,8}},48}, {{{0,9}},192},
- {{{80,7}},10}, {{{0,8}},96}, {{{0,8}},32}, {{{0,9}},160},
- {{{0,8}},0}, {{{0,8}},128}, {{{0,8}},64}, {{{0,9}},224},
- {{{80,7}},6}, {{{0,8}},88}, {{{0,8}},24}, {{{0,9}},144},
- {{{83,7}},59}, {{{0,8}},120}, {{{0,8}},56}, {{{0,9}},208},
- {{{81,7}},17}, {{{0,8}},104}, {{{0,8}},40}, {{{0,9}},176},
- {{{0,8}},8}, {{{0,8}},136}, {{{0,8}},72}, {{{0,9}},240},
- {{{80,7}},4}, {{{0,8}},84}, {{{0,8}},20}, {{{85,8}},227},
- {{{83,7}},43}, {{{0,8}},116}, {{{0,8}},52}, {{{0,9}},200},
- {{{81,7}},13}, {{{0,8}},100}, {{{0,8}},36}, {{{0,9}},168},
- {{{0,8}},4}, {{{0,8}},132}, {{{0,8}},68}, {{{0,9}},232},
- {{{80,7}},8}, {{{0,8}},92}, {{{0,8}},28}, {{{0,9}},152},
- {{{84,7}},83}, {{{0,8}},124}, {{{0,8}},60}, {{{0,9}},216},
- {{{82,7}},23}, {{{0,8}},108}, {{{0,8}},44}, {{{0,9}},184},
- {{{0,8}},12}, {{{0,8}},140}, {{{0,8}},76}, {{{0,9}},248},
- {{{80,7}},3}, {{{0,8}},82}, {{{0,8}},18}, {{{85,8}},163},
- {{{83,7}},35}, {{{0,8}},114}, {{{0,8}},50}, {{{0,9}},196},
- {{{81,7}},11}, {{{0,8}},98}, {{{0,8}},34}, {{{0,9}},164},
- {{{0,8}},2}, {{{0,8}},130}, {{{0,8}},66}, {{{0,9}},228},
- {{{80,7}},7}, {{{0,8}},90}, {{{0,8}},26}, {{{0,9}},148},
- {{{84,7}},67}, {{{0,8}},122}, {{{0,8}},58}, {{{0,9}},212},
- {{{82,7}},19}, {{{0,8}},106}, {{{0,8}},42}, {{{0,9}},180},
- {{{0,8}},10}, {{{0,8}},138}, {{{0,8}},74}, {{{0,9}},244},
- {{{80,7}},5}, {{{0,8}},86}, {{{0,8}},22}, {{{192,8}},0},
- {{{83,7}},51}, {{{0,8}},118}, {{{0,8}},54}, {{{0,9}},204},
- {{{81,7}},15}, {{{0,8}},102}, {{{0,8}},38}, {{{0,9}},172},
- {{{0,8}},6}, {{{0,8}},134}, {{{0,8}},70}, {{{0,9}},236},
- {{{80,7}},9}, {{{0,8}},94}, {{{0,8}},30}, {{{0,9}},156},
- {{{84,7}},99}, {{{0,8}},126}, {{{0,8}},62}, {{{0,9}},220},
- {{{82,7}},27}, {{{0,8}},110}, {{{0,8}},46}, {{{0,9}},188},
- {{{0,8}},14}, {{{0,8}},142}, {{{0,8}},78}, {{{0,9}},252},
- {{{96,7}},256}, {{{0,8}},81}, {{{0,8}},17}, {{{85,8}},131},
- {{{82,7}},31}, {{{0,8}},113}, {{{0,8}},49}, {{{0,9}},194},
- {{{80,7}},10}, {{{0,8}},97}, {{{0,8}},33}, {{{0,9}},162},
- {{{0,8}},1}, {{{0,8}},129}, {{{0,8}},65}, {{{0,9}},226},
- {{{80,7}},6}, {{{0,8}},89}, {{{0,8}},25}, {{{0,9}},146},
- {{{83,7}},59}, {{{0,8}},121}, {{{0,8}},57}, {{{0,9}},210},
- {{{81,7}},17}, {{{0,8}},105}, {{{0,8}},41}, {{{0,9}},178},
- {{{0,8}},9}, {{{0,8}},137}, {{{0,8}},73}, {{{0,9}},242},
- {{{80,7}},4}, {{{0,8}},85}, {{{0,8}},21}, {{{80,8}},258},
- {{{83,7}},43}, {{{0,8}},117}, {{{0,8}},53}, {{{0,9}},202},
- {{{81,7}},13}, {{{0,8}},101}, {{{0,8}},37}, {{{0,9}},170},
- {{{0,8}},5}, {{{0,8}},133}, {{{0,8}},69}, {{{0,9}},234},
- {{{80,7}},8}, {{{0,8}},93}, {{{0,8}},29}, {{{0,9}},154},
- {{{84,7}},83}, {{{0,8}},125}, {{{0,8}},61}, {{{0,9}},218},
- {{{82,7}},23}, {{{0,8}},109}, {{{0,8}},45}, {{{0,9}},186},
- {{{0,8}},13}, {{{0,8}},141}, {{{0,8}},77}, {{{0,9}},250},
- {{{80,7}},3}, {{{0,8}},83}, {{{0,8}},19}, {{{85,8}},195},
- {{{83,7}},35}, {{{0,8}},115}, {{{0,8}},51}, {{{0,9}},198},
- {{{81,7}},11}, {{{0,8}},99}, {{{0,8}},35}, {{{0,9}},166},
- {{{0,8}},3}, {{{0,8}},131}, {{{0,8}},67}, {{{0,9}},230},
- {{{80,7}},7}, {{{0,8}},91}, {{{0,8}},27}, {{{0,9}},150},
- {{{84,7}},67}, {{{0,8}},123}, {{{0,8}},59}, {{{0,9}},214},
- {{{82,7}},19}, {{{0,8}},107}, {{{0,8}},43}, {{{0,9}},182},
- {{{0,8}},11}, {{{0,8}},139}, {{{0,8}},75}, {{{0,9}},246},
- {{{80,7}},5}, {{{0,8}},87}, {{{0,8}},23}, {{{192,8}},0},
- {{{83,7}},51}, {{{0,8}},119}, {{{0,8}},55}, {{{0,9}},206},
- {{{81,7}},15}, {{{0,8}},103}, {{{0,8}},39}, {{{0,9}},174},
- {{{0,8}},7}, {{{0,8}},135}, {{{0,8}},71}, {{{0,9}},238},
- {{{80,7}},9}, {{{0,8}},95}, {{{0,8}},31}, {{{0,9}},158},
- {{{84,7}},99}, {{{0,8}},127}, {{{0,8}},63}, {{{0,9}},222},
- {{{82,7}},27}, {{{0,8}},111}, {{{0,8}},47}, {{{0,9}},190},
- {{{0,8}},15}, {{{0,8}},143}, {{{0,8}},79}, {{{0,9}},254},
- {{{96,7}},256}, {{{0,8}},80}, {{{0,8}},16}, {{{84,8}},115},
- {{{82,7}},31}, {{{0,8}},112}, {{{0,8}},48}, {{{0,9}},193},
- {{{80,7}},10}, {{{0,8}},96}, {{{0,8}},32}, {{{0,9}},161},
- {{{0,8}},0}, {{{0,8}},128}, {{{0,8}},64}, {{{0,9}},225},
- {{{80,7}},6}, {{{0,8}},88}, {{{0,8}},24}, {{{0,9}},145},
- {{{83,7}},59}, {{{0,8}},120}, {{{0,8}},56}, {{{0,9}},209},
- {{{81,7}},17}, {{{0,8}},104}, {{{0,8}},40}, {{{0,9}},177},
- {{{0,8}},8}, {{{0,8}},136}, {{{0,8}},72}, {{{0,9}},241},
- {{{80,7}},4}, {{{0,8}},84}, {{{0,8}},20}, {{{85,8}},227},
- {{{83,7}},43}, {{{0,8}},116}, {{{0,8}},52}, {{{0,9}},201},
- {{{81,7}},13}, {{{0,8}},100}, {{{0,8}},36}, {{{0,9}},169},
- {{{0,8}},4}, {{{0,8}},132}, {{{0,8}},68}, {{{0,9}},233},
- {{{80,7}},8}, {{{0,8}},92}, {{{0,8}},28}, {{{0,9}},153},
- {{{84,7}},83}, {{{0,8}},124}, {{{0,8}},60}, {{{0,9}},217},
- {{{82,7}},23}, {{{0,8}},108}, {{{0,8}},44}, {{{0,9}},185},
- {{{0,8}},12}, {{{0,8}},140}, {{{0,8}},76}, {{{0,9}},249},
- {{{80,7}},3}, {{{0,8}},82}, {{{0,8}},18}, {{{85,8}},163},
- {{{83,7}},35}, {{{0,8}},114}, {{{0,8}},50}, {{{0,9}},197},
- {{{81,7}},11}, {{{0,8}},98}, {{{0,8}},34}, {{{0,9}},165},
- {{{0,8}},2}, {{{0,8}},130}, {{{0,8}},66}, {{{0,9}},229},
- {{{80,7}},7}, {{{0,8}},90}, {{{0,8}},26}, {{{0,9}},149},
- {{{84,7}},67}, {{{0,8}},122}, {{{0,8}},58}, {{{0,9}},213},
- {{{82,7}},19}, {{{0,8}},106}, {{{0,8}},42}, {{{0,9}},181},
- {{{0,8}},10}, {{{0,8}},138}, {{{0,8}},74}, {{{0,9}},245},
- {{{80,7}},5}, {{{0,8}},86}, {{{0,8}},22}, {{{192,8}},0},
- {{{83,7}},51}, {{{0,8}},118}, {{{0,8}},54}, {{{0,9}},205},
- {{{81,7}},15}, {{{0,8}},102}, {{{0,8}},38}, {{{0,9}},173},
- {{{0,8}},6}, {{{0,8}},134}, {{{0,8}},70}, {{{0,9}},237},
- {{{80,7}},9}, {{{0,8}},94}, {{{0,8}},30}, {{{0,9}},157},
- {{{84,7}},99}, {{{0,8}},126}, {{{0,8}},62}, {{{0,9}},221},
- {{{82,7}},27}, {{{0,8}},110}, {{{0,8}},46}, {{{0,9}},189},
- {{{0,8}},14}, {{{0,8}},142}, {{{0,8}},78}, {{{0,9}},253},
- {{{96,7}},256}, {{{0,8}},81}, {{{0,8}},17}, {{{85,8}},131},
- {{{82,7}},31}, {{{0,8}},113}, {{{0,8}},49}, {{{0,9}},195},
- {{{80,7}},10}, {{{0,8}},97}, {{{0,8}},33}, {{{0,9}},163},
- {{{0,8}},1}, {{{0,8}},129}, {{{0,8}},65}, {{{0,9}},227},
- {{{80,7}},6}, {{{0,8}},89}, {{{0,8}},25}, {{{0,9}},147},
- {{{83,7}},59}, {{{0,8}},121}, {{{0,8}},57}, {{{0,9}},211},
- {{{81,7}},17}, {{{0,8}},105}, {{{0,8}},41}, {{{0,9}},179},
- {{{0,8}},9}, {{{0,8}},137}, {{{0,8}},73}, {{{0,9}},243},
- {{{80,7}},4}, {{{0,8}},85}, {{{0,8}},21}, {{{80,8}},258},
- {{{83,7}},43}, {{{0,8}},117}, {{{0,8}},53}, {{{0,9}},203},
- {{{81,7}},13}, {{{0,8}},101}, {{{0,8}},37}, {{{0,9}},171},
- {{{0,8}},5}, {{{0,8}},133}, {{{0,8}},69}, {{{0,9}},235},
- {{{80,7}},8}, {{{0,8}},93}, {{{0,8}},29}, {{{0,9}},155},
- {{{84,7}},83}, {{{0,8}},125}, {{{0,8}},61}, {{{0,9}},219},
- {{{82,7}},23}, {{{0,8}},109}, {{{0,8}},45}, {{{0,9}},187},
- {{{0,8}},13}, {{{0,8}},141}, {{{0,8}},77}, {{{0,9}},251},
- {{{80,7}},3}, {{{0,8}},83}, {{{0,8}},19}, {{{85,8}},195},
- {{{83,7}},35}, {{{0,8}},115}, {{{0,8}},51}, {{{0,9}},199},
- {{{81,7}},11}, {{{0,8}},99}, {{{0,8}},35}, {{{0,9}},167},
- {{{0,8}},3}, {{{0,8}},131}, {{{0,8}},67}, {{{0,9}},231},
- {{{80,7}},7}, {{{0,8}},91}, {{{0,8}},27}, {{{0,9}},151},
- {{{84,7}},67}, {{{0,8}},123}, {{{0,8}},59}, {{{0,9}},215},
- {{{82,7}},19}, {{{0,8}},107}, {{{0,8}},43}, {{{0,9}},183},
- {{{0,8}},11}, {{{0,8}},139}, {{{0,8}},75}, {{{0,9}},247},
- {{{80,7}},5}, {{{0,8}},87}, {{{0,8}},23}, {{{192,8}},0},
- {{{83,7}},51}, {{{0,8}},119}, {{{0,8}},55}, {{{0,9}},207},
- {{{81,7}},15}, {{{0,8}},103}, {{{0,8}},39}, {{{0,9}},175},
- {{{0,8}},7}, {{{0,8}},135}, {{{0,8}},71}, {{{0,9}},239},
- {{{80,7}},9}, {{{0,8}},95}, {{{0,8}},31}, {{{0,9}},159},
- {{{84,7}},99}, {{{0,8}},127}, {{{0,8}},63}, {{{0,9}},223},
- {{{82,7}},27}, {{{0,8}},111}, {{{0,8}},47}, {{{0,9}},191},
- {{{0,8}},15}, {{{0,8}},143}, {{{0,8}},79}, {{{0,9}},255}
- };
-local inflate_huft fixed_td[] = {
- {{{80,5}},1}, {{{87,5}},257}, {{{83,5}},17}, {{{91,5}},4097},
- {{{81,5}},5}, {{{89,5}},1025}, {{{85,5}},65}, {{{93,5}},16385},
- {{{80,5}},3}, {{{88,5}},513}, {{{84,5}},33}, {{{92,5}},8193},
- {{{82,5}},9}, {{{90,5}},2049}, {{{86,5}},129}, {{{192,5}},24577},
- {{{80,5}},2}, {{{87,5}},385}, {{{83,5}},25}, {{{91,5}},6145},
- {{{81,5}},7}, {{{89,5}},1537}, {{{85,5}},97}, {{{93,5}},24577},
- {{{80,5}},4}, {{{88,5}},769}, {{{84,5}},49}, {{{92,5}},12289},
- {{{82,5}},13}, {{{90,5}},3073}, {{{86,5}},193}, {{{192,5}},24577}
- };
+++ /dev/null
-/* inflate.c -- zlib interface to inflate modules
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "infblock.h"
-
-struct inflate_blocks_state {int dummy;}; /* for buggy compilers */
-
-typedef enum {
- METHOD, /* waiting for method byte */
- FLAG, /* waiting for flag byte */
- DICT4, /* four dictionary check bytes to go */
- DICT3, /* three dictionary check bytes to go */
- DICT2, /* two dictionary check bytes to go */
- DICT1, /* one dictionary check byte to go */
- DICT0, /* waiting for inflateSetDictionary */
- BLOCKS, /* decompressing blocks */
- CHECK4, /* four check bytes to go */
- CHECK3, /* three check bytes to go */
- CHECK2, /* two check bytes to go */
- CHECK1, /* one check byte to go */
- DONE, /* finished check, done */
- BAD} /* got an error--stay here */
-inflate_mode;
-
-/* inflate private state */
-struct internal_state {
-
- /* mode */
- inflate_mode mode; /* current inflate mode */
-
- /* mode dependent information */
- union {
- uInt method; /* if FLAGS, method byte */
- struct {
- uLong was; /* computed check value */
- uLong need; /* stream check value */
- } check; /* if CHECK, check values to compare */
- uInt marker; /* if BAD, inflateSync's marker bytes count */
- } sub; /* submode */
-
- /* mode independent information */
- int nowrap; /* flag for no wrapper */
- uInt wbits; /* log2(window size) (8..15, defaults to 15) */
- inflate_blocks_statef
- *blocks; /* current inflate_blocks state */
-
-};
-
-
-int ZEXPORT cramfs_inflateReset(z)
-z_streamp z;
-{
- if (z == Z_NULL || z->state == Z_NULL)
- return Z_STREAM_ERROR;
- z->total_in = z->total_out = 0;
- z->msg = Z_NULL;
- z->state->mode = z->state->nowrap ? BLOCKS : METHOD;
- cramfs_inflate_blocks_reset(z->state->blocks, z, Z_NULL);
- return Z_OK;
-}
-
-
-int ZEXPORT cramfs_inflateEnd(z)
-z_streamp z;
-{
- if (z == Z_NULL || z->state == Z_NULL)
- return Z_STREAM_ERROR;
- if (z->state->blocks != Z_NULL)
- cramfs_inflate_blocks_free(z->state->blocks, z);
- z->state = Z_NULL;
- return Z_OK;
-}
-
-
-int ZEXPORT cramfs_inflateInit2_(z, w, version, stream_size)
-z_streamp z;
-int w;
-const char *version;
-int stream_size;
-{
- static struct internal_state internal_state;
-
- if (version == Z_NULL || version[0] != ZLIB_VERSION[0] ||
- stream_size != sizeof(z_stream))
- return Z_VERSION_ERROR;
-
- /* initialize state */
- if (z == Z_NULL)
- return Z_STREAM_ERROR;
- z->msg = Z_NULL;
- z->state = &internal_state;
- z->state->blocks = Z_NULL;
-
- /* handle undocumented nowrap option (no zlib header or check) */
- z->state->nowrap = 0;
- if (w < 0)
- {
- w = - w;
- z->state->nowrap = 1;
- }
-
- /* set window size */
- if (w < 8 || w > 15)
- {
- cramfs_inflateEnd(z);
- return Z_STREAM_ERROR;
- }
- z->state->wbits = (uInt)w;
-
- /* create inflate_blocks state */
- if ((z->state->blocks =
- cramfs_inflate_blocks_new(z, z->state->nowrap ? Z_NULL : cramfs_adler32, (uInt)1 << w))
- == Z_NULL)
- {
- cramfs_inflateEnd(z);
- return Z_MEM_ERROR;
- }
-
- /* reset state */
- cramfs_inflateReset(z);
- return Z_OK;
-}
-
-
-int ZEXPORT cramfs_inflateInit_(z, version, stream_size)
-z_streamp z;
-const char *version;
-int stream_size;
-{
- return cramfs_inflateInit2_(z, DEF_WBITS, version, stream_size);
-}
-
-
-#define NEEDBYTE {if(z->avail_in==0)return r;r=f;}
-#define NEXTBYTE (z->avail_in--,z->total_in++,*z->next_in++)
-
-int ZEXPORT cramfs_inflate(z, f)
-z_streamp z;
-int f;
-{
- int r;
- uInt b;
-
- if (z == Z_NULL || z->state == Z_NULL || z->next_in == Z_NULL)
- return Z_STREAM_ERROR;
- f = f == Z_FINISH ? Z_BUF_ERROR : Z_OK;
- r = Z_BUF_ERROR;
- while (1) switch (z->state->mode)
- {
- case METHOD:
- NEEDBYTE
- if (((z->state->sub.method = NEXTBYTE) & 0xf) != Z_DEFLATED)
- {
- z->state->mode = BAD;
- z->msg = (char*)"unknown compression method";
- z->state->sub.marker = 5; /* can't try inflateSync */
- break;
- }
- if ((z->state->sub.method >> 4) + 8 > z->state->wbits)
- {
- z->state->mode = BAD;
- z->msg = (char*)"invalid window size";
- z->state->sub.marker = 5; /* can't try inflateSync */
- break;
- }
- z->state->mode = FLAG;
- case FLAG:
- NEEDBYTE
- b = NEXTBYTE;
- if (((z->state->sub.method << 8) + b) % 31)
- {
- z->state->mode = BAD;
- z->msg = (char*)"incorrect header check";
- z->state->sub.marker = 5; /* can't try inflateSync */
- break;
- }
- if (!(b & PRESET_DICT))
- {
- z->state->mode = BLOCKS;
- break;
- }
- z->state->mode = DICT4;
- case DICT4:
- NEEDBYTE
- z->state->sub.check.need = (uLong)NEXTBYTE << 24;
- z->state->mode = DICT3;
- case DICT3:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE << 16;
- z->state->mode = DICT2;
- case DICT2:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE << 8;
- z->state->mode = DICT1;
- case DICT1:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE;
- z->adler = z->state->sub.check.need;
- z->state->mode = DICT0;
- return Z_NEED_DICT;
- case DICT0:
- z->state->mode = BAD;
- z->msg = (char*)"need dictionary";
- z->state->sub.marker = 0; /* can try inflateSync */
- return Z_STREAM_ERROR;
- case BLOCKS:
- r = cramfs_inflate_blocks(z->state->blocks, z, r);
- if (r == Z_DATA_ERROR)
- {
- z->state->mode = BAD;
- z->state->sub.marker = 0; /* can try inflateSync */
- break;
- }
- if (r == Z_OK)
- r = f;
- if (r != Z_STREAM_END)
- return r;
- r = f;
- cramfs_inflate_blocks_reset(z->state->blocks, z, &z->state->sub.check.was);
- if (z->state->nowrap)
- {
- z->state->mode = DONE;
- break;
- }
- z->state->mode = CHECK4;
- case CHECK4:
- NEEDBYTE
- z->state->sub.check.need = (uLong)NEXTBYTE << 24;
- z->state->mode = CHECK3;
- case CHECK3:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE << 16;
- z->state->mode = CHECK2;
- case CHECK2:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE << 8;
- z->state->mode = CHECK1;
- case CHECK1:
- NEEDBYTE
- z->state->sub.check.need += (uLong)NEXTBYTE;
-
- if (z->state->sub.check.was != z->state->sub.check.need)
- {
- z->state->mode = BAD;
- z->msg = (char*)"incorrect data check";
- z->state->sub.marker = 5; /* can't try inflateSync */
- break;
- }
- z->state->mode = DONE;
- case DONE:
- return Z_STREAM_END;
- case BAD:
- return Z_DATA_ERROR;
- default:
- return Z_STREAM_ERROR;
- }
-#ifdef NEED_DUMMY_RETURN
- return Z_STREAM_ERROR; /* Some dumb compilers complain without this */
-#endif
-}
-
-
-int ZEXPORT cramfs_inflateSync(z)
-z_streamp z;
-{
- uInt n; /* number of bytes to look at */
- Bytef *p; /* pointer to bytes */
- uInt m; /* number of marker bytes found in a row */
- uLong r, w; /* temporaries to save total_in and total_out */
-
- /* set up */
- if (z == Z_NULL || z->state == Z_NULL)
- return Z_STREAM_ERROR;
- if (z->state->mode != BAD)
- {
- z->state->mode = BAD;
- z->state->sub.marker = 0;
- }
- if ((n = z->avail_in) == 0)
- return Z_BUF_ERROR;
- p = z->next_in;
- m = z->state->sub.marker;
-
- /* search */
- while (n && m < 4)
- {
- static const Byte mark[4] = {0, 0, 0xff, 0xff};
- if (*p == mark[m])
- m++;
- else if (*p)
- m = 0;
- else
- m = 4 - m;
- p++, n--;
- }
-
- /* restore */
- z->total_in += p - z->next_in;
- z->next_in = p;
- z->avail_in = n;
- z->state->sub.marker = m;
-
- /* return no joy or set up to restart on a new block */
- if (m != 4)
- return Z_DATA_ERROR;
- r = z->total_in; w = z->total_out;
- cramfs_inflateReset(z);
- z->total_in = r; z->total_out = w;
- z->state->mode = BLOCKS;
- return Z_OK;
-}
-
-
-/* Returns true if inflate is currently at the end of a block generated
- * by Z_SYNC_FLUSH or Z_FULL_FLUSH. This function is used by one PPP
- * implementation to provide an additional safety check. PPP uses Z_SYNC_FLUSH
- * but removes the length bytes of the resulting empty stored block. When
- * decompressing, PPP checks that at the end of input packet, inflate is
- * waiting for these length bytes.
- */
-int ZEXPORT cramfs_inflateSyncPoint(z)
-z_streamp z;
-{
- if (z == Z_NULL || z->state == Z_NULL || z->state->blocks == Z_NULL)
- return Z_STREAM_ERROR;
- return inflate_blocks_sync_point(z->state->blocks);
-}
+++ /dev/null
-/* inftrees.c -- generate Huffman trees for efficient decoding
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "inftrees.h"
-
-static const char inflate_copyright[] =
- " inflate 1.1.3 Copyright 1995-1998 Mark Adler ";
-/*
- If you use the zlib library in a product, an acknowledgment is welcome
- in the documentation of your product. If for some reason you cannot
- include such an acknowledgment, I would appreciate that you keep this
- copyright string in the executable of your product.
- */
-struct internal_state {int dummy;}; /* for buggy compilers */
-
-/* simplify the use of the inflate_huft type with some defines */
-#define exop word.what.Exop
-#define bits word.what.Bits
-
-
-local int huft_build OF((
- uIntf *, /* code lengths in bits */
- uInt, /* number of codes */
- uInt, /* number of "simple" codes */
- const uIntf *, /* list of base values for non-simple codes */
- const uIntf *, /* list of extra bits for non-simple codes */
- inflate_huft * FAR*,/* result: starting table */
- uIntf *, /* maximum lookup bits (returns actual) */
- inflate_huft *, /* space for trees */
- uInt *, /* hufts used in space */
- uIntf * )); /* space for values */
-
-/* Tables for deflate from PKZIP's appnote.txt. */
-local const uInt cplens[31] = { /* Copy lengths for literal codes 257..285 */
- 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31,
- 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0};
- /* see note #13 above about 258 */
-local const uInt cplext[31] = { /* Extra bits for literal codes 257..285 */
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2,
- 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 112, 112}; /* 112==invalid */
-local const uInt cpdist[30] = { /* Copy offsets for distance codes 0..29 */
- 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193,
- 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145,
- 8193, 12289, 16385, 24577};
-local const uInt cpdext[30] = { /* Extra bits for distance codes */
- 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
- 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
- 12, 12, 13, 13};
-
-/*
- Huffman code decoding is performed using a multi-level table lookup.
- The fastest way to decode is to simply build a lookup table whose
- size is determined by the longest code. However, the time it takes
- to build this table can also be a factor if the data being decoded
- is not very long. The most common codes are necessarily the
- shortest codes, so those codes dominate the decoding time, and hence
- the speed. The idea is you can have a shorter table that decodes the
- shorter, more probable codes, and then point to subsidiary tables for
- the longer codes. The time it costs to decode the longer codes is
- then traded against the time it takes to make longer tables.
-
- This results of this trade are in the variables lbits and dbits
- below. lbits is the number of bits the first level table for literal/
- length codes can decode in one step, and dbits is the same thing for
- the distance codes. Subsequent tables are also less than or equal to
- those sizes. These values may be adjusted either when all of the
- codes are shorter than that, in which case the longest code length in
- bits is used, or when the shortest code is *longer* than the requested
- table size, in which case the length of the shortest code in bits is
- used.
-
- There are two different values for the two tables, since they code a
- different number of possibilities each. The literal/length table
- codes 286 possible values, or in a flat code, a little over eight
- bits. The distance table codes 30 possible values, or a little less
- than five bits, flat. The optimum values for speed end up being
- about one bit more than those, so lbits is 8+1 and dbits is 5+1.
- The optimum values may differ though from machine to machine, and
- possibly even between compilers. Your mileage may vary.
- */
-
-
-/* If BMAX needs to be larger than 16, then h and x[] should be uLong. */
-#define BMAX 15 /* maximum bit length of any code */
-
-local int huft_build(b, n, s, d, e, t, m, hp, hn, v)
-uIntf *b; /* code lengths in bits (all assumed <= BMAX) */
-uInt n; /* number of codes (assumed <= 288) */
-uInt s; /* number of simple-valued codes (0..s-1) */
-const uIntf *d; /* list of base values for non-simple codes */
-const uIntf *e; /* list of extra bits for non-simple codes */
-inflate_huft * FAR *t; /* result: starting table */
-uIntf *m; /* maximum lookup bits, returns actual */
-inflate_huft *hp; /* space for trees */
-uInt *hn; /* hufts used in space */
-uIntf *v; /* working area: values in order of bit length */
-/* Given a list of code lengths and a maximum table size, make a set of
- tables to decode that set of codes. Return Z_OK on success, Z_BUF_ERROR
- if the given code set is incomplete (the tables are still built in this
- case), Z_DATA_ERROR if the input is invalid (an over-subscribed set of
- lengths), or Z_MEM_ERROR if not enough memory. */
-{
-
- uInt a; /* counter for codes of length k */
- uInt c[BMAX+1]; /* bit length count table */
- uInt f; /* i repeats in table every f entries */
- int g; /* maximum code length */
- int h; /* table level */
- register uInt i; /* counter, current code */
- register uInt j; /* counter */
- register int k; /* number of bits in current code */
- int l; /* bits per table (returned in m) */
- uInt mask; /* (1 << w) - 1, to avoid cc -O bug on HP */
- register uIntf *p; /* pointer into c[], b[], or v[] */
- inflate_huft *q; /* points to current table */
- struct inflate_huft_s r; /* table entry for structure assignment */
- inflate_huft *u[BMAX]; /* table stack */
- register int w; /* bits before this table == (l * h) */
- uInt x[BMAX+1]; /* bit offsets, then code stack */
- uIntf *xp; /* pointer into x */
- int y; /* number of dummy codes added */
- uInt z; /* number of entries in current table */
-
-
- /* Generate counts for each bit length */
- p = c;
-#define C0 *p++ = 0;
-#define C2 C0 C0 C0 C0
-#define C4 C2 C2 C2 C2
- C4 /* clear c[]--assume BMAX+1 is 16 */
- p = b; i = n;
- do {
- c[*p++]++; /* assume all entries <= BMAX */
- } while (--i);
- if (c[0] == n) /* null input--all zero length codes */
- {
- *t = (inflate_huft *)Z_NULL;
- *m = 0;
- return Z_OK;
- }
-
-
- /* Find minimum and maximum length, bound *m by those */
- l = *m;
- for (j = 1; j <= BMAX; j++)
- if (c[j])
- break;
- k = j; /* minimum code length */
- if ((uInt)l < j)
- l = j;
- for (i = BMAX; i; i--)
- if (c[i])
- break;
- g = i; /* maximum code length */
- if ((uInt)l > i)
- l = i;
- *m = l;
-
-
- /* Adjust last length count to fill out codes, if needed */
- for (y = 1 << j; j < i; j++, y <<= 1)
- if ((y -= c[j]) < 0)
- return Z_DATA_ERROR;
- if ((y -= c[i]) < 0)
- return Z_DATA_ERROR;
- c[i] += y;
-
-
- /* Generate starting offsets into the value table for each length */
- x[1] = j = 0;
- p = c + 1; xp = x + 2;
- while (--i) { /* note that i == g from above */
- *xp++ = (j += *p++);
- }
-
-
- /* Make a table of values in order of bit lengths */
- p = b; i = 0;
- do {
- if ((j = *p++) != 0)
- v[x[j]++] = i;
- } while (++i < n);
- n = x[g]; /* set n to length of v */
-
-
- /* Generate the Huffman codes and for each, make the table entries */
- x[0] = i = 0; /* first Huffman code is zero */
- p = v; /* grab values in bit order */
- h = -1; /* no tables yet--level -1 */
- w = -l; /* bits decoded == (l * h) */
- u[0] = (inflate_huft *)Z_NULL; /* just to keep compilers happy */
- q = (inflate_huft *)Z_NULL; /* ditto */
- z = 0; /* ditto */
-
- /* go through the bit lengths (k already is bits in shortest code) */
- for (; k <= g; k++)
- {
- a = c[k];
- while (a--)
- {
- /* here i is the Huffman code of length k bits for value *p */
- /* make tables up to required level */
- while (k > w + l)
- {
- h++;
- w += l; /* previous table always l bits */
-
- /* compute minimum size table less than or equal to l bits */
- z = g - w;
- z = z > (uInt)l ? l : z; /* table size upper limit */
- if ((f = 1 << (j = k - w)) > a + 1) /* try a k-w bit table */
- { /* too few codes for k-w bit table */
- f -= a + 1; /* deduct codes from patterns left */
- xp = c + k;
- if (j < z)
- while (++j < z) /* try smaller tables up to z bits */
- {
- if ((f <<= 1) <= *++xp)
- break; /* enough codes to use up j bits */
- f -= *xp; /* else deduct codes from patterns */
- }
- }
- z = 1 << j; /* table entries for j-bit table */
-
- /* allocate new table */
- if (*hn + z > MANY) /* (note: doesn't matter for fixed) */
- return Z_MEM_ERROR; /* not enough memory */
- u[h] = q = hp + *hn;
- *hn += z;
-
- /* connect to last table, if there is one */
- if (h)
- {
- x[h] = i; /* save pattern for backing up */
- r.bits = (Byte)l; /* bits to dump before this table */
- r.exop = (Byte)j; /* bits in this table */
- j = i >> (w - l);
- r.base = (uInt)(q - u[h-1] - j); /* offset to this table */
- u[h-1][j] = r; /* connect to last table */
- }
- else
- *t = q; /* first table is returned result */
- }
-
- /* set up table entry in r */
- r.bits = (Byte)(k - w);
- if (p >= v + n)
- r.exop = 128 + 64; /* out of values--invalid code */
- else if (*p < s)
- {
- r.exop = (Byte)(*p < 256 ? 0 : 32 + 64); /* 256 is end-of-block */
- r.base = *p++; /* simple code is just the value */
- }
- else
- {
- r.exop = (Byte)(e[*p - s] + 16 + 64);/* non-simple--look up in lists */
- r.base = d[*p++ - s];
- }
-
- /* fill code-like entries with r */
- f = 1 << (k - w);
- for (j = i >> w; j < z; j += f)
- q[j] = r;
-
- /* backwards increment the k-bit code i */
- for (j = 1 << (k - 1); i & j; j >>= 1)
- i ^= j;
- i ^= j;
-
- /* backup over finished tables */
- mask = (1 << w) - 1; /* needed on HP, cc -O bug */
- while ((i & mask) != x[h])
- {
- h--; /* don't need to update q */
- w -= l;
- mask = (1 << w) - 1;
- }
- }
- }
-
-
- /* Return Z_BUF_ERROR if we were given an incomplete table */
- return y != 0 && g != 1 ? Z_BUF_ERROR : Z_OK;
-}
-
-
-int cramfs_inflate_trees_bits(c, bb, tb, hp, z)
-uIntf *c; /* 19 code lengths */
-uIntf *bb; /* bits tree desired/actual depth */
-inflate_huft * FAR *tb; /* bits tree result */
-inflate_huft *hp; /* space for trees */
-z_streamp z; /* for messages */
-{
- int r;
- uInt hn = 0; /* hufts used in space */
- uIntf *v; /* work area for huft_build */
- static unsigned int work_area[19];
-
- v = work_area;
- r = huft_build(c, 19, 19, (uIntf*)Z_NULL, (uIntf*)Z_NULL,
- tb, bb, hp, &hn, v);
- if (r == Z_DATA_ERROR)
- z->msg = (char*)"oversubscribed dynamic bit lengths tree";
- else if (r == Z_BUF_ERROR || *bb == 0)
- {
- z->msg = (char*)"incomplete dynamic bit lengths tree";
- r = Z_DATA_ERROR;
- }
- return r;
-}
-
-int cramfs_inflate_trees_dynamic(nl, nd, c, bl, bd, tl, td, hp, z)
-uInt nl; /* number of literal/length codes */
-uInt nd; /* number of distance codes */
-uIntf *c; /* that many (total) code lengths */
-uIntf *bl; /* literal desired/actual bit depth */
-uIntf *bd; /* distance desired/actual bit depth */
-inflate_huft * FAR *tl; /* literal/length tree result */
-inflate_huft * FAR *td; /* distance tree result */
-inflate_huft *hp; /* space for trees */
-z_streamp z; /* for messages */
-{
- int r;
- uInt hn = 0; /* hufts used in space */
- uIntf *v; /* work area for huft_build */
- static unsigned int work_area[288];
-
- /* allocate work area */
- v = work_area;
-
- /* build literal/length tree */
- r = huft_build(c, nl, 257, cplens, cplext, tl, bl, hp, &hn, v);
- if (r != Z_OK || *bl == 0)
- {
- if (r == Z_DATA_ERROR)
- z->msg = (char*)"oversubscribed literal/length tree";
- else if (r != Z_MEM_ERROR)
- {
- z->msg = (char*)"incomplete literal/length tree";
- r = Z_DATA_ERROR;
- }
- return r;
- }
-
- /* build distance tree */
- r = huft_build(c + nl, nd, 0, cpdist, cpdext, td, bd, hp, &hn, v);
- if (r != Z_OK || (*bd == 0 && nl > 257))
- {
- if (r == Z_DATA_ERROR)
- z->msg = (char*)"oversubscribed distance tree";
- else if (r == Z_BUF_ERROR) {
-#ifdef PKZIP_BUG_WORKAROUND
- r = Z_OK;
- }
-#else
- z->msg = (char*)"incomplete distance tree";
- r = Z_DATA_ERROR;
- }
- else if (r != Z_MEM_ERROR)
- {
- z->msg = (char*)"empty distance tree with lengths";
- r = Z_DATA_ERROR;
- }
- return r;
-#endif
- }
-
- /* done */
- return Z_OK;
-}
-
-
-/* build fixed tables only once--keep them here */
-#include "inffixed.h"
-
-
-int cramfs_inflate_trees_fixed(bl, bd, tl, td, z)
-uIntf *bl; /* literal desired/actual bit depth */
-uIntf *bd; /* distance desired/actual bit depth */
-inflate_huft * FAR *tl; /* literal/length tree result */
-inflate_huft * FAR *td; /* distance tree result */
-z_streamp z; /* for memory allocation */
-{
- *bl = fixed_bl;
- *bd = fixed_bd;
- *tl = fixed_tl;
- *td = fixed_td;
- return Z_OK;
-}
+++ /dev/null
-/* inftrees.h -- header to use inftrees.c
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-/* Huffman code lookup table entry--this entry is four bytes for machines
- that have 16-bit pointers (e.g. PC's in the small or medium model). */
-
-typedef struct inflate_huft_s FAR inflate_huft;
-
-struct inflate_huft_s {
- union {
- struct {
- Byte Exop; /* number of extra bits or operation */
- Byte Bits; /* number of bits in this code or subcode */
- } what;
- uInt pad; /* pad structure to a power of 2 (4 bytes for */
- } word; /* 16-bit, 8 bytes for 32-bit int's) */
- uInt base; /* literal, length base, distance base,
- or table offset */
-};
-
-/* Maximum size of dynamic tree. The maximum found in a long but non-
- exhaustive search was 1004 huft structures (850 for length/literals
- and 154 for distances, the latter actually the result of an
- exhaustive search). The actual maximum is not known, but the
- value below is more than safe. */
-#define MANY 1440
-
-extern int cramfs_inflate_trees_bits OF((
- uIntf *, /* 19 code lengths */
- uIntf *, /* bits tree desired/actual depth */
- inflate_huft * FAR *, /* bits tree result */
- inflate_huft *, /* space for trees */
- z_streamp)); /* for messages */
-
-extern int cramfs_inflate_trees_dynamic OF((
- uInt, /* number of literal/length codes */
- uInt, /* number of distance codes */
- uIntf *, /* that many (total) code lengths */
- uIntf *, /* literal desired/actual bit depth */
- uIntf *, /* distance desired/actual bit depth */
- inflate_huft * FAR *, /* literal/length tree result */
- inflate_huft * FAR *, /* distance tree result */
- inflate_huft *, /* space for trees */
- z_streamp)); /* for messages */
-
-extern int cramfs_inflate_trees_fixed OF((
- uIntf *, /* literal desired/actual bit depth */
- uIntf *, /* distance desired/actual bit depth */
- inflate_huft * FAR *, /* literal/length tree result */
- inflate_huft * FAR *, /* distance tree result */
- z_streamp)); /* for memory allocation */
+++ /dev/null
-/* inflate_util.c -- data and routines common to blocks and codes
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#include "zutil.h"
-#include "infblock.h"
-#include "inftrees.h"
-#include "infcodes.h"
-#include "infutil.h"
-
-struct inflate_codes_state {int dummy;}; /* for buggy compilers */
-
-/* And'ing with mask[n] masks the lower n bits */
-uInt cramfs_inflate_mask[17] = {
- 0x0000,
- 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff,
- 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
-};
-
-
-/* copy as much as possible from the sliding window to the output area */
-int cramfs_inflate_flush(s, z, r)
-inflate_blocks_statef *s;
-z_streamp z;
-int r;
-{
- uInt n;
- Bytef *p;
- Bytef *q;
-
- /* local copies of source and destination pointers */
- p = z->next_out;
- q = s->read;
-
- /* compute number of bytes to copy as far as end of window */
- n = (uInt)((q <= s->write ? s->write : s->end) - q);
- if (n > z->avail_out) n = z->avail_out;
- if (n && r == Z_BUF_ERROR) r = Z_OK;
-
- /* update counters */
- z->avail_out -= n;
- z->total_out += n;
-
- /* update check information */
- if (s->checkfn != Z_NULL)
- z->adler = s->check = (*s->checkfn)(s->check, q, n);
-
- /* copy as far as end of window */
- memcpy(p, q, n);
- p += n;
- q += n;
-
- /* see if more to copy at beginning of window */
- if (q == s->end)
- {
- /* wrap pointers */
- q = s->window;
- if (s->write == s->end)
- s->write = s->window;
-
- /* compute bytes to copy */
- n = (uInt)(s->write - q);
- if (n > z->avail_out) n = z->avail_out;
- if (n && r == Z_BUF_ERROR) r = Z_OK;
-
- /* update counters */
- z->avail_out -= n;
- z->total_out += n;
-
- /* update check information */
- if (s->checkfn != Z_NULL)
- z->adler = s->check = (*s->checkfn)(s->check, q, n);
-
- /* copy */
- memcpy(p, q, n);
- p += n;
- q += n;
- }
-
- /* update pointers */
- z->next_out = p;
- s->read = q;
-
- /* done */
- return r;
-}
+++ /dev/null
-/* infutil.h -- types and macros common to blocks and codes
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-#ifndef _INFUTIL_H
-#define _INFUTIL_H
-
-typedef enum {
- TYPE, /* get type bits (3, including end bit) */
- LENS, /* get lengths for stored */
- STORED, /* processing stored block */
- TABLE, /* get table lengths */
- BTREE, /* get bit lengths tree for a dynamic block */
- DTREE, /* get length, distance trees for a dynamic block */
- CODES, /* processing fixed or dynamic block */
- DRY, /* output remaining window bytes */
- DONE, /* finished last block, done */
- BAD} /* got a data error--stuck here */
-inflate_block_mode;
-
-/* inflate blocks semi-private state */
-struct inflate_blocks_state {
-
- /* mode */
- inflate_block_mode mode; /* current inflate_block mode */
-
- /* mode dependent information */
- union {
- uInt left; /* if STORED, bytes left to copy */
- struct {
- uInt table; /* table lengths (14 bits) */
- uInt index; /* index into blens (or border) */
- uIntf *blens; /* bit lengths of codes */
- uInt bb; /* bit length tree depth */
- inflate_huft *tb; /* bit length decoding tree */
- } trees; /* if DTREE, decoding info for trees */
- struct {
- inflate_codes_statef
- *codes;
- } decode; /* if CODES, current state */
- } sub; /* submode */
- uInt last; /* true if this block is the last block */
-
- /* mode independent information */
- uInt bitk; /* bits in bit buffer */
- uLong bitb; /* bit buffer */
- inflate_huft *hufts; /* single malloc for tree space */
- Bytef *window; /* sliding window */
- Bytef *end; /* one byte after sliding window */
- Bytef *read; /* window read pointer */
- Bytef *write; /* window write pointer */
- check_func checkfn; /* check function */
- uLong check; /* check on output */
-
-};
-
-
-/* defines for inflate input/output */
-/* update pointers and return */
-#define UPDBITS {s->bitb=b;s->bitk=k;}
-#define UPDIN {z->avail_in=n;z->total_in+=p-z->next_in;z->next_in=p;}
-#define UPDOUT {s->write=q;}
-#define UPDATE {UPDBITS UPDIN UPDOUT}
-#define LEAVE {UPDATE return cramfs_inflate_flush(s,z,r);}
-/* get bytes and bits */
-#define LOADIN {p=z->next_in;n=z->avail_in;b=s->bitb;k=s->bitk;}
-#define NEEDBYTE {if(n)r=Z_OK;else LEAVE}
-#define NEXTBYTE (n--,*p++)
-#define NEEDBITS(j) {while(k<(j)){NEEDBYTE;b|=((uLong)NEXTBYTE)<<k;k+=8;}}
-#define DUMPBITS(j) {b>>=(j);k-=(j);}
-/* output bytes */
-#define WAVAIL (uInt)(q<s->read?s->read-q-1:s->end-q)
-#define LOADOUT {q=s->write;m=(uInt)WAVAIL;}
-#define WRAP {if(q==s->end&&s->read!=s->window){q=s->window;m=(uInt)WAVAIL;}}
-#define FLUSH {UPDOUT r=cramfs_inflate_flush(s,z,r); LOADOUT}
-#define NEEDOUT {if(m==0){WRAP if(m==0){FLUSH WRAP if(m==0) LEAVE}}r=Z_OK;}
-#define OUTBYTE(a) {*q++=(Byte)(a);m--;}
-/* load local pointers */
-#define LOAD {LOADIN LOADOUT}
-
-/* masks for lower bits (size given to avoid silly warnings with Visual C++) */
-extern uInt cramfs_inflate_mask[17];
-
-/* copy as much as possible from the sliding window to the output area */
-extern int cramfs_inflate_flush OF((
- inflate_blocks_statef *,
- z_streamp ,
- int));
-
-struct internal_state {int dummy;}; /* for buggy compilers */
-
-#endif
+++ /dev/null
-/* uncompr.c -- decompress a memory buffer
- * Copyright (C) 1995-1998 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* @(#) $Id$ */
-
-#include "zlib.h"
-
-/* ===========================================================================
- Decompresses the source buffer into the destination buffer. sourceLen is
- the byte length of the source buffer. Upon entry, destLen is the total
- size of the destination buffer, which must be large enough to hold the
- entire uncompressed data. (The size of the uncompressed data must have
- been saved previously by the compressor and transmitted to the decompressor
- by some mechanism outside the scope of this compression library.)
- Upon exit, destLen is the actual size of the compressed buffer.
- This function can be used to decompress a whole file at once if the
- input file is mmap'ed.
-
- uncompress returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory, Z_BUF_ERROR if there was not enough room in the output
- buffer, or Z_DATA_ERROR if the input data was corrupted.
-*/
-int ZEXPORT uncompress (dest, destLen, source, sourceLen)
- Bytef *dest;
- uLongf *destLen;
- const Bytef *source;
- uLong sourceLen;
-{
- z_stream stream;
- int err;
-
- stream.next_in = (Bytef*)source;
- stream.avail_in = (uInt)sourceLen;
- /* Check for source > 64K on 16-bit machine: */
- if ((uLong)stream.avail_in != sourceLen) return Z_BUF_ERROR;
-
- stream.next_out = dest;
- stream.avail_out = (uInt)*destLen;
- if ((uLong)stream.avail_out != *destLen) return Z_BUF_ERROR;
-
- err = cramfs_inflateInit(&stream);
- if (err != Z_OK) return err;
-
- err = cramfs_inflate(&stream, Z_FINISH);
- if (err != Z_STREAM_END) {
- cramfs_inflateEnd(&stream);
- return err == Z_OK ? Z_BUF_ERROR : err;
- }
- *destLen = stream.total_out;
-
- err = cramfs_inflateEnd(&stream);
- return err;
-}
+++ /dev/null
-/* zconf.h -- configuration of the zlib compression library
- * Copyright (C) 1995-1998 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* @(#) $Id$ */
-
-#ifndef _ZCONF_H
-#define _ZCONF_H
-
-#if defined(__GNUC__) || defined(__386__) || defined(i386)
-# ifndef __32BIT__
-# define __32BIT__
-# endif
-#endif
-
-#if defined(__STDC__) || defined(__cplusplus)
-# ifndef STDC
-# define STDC
-# endif
-#endif
-
-/* The memory requirements for deflate are (in bytes):
- (1 << (windowBits+2)) + (1 << (memLevel+9))
- that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)
- plus a few kilobytes for small objects. For example, if you want to reduce
- the default memory requirements from 256K to 128K, compile with
- make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
- Of course this will generally degrade compression (there's no free lunch).
-
- The memory requirements for inflate are (in bytes) 1 << windowBits
- that is, 32K for windowBits=15 (default value) plus a few kilobytes
- for small objects.
-*/
-
-/* Maximum value for memLevel in deflateInit2 */
-#ifndef MAX_MEM_LEVEL
-# define MAX_MEM_LEVEL 9
-#endif
-
-/* Maximum value for windowBits in deflateInit2 and inflateInit2.
- * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
- * created by gzip. (Files created by minigzip can still be extracted by
- * gzip.)
- */
-#ifndef MAX_WBITS
-# define MAX_WBITS 15 /* 32K LZ77 window */
-#endif
-
- /* Type declarations */
-
-#ifndef OF /* function prototypes */
-# ifdef STDC
-# define OF(args) args
-# else
-# define OF(args) ()
-# endif
-#endif
-
-#ifndef ZEXPORT
-# define ZEXPORT
-#endif
-#ifndef ZEXPORTVA
-# define ZEXPORTVA
-#endif
-#ifndef ZEXTERN
-# define ZEXTERN extern
-#endif
-#ifndef FAR
-# define FAR
-#endif
-
-typedef unsigned char Byte; /* 8 bits */
-typedef unsigned int uInt; /* 16 bits or more */
-typedef unsigned long uLong; /* 32 bits or more */
-
-typedef Byte FAR Bytef;
-typedef char FAR charf;
-typedef int FAR intf;
-typedef uInt FAR uIntf;
-typedef uLong FAR uLongf;
-
-typedef void FAR *voidpf;
-typedef void *voidp;
-
-#include <linux/types.h> /* for off_t */
-#include <linux/unistd.h> /* for SEEK_* and off_t */
-#define z_off_t off_t
-
-#endif /* _ZCONF_H */
+++ /dev/null
-/* zlib.h -- interface of the 'zlib' general purpose compression library
- version 1.1.3, July 9th, 1998
-
- Copyright (C) 1995-1998 Jean-loup Gailly and Mark Adler
-
- This software is provided 'as-is', without any express or implied
- warranty. In no event will the authors be held liable for any damages
- arising from the use of this software.
-
- Permission is granted to anyone to use this software for any purpose,
- including commercial applications, and to alter it and redistribute it
- freely, subject to the following restrictions:
-
- 1. The origin of this software must not be misrepresented; you must not
- claim that you wrote the original software. If you use this software
- in a product, an acknowledgment in the product documentation would be
- appreciated but is not required.
- 2. Altered source versions must be plainly marked as such, and must not be
- misrepresented as being the original software.
- 3. This notice may not be removed or altered from any source distribution.
-
- Jean-loup Gailly Mark Adler
- jloup@gzip.org madler@alumni.caltech.edu
-
-
- The data format used by the zlib library is described by RFCs (Request for
- Comments) 1950 to 1952 in the files ftp://ds.internic.net/rfc/rfc1950.txt
- (zlib format), rfc1951.txt (deflate format) and rfc1952.txt (gzip format).
-*/
-
-#ifndef _ZLIB_H
-#define _ZLIB_H
-
-#include "zconf.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ZLIB_VERSION "1.1.3"
-
-/*
- The 'zlib' compression library provides in-memory compression and
- decompression functions, including integrity checks of the uncompressed
- data. This version of the library supports only one compression method
- (deflation) but other algorithms will be added later and will have the same
- stream interface.
-
- Compression can be done in a single step if the buffers are large
- enough (for example if an input file is mmap'ed), or can be done by
- repeated calls of the compression function. In the latter case, the
- application must provide more input and/or consume the output
- (providing more output space) before each call.
-
- The library also supports reading and writing files in gzip (.gz) format
- with an interface similar to that of stdio.
-
- The library does not install any signal handler. The decoder checks
- the consistency of the compressed data, so the library should never
- crash even in case of corrupted input.
-*/
-
-typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
-typedef void (*free_func) OF((voidpf opaque, voidpf address));
-
-struct internal_state;
-
-typedef struct z_stream_s {
- Bytef *next_in; /* next input byte */
- uInt avail_in; /* number of bytes available at next_in */
- uLong total_in; /* total nb of input bytes read so far */
-
- Bytef *next_out; /* next output byte should be put there */
- uInt avail_out; /* remaining free space at next_out */
- uLong total_out; /* total nb of bytes output so far */
-
- char *msg; /* last error message, NULL if no error */
- struct internal_state FAR *state; /* not visible by applications */
-
- alloc_func nozalloc; /* used to allocate the internal state */
- free_func nozfree; /* used to free the internal state */
- voidpf opaque; /* private data object passed to zalloc and zfree */
-
- int data_type; /* best guess about the data type: ascii or binary */
- uLong adler; /* adler32 value of the uncompressed data */
- uLong reserved; /* reserved for future use */
-} z_stream;
-
-typedef z_stream FAR *z_streamp;
-
-/*
- The application must update next_in and avail_in when avail_in has
- dropped to zero. It must update next_out and avail_out when avail_out
- has dropped to zero. The application must initialize zalloc, zfree and
- opaque before calling the init function. All other fields are set by the
- compression library and must not be updated by the application.
-
- The opaque value provided by the application will be passed as the first
- parameter for calls of zalloc and zfree. This can be useful for custom
- memory management. The compression library attaches no meaning to the
- opaque value.
-
- zalloc must return Z_NULL if there is not enough memory for the object.
- If zlib is used in a multi-threaded application, zalloc and zfree must be
- thread safe.
-
- On 16-bit systems, the functions zalloc and zfree must be able to allocate
- exactly 65536 bytes, but will not be required to allocate more than this
- if the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS,
- pointers returned by zalloc for objects of exactly 65536 bytes *must*
- have their offset normalized to zero. The default allocation function
- provided by this library ensures this (see zutil.c). To reduce memory
- requirements and avoid any allocation of 64K objects, at the expense of
- compression ratio, compile the library with -DMAX_WBITS=14 (see zconf.h).
-
- The fields total_in and total_out can be used for statistics or
- progress reports. After compression, total_in holds the total size of
- the uncompressed data and may be saved for use in the decompressor
- (particularly if the decompressor wants to decompress everything in
- a single step).
-*/
-
- /* constants */
-
-#define Z_NO_FLUSH 0
-#define Z_PARTIAL_FLUSH 1 /* will be removed, use Z_SYNC_FLUSH instead */
-#define Z_SYNC_FLUSH 2
-#define Z_FULL_FLUSH 3
-#define Z_FINISH 4
-/* Allowed flush values; see deflate() below for details */
-
-#define Z_OK 0
-#define Z_STREAM_END 1
-#define Z_NEED_DICT 2
-#define Z_ERRNO (-1)
-#define Z_STREAM_ERROR (-2)
-#define Z_DATA_ERROR (-3)
-#define Z_MEM_ERROR (-4)
-#define Z_BUF_ERROR (-5)
-#define Z_VERSION_ERROR (-6)
-/* Return codes for the compression/decompression functions. Negative
- * values are errors, positive values are used for special but normal events.
- */
-
-#define Z_NO_COMPRESSION 0
-#define Z_BEST_SPEED 1
-#define Z_BEST_COMPRESSION 9
-#define Z_DEFAULT_COMPRESSION (-1)
-/* compression levels */
-
-#define Z_FILTERED 1
-#define Z_HUFFMAN_ONLY 2
-#define Z_DEFAULT_STRATEGY 0
-/* compression strategy; see deflateInit2() below for details */
-
-#define Z_BINARY 0
-#define Z_ASCII 1
-#define Z_UNKNOWN 2
-/* Possible values of the data_type field */
-
-#define Z_DEFLATED 8
-/* The deflate compression method (the only one supported in this version) */
-
-#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */
-
-#define zlib_version zlibVersion()
-/* for compatibility with versions < 1.0.2 */
-
- /* basic functions */
-
-ZEXTERN const char * ZEXPORT zlibVersion OF((void));
-/* The application can compare zlibVersion and ZLIB_VERSION for consistency.
- If the first character differs, the library code actually used is
- not compatible with the zlib.h header file used by the application.
- This check is automatically made by deflateInit and inflateInit.
- */
-
-/*
-ZEXTERN int ZEXPORT deflateInit OF((z_streamp strm, int level));
-
- Initializes the internal stream state for compression. The fields
- zalloc, zfree and opaque must be initialized before by the caller.
- If zalloc and zfree are set to Z_NULL, deflateInit updates them to
- use default allocation functions.
-
- The compression level must be Z_DEFAULT_COMPRESSION, or between 0 and 9:
- 1 gives best speed, 9 gives best compression, 0 gives no compression at
- all (the input data is simply copied a block at a time).
- Z_DEFAULT_COMPRESSION requests a default compromise between speed and
- compression (currently equivalent to level 6).
-
- deflateInit returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory, Z_STREAM_ERROR if level is not a valid compression level,
- Z_VERSION_ERROR if the zlib library version (zlib_version) is incompatible
- with the version assumed by the caller (ZLIB_VERSION).
- msg is set to null if there is no error message. deflateInit does not
- perform any compression: this will be done by deflate().
-*/
-
-
-ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush));
-/*
- deflate compresses as much data as possible, and stops when the input
- buffer becomes empty or the output buffer becomes full. It may introduce some
- output latency (reading input without producing any output) except when
- forced to flush.
-
- The detailed semantics are as follows. deflate performs one or both of the
- following actions:
-
- - Compress more input starting at next_in and update next_in and avail_in
- accordingly. If not all input can be processed (because there is not
- enough room in the output buffer), next_in and avail_in are updated and
- processing will resume at this point for the next call of deflate().
-
- - Provide more output starting at next_out and update next_out and avail_out
- accordingly. This action is forced if the parameter flush is non zero.
- Forcing flush frequently degrades the compression ratio, so this parameter
- should be set only when necessary (in interactive applications).
- Some output may be provided even if flush is not set.
-
- Before the call of deflate(), the application should ensure that at least
- one of the actions is possible, by providing more input and/or consuming
- more output, and updating avail_in or avail_out accordingly; avail_out
- should never be zero before the call. The application can consume the
- compressed output when it wants, for example when the output buffer is full
- (avail_out == 0), or after each call of deflate(). If deflate returns Z_OK
- and with zero avail_out, it must be called again after making room in the
- output buffer because there might be more output pending.
-
- If the parameter flush is set to Z_SYNC_FLUSH, all pending output is
- flushed to the output buffer and the output is aligned on a byte boundary, so
- that the decompressor can get all input data available so far. (In particular
- avail_in is zero after the call if enough output space has been provided
- before the call.) Flushing may degrade compression for some compression
- algorithms and so it should be used only when necessary.
-
- If flush is set to Z_FULL_FLUSH, all output is flushed as with
- Z_SYNC_FLUSH, and the compression state is reset so that decompression can
- restart from this point if previous compressed data has been damaged or if
- random access is desired. Using Z_FULL_FLUSH too often can seriously degrade
- the compression.
-
- If deflate returns with avail_out == 0, this function must be called again
- with the same value of the flush parameter and more output space (updated
- avail_out), until the flush is complete (deflate returns with non-zero
- avail_out).
-
- If the parameter flush is set to Z_FINISH, pending input is processed,
- pending output is flushed and deflate returns with Z_STREAM_END if there
- was enough output space; if deflate returns with Z_OK, this function must be
- called again with Z_FINISH and more output space (updated avail_out) but no
- more input data, until it returns with Z_STREAM_END or an error. After
- deflate has returned Z_STREAM_END, the only possible operations on the
- stream are deflateReset or deflateEnd.
-
- Z_FINISH can be used immediately after deflateInit if all the compression
- is to be done in a single step. In this case, avail_out must be at least
- 0.1% larger than avail_in plus 12 bytes. If deflate does not return
- Z_STREAM_END, then it must be called again as described above.
-
- deflate() sets strm->adler to the adler32 checksum of all input read
- so far (that is, total_in bytes).
-
- deflate() may update data_type if it can make a good guess about
- the input data type (Z_ASCII or Z_BINARY). In doubt, the data is considered
- binary. This field is only for information purposes and does not affect
- the compression algorithm in any manner.
-
- deflate() returns Z_OK if some progress has been made (more input
- processed or more output produced), Z_STREAM_END if all input has been
- consumed and all output has been produced (only when flush is set to
- Z_FINISH), Z_STREAM_ERROR if the stream state was inconsistent (for example
- if next_in or next_out was NULL), Z_BUF_ERROR if no progress is possible
- (for example avail_in or avail_out was zero).
-*/
-
-
-ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm));
-/*
- All dynamically allocated data structures for this stream are freed.
- This function discards any unprocessed input and does not flush any
- pending output.
-
- deflateEnd returns Z_OK if success, Z_STREAM_ERROR if the
- stream state was inconsistent, Z_DATA_ERROR if the stream was freed
- prematurely (some input or output was discarded). In the error case,
- msg may be set but then points to a static string (which must not be
- deallocated).
-*/
-
-
-/*
-ZEXTERN int ZEXPORT cramfs_inflateInit OF((z_streamp strm));
-
- Initializes the internal stream state for decompression. The fields
- next_in, avail_in, zalloc, zfree and opaque must be initialized before by
- the caller. If next_in is not Z_NULL and avail_in is large enough (the exact
- value depends on the compression method), inflateInit determines the
- compression method from the zlib header and allocates all data structures
- accordingly; otherwise the allocation will be deferred to the first call of
- inflate. If zalloc and zfree are set to Z_NULL, inflateInit updates them to
- use default allocation functions.
-
- inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough
- memory, Z_VERSION_ERROR if the zlib library version is incompatible with the
- version assumed by the caller. msg is set to null if there is no error
- message. inflateInit does not perform any decompression apart from reading
- the zlib header if present: this will be done by inflate(). (So next_in and
- avail_in may be modified, but next_out and avail_out are unchanged.)
-*/
-
-
-ZEXTERN int ZEXPORT cramfs_inflate OF((z_streamp strm, int flush));
-/*
- inflate decompresses as much data as possible, and stops when the input
- buffer becomes empty or the output buffer becomes full. It may some
- introduce some output latency (reading input without producing any output)
- except when forced to flush.
-
- The detailed semantics are as follows. inflate performs one or both of the
- following actions:
-
- - Decompress more input starting at next_in and update next_in and avail_in
- accordingly. If not all input can be processed (because there is not
- enough room in the output buffer), next_in is updated and processing
- will resume at this point for the next call of inflate().
-
- - Provide more output starting at next_out and update next_out and avail_out
- accordingly. inflate() provides as much output as possible, until there
- is no more input data or no more space in the output buffer (see below
- about the flush parameter).
-
- Before the call of inflate(), the application should ensure that at least
- one of the actions is possible, by providing more input and/or consuming
- more output, and updating the next_* and avail_* values accordingly.
- The application can consume the uncompressed output when it wants, for
- example when the output buffer is full (avail_out == 0), or after each
- call of inflate(). If inflate returns Z_OK and with zero avail_out, it
- must be called again after making room in the output buffer because there
- might be more output pending.
-
- If the parameter flush is set to Z_SYNC_FLUSH, inflate flushes as much
- output as possible to the output buffer. The flushing behavior of inflate is
- not specified for values of the flush parameter other than Z_SYNC_FLUSH
- and Z_FINISH, but the current implementation actually flushes as much output
- as possible anyway.
-
- inflate() should normally be called until it returns Z_STREAM_END or an
- error. However if all decompression is to be performed in a single step
- (a single call of inflate), the parameter flush should be set to
- Z_FINISH. In this case all pending input is processed and all pending
- output is flushed; avail_out must be large enough to hold all the
- uncompressed data. (The size of the uncompressed data may have been saved
- by the compressor for this purpose.) The next operation on this stream must
- be inflateEnd to deallocate the decompression state. The use of Z_FINISH
- is never required, but can be used to inform inflate that a faster routine
- may be used for the single inflate() call.
-
- If a preset dictionary is needed at this point (see inflateSetDictionary
- below), inflate sets strm-adler to the adler32 checksum of the
- dictionary chosen by the compressor and returns Z_NEED_DICT; otherwise
- it sets strm->adler to the adler32 checksum of all output produced
- so far (that is, total_out bytes) and returns Z_OK, Z_STREAM_END or
- an error code as described below. At the end of the stream, inflate()
- checks that its computed adler32 checksum is equal to that saved by the
- compressor and returns Z_STREAM_END only if the checksum is correct.
-
- inflate() returns Z_OK if some progress has been made (more input processed
- or more output produced), Z_STREAM_END if the end of the compressed data has
- been reached and all uncompressed output has been produced, Z_NEED_DICT if a
- preset dictionary is needed at this point, Z_DATA_ERROR if the input data was
- corrupted (input stream not conforming to the zlib format or incorrect
- adler32 checksum), Z_STREAM_ERROR if the stream structure was inconsistent
- (for example if next_in or next_out was NULL), Z_MEM_ERROR if there was not
- enough memory, Z_BUF_ERROR if no progress is possible or if there was not
- enough room in the output buffer when Z_FINISH is used. In the Z_DATA_ERROR
- case, the application may then call inflateSync to look for a good
- compression block.
-*/
-
-
-ZEXTERN int ZEXPORT cramfs_inflateEnd OF((z_streamp strm));
-/*
- All dynamically allocated data structures for this stream are freed.
- This function discards any unprocessed input and does not flush any
- pending output.
-
- inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
- was inconsistent. In the error case, msg may be set but then points to a
- static string (which must not be deallocated).
-*/
-
- /* Advanced functions */
-
-/*
- The following functions are needed only in some special applications.
-*/
-
-/*
-ZEXTERN int ZEXPORT deflateInit2 OF((z_streamp strm,
- int level,
- int method,
- int windowBits,
- int memLevel,
- int strategy));
-
- This is another version of deflateInit with more compression options. The
- fields next_in, zalloc, zfree and opaque must be initialized before by
- the caller.
-
- The method parameter is the compression method. It must be Z_DEFLATED in
- this version of the library.
-
- The windowBits parameter is the base two logarithm of the window size
- (the size of the history buffer). It should be in the range 8..15 for this
- version of the library. Larger values of this parameter result in better
- compression at the expense of memory usage. The default value is 15 if
- deflateInit is used instead.
-
- The memLevel parameter specifies how much memory should be allocated
- for the internal compression state. memLevel=1 uses minimum memory but
- is slow and reduces compression ratio; memLevel=9 uses maximum memory
- for optimal speed. The default value is 8. See zconf.h for total memory
- usage as a function of windowBits and memLevel.
-
- The strategy parameter is used to tune the compression algorithm. Use the
- value Z_DEFAULT_STRATEGY for normal data, Z_FILTERED for data produced by a
- filter (or predictor), or Z_HUFFMAN_ONLY to force Huffman encoding only (no
- string match). Filtered data consists mostly of small values with a
- somewhat random distribution. In this case, the compression algorithm is
- tuned to compress them better. The effect of Z_FILTERED is to force more
- Huffman coding and less string matching; it is somewhat intermediate
- between Z_DEFAULT and Z_HUFFMAN_ONLY. The strategy parameter only affects
- the compression ratio but not the correctness of the compressed output even
- if it is not set appropriately.
-
- deflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough
- memory, Z_STREAM_ERROR if a parameter is invalid (such as an invalid
- method). msg is set to null if there is no error message. deflateInit2 does
- not perform any compression: this will be done by deflate().
-*/
-
-ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm,
- const Bytef *dictionary,
- uInt dictLength));
-/*
- Initializes the compression dictionary from the given byte sequence
- without producing any compressed output. This function must be called
- immediately after deflateInit, deflateInit2 or deflateReset, before any
- call of deflate. The compressor and decompressor must use exactly the same
- dictionary (see inflateSetDictionary).
-
- The dictionary should consist of strings (byte sequences) that are likely
- to be encountered later in the data to be compressed, with the most commonly
- used strings preferably put towards the end of the dictionary. Using a
- dictionary is most useful when the data to be compressed is short and can be
- predicted with good accuracy; the data can then be compressed better than
- with the default empty dictionary.
-
- Depending on the size of the compression data structures selected by
- deflateInit or deflateInit2, a part of the dictionary may in effect be
- discarded, for example if the dictionary is larger than the window size in
- deflate or deflate2. Thus the strings most likely to be useful should be
- put at the end of the dictionary, not at the front.
-
- Upon return of this function, strm->adler is set to the Adler32 value
- of the dictionary; the decompressor may later use this value to determine
- which dictionary has been used by the compressor. (The Adler32 value
- applies to the whole dictionary even if only a subset of the dictionary is
- actually used by the compressor.)
-
- deflateSetDictionary returns Z_OK if success, or Z_STREAM_ERROR if a
- parameter is invalid (such as NULL dictionary) or the stream state is
- inconsistent (for example if deflate has already been called for this stream
- or if the compression method is bsort). deflateSetDictionary does not
- perform any compression: this will be done by deflate().
-*/
-
-ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest,
- z_streamp source));
-/*
- Sets the destination stream as a complete copy of the source stream.
-
- This function can be useful when several compression strategies will be
- tried, for example when there are several ways of pre-processing the input
- data with a filter. The streams that will be discarded should then be freed
- by calling deflateEnd. Note that deflateCopy duplicates the internal
- compression state which can be quite large, so this strategy is slow and
- can consume lots of memory.
-
- deflateCopy returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory, Z_STREAM_ERROR if the source stream state was inconsistent
- (such as zalloc being NULL). msg is left unchanged in both source and
- destination.
-*/
-
-ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm));
-/*
- This function is equivalent to deflateEnd followed by deflateInit,
- but does not free and reallocate all the internal compression state.
- The stream will keep the same compression level and any other attributes
- that may have been set by deflateInit2.
-
- deflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source
- stream state was inconsistent (such as zalloc or state being NULL).
-*/
-
-ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm,
- int level,
- int strategy));
-/*
- Dynamically update the compression level and compression strategy. The
- interpretation of level and strategy is as in deflateInit2. This can be
- used to switch between compression and straight copy of the input data, or
- to switch to a different kind of input data requiring a different
- strategy. If the compression level is changed, the input available so far
- is compressed with the old level (and may be flushed); the new level will
- take effect only at the next call of deflate().
-
- Before the call of deflateParams, the stream state must be set as for
- a call of deflate(), since the currently available input may have to
- be compressed and flushed. In particular, strm->avail_out must be non-zero.
-
- deflateParams returns Z_OK if success, Z_STREAM_ERROR if the source
- stream state was inconsistent or if a parameter was invalid, Z_BUF_ERROR
- if strm->avail_out was zero.
-*/
-
-/*
-ZEXTERN int ZEXPORT inflateInit2 OF((z_streamp strm,
- int windowBits));
-
- This is another version of inflateInit with an extra parameter. The
- fields next_in, avail_in, zalloc, zfree and opaque must be initialized
- before by the caller.
-
- The windowBits parameter is the base two logarithm of the maximum window
- size (the size of the history buffer). It should be in the range 8..15 for
- this version of the library. The default value is 15 if inflateInit is used
- instead. If a compressed stream with a larger window size is given as
- input, inflate() will return with the error code Z_DATA_ERROR instead of
- trying to allocate a larger window.
-
- inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough
- memory, Z_STREAM_ERROR if a parameter is invalid (such as a negative
- memLevel). msg is set to null if there is no error message. inflateInit2
- does not perform any decompression apart from reading the zlib header if
- present: this will be done by inflate(). (So next_in and avail_in may be
- modified, but next_out and avail_out are unchanged.)
-*/
-
-ZEXTERN int ZEXPORT inflateSetDictionary OF((z_streamp strm,
- const Bytef *dictionary,
- uInt dictLength));
-/*
- Initializes the decompression dictionary from the given uncompressed byte
- sequence. This function must be called immediately after a call of inflate
- if this call returned Z_NEED_DICT. The dictionary chosen by the compressor
- can be determined from the Adler32 value returned by this call of
- inflate. The compressor and decompressor must use exactly the same
- dictionary (see deflateSetDictionary).
-
- inflateSetDictionary returns Z_OK if success, Z_STREAM_ERROR if a
- parameter is invalid (such as NULL dictionary) or the stream state is
- inconsistent, Z_DATA_ERROR if the given dictionary doesn't match the
- expected one (incorrect Adler32 value). inflateSetDictionary does not
- perform any decompression: this will be done by subsequent calls of
- inflate().
-*/
-
-ZEXTERN int ZEXPORT cramfs_inflateSync OF((z_streamp strm));
-/*
- Skips invalid compressed data until a full flush point (see above the
- description of deflate with Z_FULL_FLUSH) can be found, or until all
- available input is skipped. No output is provided.
-
- inflateSync returns Z_OK if a full flush point has been found, Z_BUF_ERROR
- if no more input was provided, Z_DATA_ERROR if no flush point has been found,
- or Z_STREAM_ERROR if the stream structure was inconsistent. In the success
- case, the application may save the current current value of total_in which
- indicates where valid compressed data was found. In the error case, the
- application may repeatedly call inflateSync, providing more input each time,
- until success or end of the input data.
-*/
-
-ZEXTERN int ZEXPORT cramfs_inflateReset OF((z_streamp strm));
-/*
- This function is equivalent to inflateEnd followed by inflateInit,
- but does not free and reallocate all the internal decompression state.
- The stream will keep attributes that may have been set by inflateInit2.
-
- inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source
- stream state was inconsistent (such as zalloc or state being NULL).
-*/
-
-
- /* utility functions */
-
-/*
- The following utility functions are implemented on top of the
- basic stream-oriented functions. To simplify the interface, some
- default options are assumed (compression level and memory usage,
- standard memory allocation functions). The source code of these
- utility functions can easily be modified if you need special options.
-*/
-
-ZEXTERN int ZEXPORT compress OF((Bytef *dest, uLongf *destLen,
- const Bytef *source, uLong sourceLen));
-/*
- Compresses the source buffer into the destination buffer. sourceLen is
- the byte length of the source buffer. Upon entry, destLen is the total
- size of the destination buffer, which must be at least 0.1% larger than
- sourceLen plus 12 bytes. Upon exit, destLen is the actual size of the
- compressed buffer.
- This function can be used to compress a whole file at once if the
- input file is mmap'ed.
- compress returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory, Z_BUF_ERROR if there was not enough room in the output
- buffer.
-*/
-
-ZEXTERN int ZEXPORT compress2 OF((Bytef *dest, uLongf *destLen,
- const Bytef *source, uLong sourceLen,
- int level));
-/*
- Compresses the source buffer into the destination buffer. The level
- parameter has the same meaning as in deflateInit. sourceLen is the byte
- length of the source buffer. Upon entry, destLen is the total size of the
- destination buffer, which must be at least 0.1% larger than sourceLen plus
- 12 bytes. Upon exit, destLen is the actual size of the compressed buffer.
-
- compress2 returns Z_OK if success, Z_MEM_ERROR if there was not enough
- memory, Z_BUF_ERROR if there was not enough room in the output buffer,
- Z_STREAM_ERROR if the level parameter is invalid.
-*/
-
-ZEXTERN int ZEXPORT uncompress OF((Bytef *dest, uLongf *destLen,
- const Bytef *source, uLong sourceLen));
-/*
- Decompresses the source buffer into the destination buffer. sourceLen is
- the byte length of the source buffer. Upon entry, destLen is the total
- size of the destination buffer, which must be large enough to hold the
- entire uncompressed data. (The size of the uncompressed data must have
- been saved previously by the compressor and transmitted to the decompressor
- by some mechanism outside the scope of this compression library.)
- Upon exit, destLen is the actual size of the compressed buffer.
- This function can be used to decompress a whole file at once if the
- input file is mmap'ed.
-
- uncompress returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory, Z_BUF_ERROR if there was not enough room in the output
- buffer, or Z_DATA_ERROR if the input data was corrupted.
-*/
-
-
-typedef voidp gzFile;
-
-ZEXTERN gzFile ZEXPORT gzopen OF((const char *path, const char *mode));
-/*
- Opens a gzip (.gz) file for reading or writing. The mode parameter
- is as in fopen ("rb" or "wb") but can also include a compression level
- ("wb9") or a strategy: 'f' for filtered data as in "wb6f", 'h' for
- Huffman only compression as in "wb1h". (See the description
- of deflateInit2 for more information about the strategy parameter.)
-
- gzopen can be used to read a file which is not in gzip format; in this
- case gzread will directly read from the file without decompression.
-
- gzopen returns NULL if the file could not be opened or if there was
- insufficient memory to allocate the (de)compression state; errno
- can be checked to distinguish the two cases (if errno is zero, the
- zlib error is Z_MEM_ERROR). */
-
-ZEXTERN gzFile ZEXPORT gzdopen OF((int fd, const char *mode));
-/*
- gzdopen() associates a gzFile with the file descriptor fd. File
- descriptors are obtained from calls like open, dup, creat, pipe or
- fileno (in the file has been previously opened with fopen).
- The mode parameter is as in gzopen.
- The next call of gzclose on the returned gzFile will also close the
- file descriptor fd, just like fclose(fdopen(fd), mode) closes the file
- descriptor fd. If you want to keep fd open, use gzdopen(dup(fd), mode).
- gzdopen returns NULL if there was insufficient memory to allocate
- the (de)compression state.
-*/
-
-ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy));
-/*
- Dynamically update the compression level or strategy. See the description
- of deflateInit2 for the meaning of these parameters.
- gzsetparams returns Z_OK if success, or Z_STREAM_ERROR if the file was not
- opened for writing.
-*/
-
-ZEXTERN int ZEXPORT gzread OF((gzFile file, voidp buf, unsigned len));
-/*
- Reads the given number of uncompressed bytes from the compressed file.
- If the input file was not in gzip format, gzread copies the given number
- of bytes into the buffer.
- gzread returns the number of uncompressed bytes actually read (0 for
- end of file, -1 for error). */
-
-ZEXTERN int ZEXPORT gzwrite OF((gzFile file,
- const voidp buf, unsigned len));
-/*
- Writes the given number of uncompressed bytes into the compressed file.
- gzwrite returns the number of uncompressed bytes actually written
- (0 in case of error).
-*/
-
-ZEXTERN int ZEXPORTVA gzprintf OF((gzFile file, const char *format, ...));
-/*
- Converts, formats, and writes the args to the compressed file under
- control of the format string, as in fprintf. gzprintf returns the number of
- uncompressed bytes actually written (0 in case of error).
-*/
-
-ZEXTERN int ZEXPORT gzputs OF((gzFile file, const char *s));
-/*
- Writes the given null-terminated string to the compressed file, excluding
- the terminating null character.
- gzputs returns the number of characters written, or -1 in case of error.
-*/
-
-ZEXTERN char * ZEXPORT gzgets OF((gzFile file, char *buf, int len));
-/*
- Reads bytes from the compressed file until len-1 characters are read, or
- a newline character is read and transferred to buf, or an end-of-file
- condition is encountered. The string is then terminated with a null
- character.
- gzgets returns buf, or Z_NULL in case of error.
-*/
-
-ZEXTERN int ZEXPORT gzputc OF((gzFile file, int c));
-/*
- Writes c, converted to an unsigned char, into the compressed file.
- gzputc returns the value that was written, or -1 in case of error.
-*/
-
-ZEXTERN int ZEXPORT gzgetc OF((gzFile file));
-/*
- Reads one byte from the compressed file. gzgetc returns this byte
- or -1 in case of end of file or error.
-*/
-
-ZEXTERN int ZEXPORT gzflush OF((gzFile file, int flush));
-/*
- Flushes all pending output into the compressed file. The parameter
- flush is as in the deflate() function. The return value is the zlib
- error number (see function gzerror below). gzflush returns Z_OK if
- the flush parameter is Z_FINISH and all output could be flushed.
- gzflush should be called only when strictly necessary because it can
- degrade compression.
-*/
-
-ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile file,
- z_off_t offset, int whence));
-/*
- Sets the starting position for the next gzread or gzwrite on the
- given compressed file. The offset represents a number of bytes in the
- uncompressed data stream. The whence parameter is defined as in lseek(2);
- the value SEEK_END is not supported.
- If the file is opened for reading, this function is emulated but can be
- extremely slow. If the file is opened for writing, only forward seeks are
- supported; gzseek then compresses a sequence of zeroes up to the new
- starting position.
-
- gzseek returns the resulting offset location as measured in bytes from
- the beginning of the uncompressed stream, or -1 in case of error, in
- particular if the file is opened for writing and the new starting position
- would be before the current position.
-*/
-
-ZEXTERN int ZEXPORT gzrewind OF((gzFile file));
-/*
- Rewinds the given file. This function is supported only for reading.
-
- gzrewind(file) is equivalent to (int)gzseek(file, 0L, SEEK_SET)
-*/
-
-ZEXTERN z_off_t ZEXPORT gztell OF((gzFile file));
-/*
- Returns the starting position for the next gzread or gzwrite on the
- given compressed file. This position represents a number of bytes in the
- uncompressed data stream.
-
- gztell(file) is equivalent to gzseek(file, 0L, SEEK_CUR)
-*/
-
-ZEXTERN int ZEXPORT gzeof OF((gzFile file));
-/*
- Returns 1 when EOF has previously been detected reading the given
- input stream, otherwise zero.
-*/
-
-ZEXTERN int ZEXPORT gzclose OF((gzFile file));
-/*
- Flushes all pending output if necessary, closes the compressed file
- and deallocates all the (de)compression state. The return value is the zlib
- error number (see function gzerror below).
-*/
-
-ZEXTERN const char * ZEXPORT gzerror OF((gzFile file, int *errnum));
-/*
- Returns the error message for the last error which occurred on the
- given compressed file. errnum is set to zlib error number. If an
- error occurred in the file system and not in the compression library,
- errnum is set to Z_ERRNO and the application may consult errno
- to get the exact error code.
-*/
-
- /* checksum functions */
-
-/*
- These functions are not related to compression but are exported
- anyway because they might be useful in applications using the
- compression library.
-*/
-
-ZEXTERN uLong ZEXPORT cramfs_adler32 OF((uLong adler, const Bytef *buf, uInt len));
-
-/*
- Update a running Adler-32 checksum with the bytes buf[0..len-1] and
- return the updated checksum. If buf is NULL, this function returns
- the required initial value for the checksum.
- An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
- much faster. Usage example:
-
- uLong adler = adler32(0L, Z_NULL, 0);
-
- while (read_buffer(buffer, length) != EOF) {
- adler = adler32(adler, buffer, length);
- }
- if (adler != original_adler) error();
-*/
-
-ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len));
-/*
- Update a running crc with the bytes buf[0..len-1] and return the updated
- crc. If buf is NULL, this function returns the required initial value
- for the crc. Pre- and post-conditioning (one's complement) is performed
- within this function so it shouldn't be done by the application.
- Usage example:
-
- uLong crc = crc32(0L, Z_NULL, 0);
-
- while (read_buffer(buffer, length) != EOF) {
- crc = crc32(crc, buffer, length);
- }
- if (crc != original_crc) error();
-*/
-
-
- /* various hacks, don't look :) */
-
-/* deflateInit and inflateInit are macros to allow checking the zlib version
- * and the compiler's view of z_stream:
- */
-ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level,
- const char *version, int stream_size));
-ZEXTERN int ZEXPORT cramfs_inflateInit_ OF((z_streamp strm,
- const char *version, int stream_size));
-ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method,
- int windowBits, int memLevel,
- int strategy, const char *version,
- int stream_size));
-ZEXTERN int ZEXPORT cramfs_inflateInit2_ OF((z_streamp strm, int windowBits,
- const char *version, int stream_size));
-#define deflateInit(strm, level) \
- deflateInit_((strm), (level), ZLIB_VERSION, sizeof(z_stream))
-#define cramfs_inflateInit(strm) \
- cramfs_inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream))
-#define deflateInit2(strm, level, method, windowBits, memLevel, strategy) \
- deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\
- (strategy), ZLIB_VERSION, sizeof(z_stream))
-#define inflateInit2(strm, windowBits) \
- cramfs_inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream))
-
-
-#if !defined(_Z_UTIL_H) && !defined(NO_DUMMY_DECL)
- struct internal_state {int dummy;}; /* hack for buggy compilers */
-#endif
-
-ZEXTERN const char * ZEXPORT zError OF((int err));
-ZEXTERN int ZEXPORT cramfs_inflateSyncPoint OF((z_streamp z));
-ZEXTERN const uLongf * ZEXPORT get_crc_table OF((void));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ZLIB_H */
+++ /dev/null
-/* zutil.h -- internal interface and configuration of the compression library
- * Copyright (C) 1995-1998 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* WARNING: this file should *not* be used by applications. It is
- part of the implementation of the compression library and is
- subject to change. Applications should only use zlib.h.
- */
-
-/* @(#) $Id: zutil.h,v 1.1 2000/01/01 03:32:23 davem Exp $ */
-
-#ifndef _Z_UTIL_H
-#define _Z_UTIL_H
-
-#include "zlib.h"
-
-#include <linux/string.h>
-#include <linux/errno.h>
-
-#ifndef local
-# define local static
-#endif
-/* compile with -Dlocal if your debugger can't find static symbols */
-
-typedef unsigned char uch;
-typedef uch FAR uchf;
-typedef unsigned short ush;
-typedef ush FAR ushf;
-typedef unsigned long ulg;
-
- /* common constants */
-
-#ifndef DEF_WBITS
-# define DEF_WBITS MAX_WBITS
-#endif
-/* default windowBits for decompression. MAX_WBITS is for compression only */
-
-#if MAX_MEM_LEVEL >= 8
-# define DEF_MEM_LEVEL 8
-#else
-# define DEF_MEM_LEVEL MAX_MEM_LEVEL
-#endif
-/* default memLevel */
-
-#define STORED_BLOCK 0
-#define STATIC_TREES 1
-#define DYN_TREES 2
-/* The three kinds of block type */
-
-#define MIN_MATCH 3
-#define MAX_MATCH 258
-/* The minimum and maximum match lengths */
-
-#define PRESET_DICT 0x20 /* preset dictionary flag in zlib header */
-
- /* target dependencies */
-
- /* Common defaults */
-
-#ifndef OS_CODE
-# define OS_CODE 0x03 /* assume Unix */
-#endif
-
- /* functions */
-
-typedef uLong (ZEXPORT *check_func) OF((uLong check, const Bytef *buf,
- uInt len));
-
-#endif /* _Z_UTIL_H */
struct buffer_head * bh = bh_array[i];
if (bh) {
memcpy(data, bh->b_data, PAGE_CACHE_SIZE);
- bforget(bh);
+ brelse(bh);
} else
memset(data, 0, PAGE_CACHE_SIZE);
data += PAGE_CACHE_SIZE;
module_init(init_cramfs_fs)
module_exit(exit_cramfs_fs)
+MODULE_LICENSE("GPL");
+
*/
#include <linux/kernel.h>
-
-#include "inflate/zlib.h"
+#include <linux/errno.h>
+#include <linux/vmalloc.h>
+#include <linux/zlib_fs.h>
static z_stream stream;
static int initialized;
stream.next_out = dst;
stream.avail_out = dstlen;
- err = cramfs_inflateReset(&stream);
+ err = zlib_fs_inflateReset(&stream);
if (err != Z_OK) {
- printk("cramfs_inflateReset error %d\n", err);
- cramfs_inflateEnd(&stream);
- cramfs_inflateInit(&stream);
+ printk("zlib_fs_inflateReset error %d\n", err);
+ zlib_fs_inflateEnd(&stream);
+ zlib_fs_inflateInit(&stream);
}
- err = cramfs_inflate(&stream, Z_FINISH);
+ err = zlib_fs_inflate(&stream, Z_FINISH);
if (err != Z_STREAM_END)
goto err;
return stream.total_out;
int cramfs_uncompress_init(void)
{
if (!initialized++) {
+ stream.workspace = vmalloc(zlib_fs_inflate_workspacesize());
+ if ( !stream.workspace ) {
+ initialized = 0;
+ return -ENOMEM;
+ }
stream.next_in = NULL;
stream.avail_in = 0;
- cramfs_inflateInit(&stream);
+ zlib_fs_inflateInit(&stream);
}
return 0;
}
int cramfs_uncompress_exit(void)
{
- if (!--initialized)
- cramfs_inflateEnd(&stream);
+ if (!--initialized) {
+ zlib_fs_inflateEnd(&stream);
+ vfree(stream.workspace);
+ }
return 0;
}
goto out;
if (!pte_none(*pte))
goto out;
+ lru_cache_add(page);
flush_dcache_page(page);
flush_page_to_ram(page);
set_pte(pte, pte_mkdirty(pte_mkwrite(mk_pte(page, PAGE_COPY))));
--- /dev/null
+#
+# This is a modified version of zlib, which does all memory
+# allocation ahead of time.
+#
+# Currently only decompression is supported.
+#
+# Decompression needs to be serialized for each memory
+# allocation.
+#
+#
+# (The upsides of the simplification is that you can't get in
+# any nasty situations wrt memory management, and that the
+# uncompression can be done without blocking on allocation).
+#
+# The modules are named *_fs.o to distinguish from other modified
+# compression libraries, like the one used by ppp.
+#
+# It is expected that when a deflate module is added it will be
+# a separate module in a deflate_fs directory, to avoid having to
+# load the deflate code for readonly filesystems.
+#
+
+O_TARGET := inflate_fs.o
+
+export-objs := inflate_syms.o
+
+obj-y := adler32.o infblock.o infcodes.o inffast.o inflate.o \
+ inftrees.o infutil.o inflate_syms.o
+obj-m := $(O_TARGET)
+
+EXTRA_CFLAGS += -I $(TOPDIR)/fs/inflate_fs
+
+include $(TOPDIR)/Rules.make
--- /dev/null
+/* adler32.c -- compute the Adler-32 checksum of a data stream
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* @(#) $Id$ */
+
+#include <linux/zlib_fs.h>
+
+#define BASE 65521L /* largest prime smaller than 65536 */
+#define NMAX 5552
+/* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
+
+#define DO1(buf,i) {s1 += buf[i]; s2 += s1;}
+#define DO2(buf,i) DO1(buf,i); DO1(buf,i+1);
+#define DO4(buf,i) DO2(buf,i); DO2(buf,i+2);
+#define DO8(buf,i) DO4(buf,i); DO4(buf,i+4);
+#define DO16(buf) DO8(buf,0); DO8(buf,8);
+
+/* ========================================================================= */
+uLong ZEXPORT zlib_fs_adler32(adler, buf, len)
+ uLong adler;
+ const Bytef *buf;
+ uInt len;
+{
+ unsigned long s1 = adler & 0xffff;
+ unsigned long s2 = (adler >> 16) & 0xffff;
+ int k;
+
+ if (buf == Z_NULL) return 1L;
+
+ while (len > 0) {
+ k = len < NMAX ? len : NMAX;
+ len -= k;
+ while (k >= 16) {
+ DO16(buf);
+ buf += 16;
+ k -= 16;
+ }
+ if (k != 0) do {
+ s1 += *buf++;
+ s2 += s1;
+ } while (--k);
+ s1 %= BASE;
+ s2 %= BASE;
+ }
+ return (s2 << 16) | s1;
+}
--- /dev/null
+/* infblock.c -- interpret and process block types to last block
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include "zutil.h"
+#include "infblock.h"
+#include "inftrees.h"
+#include "infcodes.h"
+#include "infutil.h"
+
+struct inflate_codes_state;
+
+/* simplify the use of the inflate_huft type with some defines */
+#define exop word.what.Exop
+#define bits word.what.Bits
+
+/* Table for deflate from PKZIP's appnote.txt. */
+local const uInt border[] = { /* Order of the bit length code lengths */
+ 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15};
+
+/*
+ Notes beyond the 1.93a appnote.txt:
+
+ 1. Distance pointers never point before the beginning of the output
+ stream.
+ 2. Distance pointers can point back across blocks, up to 32k away.
+ 3. There is an implied maximum of 7 bits for the bit length table and
+ 15 bits for the actual data.
+ 4. If only one code exists, then it is encoded using one bit. (Zero
+ would be more efficient, but perhaps a little confusing.) If two
+ codes exist, they are coded using one bit each (0 and 1).
+ 5. There is no way of sending zero distance codes--a dummy must be
+ sent if there are none. (History: a pre 2.0 version of PKZIP would
+ store blocks with no distance codes, but this was discovered to be
+ too harsh a criterion.) Valid only for 1.93a. 2.04c does allow
+ zero distance codes, which is sent as one code of zero bits in
+ length.
+ 6. There are up to 286 literal/length codes. Code 256 represents the
+ end-of-block. Note however that the static length tree defines
+ 288 codes just to fill out the Huffman codes. Codes 286 and 287
+ cannot be used though, since there is no length base or extra bits
+ defined for them. Similarily, there are up to 30 distance codes.
+ However, static trees define 32 codes (all 5 bits) to fill out the
+ Huffman codes, but the last two had better not show up in the data.
+ 7. Unzip can check dynamic Huffman blocks for complete code sets.
+ The exception is that a single code would not be complete (see #4).
+ 8. The five bits following the block type is really the number of
+ literal codes sent minus 257.
+ 9. Length codes 8,16,16 are interpreted as 13 length codes of 8 bits
+ (1+6+6). Therefore, to output three times the length, you output
+ three codes (1+1+1), whereas to output four times the same length,
+ you only need two codes (1+3). Hmm.
+ 10. In the tree reconstruction algorithm, Code = Code + Increment
+ only if BitLength(i) is not zero. (Pretty obvious.)
+ 11. Correction: 4 Bits: # of Bit Length codes - 4 (4 - 19)
+ 12. Note: length code 284 can represent 227-258, but length code 285
+ really is 258. The last length deserves its own, short code
+ since it gets used a lot in very redundant files. The length
+ 258 is special since 258 - 3 (the min match length) is 255.
+ 13. The literal/length and distance code bit lengths are read as a
+ single stream of lengths. It is possible (and advantageous) for
+ a repeat code (16, 17, or 18) to go across the boundary between
+ the two sets of lengths.
+ */
+
+
+void zlib_fs_inflate_blocks_reset(s, z, c)
+inflate_blocks_statef *s;
+z_streamp z;
+uLongf *c;
+{
+ if (c != Z_NULL)
+ *c = s->check;
+ if (s->mode == CODES)
+ zlib_fs_inflate_codes_free(s->sub.decode.codes, z);
+ s->mode = TYPE;
+ s->bitk = 0;
+ s->bitb = 0;
+ s->read = s->write = s->window;
+ if (s->checkfn != Z_NULL)
+ z->adler = s->check = (*s->checkfn)(0L, (const Bytef *)Z_NULL, 0);
+}
+
+inflate_blocks_statef *zlib_fs_inflate_blocks_new(z, c, w)
+z_streamp z;
+check_func c;
+uInt w;
+{
+ inflate_blocks_statef *s;
+
+ s = &WS(z)->working_blocks_state;
+ s->hufts = WS(z)->working_hufts;
+ s->window = WS(z)->working_window;
+ s->end = s->window + w;
+ s->checkfn = c;
+ s->mode = TYPE;
+ zlib_fs_inflate_blocks_reset(s, z, Z_NULL);
+ return s;
+}
+
+
+int zlib_fs_inflate_blocks(s, z, r)
+inflate_blocks_statef *s;
+z_streamp z;
+int r;
+{
+ uInt t; /* temporary storage */
+ uLong b; /* bit buffer */
+ uInt k; /* bits in bit buffer */
+ Bytef *p; /* input data pointer */
+ uInt n; /* bytes available there */
+ Bytef *q; /* output window write pointer */
+ uInt m; /* bytes to end of window or read pointer */
+
+ /* copy input/output information to locals (UPDATE macro restores) */
+ LOAD
+
+ /* process input based on current state */
+ while (1) switch (s->mode)
+ {
+ case TYPE:
+ NEEDBITS(3)
+ t = (uInt)b & 7;
+ s->last = t & 1;
+ switch (t >> 1)
+ {
+ case 0: /* stored */
+ DUMPBITS(3)
+ t = k & 7; /* go to byte boundary */
+ DUMPBITS(t)
+ s->mode = LENS; /* get length of stored block */
+ break;
+ case 1: /* fixed */
+ {
+ uInt bl, bd;
+ inflate_huft *tl, *td;
+
+ zlib_fs_inflate_trees_fixed(&bl, &bd, &tl, &td, z);
+ s->sub.decode.codes = zlib_fs_inflate_codes_new(bl, bd, tl, td, z);
+ if (s->sub.decode.codes == Z_NULL)
+ {
+ r = Z_MEM_ERROR;
+ LEAVE
+ }
+ }
+ DUMPBITS(3)
+ s->mode = CODES;
+ break;
+ case 2: /* dynamic */
+ DUMPBITS(3)
+ s->mode = TABLE;
+ break;
+ case 3: /* illegal */
+ DUMPBITS(3)
+ s->mode = B_BAD;
+ z->msg = (char*)"invalid block type";
+ r = Z_DATA_ERROR;
+ LEAVE
+ }
+ break;
+ case LENS:
+ NEEDBITS(32)
+ if ((((~b) >> 16) & 0xffff) != (b & 0xffff))
+ {
+ s->mode = B_BAD;
+ z->msg = (char*)"invalid stored block lengths";
+ r = Z_DATA_ERROR;
+ LEAVE
+ }
+ s->sub.left = (uInt)b & 0xffff;
+ b = k = 0; /* dump bits */
+ s->mode = s->sub.left ? STORED : (s->last ? DRY : TYPE);
+ break;
+ case STORED:
+ if (n == 0)
+ LEAVE
+ NEEDOUT
+ t = s->sub.left;
+ if (t > n) t = n;
+ if (t > m) t = m;
+ memcpy(q, p, t);
+ p += t; n -= t;
+ q += t; m -= t;
+ if ((s->sub.left -= t) != 0)
+ break;
+ s->mode = s->last ? DRY : TYPE;
+ break;
+ case TABLE:
+ NEEDBITS(14)
+ s->sub.trees.table = t = (uInt)b & 0x3fff;
+#ifndef PKZIP_BUG_WORKAROUND
+ if ((t & 0x1f) > 29 || ((t >> 5) & 0x1f) > 29)
+ {
+ s->mode = B_BAD;
+ z->msg = (char*)"too many length or distance symbols";
+ r = Z_DATA_ERROR;
+ LEAVE
+ }
+#endif
+ {
+ s->sub.trees.blens = WS(z)->working_blens;
+ }
+ DUMPBITS(14)
+ s->sub.trees.index = 0;
+ s->mode = BTREE;
+ case BTREE:
+ while (s->sub.trees.index < 4 + (s->sub.trees.table >> 10))
+ {
+ NEEDBITS(3)
+ s->sub.trees.blens[border[s->sub.trees.index++]] = (uInt)b & 7;
+ DUMPBITS(3)
+ }
+ while (s->sub.trees.index < 19)
+ s->sub.trees.blens[border[s->sub.trees.index++]] = 0;
+ s->sub.trees.bb = 7;
+ t = zlib_fs_inflate_trees_bits(s->sub.trees.blens, &s->sub.trees.bb,
+ &s->sub.trees.tb, s->hufts, z);
+ if (t != Z_OK)
+ {
+ r = t;
+ if (r == Z_DATA_ERROR)
+ s->mode = B_BAD;
+ LEAVE
+ }
+ s->sub.trees.index = 0;
+ s->mode = DTREE;
+ case DTREE:
+ while (t = s->sub.trees.table,
+ s->sub.trees.index < 258 + (t & 0x1f) + ((t >> 5) & 0x1f))
+ {
+ inflate_huft *h;
+ uInt i, j, c;
+
+ t = s->sub.trees.bb;
+ NEEDBITS(t)
+ h = s->sub.trees.tb + ((uInt)b & zlib_fs_inflate_mask[t]);
+ t = h->bits;
+ c = h->base;
+ if (c < 16)
+ {
+ DUMPBITS(t)
+ s->sub.trees.blens[s->sub.trees.index++] = c;
+ }
+ else /* c == 16..18 */
+ {
+ i = c == 18 ? 7 : c - 14;
+ j = c == 18 ? 11 : 3;
+ NEEDBITS(t + i)
+ DUMPBITS(t)
+ j += (uInt)b & zlib_fs_inflate_mask[i];
+ DUMPBITS(i)
+ i = s->sub.trees.index;
+ t = s->sub.trees.table;
+ if (i + j > 258 + (t & 0x1f) + ((t >> 5) & 0x1f) ||
+ (c == 16 && i < 1))
+ {
+ s->mode = B_BAD;
+ z->msg = (char*)"invalid bit length repeat";
+ r = Z_DATA_ERROR;
+ LEAVE
+ }
+ c = c == 16 ? s->sub.trees.blens[i - 1] : 0;
+ do {
+ s->sub.trees.blens[i++] = c;
+ } while (--j);
+ s->sub.trees.index = i;
+ }
+ }
+ s->sub.trees.tb = Z_NULL;
+ {
+ uInt bl, bd;
+ inflate_huft *tl, *td;
+ inflate_codes_statef *c;
+
+ bl = 9; /* must be <= 9 for lookahead assumptions */
+ bd = 6; /* must be <= 9 for lookahead assumptions */
+ t = s->sub.trees.table;
+ t = zlib_fs_inflate_trees_dynamic(257 + (t & 0x1f), 1 + ((t >> 5) & 0x1f),
+ s->sub.trees.blens, &bl, &bd, &tl, &td,
+ s->hufts, z);
+ if (t != Z_OK)
+ {
+ if (t == (uInt)Z_DATA_ERROR)
+ s->mode = B_BAD;
+ r = t;
+ LEAVE
+ }
+ if ((c = zlib_fs_inflate_codes_new(bl, bd, tl, td, z)) == Z_NULL)
+ {
+ r = Z_MEM_ERROR;
+ LEAVE
+ }
+ s->sub.decode.codes = c;
+ }
+ s->mode = CODES;
+ case CODES:
+ UPDATE
+ if ((r = zlib_fs_inflate_codes(s, z, r)) != Z_STREAM_END)
+ return zlib_fs_inflate_flush(s, z, r);
+ r = Z_OK;
+ zlib_fs_inflate_codes_free(s->sub.decode.codes, z);
+ LOAD
+ if (!s->last)
+ {
+ s->mode = TYPE;
+ break;
+ }
+ s->mode = DRY;
+ case DRY:
+ FLUSH
+ if (s->read != s->write)
+ LEAVE
+ s->mode = B_DONE;
+ case B_DONE:
+ r = Z_STREAM_END;
+ LEAVE
+ case B_BAD:
+ r = Z_DATA_ERROR;
+ LEAVE
+ default:
+ r = Z_STREAM_ERROR;
+ LEAVE
+ }
+}
+
+
+int zlib_fs_inflate_blocks_free(s, z)
+inflate_blocks_statef *s;
+z_streamp z;
+{
+ zlib_fs_inflate_blocks_reset(s, z, Z_NULL);
+ return Z_OK;
+}
+
+
+void zlib_fs_inflate_set_dictionary(s, d, n)
+inflate_blocks_statef *s;
+const Bytef *d;
+uInt n;
+{
+ memcpy(s->window, d, n);
+ s->read = s->write = s->window + n;
+}
+
+
+/* Returns true if inflate is currently at the end of a block generated
+ * by Z_SYNC_FLUSH or Z_FULL_FLUSH.
+ * IN assertion: s != Z_NULL
+ */
+int zlib_fs_inflate_blocks_sync_point(s)
+inflate_blocks_statef *s;
+{
+ return s->mode == LENS;
+}
--- /dev/null
+/* infblock.h -- header to use infblock.c
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+#ifndef _INFBLOCK_H
+#define _INFBLOCK_H
+
+struct inflate_blocks_state;
+typedef struct inflate_blocks_state FAR inflate_blocks_statef;
+
+extern inflate_blocks_statef * zlib_fs_inflate_blocks_new OF((
+ z_streamp z,
+ check_func c, /* check function */
+ uInt w)); /* window size */
+
+extern int zlib_fs_inflate_blocks OF((
+ inflate_blocks_statef *,
+ z_streamp ,
+ int)); /* initial return code */
+
+extern void zlib_fs_inflate_blocks_reset OF((
+ inflate_blocks_statef *,
+ z_streamp ,
+ uLongf *)); /* check value on output */
+
+extern int zlib_fs_inflate_blocks_free OF((
+ inflate_blocks_statef *,
+ z_streamp));
+
+extern void zlib_fs_inflate_set_dictionary OF((
+ inflate_blocks_statef *s,
+ const Bytef *d, /* dictionary */
+ uInt n)); /* dictionary length */
+
+extern int zlib_fs_inflate_blocks_sync_point OF((
+ inflate_blocks_statef *s));
+
+#endif /* _INFBLOCK_H */
--- /dev/null
+/* infcodes.c -- process literals and length/distance pairs
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include "zutil.h"
+#include "inftrees.h"
+#include "infblock.h"
+#include "infcodes.h"
+#include "infutil.h"
+#include "inffast.h"
+
+/* simplify the use of the inflate_huft type with some defines */
+#define exop word.what.Exop
+#define bits word.what.Bits
+
+inflate_codes_statef *zlib_fs_inflate_codes_new(bl, bd, tl, td, z)
+uInt bl, bd;
+inflate_huft *tl;
+inflate_huft *td; /* need separate declaration for Borland C++ */
+z_streamp z;
+{
+ inflate_codes_statef *c;
+
+ c = &WS(z)->working_state;
+ {
+ c->mode = START;
+ c->lbits = (Byte)bl;
+ c->dbits = (Byte)bd;
+ c->ltree = tl;
+ c->dtree = td;
+ }
+ return c;
+}
+
+
+int zlib_fs_inflate_codes(s, z, r)
+inflate_blocks_statef *s;
+z_streamp z;
+int r;
+{
+ uInt j; /* temporary storage */
+ inflate_huft *t; /* temporary pointer */
+ uInt e; /* extra bits or operation */
+ uLong b; /* bit buffer */
+ uInt k; /* bits in bit buffer */
+ Bytef *p; /* input data pointer */
+ uInt n; /* bytes available there */
+ Bytef *q; /* output window write pointer */
+ uInt m; /* bytes to end of window or read pointer */
+ Bytef *f; /* pointer to copy strings from */
+ inflate_codes_statef *c = s->sub.decode.codes; /* codes state */
+
+ /* copy input/output information to locals (UPDATE macro restores) */
+ LOAD
+
+ /* process input and output based on current state */
+ while (1) switch (c->mode)
+ { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */
+ case START: /* x: set up for LEN */
+#ifndef SLOW
+ if (m >= 258 && n >= 10)
+ {
+ UPDATE
+ r = zlib_fs_inflate_fast(c->lbits, c->dbits, c->ltree, c->dtree, s, z);
+ LOAD
+ if (r != Z_OK)
+ {
+ c->mode = r == Z_STREAM_END ? WASH : BADCODE;
+ break;
+ }
+ }
+#endif /* !SLOW */
+ c->sub.code.need = c->lbits;
+ c->sub.code.tree = c->ltree;
+ c->mode = LEN;
+ case LEN: /* i: get length/literal/eob next */
+ j = c->sub.code.need;
+ NEEDBITS(j)
+ t = c->sub.code.tree + ((uInt)b & zlib_fs_inflate_mask[j]);
+ DUMPBITS(t->bits)
+ e = (uInt)(t->exop);
+ if (e == 0) /* literal */
+ {
+ c->sub.lit = t->base;
+ c->mode = LIT;
+ break;
+ }
+ if (e & 16) /* length */
+ {
+ c->sub.copy.get = e & 15;
+ c->len = t->base;
+ c->mode = LENEXT;
+ break;
+ }
+ if ((e & 64) == 0) /* next table */
+ {
+ c->sub.code.need = e;
+ c->sub.code.tree = t + t->base;
+ break;
+ }
+ if (e & 32) /* end of block */
+ {
+ c->mode = WASH;
+ break;
+ }
+ c->mode = BADCODE; /* invalid code */
+ z->msg = (char*)"invalid literal/length code";
+ r = Z_DATA_ERROR;
+ LEAVE
+ case LENEXT: /* i: getting length extra (have base) */
+ j = c->sub.copy.get;
+ NEEDBITS(j)
+ c->len += (uInt)b & zlib_fs_inflate_mask[j];
+ DUMPBITS(j)
+ c->sub.code.need = c->dbits;
+ c->sub.code.tree = c->dtree;
+ c->mode = DIST;
+ case DIST: /* i: get distance next */
+ j = c->sub.code.need;
+ NEEDBITS(j)
+ t = c->sub.code.tree + ((uInt)b & zlib_fs_inflate_mask[j]);
+ DUMPBITS(t->bits)
+ e = (uInt)(t->exop);
+ if (e & 16) /* distance */
+ {
+ c->sub.copy.get = e & 15;
+ c->sub.copy.dist = t->base;
+ c->mode = DISTEXT;
+ break;
+ }
+ if ((e & 64) == 0) /* next table */
+ {
+ c->sub.code.need = e;
+ c->sub.code.tree = t + t->base;
+ break;
+ }
+ c->mode = BADCODE; /* invalid code */
+ z->msg = (char*)"invalid distance code";
+ r = Z_DATA_ERROR;
+ LEAVE
+ case DISTEXT: /* i: getting distance extra */
+ j = c->sub.copy.get;
+ NEEDBITS(j)
+ c->sub.copy.dist += (uInt)b & zlib_fs_inflate_mask[j];
+ DUMPBITS(j)
+ c->mode = COPY;
+ case COPY: /* o: copying bytes in window, waiting for space */
+#ifndef __TURBOC__ /* Turbo C bug for following expression */
+ f = (uInt)(q - s->window) < c->sub.copy.dist ?
+ s->end - (c->sub.copy.dist - (q - s->window)) :
+ q - c->sub.copy.dist;
+#else
+ f = q - c->sub.copy.dist;
+ if ((uInt)(q - s->window) < c->sub.copy.dist)
+ f = s->end - (c->sub.copy.dist - (uInt)(q - s->window));
+#endif
+ while (c->len)
+ {
+ NEEDOUT
+ OUTBYTE(*f++)
+ if (f == s->end)
+ f = s->window;
+ c->len--;
+ }
+ c->mode = START;
+ break;
+ case LIT: /* o: got literal, waiting for output space */
+ NEEDOUT
+ OUTBYTE(c->sub.lit)
+ c->mode = START;
+ break;
+ case WASH: /* o: got eob, possibly more output */
+ if (k > 7) /* return unused byte, if any */
+ {
+ k -= 8;
+ n++;
+ p--; /* can always return one */
+ }
+ FLUSH
+ if (s->read != s->write)
+ LEAVE
+ c->mode = END;
+ case END:
+ r = Z_STREAM_END;
+ LEAVE
+ case BADCODE: /* x: got error */
+ r = Z_DATA_ERROR;
+ LEAVE
+ default:
+ r = Z_STREAM_ERROR;
+ LEAVE
+ }
+#ifdef NEED_DUMMY_RETURN
+ return Z_STREAM_ERROR; /* Some dumb compilers complain without this */
+#endif
+}
+
+
+void zlib_fs_inflate_codes_free(c, z)
+inflate_codes_statef *c;
+z_streamp z;
+{
+}
--- /dev/null
+/* infcodes.h -- header to use infcodes.c
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+#ifndef _INFCODES_H
+#define _INFCODES_H
+
+#include "infblock.h"
+
+struct inflate_codes_state;
+typedef struct inflate_codes_state FAR inflate_codes_statef;
+
+extern inflate_codes_statef *zlib_fs_inflate_codes_new OF((
+ uInt, uInt,
+ inflate_huft *, inflate_huft *,
+ z_streamp ));
+
+extern int zlib_fs_inflate_codes OF((
+ inflate_blocks_statef *,
+ z_streamp ,
+ int));
+
+extern void zlib_fs_inflate_codes_free OF((
+ inflate_codes_statef *,
+ z_streamp ));
+
+#endif /* _INFCODES_H */
--- /dev/null
+/* inffast.c -- process literals and length/distance pairs fast
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include "zutil.h"
+#include "inftrees.h"
+#include "infblock.h"
+#include "infcodes.h"
+#include "infutil.h"
+#include "inffast.h"
+
+struct inflate_codes_state;
+
+/* simplify the use of the inflate_huft type with some defines */
+#define exop word.what.Exop
+#define bits word.what.Bits
+
+/* macros for bit input with no checking and for returning unused bytes */
+#define GRABBITS(j) {while(k<(j)){b|=((uLong)NEXTBYTE)<<k;k+=8;}}
+#define UNGRAB {c=z->avail_in-n;c=(k>>3)<c?k>>3:c;n+=c;p-=c;k-=c<<3;}
+
+/* Called with number of bytes left to write in window at least 258
+ (the maximum string length) and number of input bytes available
+ at least ten. The ten bytes are six bytes for the longest length/
+ distance pair plus four bytes for overloading the bit buffer. */
+
+int zlib_fs_inflate_fast(bl, bd, tl, td, s, z)
+uInt bl, bd;
+inflate_huft *tl;
+inflate_huft *td; /* need separate declaration for Borland C++ */
+inflate_blocks_statef *s;
+z_streamp z;
+{
+ inflate_huft *t; /* temporary pointer */
+ uInt e; /* extra bits or operation */
+ uLong b; /* bit buffer */
+ uInt k; /* bits in bit buffer */
+ Bytef *p; /* input data pointer */
+ uInt n; /* bytes available there */
+ Bytef *q; /* output window write pointer */
+ uInt m; /* bytes to end of window or read pointer */
+ uInt ml; /* mask for literal/length tree */
+ uInt md; /* mask for distance tree */
+ uInt c; /* bytes to copy */
+ uInt d; /* distance back to copy from */
+ Bytef *r; /* copy source pointer */
+
+ /* load input, output, bit values */
+ LOAD
+
+ /* initialize masks */
+ ml = zlib_fs_inflate_mask[bl];
+ md = zlib_fs_inflate_mask[bd];
+
+ /* do until not enough input or output space for fast loop */
+ do { /* assume called with m >= 258 && n >= 10 */
+ /* get literal/length code */
+ GRABBITS(20) /* max bits for literal/length code */
+ if ((e = (t = tl + ((uInt)b & ml))->exop) == 0)
+ {
+ DUMPBITS(t->bits)
+ *q++ = (Byte)t->base;
+ m--;
+ continue;
+ }
+ do {
+ DUMPBITS(t->bits)
+ if (e & 16)
+ {
+ /* get extra bits for length */
+ e &= 15;
+ c = t->base + ((uInt)b & zlib_fs_inflate_mask[e]);
+ DUMPBITS(e)
+
+ /* decode distance base of block to copy */
+ GRABBITS(15); /* max bits for distance code */
+ e = (t = td + ((uInt)b & md))->exop;
+ do {
+ DUMPBITS(t->bits)
+ if (e & 16)
+ {
+ /* get extra bits to add to distance base */
+ e &= 15;
+ GRABBITS(e) /* get extra bits (up to 13) */
+ d = t->base + ((uInt)b & zlib_fs_inflate_mask[e]);
+ DUMPBITS(e)
+
+ /* do the copy */
+ m -= c;
+ if ((uInt)(q - s->window) >= d) /* offset before dest */
+ { /* just copy */
+ r = q - d;
+ *q++ = *r++; c--; /* minimum count is three, */
+ *q++ = *r++; c--; /* so unroll loop a little */
+ }
+ else /* else offset after destination */
+ {
+ e = d - (uInt)(q - s->window); /* bytes from offset to end */
+ r = s->end - e; /* pointer to offset */
+ if (c > e) /* if source crosses, */
+ {
+ c -= e; /* copy to end of window */
+ do {
+ *q++ = *r++;
+ } while (--e);
+ r = s->window; /* copy rest from start of window */
+ }
+ }
+ do { /* copy all or what's left */
+ *q++ = *r++;
+ } while (--c);
+ break;
+ }
+ else if ((e & 64) == 0)
+ {
+ t += t->base;
+ e = (t += ((uInt)b & zlib_fs_inflate_mask[e]))->exop;
+ }
+ else
+ {
+ z->msg = (char*)"invalid distance code";
+ UNGRAB
+ UPDATE
+ return Z_DATA_ERROR;
+ }
+ } while (1);
+ break;
+ }
+ if ((e & 64) == 0)
+ {
+ t += t->base;
+ if ((e = (t += ((uInt)b & zlib_fs_inflate_mask[e]))->exop) == 0)
+ {
+ DUMPBITS(t->bits)
+ *q++ = (Byte)t->base;
+ m--;
+ break;
+ }
+ }
+ else if (e & 32)
+ {
+ UNGRAB
+ UPDATE
+ return Z_STREAM_END;
+ }
+ else
+ {
+ z->msg = (char*)"invalid literal/length code";
+ UNGRAB
+ UPDATE
+ return Z_DATA_ERROR;
+ }
+ } while (1);
+ } while (m >= 258 && n >= 10);
+
+ /* not enough input or output--restore pointers and return */
+ UNGRAB
+ UPDATE
+ return Z_OK;
+}
--- /dev/null
+/* inffast.h -- header to use inffast.c
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+extern int zlib_fs_inflate_fast OF((
+ uInt,
+ uInt,
+ inflate_huft *,
+ inflate_huft *,
+ inflate_blocks_statef *,
+ z_streamp ));
--- /dev/null
+/* inffixed.h -- table for decoding fixed codes
+ * Generated automatically by the maketree.c program
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+local uInt fixed_bl = 9;
+local uInt fixed_bd = 5;
+local inflate_huft fixed_tl[] = {
+ {{{96,7}},256}, {{{0,8}},80}, {{{0,8}},16}, {{{84,8}},115},
+ {{{82,7}},31}, {{{0,8}},112}, {{{0,8}},48}, {{{0,9}},192},
+ {{{80,7}},10}, {{{0,8}},96}, {{{0,8}},32}, {{{0,9}},160},
+ {{{0,8}},0}, {{{0,8}},128}, {{{0,8}},64}, {{{0,9}},224},
+ {{{80,7}},6}, {{{0,8}},88}, {{{0,8}},24}, {{{0,9}},144},
+ {{{83,7}},59}, {{{0,8}},120}, {{{0,8}},56}, {{{0,9}},208},
+ {{{81,7}},17}, {{{0,8}},104}, {{{0,8}},40}, {{{0,9}},176},
+ {{{0,8}},8}, {{{0,8}},136}, {{{0,8}},72}, {{{0,9}},240},
+ {{{80,7}},4}, {{{0,8}},84}, {{{0,8}},20}, {{{85,8}},227},
+ {{{83,7}},43}, {{{0,8}},116}, {{{0,8}},52}, {{{0,9}},200},
+ {{{81,7}},13}, {{{0,8}},100}, {{{0,8}},36}, {{{0,9}},168},
+ {{{0,8}},4}, {{{0,8}},132}, {{{0,8}},68}, {{{0,9}},232},
+ {{{80,7}},8}, {{{0,8}},92}, {{{0,8}},28}, {{{0,9}},152},
+ {{{84,7}},83}, {{{0,8}},124}, {{{0,8}},60}, {{{0,9}},216},
+ {{{82,7}},23}, {{{0,8}},108}, {{{0,8}},44}, {{{0,9}},184},
+ {{{0,8}},12}, {{{0,8}},140}, {{{0,8}},76}, {{{0,9}},248},
+ {{{80,7}},3}, {{{0,8}},82}, {{{0,8}},18}, {{{85,8}},163},
+ {{{83,7}},35}, {{{0,8}},114}, {{{0,8}},50}, {{{0,9}},196},
+ {{{81,7}},11}, {{{0,8}},98}, {{{0,8}},34}, {{{0,9}},164},
+ {{{0,8}},2}, {{{0,8}},130}, {{{0,8}},66}, {{{0,9}},228},
+ {{{80,7}},7}, {{{0,8}},90}, {{{0,8}},26}, {{{0,9}},148},
+ {{{84,7}},67}, {{{0,8}},122}, {{{0,8}},58}, {{{0,9}},212},
+ {{{82,7}},19}, {{{0,8}},106}, {{{0,8}},42}, {{{0,9}},180},
+ {{{0,8}},10}, {{{0,8}},138}, {{{0,8}},74}, {{{0,9}},244},
+ {{{80,7}},5}, {{{0,8}},86}, {{{0,8}},22}, {{{192,8}},0},
+ {{{83,7}},51}, {{{0,8}},118}, {{{0,8}},54}, {{{0,9}},204},
+ {{{81,7}},15}, {{{0,8}},102}, {{{0,8}},38}, {{{0,9}},172},
+ {{{0,8}},6}, {{{0,8}},134}, {{{0,8}},70}, {{{0,9}},236},
+ {{{80,7}},9}, {{{0,8}},94}, {{{0,8}},30}, {{{0,9}},156},
+ {{{84,7}},99}, {{{0,8}},126}, {{{0,8}},62}, {{{0,9}},220},
+ {{{82,7}},27}, {{{0,8}},110}, {{{0,8}},46}, {{{0,9}},188},
+ {{{0,8}},14}, {{{0,8}},142}, {{{0,8}},78}, {{{0,9}},252},
+ {{{96,7}},256}, {{{0,8}},81}, {{{0,8}},17}, {{{85,8}},131},
+ {{{82,7}},31}, {{{0,8}},113}, {{{0,8}},49}, {{{0,9}},194},
+ {{{80,7}},10}, {{{0,8}},97}, {{{0,8}},33}, {{{0,9}},162},
+ {{{0,8}},1}, {{{0,8}},129}, {{{0,8}},65}, {{{0,9}},226},
+ {{{80,7}},6}, {{{0,8}},89}, {{{0,8}},25}, {{{0,9}},146},
+ {{{83,7}},59}, {{{0,8}},121}, {{{0,8}},57}, {{{0,9}},210},
+ {{{81,7}},17}, {{{0,8}},105}, {{{0,8}},41}, {{{0,9}},178},
+ {{{0,8}},9}, {{{0,8}},137}, {{{0,8}},73}, {{{0,9}},242},
+ {{{80,7}},4}, {{{0,8}},85}, {{{0,8}},21}, {{{80,8}},258},
+ {{{83,7}},43}, {{{0,8}},117}, {{{0,8}},53}, {{{0,9}},202},
+ {{{81,7}},13}, {{{0,8}},101}, {{{0,8}},37}, {{{0,9}},170},
+ {{{0,8}},5}, {{{0,8}},133}, {{{0,8}},69}, {{{0,9}},234},
+ {{{80,7}},8}, {{{0,8}},93}, {{{0,8}},29}, {{{0,9}},154},
+ {{{84,7}},83}, {{{0,8}},125}, {{{0,8}},61}, {{{0,9}},218},
+ {{{82,7}},23}, {{{0,8}},109}, {{{0,8}},45}, {{{0,9}},186},
+ {{{0,8}},13}, {{{0,8}},141}, {{{0,8}},77}, {{{0,9}},250},
+ {{{80,7}},3}, {{{0,8}},83}, {{{0,8}},19}, {{{85,8}},195},
+ {{{83,7}},35}, {{{0,8}},115}, {{{0,8}},51}, {{{0,9}},198},
+ {{{81,7}},11}, {{{0,8}},99}, {{{0,8}},35}, {{{0,9}},166},
+ {{{0,8}},3}, {{{0,8}},131}, {{{0,8}},67}, {{{0,9}},230},
+ {{{80,7}},7}, {{{0,8}},91}, {{{0,8}},27}, {{{0,9}},150},
+ {{{84,7}},67}, {{{0,8}},123}, {{{0,8}},59}, {{{0,9}},214},
+ {{{82,7}},19}, {{{0,8}},107}, {{{0,8}},43}, {{{0,9}},182},
+ {{{0,8}},11}, {{{0,8}},139}, {{{0,8}},75}, {{{0,9}},246},
+ {{{80,7}},5}, {{{0,8}},87}, {{{0,8}},23}, {{{192,8}},0},
+ {{{83,7}},51}, {{{0,8}},119}, {{{0,8}},55}, {{{0,9}},206},
+ {{{81,7}},15}, {{{0,8}},103}, {{{0,8}},39}, {{{0,9}},174},
+ {{{0,8}},7}, {{{0,8}},135}, {{{0,8}},71}, {{{0,9}},238},
+ {{{80,7}},9}, {{{0,8}},95}, {{{0,8}},31}, {{{0,9}},158},
+ {{{84,7}},99}, {{{0,8}},127}, {{{0,8}},63}, {{{0,9}},222},
+ {{{82,7}},27}, {{{0,8}},111}, {{{0,8}},47}, {{{0,9}},190},
+ {{{0,8}},15}, {{{0,8}},143}, {{{0,8}},79}, {{{0,9}},254},
+ {{{96,7}},256}, {{{0,8}},80}, {{{0,8}},16}, {{{84,8}},115},
+ {{{82,7}},31}, {{{0,8}},112}, {{{0,8}},48}, {{{0,9}},193},
+ {{{80,7}},10}, {{{0,8}},96}, {{{0,8}},32}, {{{0,9}},161},
+ {{{0,8}},0}, {{{0,8}},128}, {{{0,8}},64}, {{{0,9}},225},
+ {{{80,7}},6}, {{{0,8}},88}, {{{0,8}},24}, {{{0,9}},145},
+ {{{83,7}},59}, {{{0,8}},120}, {{{0,8}},56}, {{{0,9}},209},
+ {{{81,7}},17}, {{{0,8}},104}, {{{0,8}},40}, {{{0,9}},177},
+ {{{0,8}},8}, {{{0,8}},136}, {{{0,8}},72}, {{{0,9}},241},
+ {{{80,7}},4}, {{{0,8}},84}, {{{0,8}},20}, {{{85,8}},227},
+ {{{83,7}},43}, {{{0,8}},116}, {{{0,8}},52}, {{{0,9}},201},
+ {{{81,7}},13}, {{{0,8}},100}, {{{0,8}},36}, {{{0,9}},169},
+ {{{0,8}},4}, {{{0,8}},132}, {{{0,8}},68}, {{{0,9}},233},
+ {{{80,7}},8}, {{{0,8}},92}, {{{0,8}},28}, {{{0,9}},153},
+ {{{84,7}},83}, {{{0,8}},124}, {{{0,8}},60}, {{{0,9}},217},
+ {{{82,7}},23}, {{{0,8}},108}, {{{0,8}},44}, {{{0,9}},185},
+ {{{0,8}},12}, {{{0,8}},140}, {{{0,8}},76}, {{{0,9}},249},
+ {{{80,7}},3}, {{{0,8}},82}, {{{0,8}},18}, {{{85,8}},163},
+ {{{83,7}},35}, {{{0,8}},114}, {{{0,8}},50}, {{{0,9}},197},
+ {{{81,7}},11}, {{{0,8}},98}, {{{0,8}},34}, {{{0,9}},165},
+ {{{0,8}},2}, {{{0,8}},130}, {{{0,8}},66}, {{{0,9}},229},
+ {{{80,7}},7}, {{{0,8}},90}, {{{0,8}},26}, {{{0,9}},149},
+ {{{84,7}},67}, {{{0,8}},122}, {{{0,8}},58}, {{{0,9}},213},
+ {{{82,7}},19}, {{{0,8}},106}, {{{0,8}},42}, {{{0,9}},181},
+ {{{0,8}},10}, {{{0,8}},138}, {{{0,8}},74}, {{{0,9}},245},
+ {{{80,7}},5}, {{{0,8}},86}, {{{0,8}},22}, {{{192,8}},0},
+ {{{83,7}},51}, {{{0,8}},118}, {{{0,8}},54}, {{{0,9}},205},
+ {{{81,7}},15}, {{{0,8}},102}, {{{0,8}},38}, {{{0,9}},173},
+ {{{0,8}},6}, {{{0,8}},134}, {{{0,8}},70}, {{{0,9}},237},
+ {{{80,7}},9}, {{{0,8}},94}, {{{0,8}},30}, {{{0,9}},157},
+ {{{84,7}},99}, {{{0,8}},126}, {{{0,8}},62}, {{{0,9}},221},
+ {{{82,7}},27}, {{{0,8}},110}, {{{0,8}},46}, {{{0,9}},189},
+ {{{0,8}},14}, {{{0,8}},142}, {{{0,8}},78}, {{{0,9}},253},
+ {{{96,7}},256}, {{{0,8}},81}, {{{0,8}},17}, {{{85,8}},131},
+ {{{82,7}},31}, {{{0,8}},113}, {{{0,8}},49}, {{{0,9}},195},
+ {{{80,7}},10}, {{{0,8}},97}, {{{0,8}},33}, {{{0,9}},163},
+ {{{0,8}},1}, {{{0,8}},129}, {{{0,8}},65}, {{{0,9}},227},
+ {{{80,7}},6}, {{{0,8}},89}, {{{0,8}},25}, {{{0,9}},147},
+ {{{83,7}},59}, {{{0,8}},121}, {{{0,8}},57}, {{{0,9}},211},
+ {{{81,7}},17}, {{{0,8}},105}, {{{0,8}},41}, {{{0,9}},179},
+ {{{0,8}},9}, {{{0,8}},137}, {{{0,8}},73}, {{{0,9}},243},
+ {{{80,7}},4}, {{{0,8}},85}, {{{0,8}},21}, {{{80,8}},258},
+ {{{83,7}},43}, {{{0,8}},117}, {{{0,8}},53}, {{{0,9}},203},
+ {{{81,7}},13}, {{{0,8}},101}, {{{0,8}},37}, {{{0,9}},171},
+ {{{0,8}},5}, {{{0,8}},133}, {{{0,8}},69}, {{{0,9}},235},
+ {{{80,7}},8}, {{{0,8}},93}, {{{0,8}},29}, {{{0,9}},155},
+ {{{84,7}},83}, {{{0,8}},125}, {{{0,8}},61}, {{{0,9}},219},
+ {{{82,7}},23}, {{{0,8}},109}, {{{0,8}},45}, {{{0,9}},187},
+ {{{0,8}},13}, {{{0,8}},141}, {{{0,8}},77}, {{{0,9}},251},
+ {{{80,7}},3}, {{{0,8}},83}, {{{0,8}},19}, {{{85,8}},195},
+ {{{83,7}},35}, {{{0,8}},115}, {{{0,8}},51}, {{{0,9}},199},
+ {{{81,7}},11}, {{{0,8}},99}, {{{0,8}},35}, {{{0,9}},167},
+ {{{0,8}},3}, {{{0,8}},131}, {{{0,8}},67}, {{{0,9}},231},
+ {{{80,7}},7}, {{{0,8}},91}, {{{0,8}},27}, {{{0,9}},151},
+ {{{84,7}},67}, {{{0,8}},123}, {{{0,8}},59}, {{{0,9}},215},
+ {{{82,7}},19}, {{{0,8}},107}, {{{0,8}},43}, {{{0,9}},183},
+ {{{0,8}},11}, {{{0,8}},139}, {{{0,8}},75}, {{{0,9}},247},
+ {{{80,7}},5}, {{{0,8}},87}, {{{0,8}},23}, {{{192,8}},0},
+ {{{83,7}},51}, {{{0,8}},119}, {{{0,8}},55}, {{{0,9}},207},
+ {{{81,7}},15}, {{{0,8}},103}, {{{0,8}},39}, {{{0,9}},175},
+ {{{0,8}},7}, {{{0,8}},135}, {{{0,8}},71}, {{{0,9}},239},
+ {{{80,7}},9}, {{{0,8}},95}, {{{0,8}},31}, {{{0,9}},159},
+ {{{84,7}},99}, {{{0,8}},127}, {{{0,8}},63}, {{{0,9}},223},
+ {{{82,7}},27}, {{{0,8}},111}, {{{0,8}},47}, {{{0,9}},191},
+ {{{0,8}},15}, {{{0,8}},143}, {{{0,8}},79}, {{{0,9}},255}
+ };
+local inflate_huft fixed_td[] = {
+ {{{80,5}},1}, {{{87,5}},257}, {{{83,5}},17}, {{{91,5}},4097},
+ {{{81,5}},5}, {{{89,5}},1025}, {{{85,5}},65}, {{{93,5}},16385},
+ {{{80,5}},3}, {{{88,5}},513}, {{{84,5}},33}, {{{92,5}},8193},
+ {{{82,5}},9}, {{{90,5}},2049}, {{{86,5}},129}, {{{192,5}},24577},
+ {{{80,5}},2}, {{{87,5}},385}, {{{83,5}},25}, {{{91,5}},6145},
+ {{{81,5}},7}, {{{89,5}},1537}, {{{85,5}},97}, {{{93,5}},24577},
+ {{{80,5}},4}, {{{88,5}},769}, {{{84,5}},49}, {{{92,5}},12289},
+ {{{82,5}},13}, {{{90,5}},3073}, {{{86,5}},193}, {{{192,5}},24577}
+ };
--- /dev/null
+/* inflate.c -- zlib interface to inflate modules
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include <linux/module.h>
+#include "zutil.h"
+#include "infblock.h"
+#include "infutil.h"
+
+int ZEXPORT zlib_fs_inflate_workspacesize(void)
+{
+ return sizeof(struct inflate_workspace);
+}
+
+
+int ZEXPORT zlib_fs_inflateReset(z)
+z_streamp z;
+{
+ if (z == Z_NULL || z->state == Z_NULL || z->workspace == Z_NULL)
+ return Z_STREAM_ERROR;
+ z->total_in = z->total_out = 0;
+ z->msg = Z_NULL;
+ z->state->mode = z->state->nowrap ? BLOCKS : METHOD;
+ zlib_fs_inflate_blocks_reset(z->state->blocks, z, Z_NULL);
+ return Z_OK;
+}
+
+
+int ZEXPORT zlib_fs_inflateEnd(z)
+z_streamp z;
+{
+ if (z == Z_NULL || z->state == Z_NULL || z->workspace == Z_NULL)
+ return Z_STREAM_ERROR;
+ if (z->state->blocks != Z_NULL)
+ zlib_fs_inflate_blocks_free(z->state->blocks, z);
+ z->state = Z_NULL;
+ return Z_OK;
+}
+
+
+int ZEXPORT zlib_fs_inflateInit2_(z, w, version, stream_size)
+z_streamp z;
+int w;
+const char *version;
+int stream_size;
+{
+ if (version == Z_NULL || version[0] != ZLIB_VERSION[0] ||
+ stream_size != sizeof(z_stream) || z->workspace == Z_NULL)
+ return Z_VERSION_ERROR;
+
+ /* initialize state */
+ if (z == Z_NULL)
+ return Z_STREAM_ERROR;
+ z->msg = Z_NULL;
+ z->state = &WS(z)->internal_state;
+ z->state->blocks = Z_NULL;
+
+ /* handle undocumented nowrap option (no zlib header or check) */
+ z->state->nowrap = 0;
+ if (w < 0)
+ {
+ w = - w;
+ z->state->nowrap = 1;
+ }
+
+ /* set window size */
+ if (w < 8 || w > 15)
+ {
+ zlib_fs_inflateEnd(z);
+ return Z_STREAM_ERROR;
+ }
+ z->state->wbits = (uInt)w;
+
+ /* create inflate_blocks state */
+ if ((z->state->blocks =
+ zlib_fs_inflate_blocks_new(z, z->state->nowrap ? Z_NULL : zlib_fs_adler32, (uInt)1 << w))
+ == Z_NULL)
+ {
+ zlib_fs_inflateEnd(z);
+ return Z_MEM_ERROR;
+ }
+
+ /* reset state */
+ zlib_fs_inflateReset(z);
+ return Z_OK;
+}
+
+
+int ZEXPORT zlib_fs_inflateInit_(z, version, stream_size)
+z_streamp z;
+const char *version;
+int stream_size;
+{
+ return zlib_fs_inflateInit2_(z, DEF_WBITS, version, stream_size);
+}
+
+#undef NEEDBYTE
+#undef NEXTBYTE
+#define NEEDBYTE {if(z->avail_in==0)return r;r=f;}
+#define NEXTBYTE (z->avail_in--,z->total_in++,*z->next_in++)
+
+int ZEXPORT zlib_fs_inflate(z, f)
+z_streamp z;
+int f;
+{
+ int r;
+ uInt b;
+
+ if (z == Z_NULL || z->state == Z_NULL || z->next_in == Z_NULL)
+ return Z_STREAM_ERROR;
+ f = f == Z_FINISH ? Z_BUF_ERROR : Z_OK;
+ r = Z_BUF_ERROR;
+ while (1) switch (z->state->mode)
+ {
+ case METHOD:
+ NEEDBYTE
+ if (((z->state->sub.method = NEXTBYTE) & 0xf) != Z_DEFLATED)
+ {
+ z->state->mode = I_BAD;
+ z->msg = (char*)"unknown compression method";
+ z->state->sub.marker = 5; /* can't try inflateSync */
+ break;
+ }
+ if ((z->state->sub.method >> 4) + 8 > z->state->wbits)
+ {
+ z->state->mode = I_BAD;
+ z->msg = (char*)"invalid window size";
+ z->state->sub.marker = 5; /* can't try inflateSync */
+ break;
+ }
+ z->state->mode = FLAG;
+ case FLAG:
+ NEEDBYTE
+ b = NEXTBYTE;
+ if (((z->state->sub.method << 8) + b) % 31)
+ {
+ z->state->mode = I_BAD;
+ z->msg = (char*)"incorrect header check";
+ z->state->sub.marker = 5; /* can't try inflateSync */
+ break;
+ }
+ if (!(b & PRESET_DICT))
+ {
+ z->state->mode = BLOCKS;
+ break;
+ }
+ z->state->mode = DICT4;
+ case DICT4:
+ NEEDBYTE
+ z->state->sub.check.need = (uLong)NEXTBYTE << 24;
+ z->state->mode = DICT3;
+ case DICT3:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE << 16;
+ z->state->mode = DICT2;
+ case DICT2:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE << 8;
+ z->state->mode = DICT1;
+ case DICT1:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE;
+ z->adler = z->state->sub.check.need;
+ z->state->mode = DICT0;
+ return Z_NEED_DICT;
+ case DICT0:
+ z->state->mode = I_BAD;
+ z->msg = (char*)"need dictionary";
+ z->state->sub.marker = 0; /* can try inflateSync */
+ return Z_STREAM_ERROR;
+ case BLOCKS:
+ r = zlib_fs_inflate_blocks(z->state->blocks, z, r);
+ if (r == Z_DATA_ERROR)
+ {
+ z->state->mode = I_BAD;
+ z->state->sub.marker = 0; /* can try inflateSync */
+ break;
+ }
+ if (r == Z_OK)
+ r = f;
+ if (r != Z_STREAM_END)
+ return r;
+ r = f;
+ zlib_fs_inflate_blocks_reset(z->state->blocks, z, &z->state->sub.check.was);
+ if (z->state->nowrap)
+ {
+ z->state->mode = I_DONE;
+ break;
+ }
+ z->state->mode = CHECK4;
+ case CHECK4:
+ NEEDBYTE
+ z->state->sub.check.need = (uLong)NEXTBYTE << 24;
+ z->state->mode = CHECK3;
+ case CHECK3:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE << 16;
+ z->state->mode = CHECK2;
+ case CHECK2:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE << 8;
+ z->state->mode = CHECK1;
+ case CHECK1:
+ NEEDBYTE
+ z->state->sub.check.need += (uLong)NEXTBYTE;
+
+ if (z->state->sub.check.was != z->state->sub.check.need)
+ {
+ z->state->mode = I_BAD;
+ z->msg = (char*)"incorrect data check";
+ z->state->sub.marker = 5; /* can't try inflateSync */
+ break;
+ }
+ z->state->mode = I_DONE;
+ case I_DONE:
+ return Z_STREAM_END;
+ case I_BAD:
+ return Z_DATA_ERROR;
+ default:
+ return Z_STREAM_ERROR;
+ }
+#ifdef NEED_DUMMY_RETURN
+ return Z_STREAM_ERROR; /* Some dumb compilers complain without this */
+#endif
+}
+
+
+int ZEXPORT zlib_fs_inflateSync(z)
+z_streamp z;
+{
+ uInt n; /* number of bytes to look at */
+ Bytef *p; /* pointer to bytes */
+ uInt m; /* number of marker bytes found in a row */
+ uLong r, w; /* temporaries to save total_in and total_out */
+
+ /* set up */
+ if (z == Z_NULL || z->state == Z_NULL)
+ return Z_STREAM_ERROR;
+ if (z->state->mode != I_BAD)
+ {
+ z->state->mode = I_BAD;
+ z->state->sub.marker = 0;
+ }
+ if ((n = z->avail_in) == 0)
+ return Z_BUF_ERROR;
+ p = z->next_in;
+ m = z->state->sub.marker;
+
+ /* search */
+ while (n && m < 4)
+ {
+ static const Byte mark[4] = {0, 0, 0xff, 0xff};
+ if (*p == mark[m])
+ m++;
+ else if (*p)
+ m = 0;
+ else
+ m = 4 - m;
+ p++, n--;
+ }
+
+ /* restore */
+ z->total_in += p - z->next_in;
+ z->next_in = p;
+ z->avail_in = n;
+ z->state->sub.marker = m;
+
+ /* return no joy or set up to restart on a new block */
+ if (m != 4)
+ return Z_DATA_ERROR;
+ r = z->total_in; w = z->total_out;
+ zlib_fs_inflateReset(z);
+ z->total_in = r; z->total_out = w;
+ z->state->mode = BLOCKS;
+ return Z_OK;
+}
+
+
+/* Returns true if inflate is currently at the end of a block generated
+ * by Z_SYNC_FLUSH or Z_FULL_FLUSH. This function is used by one PPP
+ * implementation to provide an additional safety check. PPP uses Z_SYNC_FLUSH
+ * but removes the length bytes of the resulting empty stored block. When
+ * decompressing, PPP checks that at the end of input packet, inflate is
+ * waiting for these length bytes.
+ */
+int ZEXPORT zlib_fs_inflateSyncPoint(z)
+z_streamp z;
+{
+ if (z == Z_NULL || z->state == Z_NULL || z->state->blocks == Z_NULL)
+ return Z_STREAM_ERROR;
+ return zlib_fs_inflate_blocks_sync_point(z->state->blocks);
+}
--- /dev/null
+/*
+ * linux/fs/zlib/inflate_syms.c
+ *
+ * Exported symbols for the inflate functionality.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/zlib_fs.h>
+
+EXPORT_SYMBOL(zlib_fs_inflate_workspacesize);
+EXPORT_SYMBOL(zlib_fs_inflate);
+EXPORT_SYMBOL(zlib_fs_inflateInit_);
+EXPORT_SYMBOL(zlib_fs_inflateInit2_);
+EXPORT_SYMBOL(zlib_fs_inflateEnd);
+EXPORT_SYMBOL(zlib_fs_inflateSync);
+EXPORT_SYMBOL(zlib_fs_inflateReset);
+EXPORT_SYMBOL(zlib_fs_adler32);
+EXPORT_SYMBOL(zlib_fs_inflateSyncPoint);
--- /dev/null
+/* inftrees.c -- generate Huffman trees for efficient decoding
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include "zutil.h"
+#include "inftrees.h"
+#include "infutil.h"
+
+static const char inflate_copyright[] =
+ " inflate 1.1.3 Copyright 1995-1998 Mark Adler ";
+/*
+ If you use the zlib library in a product, an acknowledgment is welcome
+ in the documentation of your product. If for some reason you cannot
+ include such an acknowledgment, I would appreciate that you keep this
+ copyright string in the executable of your product.
+ */
+struct internal_state;
+
+/* simplify the use of the inflate_huft type with some defines */
+#define exop word.what.Exop
+#define bits word.what.Bits
+
+
+local int huft_build OF((
+ uIntf *, /* code lengths in bits */
+ uInt, /* number of codes */
+ uInt, /* number of "simple" codes */
+ const uIntf *, /* list of base values for non-simple codes */
+ const uIntf *, /* list of extra bits for non-simple codes */
+ inflate_huft * FAR*,/* result: starting table */
+ uIntf *, /* maximum lookup bits (returns actual) */
+ inflate_huft *, /* space for trees */
+ uInt *, /* hufts used in space */
+ uIntf * )); /* space for values */
+
+/* Tables for deflate from PKZIP's appnote.txt. */
+local const uInt cplens[31] = { /* Copy lengths for literal codes 257..285 */
+ 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31,
+ 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0};
+ /* see note #13 above about 258 */
+local const uInt cplext[31] = { /* Extra bits for literal codes 257..285 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2,
+ 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 112, 112}; /* 112==invalid */
+local const uInt cpdist[30] = { /* Copy offsets for distance codes 0..29 */
+ 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193,
+ 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145,
+ 8193, 12289, 16385, 24577};
+local const uInt cpdext[30] = { /* Extra bits for distance codes */
+ 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
+ 7, 7, 8, 8, 9, 9, 10, 10, 11, 11,
+ 12, 12, 13, 13};
+
+/*
+ Huffman code decoding is performed using a multi-level table lookup.
+ The fastest way to decode is to simply build a lookup table whose
+ size is determined by the longest code. However, the time it takes
+ to build this table can also be a factor if the data being decoded
+ is not very long. The most common codes are necessarily the
+ shortest codes, so those codes dominate the decoding time, and hence
+ the speed. The idea is you can have a shorter table that decodes the
+ shorter, more probable codes, and then point to subsidiary tables for
+ the longer codes. The time it costs to decode the longer codes is
+ then traded against the time it takes to make longer tables.
+
+ This results of this trade are in the variables lbits and dbits
+ below. lbits is the number of bits the first level table for literal/
+ length codes can decode in one step, and dbits is the same thing for
+ the distance codes. Subsequent tables are also less than or equal to
+ those sizes. These values may be adjusted either when all of the
+ codes are shorter than that, in which case the longest code length in
+ bits is used, or when the shortest code is *longer* than the requested
+ table size, in which case the length of the shortest code in bits is
+ used.
+
+ There are two different values for the two tables, since they code a
+ different number of possibilities each. The literal/length table
+ codes 286 possible values, or in a flat code, a little over eight
+ bits. The distance table codes 30 possible values, or a little less
+ than five bits, flat. The optimum values for speed end up being
+ about one bit more than those, so lbits is 8+1 and dbits is 5+1.
+ The optimum values may differ though from machine to machine, and
+ possibly even between compilers. Your mileage may vary.
+ */
+
+
+/* If BMAX needs to be larger than 16, then h and x[] should be uLong. */
+#define BMAX 15 /* maximum bit length of any code */
+
+local int huft_build(b, n, s, d, e, t, m, hp, hn, v)
+uIntf *b; /* code lengths in bits (all assumed <= BMAX) */
+uInt n; /* number of codes (assumed <= 288) */
+uInt s; /* number of simple-valued codes (0..s-1) */
+const uIntf *d; /* list of base values for non-simple codes */
+const uIntf *e; /* list of extra bits for non-simple codes */
+inflate_huft * FAR *t; /* result: starting table */
+uIntf *m; /* maximum lookup bits, returns actual */
+inflate_huft *hp; /* space for trees */
+uInt *hn; /* hufts used in space */
+uIntf *v; /* working area: values in order of bit length */
+/* Given a list of code lengths and a maximum table size, make a set of
+ tables to decode that set of codes. Return Z_OK on success, Z_BUF_ERROR
+ if the given code set is incomplete (the tables are still built in this
+ case), Z_DATA_ERROR if the input is invalid (an over-subscribed set of
+ lengths), or Z_MEM_ERROR if not enough memory. */
+{
+
+ uInt a; /* counter for codes of length k */
+ uInt c[BMAX+1]; /* bit length count table */
+ uInt f; /* i repeats in table every f entries */
+ int g; /* maximum code length */
+ int h; /* table level */
+ register uInt i; /* counter, current code */
+ register uInt j; /* counter */
+ register int k; /* number of bits in current code */
+ int l; /* bits per table (returned in m) */
+ uInt mask; /* (1 << w) - 1, to avoid cc -O bug on HP */
+ register uIntf *p; /* pointer into c[], b[], or v[] */
+ inflate_huft *q; /* points to current table */
+ struct inflate_huft_s r; /* table entry for structure assignment */
+ inflate_huft *u[BMAX]; /* table stack */
+ register int w; /* bits before this table == (l * h) */
+ uInt x[BMAX+1]; /* bit offsets, then code stack */
+ uIntf *xp; /* pointer into x */
+ int y; /* number of dummy codes added */
+ uInt z; /* number of entries in current table */
+
+
+ /* Generate counts for each bit length */
+ p = c;
+#define C0 *p++ = 0;
+#define C2 C0 C0 C0 C0
+#define C4 C2 C2 C2 C2
+ C4 /* clear c[]--assume BMAX+1 is 16 */
+ p = b; i = n;
+ do {
+ c[*p++]++; /* assume all entries <= BMAX */
+ } while (--i);
+ if (c[0] == n) /* null input--all zero length codes */
+ {
+ *t = (inflate_huft *)Z_NULL;
+ *m = 0;
+ return Z_OK;
+ }
+
+
+ /* Find minimum and maximum length, bound *m by those */
+ l = *m;
+ for (j = 1; j <= BMAX; j++)
+ if (c[j])
+ break;
+ k = j; /* minimum code length */
+ if ((uInt)l < j)
+ l = j;
+ for (i = BMAX; i; i--)
+ if (c[i])
+ break;
+ g = i; /* maximum code length */
+ if ((uInt)l > i)
+ l = i;
+ *m = l;
+
+
+ /* Adjust last length count to fill out codes, if needed */
+ for (y = 1 << j; j < i; j++, y <<= 1)
+ if ((y -= c[j]) < 0)
+ return Z_DATA_ERROR;
+ if ((y -= c[i]) < 0)
+ return Z_DATA_ERROR;
+ c[i] += y;
+
+
+ /* Generate starting offsets into the value table for each length */
+ x[1] = j = 0;
+ p = c + 1; xp = x + 2;
+ while (--i) { /* note that i == g from above */
+ *xp++ = (j += *p++);
+ }
+
+
+ /* Make a table of values in order of bit lengths */
+ p = b; i = 0;
+ do {
+ if ((j = *p++) != 0)
+ v[x[j]++] = i;
+ } while (++i < n);
+ n = x[g]; /* set n to length of v */
+
+
+ /* Generate the Huffman codes and for each, make the table entries */
+ x[0] = i = 0; /* first Huffman code is zero */
+ p = v; /* grab values in bit order */
+ h = -1; /* no tables yet--level -1 */
+ w = -l; /* bits decoded == (l * h) */
+ u[0] = (inflate_huft *)Z_NULL; /* just to keep compilers happy */
+ q = (inflate_huft *)Z_NULL; /* ditto */
+ z = 0; /* ditto */
+
+ /* go through the bit lengths (k already is bits in shortest code) */
+ for (; k <= g; k++)
+ {
+ a = c[k];
+ while (a--)
+ {
+ /* here i is the Huffman code of length k bits for value *p */
+ /* make tables up to required level */
+ while (k > w + l)
+ {
+ h++;
+ w += l; /* previous table always l bits */
+
+ /* compute minimum size table less than or equal to l bits */
+ z = g - w;
+ z = z > (uInt)l ? l : z; /* table size upper limit */
+ if ((f = 1 << (j = k - w)) > a + 1) /* try a k-w bit table */
+ { /* too few codes for k-w bit table */
+ f -= a + 1; /* deduct codes from patterns left */
+ xp = c + k;
+ if (j < z)
+ while (++j < z) /* try smaller tables up to z bits */
+ {
+ if ((f <<= 1) <= *++xp)
+ break; /* enough codes to use up j bits */
+ f -= *xp; /* else deduct codes from patterns */
+ }
+ }
+ z = 1 << j; /* table entries for j-bit table */
+
+ /* allocate new table */
+ if (*hn + z > MANY) /* (note: doesn't matter for fixed) */
+ return Z_MEM_ERROR; /* not enough memory */
+ u[h] = q = hp + *hn;
+ *hn += z;
+
+ /* connect to last table, if there is one */
+ if (h)
+ {
+ x[h] = i; /* save pattern for backing up */
+ r.bits = (Byte)l; /* bits to dump before this table */
+ r.exop = (Byte)j; /* bits in this table */
+ j = i >> (w - l);
+ r.base = (uInt)(q - u[h-1] - j); /* offset to this table */
+ u[h-1][j] = r; /* connect to last table */
+ }
+ else
+ *t = q; /* first table is returned result */
+ }
+
+ /* set up table entry in r */
+ r.bits = (Byte)(k - w);
+ if (p >= v + n)
+ r.exop = 128 + 64; /* out of values--invalid code */
+ else if (*p < s)
+ {
+ r.exop = (Byte)(*p < 256 ? 0 : 32 + 64); /* 256 is end-of-block */
+ r.base = *p++; /* simple code is just the value */
+ }
+ else
+ {
+ r.exop = (Byte)(e[*p - s] + 16 + 64);/* non-simple--look up in lists */
+ r.base = d[*p++ - s];
+ }
+
+ /* fill code-like entries with r */
+ f = 1 << (k - w);
+ for (j = i >> w; j < z; j += f)
+ q[j] = r;
+
+ /* backwards increment the k-bit code i */
+ for (j = 1 << (k - 1); i & j; j >>= 1)
+ i ^= j;
+ i ^= j;
+
+ /* backup over finished tables */
+ mask = (1 << w) - 1; /* needed on HP, cc -O bug */
+ while ((i & mask) != x[h])
+ {
+ h--; /* don't need to update q */
+ w -= l;
+ mask = (1 << w) - 1;
+ }
+ }
+ }
+
+
+ /* Return Z_BUF_ERROR if we were given an incomplete table */
+ return y != 0 && g != 1 ? Z_BUF_ERROR : Z_OK;
+}
+
+
+int zlib_fs_inflate_trees_bits(c, bb, tb, hp, z)
+uIntf *c; /* 19 code lengths */
+uIntf *bb; /* bits tree desired/actual depth */
+inflate_huft * FAR *tb; /* bits tree result */
+inflate_huft *hp; /* space for trees */
+z_streamp z; /* for messages */
+{
+ int r;
+ uInt hn = 0; /* hufts used in space */
+ uIntf *v; /* work area for huft_build */
+
+ v = WS(z)->tree_work_area_1;
+ r = huft_build(c, 19, 19, (uIntf*)Z_NULL, (uIntf*)Z_NULL,
+ tb, bb, hp, &hn, v);
+ if (r == Z_DATA_ERROR)
+ z->msg = (char*)"oversubscribed dynamic bit lengths tree";
+ else if (r == Z_BUF_ERROR || *bb == 0)
+ {
+ z->msg = (char*)"incomplete dynamic bit lengths tree";
+ r = Z_DATA_ERROR;
+ }
+ return r;
+}
+
+int zlib_fs_inflate_trees_dynamic(nl, nd, c, bl, bd, tl, td, hp, z)
+uInt nl; /* number of literal/length codes */
+uInt nd; /* number of distance codes */
+uIntf *c; /* that many (total) code lengths */
+uIntf *bl; /* literal desired/actual bit depth */
+uIntf *bd; /* distance desired/actual bit depth */
+inflate_huft * FAR *tl; /* literal/length tree result */
+inflate_huft * FAR *td; /* distance tree result */
+inflate_huft *hp; /* space for trees */
+z_streamp z; /* for messages */
+{
+ int r;
+ uInt hn = 0; /* hufts used in space */
+ uIntf *v; /* work area for huft_build */
+
+ /* allocate work area */
+ v = WS(z)->tree_work_area_2;
+
+ /* build literal/length tree */
+ r = huft_build(c, nl, 257, cplens, cplext, tl, bl, hp, &hn, v);
+ if (r != Z_OK || *bl == 0)
+ {
+ if (r == Z_DATA_ERROR)
+ z->msg = (char*)"oversubscribed literal/length tree";
+ else if (r != Z_MEM_ERROR)
+ {
+ z->msg = (char*)"incomplete literal/length tree";
+ r = Z_DATA_ERROR;
+ }
+ return r;
+ }
+
+ /* build distance tree */
+ r = huft_build(c + nl, nd, 0, cpdist, cpdext, td, bd, hp, &hn, v);
+ if (r != Z_OK || (*bd == 0 && nl > 257))
+ {
+ if (r == Z_DATA_ERROR)
+ z->msg = (char*)"oversubscribed distance tree";
+ else if (r == Z_BUF_ERROR) {
+#ifdef PKZIP_BUG_WORKAROUND
+ r = Z_OK;
+ }
+#else
+ z->msg = (char*)"incomplete distance tree";
+ r = Z_DATA_ERROR;
+ }
+ else if (r != Z_MEM_ERROR)
+ {
+ z->msg = (char*)"empty distance tree with lengths";
+ r = Z_DATA_ERROR;
+ }
+ return r;
+#endif
+ }
+
+ /* done */
+ return Z_OK;
+}
+
+
+/* build fixed tables only once--keep them here */
+#include "inffixed.h"
+
+
+int zlib_fs_inflate_trees_fixed(bl, bd, tl, td, z)
+uIntf *bl; /* literal desired/actual bit depth */
+uIntf *bd; /* distance desired/actual bit depth */
+inflate_huft * FAR *tl; /* literal/length tree result */
+inflate_huft * FAR *td; /* distance tree result */
+z_streamp z; /* for memory allocation */
+{
+ *bl = fixed_bl;
+ *bd = fixed_bd;
+ *tl = fixed_tl;
+ *td = fixed_td;
+ return Z_OK;
+}
--- /dev/null
+/* inftrees.h -- header to use inftrees.c
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+/* Huffman code lookup table entry--this entry is four bytes for machines
+ that have 16-bit pointers (e.g. PC's in the small or medium model). */
+
+#ifndef _INFTREES_H
+#define _INFTREES_H
+
+typedef struct inflate_huft_s FAR inflate_huft;
+
+struct inflate_huft_s {
+ union {
+ struct {
+ Byte Exop; /* number of extra bits or operation */
+ Byte Bits; /* number of bits in this code or subcode */
+ } what;
+ uInt pad; /* pad structure to a power of 2 (4 bytes for */
+ } word; /* 16-bit, 8 bytes for 32-bit int's) */
+ uInt base; /* literal, length base, distance base,
+ or table offset */
+};
+
+/* Maximum size of dynamic tree. The maximum found in a long but non-
+ exhaustive search was 1004 huft structures (850 for length/literals
+ and 154 for distances, the latter actually the result of an
+ exhaustive search). The actual maximum is not known, but the
+ value below is more than safe. */
+#define MANY 1440
+
+extern int zlib_fs_inflate_trees_bits OF((
+ uIntf *, /* 19 code lengths */
+ uIntf *, /* bits tree desired/actual depth */
+ inflate_huft * FAR *, /* bits tree result */
+ inflate_huft *, /* space for trees */
+ z_streamp)); /* for messages */
+
+extern int zlib_fs_inflate_trees_dynamic OF((
+ uInt, /* number of literal/length codes */
+ uInt, /* number of distance codes */
+ uIntf *, /* that many (total) code lengths */
+ uIntf *, /* literal desired/actual bit depth */
+ uIntf *, /* distance desired/actual bit depth */
+ inflate_huft * FAR *, /* literal/length tree result */
+ inflate_huft * FAR *, /* distance tree result */
+ inflate_huft *, /* space for trees */
+ z_streamp)); /* for messages */
+
+extern int zlib_fs_inflate_trees_fixed OF((
+ uIntf *, /* literal desired/actual bit depth */
+ uIntf *, /* distance desired/actual bit depth */
+ inflate_huft * FAR *, /* literal/length tree result */
+ inflate_huft * FAR *, /* distance tree result */
+ z_streamp)); /* for memory allocation */
+
+#endif /* _INFTREES_H */
--- /dev/null
+/* inflate_util.c -- data and routines common to blocks and codes
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include "zutil.h"
+#include "infblock.h"
+#include "inftrees.h"
+#include "infcodes.h"
+#include "infutil.h"
+
+struct inflate_codes_state;
+
+/* And'ing with mask[n] masks the lower n bits */
+uInt zlib_fs_inflate_mask[17] = {
+ 0x0000,
+ 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff,
+ 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
+};
+
+
+/* copy as much as possible from the sliding window to the output area */
+int zlib_fs_inflate_flush(s, z, r)
+inflate_blocks_statef *s;
+z_streamp z;
+int r;
+{
+ uInt n;
+ Bytef *p;
+ Bytef *q;
+
+ /* local copies of source and destination pointers */
+ p = z->next_out;
+ q = s->read;
+
+ /* compute number of bytes to copy as far as end of window */
+ n = (uInt)((q <= s->write ? s->write : s->end) - q);
+ if (n > z->avail_out) n = z->avail_out;
+ if (n && r == Z_BUF_ERROR) r = Z_OK;
+
+ /* update counters */
+ z->avail_out -= n;
+ z->total_out += n;
+
+ /* update check information */
+ if (s->checkfn != Z_NULL)
+ z->adler = s->check = (*s->checkfn)(s->check, q, n);
+
+ /* copy as far as end of window */
+ memcpy(p, q, n);
+ p += n;
+ q += n;
+
+ /* see if more to copy at beginning of window */
+ if (q == s->end)
+ {
+ /* wrap pointers */
+ q = s->window;
+ if (s->write == s->end)
+ s->write = s->window;
+
+ /* compute bytes to copy */
+ n = (uInt)(s->write - q);
+ if (n > z->avail_out) n = z->avail_out;
+ if (n && r == Z_BUF_ERROR) r = Z_OK;
+
+ /* update counters */
+ z->avail_out -= n;
+ z->total_out += n;
+
+ /* update check information */
+ if (s->checkfn != Z_NULL)
+ z->adler = s->check = (*s->checkfn)(s->check, q, n);
+
+ /* copy */
+ memcpy(p, q, n);
+ p += n;
+ q += n;
+ }
+
+ /* update pointers */
+ z->next_out = p;
+ s->read = q;
+
+ /* done */
+ return r;
+}
--- /dev/null
+/* infutil.h -- types and macros common to blocks and codes
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+#ifndef _INFUTIL_H
+#define _INFUTIL_H
+
+#include "zconf.h"
+#include "inftrees.h"
+#include "infcodes.h"
+
+typedef enum {
+ TYPE, /* get type bits (3, including end bit) */
+ LENS, /* get lengths for stored */
+ STORED, /* processing stored block */
+ TABLE, /* get table lengths */
+ BTREE, /* get bit lengths tree for a dynamic block */
+ DTREE, /* get length, distance trees for a dynamic block */
+ CODES, /* processing fixed or dynamic block */
+ DRY, /* output remaining window bytes */
+ B_DONE, /* finished last block, done */
+ B_BAD} /* got a data error--stuck here */
+inflate_block_mode;
+
+/* inflate blocks semi-private state */
+struct inflate_blocks_state {
+
+ /* mode */
+ inflate_block_mode mode; /* current inflate_block mode */
+
+ /* mode dependent information */
+ union {
+ uInt left; /* if STORED, bytes left to copy */
+ struct {
+ uInt table; /* table lengths (14 bits) */
+ uInt index; /* index into blens (or border) */
+ uIntf *blens; /* bit lengths of codes */
+ uInt bb; /* bit length tree depth */
+ inflate_huft *tb; /* bit length decoding tree */
+ } trees; /* if DTREE, decoding info for trees */
+ struct {
+ inflate_codes_statef
+ *codes;
+ } decode; /* if CODES, current state */
+ } sub; /* submode */
+ uInt last; /* true if this block is the last block */
+
+ /* mode independent information */
+ uInt bitk; /* bits in bit buffer */
+ uLong bitb; /* bit buffer */
+ inflate_huft *hufts; /* single malloc for tree space */
+ Bytef *window; /* sliding window */
+ Bytef *end; /* one byte after sliding window */
+ Bytef *read; /* window read pointer */
+ Bytef *write; /* window write pointer */
+ check_func checkfn; /* check function */
+ uLong check; /* check on output */
+
+};
+
+
+/* defines for inflate input/output */
+/* update pointers and return */
+#define UPDBITS {s->bitb=b;s->bitk=k;}
+#define UPDIN {z->avail_in=n;z->total_in+=p-z->next_in;z->next_in=p;}
+#define UPDOUT {s->write=q;}
+#define UPDATE {UPDBITS UPDIN UPDOUT}
+#define LEAVE {UPDATE return zlib_fs_inflate_flush(s,z,r);}
+/* get bytes and bits */
+#define LOADIN {p=z->next_in;n=z->avail_in;b=s->bitb;k=s->bitk;}
+#define NEEDBYTE {if(n)r=Z_OK;else LEAVE}
+#define NEXTBYTE (n--,*p++)
+#define NEEDBITS(j) {while(k<(j)){NEEDBYTE;b|=((uLong)NEXTBYTE)<<k;k+=8;}}
+#define DUMPBITS(j) {b>>=(j);k-=(j);}
+/* output bytes */
+#define WAVAIL (uInt)(q<s->read?s->read-q-1:s->end-q)
+#define LOADOUT {q=s->write;m=(uInt)WAVAIL;}
+#define WRAP {if(q==s->end&&s->read!=s->window){q=s->window;m=(uInt)WAVAIL;}}
+#define FLUSH {UPDOUT r=zlib_fs_inflate_flush(s,z,r); LOADOUT}
+#define NEEDOUT {if(m==0){WRAP if(m==0){FLUSH WRAP if(m==0) LEAVE}}r=Z_OK;}
+#define OUTBYTE(a) {*q++=(Byte)(a);m--;}
+/* load local pointers */
+#define LOAD {LOADIN LOADOUT}
+
+/* masks for lower bits (size given to avoid silly warnings with Visual C++) */
+extern uInt zlib_fs_inflate_mask[17];
+
+/* copy as much as possible from the sliding window to the output area */
+extern int zlib_fs_inflate_flush OF((
+ inflate_blocks_statef *,
+ z_streamp ,
+ int));
+
+/* inflate private state */
+typedef enum {
+ METHOD, /* waiting for method byte */
+ FLAG, /* waiting for flag byte */
+ DICT4, /* four dictionary check bytes to go */
+ DICT3, /* three dictionary check bytes to go */
+ DICT2, /* two dictionary check bytes to go */
+ DICT1, /* one dictionary check byte to go */
+ DICT0, /* waiting for inflateSetDictionary */
+ BLOCKS, /* decompressing blocks */
+ CHECK4, /* four check bytes to go */
+ CHECK3, /* three check bytes to go */
+ CHECK2, /* two check bytes to go */
+ CHECK1, /* one check byte to go */
+ I_DONE, /* finished check, done */
+ I_BAD} /* got an error--stay here */
+inflate_mode;
+
+struct internal_state {
+
+ /* mode */
+ inflate_mode mode; /* current inflate mode */
+
+ /* mode dependent information */
+ union {
+ uInt method; /* if FLAGS, method byte */
+ struct {
+ uLong was; /* computed check value */
+ uLong need; /* stream check value */
+ } check; /* if CHECK, check values to compare */
+ uInt marker; /* if BAD, inflateSync's marker bytes count */
+ } sub; /* submode */
+
+ /* mode independent information */
+ int nowrap; /* flag for no wrapper */
+ uInt wbits; /* log2(window size) (8..15, defaults to 15) */
+ inflate_blocks_statef
+ *blocks; /* current inflate_blocks state */
+
+};
+
+/* inflate codes private state */
+typedef enum { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */
+ START, /* x: set up for LEN */
+ LEN, /* i: get length/literal/eob next */
+ LENEXT, /* i: getting length extra (have base) */
+ DIST, /* i: get distance next */
+ DISTEXT, /* i: getting distance extra */
+ COPY, /* o: copying bytes in window, waiting for space */
+ LIT, /* o: got literal, waiting for output space */
+ WASH, /* o: got eob, possibly still output waiting */
+ END, /* x: got eob and all data flushed */
+ BADCODE} /* x: got error */
+inflate_codes_mode;
+
+struct inflate_codes_state {
+
+ /* mode */
+ inflate_codes_mode mode; /* current inflate_codes mode */
+
+ /* mode dependent information */
+ uInt len;
+ union {
+ struct {
+ inflate_huft *tree; /* pointer into tree */
+ uInt need; /* bits needed */
+ } code; /* if LEN or DIST, where in tree */
+ uInt lit; /* if LIT, literal */
+ struct {
+ uInt get; /* bits to get for extra */
+ uInt dist; /* distance back to copy from */
+ } copy; /* if EXT or COPY, where and how much */
+ } sub; /* submode */
+
+ /* mode independent information */
+ Byte lbits; /* ltree bits decoded per branch */
+ Byte dbits; /* dtree bits decoder per branch */
+ inflate_huft *ltree; /* literal/length/eob tree */
+ inflate_huft *dtree; /* distance tree */
+
+};
+
+/* memory allocation for inflation */
+
+struct inflate_workspace {
+ inflate_codes_statef working_state;
+ struct inflate_blocks_state working_blocks_state;
+ struct internal_state internal_state;
+ unsigned int tree_work_area_1[19];
+ unsigned int tree_work_area_2[288];
+ unsigned working_blens[258 + 0x1f + 0x1f];
+ inflate_huft working_hufts[MANY];
+ unsigned char working_window[1 << MAX_WBITS];
+};
+
+#define WS(z) ((struct inflate_workspace *)(z->workspace))
+
+#endif
--- /dev/null
+/* zconf.h -- configuration of the zlib compression library
+ * Copyright (C) 1995-1998 Jean-loup Gailly.
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* @(#) $Id$ */
+
+#ifndef _ZCONF_H
+#define _ZCONF_H
+
+#if defined(__GNUC__) || defined(__386__) || defined(i386)
+# ifndef __32BIT__
+# define __32BIT__
+# endif
+#endif
+
+#if defined(__STDC__) || defined(__cplusplus)
+# ifndef STDC
+# define STDC
+# endif
+#endif
+
+/* The memory requirements for deflate are (in bytes):
+ (1 << (windowBits+2)) + (1 << (memLevel+9))
+ that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)
+ plus a few kilobytes for small objects. For example, if you want to reduce
+ the default memory requirements from 256K to 128K, compile with
+ make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
+ Of course this will generally degrade compression (there's no free lunch).
+
+ The memory requirements for inflate are (in bytes) 1 << windowBits
+ that is, 32K for windowBits=15 (default value) plus a few kilobytes
+ for small objects.
+*/
+
+/* Maximum value for memLevel in deflateInit2 */
+#ifndef MAX_MEM_LEVEL
+# define MAX_MEM_LEVEL 9
+#endif
+
+/* Maximum value for windowBits in deflateInit2 and inflateInit2.
+ * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
+ * created by gzip. (Files created by minigzip can still be extracted by
+ * gzip.)
+ */
+#ifndef MAX_WBITS
+# define MAX_WBITS 15 /* 32K LZ77 window */
+#endif
+
+ /* Type declarations */
+
+#ifndef OF /* function prototypes */
+# ifdef STDC
+# define OF(args) args
+# else
+# define OF(args) ()
+# endif
+#endif
+
+#ifndef ZEXPORT
+# define ZEXPORT
+#endif
+#ifndef ZEXPORTVA
+# define ZEXPORTVA
+#endif
+#ifndef ZEXTERN
+# define ZEXTERN extern
+#endif
+#ifndef FAR
+# define FAR
+#endif
+
+typedef unsigned char Byte; /* 8 bits */
+typedef unsigned int uInt; /* 16 bits or more */
+typedef unsigned long uLong; /* 32 bits or more */
+
+typedef Byte FAR Bytef;
+typedef char FAR charf;
+typedef int FAR intf;
+typedef uInt FAR uIntf;
+typedef uLong FAR uLongf;
+
+typedef void FAR *voidpf;
+typedef void *voidp;
+
+#include <linux/types.h> /* for off_t */
+#include <linux/unistd.h> /* for SEEK_* and off_t */
+#define z_off_t off_t
+
+#endif /* _ZCONF_H */
--- /dev/null
+/* zutil.h -- internal interface and configuration of the compression library
+ * Copyright (C) 1995-1998 Jean-loup Gailly.
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* WARNING: this file should *not* be used by applications. It is
+ part of the implementation of the compression library and is
+ subject to change. Applications should only use zlib.h.
+ */
+
+/* @(#) $Id: zutil.h,v 1.1 2000/01/01 03:32:23 davem Exp $ */
+
+#ifndef _Z_UTIL_H
+#define _Z_UTIL_H
+
+#include <linux/zlib_fs.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+
+#ifndef local
+# define local static
+#endif
+/* compile with -Dlocal if your debugger can't find static symbols */
+
+typedef unsigned char uch;
+typedef uch FAR uchf;
+typedef unsigned short ush;
+typedef ush FAR ushf;
+typedef unsigned long ulg;
+
+ /* common constants */
+
+#ifndef DEF_WBITS
+# define DEF_WBITS MAX_WBITS
+#endif
+/* default windowBits for decompression. MAX_WBITS is for compression only */
+
+#if MAX_MEM_LEVEL >= 8
+# define DEF_MEM_LEVEL 8
+#else
+# define DEF_MEM_LEVEL MAX_MEM_LEVEL
+#endif
+/* default memLevel */
+
+#define STORED_BLOCK 0
+#define STATIC_TREES 1
+#define DYN_TREES 2
+/* The three kinds of block type */
+
+#define MIN_MATCH 3
+#define MAX_MATCH 258
+/* The minimum and maximum match lengths */
+
+#define PRESET_DICT 0x20 /* preset dictionary flag in zlib header */
+
+ /* target dependencies */
+
+ /* Common defaults */
+
+#ifndef OS_CODE
+# define OS_CODE 0x03 /* assume Unix */
+#endif
+
+ /* functions */
+
+typedef uLong (ZEXPORT *check_func) OF((uLong check, const Bytef *buf,
+ uInt len));
+
+#endif /* _Z_UTIL_H */
obj-y := namei.o inode.o dir.o util.o rock.o
obj-$(CONFIG_JOLIET) += joliet.o
+obj-$(CONFIG_ZISOFS) += compress.o
obj-m := $(O_TARGET)
+CFLAGS_compress.o := -I $(TOPDIR)/fs/inflate_fs
+
include $(TOPDIR)/Rules.make
--- /dev/null
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ * Copyright 2001 H. Peter Anvin - All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * linux/fs/isofs/compress.c
+ *
+ * Transparent decompression of files on an iso9660 filesystem
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/stat.h>
+#include <linux/sched.h>
+#include <linux/iso_fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/locks.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/cdrom.h>
+#include <linux/init.h>
+#include <linux/nls.h>
+#include <linux/ctype.h>
+#include <linux/smp_lock.h>
+#include <linux/blkdev.h>
+#include <linux/vmalloc.h>
+#include <linux/zlib_fs.h>
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/semaphore.h>
+
+#include "zisofs.h"
+
+#define min(a,b) ((a)<(b)?(a):(b))
+#define max(a,b) ((a)>(b)?(a):(b))
+
+/* This should probably be global. */
+static char zisofs_sink_page[PAGE_CACHE_SIZE];
+
+/*
+ * This contains the zlib memory allocation and the mutex for the
+ * allocation; this avoids failures at block-decompression time.
+ */
+static void *zisofs_zlib_workspace;
+static struct semaphore zisofs_zlib_semaphore;
+
+/*
+ * When decompressing, we typically obtain more than one page
+ * per reference. We inject the additional pages into the page
+ * cache as a form of readahead.
+ */
+static int zisofs_readpage(struct file *file, struct page *page)
+{
+ struct inode *inode = file->f_dentry->d_inode;
+ struct address_space *mapping = inode->i_mapping;
+ unsigned int maxpage, xpage, fpage, blockindex;
+ unsigned long offset;
+ unsigned long blockptr, blockendptr, cstart, cend, csize;
+ struct buffer_head *bh, *ptrbh[2];
+ unsigned long bufsize = ISOFS_BUFFER_SIZE(inode);
+ unsigned int bufshift = ISOFS_BUFFER_BITS(inode);
+ unsigned long bufmask = bufsize - 1;
+ int err = -EIO;
+ int i;
+ unsigned int header_size = inode->u.isofs_i.i_format_parm[0];
+ unsigned int zisofs_block_shift = inode->u.isofs_i.i_format_parm[1];
+ /* unsigned long zisofs_block_size = 1UL << zisofs_block_shift; */
+ unsigned int zisofs_block_page_shift = zisofs_block_shift-PAGE_CACHE_SHIFT;
+ unsigned long zisofs_block_pages = 1UL << zisofs_block_page_shift;
+ unsigned long zisofs_block_page_mask = zisofs_block_pages-1;
+ struct page *pages[zisofs_block_pages];
+ unsigned long index = page->index;
+ int indexblocks;
+
+ /* We have already been given one page, this is the one
+ we must do. */
+ xpage = index & zisofs_block_page_mask;
+ pages[xpage] = page;
+
+ /* The remaining pages need to be allocated and inserted */
+ offset = index & ~zisofs_block_page_mask;
+ blockindex = offset >> zisofs_block_page_shift;
+ maxpage = (inode->i_size + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT;
+ maxpage = min(zisofs_block_pages, maxpage-offset);
+
+ for ( i = 0 ; i < maxpage ; i++, offset++ ) {
+ if ( i != xpage ) {
+ pages[i] = grab_cache_page_nowait(mapping, offset);
+ }
+ page = pages[i];
+ if ( page ) {
+ ClearPageError(page);
+ kmap(page);
+ }
+ }
+
+ /* This is the last page filled, plus one; used in case of abort. */
+ fpage = 0;
+
+ /* Find the pointer to this specific chunk */
+ /* Note: we're not using isonum_731() here because the data is known aligned */
+ /* Note: header_size is in 32-bit words (4 bytes) */
+ blockptr = (header_size + blockindex) << 2;
+ blockendptr = blockptr + 4;
+
+ indexblocks = ((blockptr^blockendptr) >> bufshift) ? 2 : 1;
+ ptrbh[0] = ptrbh[1] = 0;
+
+ if ( isofs_get_blocks(inode, blockptr >> bufshift, ptrbh, indexblocks) != indexblocks ) {
+ if ( ptrbh[0] ) brelse(ptrbh[0]);
+ printk(KERN_DEBUG "zisofs: Null buffer on reading block table, inode = %lu, block = %lu\n",
+ inode->i_ino, blockptr >> bufshift);
+ goto eio;
+ }
+ ll_rw_block(READ, indexblocks, ptrbh);
+
+ bh = ptrbh[0];
+ if ( !bh || (wait_on_buffer(bh), !buffer_uptodate(bh)) ) {
+ printk(KERN_DEBUG "zisofs: Failed to read block table, inode = %lu, block = %lu\n",
+ inode->i_ino, blockptr >> bufshift);
+ if ( ptrbh[1] )
+ brelse(ptrbh[1]);
+ goto eio;
+ }
+ cstart = le32_to_cpu(*(u32 *)(bh->b_data + (blockptr & bufmask)));
+
+ if ( indexblocks == 2 ) {
+ /* We just crossed a block boundary. Switch to the next block */
+ brelse(bh);
+ bh = ptrbh[1];
+ if ( !bh || (wait_on_buffer(bh), !buffer_uptodate(bh)) ) {
+ printk(KERN_DEBUG "zisofs: Failed to read block table, inode = %lu, block = %lu\n",
+ inode->i_ino, blockendptr >> bufshift);
+ goto eio;
+ }
+ }
+ cend = le32_to_cpu(*(u32 *)(bh->b_data + (blockendptr & bufmask)));
+ brelse(bh);
+
+ csize = cend-cstart;
+
+ /* Now page[] contains an array of pages, any of which can be NULL,
+ and the locks on which we hold. We should now read the data and
+ release the pages. If the pages are NULL the decompressed data
+ for that particular page should be discarded. */
+
+ if ( csize == 0 ) {
+ /* This data block is empty. */
+
+ for ( fpage = 0 ; fpage < maxpage ; fpage++ ) {
+ if ( (page = pages[fpage]) != NULL ) {
+ memset(page_address(page), 0, PAGE_CACHE_SIZE);
+
+ flush_dcache_page(page);
+ SetPageUptodate(page);
+ kunmap(page);
+ UnlockPage(page);
+ if ( fpage == xpage )
+ err = 0; /* The critical page */
+ else
+ page_cache_release(page);
+ }
+ }
+ } else {
+ /* This data block is compressed. */
+ z_stream stream;
+ int bail = 0, left_out = -1;
+ int zerr;
+ int needblocks = (csize + (cstart & bufmask) + bufmask) >> bufshift;
+ int haveblocks;
+ struct buffer_head *bhs[needblocks+1];
+ struct buffer_head **bhptr;
+
+ /* Because zlib is not thread-safe, do all the I/O at the top. */
+
+ blockptr = cstart >> bufshift;
+ memset(bhs, 0, (needblocks+1)*sizeof(struct buffer_head *));
+ haveblocks = isofs_get_blocks(inode, blockptr, bhs, needblocks);
+ ll_rw_block(READ, haveblocks, bhs);
+
+ bhptr = &bhs[0];
+ bh = *bhptr++;
+
+ /* First block is special since it may be fractional.
+ We also wait for it before grabbing the zlib
+ semaphore; odds are that the subsequent blocks are
+ going to come in in short order so we don't hold
+ the zlib semaphore longer than necessary. */
+
+ if ( !bh || (wait_on_buffer(bh), !buffer_uptodate(bh)) ) {
+ printk(KERN_DEBUG "zisofs: Hit null buffer, fpage = %d, xpage = %d, csize = %ld\n",
+ fpage, xpage, csize);
+ goto b_eio;
+ }
+ stream.next_in = bh->b_data + (cstart & bufmask);
+ stream.avail_in = min(bufsize-(cstart & bufmask), csize);
+ csize -= stream.avail_in;
+
+ stream.workspace = zisofs_zlib_workspace;
+ down(&zisofs_zlib_semaphore);
+
+ zerr = zlib_fs_inflateInit(&stream);
+ if ( zerr != Z_OK ) {
+ if ( err && zerr == Z_MEM_ERROR )
+ err = -ENOMEM;
+ printk(KERN_DEBUG "zisofs: zisofs_inflateInit returned %d\n",
+ zerr);
+ goto z_eio;
+ }
+
+ while ( !bail && fpage < maxpage ) {
+ page = pages[fpage];
+ if ( page )
+ stream.next_out = page_address(page);
+ else
+ stream.next_out = (void *)&zisofs_sink_page;
+ stream.avail_out = PAGE_CACHE_SIZE;
+
+ while ( stream.avail_out ) {
+ int ao, ai;
+ if ( stream.avail_in == 0 && left_out ) {
+ if ( !csize ) {
+ printk(KERN_WARNING "zisofs: ZF read beyond end of input\n");
+ bail = 1;
+ break;
+ } else {
+ bh = *bhptr++;
+ if ( !bh ||
+ (wait_on_buffer(bh), !buffer_uptodate(bh)) ) {
+ /* Reached an EIO */
+ printk(KERN_DEBUG "zisofs: Hit null buffer, fpage = %d, xpage = %d, csize = %ld\n",
+ fpage, xpage, csize);
+
+ bail = 1;
+ break;
+ }
+ stream.next_in = bh->b_data;
+ stream.avail_in = min(csize,bufsize);
+ csize -= stream.avail_in;
+ }
+ }
+ ao = stream.avail_out; ai = stream.avail_in;
+ zerr = zlib_fs_inflate(&stream, Z_SYNC_FLUSH);
+ left_out = stream.avail_out;
+ if ( zerr == Z_BUF_ERROR && stream.avail_in == 0 )
+ continue;
+ if ( zerr != Z_OK ) {
+ /* EOF, error, or trying to read beyond end of input */
+ if ( err && zerr == Z_MEM_ERROR )
+ err = -ENOMEM;
+ if ( zerr != Z_STREAM_END )
+ printk(KERN_DEBUG "zisofs: zisofs_inflate returned %d, inode = %lu, index = %lu, fpage = %d, xpage = %d, avail_in = %d, avail_out = %d, ai = %d, ao = %d\n",
+ zerr, inode->i_ino, index,
+ fpage, xpage,
+ stream.avail_in, stream.avail_out,
+ ai, ao);
+ bail = 1;
+ break;
+ }
+ }
+
+ if ( stream.avail_out && zerr == Z_STREAM_END ) {
+ /* Fractional page written before EOF. This may
+ be the last page in the file. */
+ memset(stream.next_out, 0, stream.avail_out);
+ stream.avail_out = 0;
+ }
+
+ if ( !stream.avail_out ) {
+ /* This page completed */
+ if ( page ) {
+ flush_dcache_page(page);
+ SetPageUptodate(page);
+ kunmap(page);
+ UnlockPage(page);
+ if ( fpage == xpage )
+ err = 0; /* The critical page */
+ else
+ page_cache_release(page);
+ }
+ fpage++;
+ }
+ }
+ zlib_fs_inflateEnd(&stream);
+
+ z_eio:
+ up(&zisofs_zlib_semaphore);
+
+ b_eio:
+ for ( i = 0 ; i < haveblocks ; i++ ) {
+ if ( bhs[i] )
+ brelse(bhs[i]);
+ }
+ }
+
+eio:
+
+ /* Release any residual pages, do not SetPageUptodate */
+ while ( fpage < maxpage ) {
+ page = pages[fpage];
+ if ( page ) {
+ flush_dcache_page(page);
+ if ( fpage == xpage )
+ SetPageError(page);
+ kunmap(page);
+ UnlockPage(page);
+ if ( fpage != xpage )
+ page_cache_release(page);
+ }
+ fpage++;
+ }
+
+ /* At this point, err contains 0 or -EIO depending on the "critical" page */
+ return err;
+}
+
+struct address_space_operations zisofs_aops = {
+ readpage: zisofs_readpage,
+ /* No sync_page operation supported? */
+ /* No bmap operation supported */
+};
+
+static int initialized = 0;
+
+int __init zisofs_init(void)
+{
+ if ( initialized ) {
+ printk("zisofs_init: called more than once\n");
+ return 0;
+ }
+
+ zisofs_zlib_workspace = vmalloc(zlib_fs_inflate_workspacesize());
+ if ( !zisofs_zlib_workspace )
+ return -ENOMEM;
+ init_MUTEX(&zisofs_zlib_semaphore);
+
+ initialized = 1;
+ return 0;
+}
+
+void __exit zisofs_cleanup(void)
+{
+ if ( !initialized ) {
+ printk("zisofs_cleanup: called without initialization\n");
+ return;
+ }
+
+ vfree(zisofs_zlib_workspace);
+ initialized = 0;
+}
#include <asm/system.h>
#include <asm/uaccess.h>
+#include "zisofs.h"
+
/*
* We have no support for "multi volume" CDs, but more and more disks carry
* wrong information within the volume descriptors.
char joliet;
char cruft;
char unhide;
+ char nocompress;
unsigned char check;
unsigned int blocksize;
mode_t mode;
popt->cruft = 'n';
popt->unhide = 'n';
popt->check = 'u'; /* unset */
+ popt->nocompress = 0;
popt->blocksize = 1024;
popt->mode = S_IRUGO | S_IXUGO; /* r-x for all. The disc could
be shared with DOS machines so
popt->utf8 = 1;
continue;
}
+ if (strncmp(this_char,"nocompress",10) == 0) {
+ popt->nocompress = 1;
+ continue;
+ }
if ((value = strchr(this_char,'=')) != NULL)
*value++ = 0;
s->u.isofs_sb.s_uid = opt.uid;
s->u.isofs_sb.s_gid = opt.gid;
s->u.isofs_sb.s_utf8 = opt.utf8;
+ s->u.isofs_sb.s_nocompress = opt.nocompress;
/*
* It would be incredibly stupid to allow people to mark every file
* on the disk as suid, so we merely allow them to set the default
return 0;
}
-/* Life is simpler than for other filesystem since we never
- * have to create a new block, only find an existing one.
+/*
+ * Get a set of blocks; filling in buffer_heads if already allocated
+ * or getblk() if they are not. Returns the number of blocks inserted
+ * (0 == error.)
*/
-static int isofs_get_block(struct inode *inode, long iblock,
- struct buffer_head *bh_result, int create)
+int isofs_get_blocks(struct inode *inode, long iblock,
+ struct buffer_head **bh_result, unsigned long nblocks)
{
unsigned long b_off;
unsigned offset, sect_size;
unsigned int firstext;
unsigned long nextino;
- int i, err;
+ int section, rv;
+ unsigned int blocksize = inode->i_sb->s_blocksize;
lock_kernel();
- err = -EROFS;
- if (create)
- goto abort_create_attempted;
-
- err = -EIO;
- if (iblock < 0)
- goto abort_negative;
+ rv = 0;
+ if (iblock < 0) {
+ printk("isofs_get_blocks: block < 0\n");
+ goto abort;
+ }
b_off = iblock;
-
- /* If we are *way* beyond the end of the file, print a message.
- * Access beyond the end of the file up to the next page boundary
- * is normal, however because of the way the page cache works.
- * In this case, we just return 0 so that we can properly fill
- * the page with useless information without generating any
- * I/O errors.
- */
- if (b_off > ((inode->i_size + PAGE_SIZE - 1) >> ISOFS_BUFFER_BITS(inode)))
- goto abort_beyond_end;
-
+
offset = 0;
firstext = inode->u.isofs_i.i_first_extent;
sect_size = inode->u.isofs_i.i_section_size >> ISOFS_BUFFER_BITS(inode);
nextino = inode->u.isofs_i.i_next_section_ino;
-
- i = 0;
- if (nextino) {
- while (b_off >= (offset + sect_size)) {
- struct inode *ninode;
-
- offset += sect_size;
- if (nextino == 0)
- goto abort;
- ninode = iget(inode->i_sb, nextino);
- if (!ninode)
+ section = 0;
+
+ while ( nblocks ) {
+ /* If we are *way* beyond the end of the file, print a message.
+ * Access beyond the end of the file up to the next page boundary
+ * is normal, however because of the way the page cache works.
+ * In this case, we just return 0 so that we can properly fill
+ * the page with useless information without generating any
+ * I/O errors.
+ */
+ if (b_off > ((inode->i_size + PAGE_CACHE_SIZE - 1) >> ISOFS_BUFFER_BITS(inode))) {
+ printk("isofs_get_blocks: block >= EOF (%ld, %ld)\n",
+ iblock, (unsigned long) inode->i_size);
+ goto abort;
+ }
+
+ if (nextino) {
+ while (b_off >= (offset + sect_size)) {
+ struct inode *ninode;
+
+ offset += sect_size;
+ if (nextino == 0)
+ goto abort;
+ ninode = iget(inode->i_sb, nextino);
+ if (!ninode)
+ goto abort;
+ firstext = ninode->u.isofs_i.i_first_extent;
+ sect_size = ninode->u.isofs_i.i_section_size;
+ nextino = ninode->u.isofs_i.i_next_section_ino;
+ iput(ninode);
+
+ if (++section > 100) {
+ printk("isofs_get_blocks: More than 100 file sections ?!?, aborting...\n");
+ printk("isofs_get_blocks: ino=%lu block=%ld firstext=%u sect_size=%u nextino=%lu\n",
+ inode->i_ino, iblock, firstext, (unsigned) sect_size, nextino);
+ goto abort;
+ }
+ }
+ }
+
+ if ( *bh_result ) {
+ (*bh_result)->b_dev = inode->i_dev;
+ (*bh_result)->b_blocknr = firstext + b_off - offset;
+ (*bh_result)->b_state |= (1UL << BH_Mapped);
+ } else {
+ *bh_result = getblk(inode->i_dev, firstext+b_off-offset, blocksize);
+ if ( !*bh_result )
goto abort;
- firstext = ninode->u.isofs_i.i_first_extent;
- sect_size = ninode->u.isofs_i.i_section_size;
- nextino = ninode->u.isofs_i.i_next_section_ino;
- iput(ninode);
-
- if (++i > 100)
- goto abort_too_many_sections;
}
+ bh_result++; /* Next buffer head */
+ b_off++; /* Next buffer offset */
+ nblocks--;
+ rv++;
}
- bh_result->b_dev = inode->i_dev;
- bh_result->b_blocknr = firstext + b_off - offset;
- bh_result->b_state |= (1UL << BH_Mapped);
- err = 0;
abort:
unlock_kernel();
- return err;
-
-abort_create_attempted:
- printk("isofs_get_block: Kernel tries to allocate a block\n");
- goto abort;
-
-abort_negative:
- printk("isofs_get_block: block < 0\n");
- goto abort;
-
-abort_beyond_end:
- printk("isofs_get_block: block >= EOF (%ld, %ld)\n",
- iblock, (unsigned long) inode->i_size);
- goto abort;
-
-abort_too_many_sections:
- printk("isofs_get_block: More than 100 file sections ?!?, aborting...\n");
- printk("isofs_get_block: ino=%lu block=%ld firstext=%u sect_size=%u nextino=%lu\n",
- inode->i_ino, iblock, firstext, (unsigned) sect_size, nextino);
- goto abort;
+ return rv;
+}
+
+/*
+ * Used by the standard interfaces.
+ */
+static int isofs_get_block(struct inode *inode, long iblock,
+ struct buffer_head *bh_result, int create)
+{
+ if ( create ) {
+ printk("isofs_get_block: Kernel tries to allocate a block\n");
+ return -EROFS;
+ }
+
+ return isofs_get_blocks(inode, iblock, &bh_result, 1) ? 0 : -EIO;
}
static int isofs_bmap(struct inode *inode, int block)
de = tmpde;
}
+ /* Assume it is a normal-format file unless told otherwise */
+ inode->u.isofs_i.i_file_format = isofs_file_normal;
+
if (de->flags[-high_sierra] & 2) {
inode->i_mode = S_IRUGO | S_IXUGO | S_IFDIR;
inode->i_nlink = 1; /* Set to 1. We know there are 2, but
inode->u.isofs_i.i_first_extent = (isonum_733 (de->extent) +
isonum_711 (de->ext_attr_length));
+ /* Set the number of blocks for stat() - should be done before RR */
+ inode->i_blksize = PAGE_CACHE_SIZE; /* For stat() only */
+ inode->i_blocks = (inode->i_size + 511) >> 9;
+
/*
* Now test for possible Rock Ridge extensions which will override
* some of these numbers in the inode structure.
{
if (S_ISREG(inode->i_mode)) {
inode->i_fop = &generic_ro_fops;
- inode->i_data.a_ops = &isofs_aops;
+ switch ( inode->u.isofs_i.i_file_format ) {
+#ifdef CONFIG_ZISOFS
+ case isofs_file_compressed:
+ inode->i_data.a_ops = &zisofs_aops;
+ break;
+#endif
+ default:
+ inode->i_data.a_ops = &isofs_aops;
+ break;
+ }
} else if (S_ISDIR(inode->i_mode)) {
inode->i_op = &isofs_dir_inode_operations;
inode->i_fop = &isofs_dir_operations;
static int __init init_iso9660_fs(void)
{
+#ifdef CONFIG_ZISOFS
+ int err;
+
+ err = zisofs_init();
+ if ( err )
+ return err;
+#endif
return register_filesystem(&iso9660_fs_type);
}
static void __exit exit_iso9660_fs(void)
{
unregister_filesystem(&iso9660_fs_type);
+#ifdef CONFIG_ZISOFS
+ zisofs_cleanup();
+#endif
}
EXPORT_NO_SYMBOLS;
module_init(init_iso9660_fs)
module_exit(exit_iso9660_fs)
+MODULE_LICENSE("GPL");
+
* returns a symbolic link name, and a fourth one returns the extent number
* for the file. */
-#define SIG(A,B) ((A << 8) | B)
+#define SIG(A,B) ((A) | ((B) << 8)) /* isonum_721() */
/* This is a way of ensuring that we have something in the system
while (len > 1){ /* There may be one byte for padding somewhere */
rr = (struct rock_ridge *) chr;
if (rr->len == 0) goto out; /* Something got screwed up here */
- sig = (chr[0] << 8) + chr[1];
+ sig = isonum_721(chr);
chr += rr->len;
len -= rr->len;
while (len > 1){ /* There may be one byte for padding somewhere */
rr = (struct rock_ridge *) chr;
if (rr->len == 0) goto out; /* Something got screwed up here */
- sig = (chr[0] << 8) + chr[1];
+ sig = isonum_721(chr);
chr += rr->len;
len -= rr->len;
while (len > 1){ /* There may be one byte for padding somewhere */
rr = (struct rock_ridge *) chr;
if (rr->len == 0) goto out; /* Something got screwed up here */
- sig = (chr[0] << 8) + chr[1];
+ sig = isonum_721(chr);
chr += rr->len;
len -= rr->len;
switch(sig){
+#ifndef CONFIG_ZISOFS /* No flag for SF or ZF */
case SIG('R','R'):
if((rr->u.RR.flags[0] &
(RR_PX | RR_TF | RR_SL | RR_CL)) == 0) goto out;
break;
+#endif
case SIG('S','P'):
CHECK_SP(goto out);
break;
inode->i_gid = reloc->i_gid;
inode->i_rdev = reloc->i_rdev;
inode->i_size = reloc->i_size;
+ inode->i_blocks = reloc->i_blocks;
inode->i_atime = reloc->i_atime;
inode->i_ctime = reloc->i_ctime;
inode->i_mtime = reloc->i_mtime;
iput(reloc);
break;
+#ifdef CONFIG_ZISOFS
+ case SIG('Z','F'):
+ if ( !inode->i_sb->u.isofs_sb.s_nocompress ) {
+ int algo;
+ algo = isonum_721(rr->u.ZF.algorithm);
+ if ( algo == SIG('p','z') ) {
+ int block_shift = isonum_711(&rr->u.ZF.parms[1]);
+ if ( block_shift < PAGE_CACHE_SHIFT || block_shift > 17 ) {
+ printk(KERN_WARNING "isofs: Can't handle ZF block size of 2^%d\n", block_shift);
+ } else {
+ /* Note: we don't change i_blocks here */
+ inode->u.isofs_i.i_file_format = isofs_file_compressed;
+ /* Parameters to compression algorithm (header size, block size) */
+ inode->u.isofs_i.i_format_parm[0] = isonum_711(&rr->u.ZF.parms[0]);
+ inode->u.isofs_i.i_format_parm[1] = isonum_711(&rr->u.ZF.parms[1]);
+ inode->i_size = isonum_733(rr->u.ZF.real_size);
+ }
+ } else {
+ printk(KERN_WARNING "isofs: Unknown ZF compression algorithm: %c%c\n",
+ rr->u.ZF.algorithm[0], rr->u.ZF.algorithm[1]);
+ }
+ }
+ break;
+#endif
default:
break;
}
rr = (struct rock_ridge *) chr;
if (rr->len == 0)
goto out; /* Something got screwed up here */
- sig = (chr[0] << 8) + chr[1];
+ sig = isonum_721(chr);
chr += rr->len;
len -= rr->len;
struct SU_SP{
unsigned char magic[2];
unsigned char skip;
-};
+} __attribute__((packed));
struct SU_CE{
char extent[8];
unsigned char len_src;
unsigned char ext_ver;
char data[0];
-};
+} __attribute__((packed));
struct RR_RR{
char flags[1];
-};
+} __attribute__((packed));
struct RR_PX{
char mode[8];
unsigned char flags;
unsigned char len;
char text[0];
-};
+} __attribute__((packed));
struct RR_SL{
unsigned char flags;
struct SL_component link;
-};
+} __attribute__((packed));
struct RR_NM{
unsigned char flags;
char name[0];
-};
+} __attribute__((packed));
struct RR_CL{
char location[8];
struct stamp{
char time[7];
-};
+} __attribute__((packed));
struct RR_TF{
char flags;
struct stamp times[0]; /* Variable number of these beasts */
+} __attribute__((packed));
+
+/* Linux-specific extension for transparent decompression */
+struct RR_ZF{
+ char algorithm[2];
+ char parms[2];
+ char real_size[8];
};
/* These are the bits and their meanings for flags in the TF structure. */
struct RR_CL CL;
struct RR_PL PL;
struct RR_TF TF;
+ struct RR_ZF ZF;
} u;
};
*/
#include <linux/time.h>
-#include <linux/fs.h>
#include <linux/iso_fs.h>
/*
--- /dev/null
+/* ----------------------------------------------------------------------- *
+ *
+ * Copyright 2001 H. Peter Anvin - All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * Prototypes for functions exported from the compressed isofs subsystem
+ */
+
+#ifdef CONFIG_ZISOFS
+extern struct address_space_operations zisofs_aops;
+extern int __init zisofs_init(void);
+extern void __exit zisofs_cleanup(void);
+#endif
# endif
#endif
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* __ASM_ALPHA_FLOPPY_H */
*/
#define pgtable_cache_init() do { } while (0)
+/* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT. */
+#define HAVE_ARCH_UNMAPPED_AREA
+
#endif /* _ALPHA_PGTABLE_H */
* Changelog:
* 11-Apr-2001 TTC Created
*/
-
-#ifndef __ASM_ARCH_KEYBOARD_H
-#define __ASM_ARCH_KEYBOARD_H
-
-#define kbd_setkeycode(s, k) (-EINVAL)
-#define kbd_getkeycode(s) (-EINVAL)
-#define kbd_translate(s, k, r) 0
-#define kbd_unexpected_up(k) 0
-#define kbd_leds(l)
-#define kbd_init_hw()
-#define kbd_sysrq_xlate ((int *) 0)
-#define kbd_disable_irq()
-#define kbd_enable_irq()
-
-#define SYSRQ_KEY 0x54
-
-#endif
+#define kbd_init_hw() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
+#define kbd_disable_irq() do { } while (0)
/*
* linux/include/asm-arm/arch-arc/keyboard.h
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* Keyboard driver definitions for Acorn Archimedes/A5000
* architecture
*/
-
#include <asm/irq.h>
#define NR_SCANCODES 128
-extern void a5kkbd_leds(unsigned char leds);
extern void a5kkbd_init_hw(void);
-extern unsigned char a5kkbd_sysrq_xlate[NR_SCANCODES];
-
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) a5kkbd_leds(leds)
-#define kbd_init_hw() a5kkbd_init_hw()
-#define kbd_sysrq_xlate a5kkbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() a5kkbd_init_hw()
*
* Keyboard driver definitions for CL7500 architecture
*
- * (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*/
-
-#include <asm/irq.h>
-
#define NR_SCANCODES 128
-extern void ps2kbd_leds(unsigned char leds);
-extern void ps2kbd_init_hw(void);
-extern unsigned char ps2kbd_sysrq_xlate[NR_SCANCODES];
-
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) ps2kbd_leds(leds)
-#define kbd_init_hw() ps2kbd_init_hw()
-#define kbd_sysrq_xlate ps2kbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+extern int ps2kbd_init_hw(void);
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() ps2kbd_init_hw()
*
* Keyboard driver definitions for EBSA285 architecture
*
- * (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* (C) 1998 Phil Blundell
*/
#include <linux/ioport.h>
#include <asm/irq.h>
#include <asm/system.h>
+#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
+#define NR_SCANCODES 128
+
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
+
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
extern void pckbd_init_hw(void);
extern unsigned char pckbd_sysrq_xlate[128];
-#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
-
-#define NR_SCANCODES 128
-
-#define kbd_setkeycode(sc,kc) \
- ({ \
- int __ret; \
- if (have_isa_bridge) \
- __ret = pckbd_setkeycode(sc,kc);\
- else \
- __ret = -EINVAL; \
- __ret; \
- })
-
-#define kbd_getkeycode(sc) \
- ({ \
- int __ret; \
- if (have_isa_bridge) \
- __ret = pckbd_getkeycode(sc); \
- else \
- __ret = -EINVAL; \
- __ret; \
- })
-
-#define kbd_translate(sc, kcp, rm) \
- ({ \
- pckbd_translate(sc, kcp, rm); \
- })
+static inline void kbd_init_hw(void)
+{
+ if (have_isa_bridge) {
+ k_setkeycode = pckbd_setkeycode;
+ k_getkeycode = pckbd_getkeycode;
+ k_translate = pckbd_translate;
+ k_unexpected_up = pckbd_unexpected_up;
+ k_leds = pckbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+ k_sysrq_key = 0x54;
+ k_sysrq_xlate = pckbd_sysrq_xlate;
+#endif
+ pckbd_init_hw();
+ }
+}
-#define kbd_unexpected_up pckbd_unexpected_up
-#define kbd_leds(leds) \
- do { \
- if (have_isa_bridge) \
- pckbd_leds(leds); \
- } while (0)
-
-#define kbd_init_hw() \
- do { \
- if (have_isa_bridge) \
- pckbd_init_hw(); \
- } while (0)
-
-#define kbd_sysrq_xlate pckbd_sysrq_xlate
-
-#define kbd_disable_irq()
-#define kbd_enable_irq()
-
-#define SYSRQ_KEY 0x54
+/*
+ * The rest of this file is to do with supporting pc_keyb.c
+ */
/* resource allocation */
#define kbd_request_region() request_region(0x60, 16, "keyboard")
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-camelot/dma.h
+ *
+ * Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS 0xffffffff
+
+#define MAX_DMA_CHANNELS 0
+
+#endif /* _ASM_ARCH_DMA_H */
+
--- /dev/null
+/* megafunction wizard: %ARM-Based Excalibur%
+ GENERATION: STANDARD
+ VERSION: WM1.0
+ MODULE: ARM-Based Excalibur
+ PROJECT: excalibur
+ ============================================================
+ File Name: v:\embedded\linux\bootldr\excalibur.h
+ Megafunction Name(s): ARM-Based Excalibur
+ ============================================================
+
+ ************************************************************
+ THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+ ************************************************************/
+
+#ifndef EXCALIBUR_H_INCLUDED
+#define EXCALIBUR_H_INCLUDED
+
+#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
+#define EXC_DEFINE_BOOT_FROM_FLASH
+
+#define EXC_INPUT_CLK_FREQUENCY (50000000)
+#define EXC_AHB1_CLK_FREQUENCY (150000000)
+#define EXC_AHB2_CLK_FREQUENCY (75000000)
+#define EXC_SDRAM_CLK_FREQUENCY (75000000)
+
+/* Registers Block */
+#define EXC_REGISTERS_BASE (0x7fffc000)
+#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
+#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
+#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
+#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
+#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
+#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
+#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
+#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
+#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
+#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
+#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
+#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
+#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+
+#define EXC_REGISTERS_SIZE (0x00004000)
+
+/* EBI Block(s) */
+#define EXC_EBI_BLOCK0_BASE (0x40000000)
+#define EXC_EBI_BLOCK0_SIZE (0x00400000)
+#define EXC_EBI_BLOCK0_WIDTH (8)
+#define EXC_EBI_BLOCK0_NON_CACHEABLE
+#define EXC_EBI_BLOCK1_BASE (0x40400000)
+#define EXC_EBI_BLOCK1_SIZE (0x00400000)
+#define EXC_EBI_BLOCK1_WIDTH (16)
+#define EXC_EBI_BLOCK1_NON_CACHEABLE
+#define EXC_EBI_BLOCK2_BASE (0x40800000)
+#define EXC_EBI_BLOCK2_SIZE (0x00400000)
+#define EXC_EBI_BLOCK2_WIDTH (16)
+#define EXC_EBI_BLOCK2_NON_CACHEABLE
+#define EXC_EBI_BLOCK3_BASE (0x40c00000)
+#define EXC_EBI_BLOCK3_SIZE (0x00400000)
+#define EXC_EBI_BLOCK3_WIDTH (16)
+#define EXC_EBI_BLOCK3_NON_CACHEABLE
+
+/* SDRAM Block(s) */
+#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
+#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
+#define EXC_SDRAM_BLOCK0_WIDTH (32)
+#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
+#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
+#define EXC_SDRAM_BLOCK1_WIDTH (32)
+
+/* Single Port SRAM Block(s) */
+#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
+#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
+#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
+#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
+
+/* PLD Block(s) */
+#define EXC_PLD_BLOCK0_BASE (0x80000000)
+#define EXC_PLD_BLOCK0_SIZE (0x00004000)
+#define EXC_PLD_BLOCK0_NON_CACHEABLE
+#define EXC_PLD_BLOCK1_BASE (0xf000000)
+#define EXC_PLD_BLOCK1_SIZE (0x00004000)
+#define EXC_PLD_BLOCK1_NON_CACHEABLE
+#define EXC_PLD_BLOCK2_BASE (0x80008000)
+#define EXC_PLD_BLOCK2_SIZE (0x00004000)
+#define EXC_PLD_BLOCK2_NON_CACHEABLE
+#define EXC_PLD_BLOCK3_BASE (0x8000c000)
+#define EXC_PLD_BLOCK3_SIZE (0x00004000)
+#define EXC_PLD_BLOCK3_NON_CACHEABLE
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10/hardware.h
+ *
+ * This file contains the hardware definitions of the Integrator.
+ *
+ * Copyright (C) 1999 ARM Limited.
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/arch/sizes.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE 0xf0000000 // VA of IO
+#define IO_SIZE 0x10000000 // How much?
+#define IO_START EXC_REGISTERS_BASE // PA of IO
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x) | 0xf0000000)
+
+#define FLASH_VBASE 0xFE000000
+#define FLASH_SIZE 0x01000000
+#define FLASH_START EXC_EBI_BLOCK0_BASE
+#define FLASH_VADDR(x) ((x)|0xFE000000)
+/*
+ * Similar to above, but for PCI addresses (memory, IO, Config and the
+ * V3 chip itself). WARNING: this has to mirror definitions in platform.h
+ */
+#if 0
+#define PCI_MEMORY_VADDR 0xe8000000
+#define PCI_CONFIG_VADDR 0xec000000
+#define PCI_V3_VADDR 0xed000000
+#define PCI_IO_VADDR 0xee000000
+
+#define PCIO_BASE PCI_IO_VADDR
+#define PCIMEM_BASE PCI_MEMORY_VADDR
+
+
+#define pcibios_assign_all_busses() 1
+
+#define PCIBIOS_MIN_IO 0x6000
+#define PCIBIOS_MIN_MEM 0x00100000
+#endif
+
+
+#endif
+
--- /dev/null
+/*
+ *
+ * This file contains the register definitions for the Excalibur
+ * Timer TIMER00.
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __INT_CTRL00_H
+#define __INT_CTRL00_H
+
+#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 ))
+#define INT_MS_FC_MSK (0x10000)
+#define INT_MS_FC_OFST (16)
+#define INT_MS_M1_MSK (0x8000)
+#define INT_MS_M1_OFST (15)
+#define INT_MS_M0_MSK (0x4000)
+#define INT_MS_M0_OFST (14)
+#define INT_MS_AE_MSK (0x2000)
+#define INT_MS_AE_OFST (13)
+#define INT_MS_PE_MSK (0x1000)
+#define INT_MS_PE_OFST (12)
+#define INT_MS_EE_MSK (0x0800)
+#define INT_MS_EE_OFST (11)
+#define INT_MS_PS_MSK (0x0400)
+#define INT_MS_PS_OFST (10)
+#define INT_MS_T1_MSK (0x0200)
+#define INT_MS_T1_OFST (9)
+#define INT_MS_T0_MSK (0x0100)
+#define INT_MS_T0_OFST (8)
+#define INT_MS_UA_MSK (0x0080)
+#define INT_MS_UA_OFST (7)
+#define INT_MS_IP_MSK (0x0040)
+#define INT_MS_IP_OFST (6)
+#define INT_MS_P5_MSK (0x0020)
+#define INT_MS_P5_OFST (5)
+#define INT_MS_P4_MSK (0x0010)
+#define INT_MS_P4_OFST (4)
+#define INT_MS_P3_MSK (0x0008)
+#define INT_MS_P3_OFST (3)
+#define INT_MS_P2_MSK (0x0004)
+#define INT_MS_P2_OFST (2)
+#define INT_MS_P1_MSK (0x0002)
+#define INT_MS_P1_OFST (1)
+#define INT_MS_P0_MSK (0x0001)
+#define INT_MS_P0_OFST (0)
+
+#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 ))
+#define INT_MC_FC_MSK (0x10000)
+#define INT_MC_FC_OFST (16)
+#define INT_MC_M1_MSK (0x8000)
+#define INT_MC_M1_OFST (15)
+#define INT_MC_M0_MSK (0x4000)
+#define INT_MC_M0_OFST (14)
+#define INT_MC_AE_MSK (0x2000)
+#define INT_MC_AE_OFST (13)
+#define INT_MC_PE_MSK (0x1000)
+#define INT_MC_PE_OFST (12)
+#define INT_MC_EE_MSK (0x0800)
+#define INT_MC_EE_OFST (11)
+#define INT_MC_PS_MSK (0x0400)
+#define INT_MC_PS_OFST (10)
+#define INT_MC_T1_MSK (0x0200)
+#define INT_MC_T1_OFST (9)
+#define INT_MC_T0_MSK (0x0100)
+#define INT_MC_T0_OFST (8)
+#define INT_MC_UA_MSK (0x0080)
+#define INT_MC_UA_OFST (7)
+#define INT_MC_IP_MSK (0x0040)
+#define INT_MC_IP_OFST (6)
+#define INT_MC_P5_MSK (0x0020)
+#define INT_MC_P5_OFST (5)
+#define INT_MC_P4_MSK (0x0010)
+#define INT_MC_P4_OFST (4)
+#define INT_MC_P3_MSK (0x0008)
+#define INT_MC_P3_OFST (3)
+#define INT_MC_P2_MSK (0x0004)
+#define INT_MC_P2_OFST (2)
+#define INT_MC_P1_MSK (0x0002)
+#define INT_MC_P1_OFST (1)
+#define INT_MC_P0_MSK (0x0001)
+#define INT_MC_P0_OFST (0)
+
+#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 ))
+#define INT_SS_FC_SSK (0x8000)
+#define INT_SS_FC_OFST (15)
+#define INT_SS_M1_SSK (0x8000)
+#define INT_SS_M1_OFST (15)
+#define INT_SS_M0_SSK (0x4000)
+#define INT_SS_M0_OFST (14)
+#define INT_SS_AE_SSK (0x2000)
+#define INT_SS_AE_OFST (13)
+#define INT_SS_PE_SSK (0x1000)
+#define INT_SS_PE_OFST (12)
+#define INT_SS_EE_SSK (0x0800)
+#define INT_SS_EE_OFST (11)
+#define INT_SS_PS_SSK (0x0400)
+#define INT_SS_PS_OFST (10)
+#define INT_SS_T1_SSK (0x0200)
+#define INT_SS_T1_OFST (9)
+#define INT_SS_T0_SSK (0x0100)
+#define INT_SS_T0_OFST (8)
+#define INT_SS_UA_SSK (0x0080)
+#define INT_SS_UA_OFST (7)
+#define INT_SS_IP_SSK (0x0040)
+#define INT_SS_IP_OFST (6)
+#define INT_SS_P5_SSK (0x0020)
+#define INT_SS_P5_OFST (5)
+#define INT_SS_P4_SSK (0x0010)
+#define INT_SS_P4_OFST (4)
+#define INT_SS_P3_SSK (0x0008)
+#define INT_SS_P3_OFST (3)
+#define INT_SS_P2_SSK (0x0004)
+#define INT_SS_P2_OFST (2)
+#define INT_SS_P1_SSK (0x0002)
+#define INT_SS_P1_OFST (1)
+#define INT_SS_P0_SSK (0x0001)
+#define INT_SS_P0_OFST (0)
+
+#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C ))
+#define INT_RS_FC_RSK (0x10000)
+#define INT_RS_FC_OFST (16)
+#define INT_RS_M1_RSK (0x8000)
+#define INT_RS_M1_OFST (15)
+#define INT_RS_M0_RSK (0x4000)
+#define INT_RS_M0_OFST (14)
+#define INT_RS_AE_RSK (0x2000)
+#define INT_RS_AE_OFST (13)
+#define INT_RS_PE_RSK (0x1000)
+#define INT_RS_PE_OFST (12)
+#define INT_RS_EE_RSK (0x0800)
+#define INT_RS_EE_OFST (11)
+#define INT_RS_PS_RSK (0x0400)
+#define INT_RS_PS_OFST (10)
+#define INT_RS_T1_RSK (0x0200)
+#define INT_RS_T1_OFST (9)
+#define INT_RS_T0_RSK (0x0100)
+#define INT_RS_T0_OFST (8)
+#define INT_RS_UA_RSK (0x0080)
+#define INT_RS_UA_OFST (7)
+#define INT_RS_IP_RSK (0x0040)
+#define INT_RS_IP_OFST (6)
+#define INT_RS_P5_RSK (0x0020)
+#define INT_RS_P5_OFST (5)
+#define INT_RS_P4_RSK (0x0010)
+#define INT_RS_P4_OFST (4)
+#define INT_RS_P3_RSK (0x0008)
+#define INT_RS_P3_OFST (3)
+#define INT_RS_P2_RSK (0x0004)
+#define INT_RS_P2_OFST (2)
+#define INT_RS_P1_RSK (0x0002)
+#define INT_RS_P1_OFST (1)
+#define INT_RS_P0_RSK (0x0001)
+#define INT_RS_P0_OFST (0)
+
+#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 ))
+#define INT_ID_ID_MSK (0x3F)
+#define INT_ID_ID_OFST (0)
+
+#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 ))
+#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
+#define INT_PLD_PRIORITY_PRI_OFST (0)
+#define INT_PLD_PRIORITY_GA_MSK (0x40)
+#define INT_PLD_PRIORITY_GA_OFST (6)
+
+#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 ))
+#define INT_MODE_MODE_MSK (0x3)
+#define INT_MODE_MODE_OFST (0)
+
+#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 ))
+#define INT_PRIORITY_P0_PRI_MSK (0x3F)
+#define INT_PRIORITY_P0_PRI_OFST (0)
+#define INT_PRIORITY_P0_FQ_MSK (0x40)
+#define INT_PRIORITY_P0_FQ_OFST (6)
+
+#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 ))
+#define INT_PRIORITY_P1_PRI_MSK (0x3F)
+#define INT_PRIORITY_P1_PRI_OFST (0)
+#define INT_PRIORITY_P1_FQ_MSK (0x40)
+#define INT_PRIORITY_P1_FQ_OFST (6)
+
+#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 ))
+#define INT_PRIORITY_P2_PRI_MSK (0x3F)
+#define INT_PRIORITY_P2_PRI_OFST (0)
+#define INT_PRIORITY_P2_FQ_MSK (0x40)
+#define INT_PRIORITY_P2_FQ_OFST (6)
+
+#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C ))
+#define INT_PRIORITY_P3_PRI_MSK (0x3F)
+#define INT_PRIORITY_P3_PRI_OFST (0)
+#define INT_PRIORITY_P3_FQ_MSK (0x40)
+#define INT_PRIORITY_P3_FQ_OFST (6)
+
+#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 ))
+#define INT_PRIORITY_P4_PRI_MSK (0x3F)
+#define INT_PRIORITY_P4_PRI_OFST (0)
+#define INT_PRIORITY_P4_FQ_MSK (0x40)
+#define INT_PRIORITY_P4_FQ_OFST (6)
+
+#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
+#define INT_PRIORITY_P5_PRI_MSK (0x3F)
+#define INT_PRIORITY_P5_PRI_OFST (0)
+#define INT_PRIORITY_P5_FQ_MSK (0x40)
+#define INT_PRIORITY_P5_FQ_OFST (6)
+
+#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
+#define INT_PRIORITY_IP_PRI_MSK (0x3F)
+#define INT_PRIORITY_IP_PRI_OFST (0)
+#define INT_PRIORITY_IP_FQ_MSK (0x40)
+#define INT_PRIORITY_IP_FQ_OFST (6)
+
+#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C ))
+#define INT_PRIORITY_UA_PRI_MSK (0x3F)
+#define INT_PRIORITY_UA_PRI_OFST (0)
+#define INT_PRIORITY_UA_FQ_MSK (0x40)
+#define INT_PRIORITY_UA_FQ_OFST (6)
+
+#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 ))
+#define INT_PRIORITY_T0_PRI_MSK (0x3F)
+#define INT_PRIORITY_T0_PRI_OFST (0)
+#define INT_PRIORITY_T0_FQ_MSK (0x40)
+#define INT_PRIORITY_T0_FQ_OFST (6)
+
+#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 ))
+#define INT_PRIORITY_T1_PRI_MSK (0x3F)
+#define INT_PRIORITY_T1_PRI_OFST (0)
+#define INT_PRIORITY_T1_FQ_MSK (0x40)
+#define INT_PRIORITY_T1_FQ_OFST (6)
+
+#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 ))
+#define INT_PRIORITY_PS_PRI_MSK (0x3F)
+#define INT_PRIORITY_PS_PRI_OFST (0)
+#define INT_PRIORITY_PS_FQ_MSK (0x40)
+#define INT_PRIORITY_PS_FQ_OFST (6)
+
+#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC ))
+#define INT_PRIORITY_EE_PRI_MSK (0x3F)
+#define INT_PRIORITY_EE_PRI_OFST (0)
+#define INT_PRIORITY_EE_FQ_MSK (0x40)
+#define INT_PRIORITY_EE_FQ_OFST (6)
+
+#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 ))
+#define INT_PRIORITY_PE_PRI_MSK (0x3F)
+#define INT_PRIORITY_PE_PRI_OFST (0)
+#define INT_PRIORITY_PE_FQ_MSK (0x40)
+#define INT_PRIORITY_PE_FQ_OFST (6)
+
+#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 ))
+#define INT_PRIORITY_AE_PRI_MSK (0x3F)
+#define INT_PRIORITY_AE_PRI_OFST (0)
+#define INT_PRIORITY_AE_FQ_MSK (0x40)
+#define INT_PRIORITY_AE_FQ_OFST (6)
+
+#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 ))
+#define INT_PRIORITY_M0_PRI_MSK (0x3F)
+#define INT_PRIORITY_M0_PRI_OFST (0)
+#define INT_PRIORITY_M0_FQ_MSK (0x40)
+#define INT_PRIORITY_M0_FQ_OFST (6)
+
+#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC ))
+#define INT_PRIORITY_M1_PRI_MSK (0x3F)
+#define INT_PRIORITY_M1_PRI_OFST (0)
+#define INT_PRIORITY_M1_FQ_MSK (0x40)
+#define INT_PRIORITY_M1_FQ_OFST (6)
+
+#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 ))
+#define INT_PRIORITY_FC_PRI_MSK (0x3F)
+#define INT_PRIORITY_FC_PRI_OFST (0)
+#define INT_PRIORITY_FC_FQ_MSK (0x40)
+#define INT_PRIORITY_FC_FQ_OFST (6)
+
+#endif /* __INT_CTRL00_H */
+
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/io.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+
+/*
+ * Generic virtual read/write
+ */
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
+/*#define outsw __arch_writesw
+#define outsl __arch_writesl
+#define outsb __arch_writesb
+#define insb __arch_readsb
+#define insw __arch_readsw
+#define insl __arch_readsl*/
+
+#define __io(a) (a)
+#if 0
+#define __mem_pci(a) ((unsigned long)(a))
+#define __mem_isa(a) (PCI_MEMORY_VADDR + (unsigned long)(a))
+/*
+ * Validate the pci memory address for ioremap.
+ */
+#define iomem_valid_addr(iomem,size) \
+ ((iomem) > 0 && (iomem) + (size) <= 0x20000000)
+
+/*
+ * Convert PCI memory space to a CPU physical address
+ */
+#define iomem_to_phys(iomem) ((iomem) + PHYS_PCI_MEM_BASE)
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10/irq.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define fixup_irq(i) (i)
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-camelot/irqs.h
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/* Use the Excalibur chip definitions */
+#define INT_CTRL00_TYPE
+#include "asm/arch/int_ctrl00.h"
+
+
+#define IRQ_PLD0 INT_MS_P0_OFST
+#define IRQ_PLD1 INT_MS_P1_OFST
+#define IRQ_PLD2 INT_MS_P2_OFST
+#define IRQ_PLD3 INT_MS_P3_OFST
+#define IRQ_PLD4 INT_MS_P4_OFST
+#define IRQ_PLD5 INT_MS_P5_OFST
+#define IRQ_EXT INT_MS_IP_OFST
+#define IRQ_UART INT_MS_UA_OFST
+#define IRQ_TIMER0 INT_MS_T0_OFST
+#define IRQ_TIMER1 INT_MS_T1_OFST
+#define IRQ_PLL INT_MS_PLL_OFST
+#define IRQ_EBI INT_MS_EBI_OFST
+#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST
+#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST
+#define IRQ_COMMRX INT_MS_CR_OFST
+#define IRQ_COMMTX INT_MS_CT_OFST
+#define IRQ_FAST_COMM INT_MS_FC_OFST
+
+#define NR_IRQS (INT_MS_FC_OFST + 1)
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10/memory.h
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE (0xc0000000UL)
+#define TASK_SIZE_26 (0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET (0xc0000000UL)
+#define PHYS_OFFSET (0x00000000UL)
+
+#define PHYS_TO_NID(addr) (0)
+
+/*
+ * On epxa10, the dram is contiguous
+ */
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
+
+#endif
--- /dev/null
+#ifndef __MODE_CTRL00_H
+#define __MODE_CTRL00_H
+
+/*
+ * Register definitions for the reset and mode control
+ */
+
+/*
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+
+#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR ))
+#define BOOT_CR_BF_MSK (0x1)
+#define BOOT_CR_BF_OFST (0)
+#define BOOT_CR_HM_MSK (0x2)
+#define BOOT_CR_HM_OFST (1)
+#define BOOT_CR_RE_MSK (0x4)
+#define BOOT_CR_RE_OFST (2)
+
+#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 ))
+#define RESET_SR_WR_MSK (0x1)
+#define RESET_SR_WR_OFST (0)
+#define RESET_SR_CR_MSK (0x2)
+#define RESET_SR_CR_OFST (1)
+#define RESET_SR_JT_MSK (0x4)
+#define RESET_SR_JT_OFST (2)
+#define RESET_SR_ER_MSK (0x8)
+#define RESET_SR_ER_OFST (3)
+
+#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 ))
+
+#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 ))
+#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM0_SR_SIZE_OFST (12)
+
+#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 ))
+#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 ))
+
+#define DPSRAM0_SR_MODE_MSK (0xF)
+#define DPSRAM0_SR_MODE_OFST (0)
+#define DPSRAM0_SR_GLBL_MSK (0x30)
+#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM0_SR_SIZE_OFST (12)
+
+#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 ))
+#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM0_LCR_LCKADDR_OFST (4)
+
+#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 ))
+#define DPSRAM1_SR_MODE_MSK (0xF)
+#define DPSRAM1_SR_MODE_OFST (0)
+#define DPSRAM1_SR_GLBL_MSK (0x30)
+#define DPSRAM1_SR_GLBL_OFST (4)
+#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C ))
+#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM1_LCR_LCKADDR_OFST (4)
+
+#endif /* __MODE_CTRL00_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/param.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define HZ 100
--- /dev/null
+#ifndef PLATFORM_H
+#define PLATFORM_H
+#include "excalibur.h"
+
+#define MAXIRQNUM 15
+#endif
+
--- /dev/null
+#ifndef __PLD_CONF00_H
+#define __PLD_CONF00_H
+
+/*
+ * Register definitions for the PLD Configuration Logic
+ */
+
+/*
+ *
+ * This file contains the register definitions for the Excalibur
+ * Interrupnt controller INT_CTRL00.
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))
+#define CONFIG_CONTROL_LK_MSK (0x1)
+#define CONFIG_CONTROL_LK_OFST (0)
+#define CONFIG_CONTROL_CO_MSK (0x2)
+#define CONFIG_CONTROL_CO_OFST (1)
+#define CONFIG_CONTROL_B_MSK (0x4)
+#define CONFIG_CONTROL_B_OFST (2)
+#define CONFIG_CONTROL_PC_MSK (0x8)
+#define CONFIG_CONTROL_PC_OFST (3)
+#define CONFIG_CONTROL_E_MSK (0x10)
+#define CONFIG_CONTROL_E_OFST (4)
+#define CONFIG_CONTROL_ES_MSK (0xE0)
+#define CONFIG_CONTROL_ES_OFST (5)
+#define CONFIG_CONTROL_ES_0_MSK (0x20)
+#define CONFIG_CONTROL_ES_1_MSK (0x40)
+#define CONFIG_CONTROL_ES_2_MSK (0x80)
+
+#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 ))
+#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
+#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
+
+#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 ))
+#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
+#define CONFIG_CONTROL_DATA_OFST (0)
+
+#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC ))
+#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
+#define CONFIG_UNLOCK_OFST (0)
+
+#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
+
+#endif /* __PLD_CONF00_H */
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/serial.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <asm/arch/platform.h>
+#include <asm/irq.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1 / 16)
+
+#define _SER_IRQ0 IRQ_UARTINT0
+#define _SER_IRQ1 IRQ_UARTINT1
+
+#define RS_TABLE_SIZE 2
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+ /* UART CLK PORT IRQ FLAGS */
+#define STD_SERIAL_PORT_DEFNS \
+ { 0, BASE_BAUD, 0x3F8, _SER_IRQ0, STD_COM_FLAGS }, /* ttyS0 */ \
+ { 0, BASE_BAUD, 0x2F8, _SER_IRQ1, STD_COM_FLAGS }, /* ttyS1 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/system.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/platform.h>
+
+static void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle(0);
+}
+
+extern __inline__ void arch_reset(char mode)
+{
+ /* Hmm... We can probably do something with the watchdog... */
+}
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/time.h
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/config.h>
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/arch/hardware.h>
+#define TIMER00_TYPE (volatile unsigned int*)
+#include <asm/arch/timer00.h>
+
+
+/*
+ * IRQ handler for the timer
+ */
+static void excalibur_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+
+ // ...clear the interrupt
+ *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK;
+
+ do_leds();
+ do_timer(regs);
+ do_profile(regs);
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+extern __inline__ void setup_timer(void)
+{
+
+
+ timer_irq.handler = excalibur_timer_interrupt;
+
+
+ /*
+ * Make irqs happen for the system timer
+ */
+ setup_arm_irq(IRQ_TIMER0, &timer_irq);
+
+ /* Start the timer */
+ *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/50);
+ *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1;
+ *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK;
+}
--- /dev/null
+/*
+ *
+ * This file contains the register definitions for the Excalibur
+ * Timer TIMER00.
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __TIMER00_H
+#define __TIMER00_H
+
+/*
+ * Register definitions for the timers
+ */
+
+
+#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
+#define TIMER0_CR_B_MSK (0x20)
+#define TIMER0_CR_B_OFST (0x5)
+#define TIMER0_CR_S_MSK (0x10)
+#define TIMER0_CR_S_OFST (0x4)
+#define TIMER0_CR_CI_MSK (0x08)
+#define TIMER0_CR_CI_OFST (0x3)
+#define TIMER0_CR_IE_MSK (0x04)
+#define TIMER0_CR_IE_OFST (0x2)
+#define TIMER0_CR_MODE_MSK (0x3)
+#define TIMER0_CR_MODE_OFST (0)
+#define TIMER0_CR_MODE_FREE (0)
+#define TIMER0_CR_MODE_ONE (1)
+#define TIMER0_CR_MODE_INTVL (2)
+
+#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
+#define TIMER0_SR_B_MSK (0x20)
+#define TIMER0_SR_B_OFST (0x5)
+#define TIMER0_SR_S_MSK (0x10)
+#define TIMER0_SR_S_OFST (0x4)
+#define TIMER0_SR_CI_MSK (0x08)
+#define TIMER0_SR_CI_OFST (0x3)
+#define TIMER0_SR_IE_MSK (0x04)
+#define TIMER0_SR_IE_OFST (0x2)
+#define TIMER0_SR_MODE_MSK (0x3)
+#define TIMER0_SR_MODE_OFST (0)
+#define TIMER0_SR_MODE_FREE (0)
+#define TIMER0_SR_MODE_ONE (1)
+#define TIMER0_SR_MODE_INTVL (2)
+
+#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 ))
+#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 ))
+#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 ))
+
+#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
+#define TIMER1_CR_B_MSK (0x20)
+#define TIMER1_CR_B_OFST (0x5)
+#define TIMER1_CR_S_MSK (0x10)
+#define TIMER1_CR_S_OFST (0x4)
+#define TIMER1_CR_CI_MSK (0x08)
+#define TIMER1_CR_CI_OFST (0x3)
+#define TIMER1_CR_IE_MSK (0x04)
+#define TIMER1_CR_IE_OFST (0x2)
+#define TIMER1_CR_MODE_MSK (0x3)
+#define TIMER1_CR_MODE_OFST (0)
+#define TIMER1_CR_MODE_FREE (0)
+#define TIMER1_CR_MODE_ONE (1)
+#define TIMER1_CR_MODE_INTVL (2)
+
+#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
+#define TIMER1_SR_B_MSK (0x20)
+#define TIMER1_SR_B_OFST (0x5)
+#define TIMER1_SR_S_MSK (0x10)
+#define TIMER1_SR_S_OFST (0x4)
+#define TIMER1_SR_CI_MSK (0x08)
+#define TIMER1_SR_CI_OFST (0x3)
+#define TIMER1_SR_IE_MSK (0x04)
+#define TIMER1_SR_IE_OFST (0x2)
+#define TIMER1_SR_MODE_MSK (0x3)
+#define TIMER1_SR_MODE_OFST (0)
+#define TIMER1_SR_MODE_FREE (0)
+#define TIMER1_SR_MODE_ONE (1)
+#define TIMER1_SR_MODE_INTVL (2)
+
+#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 ))
+#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 ))
+#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 ))
+
+#endif /* __TIMER00_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/timex.h
+ *
+ * Excalibur timex specifications
+ *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * ??
+ */
+#define CLOCK_TICK_RATE (50000000 / 16)
--- /dev/null
+/* *
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __UART00_H
+#define __UART00_H
+
+/*
+ * Register definitions for the UART
+ */
+
+#define UART_TX_FIFO_SIZE (15)
+
+#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 ))
+#define UART_RSR_RX_LEVEL_MSK (0x1f)
+#define UART_RSR_RX_LEVEL_OFST (0)
+#define UART_RSR_RE_MSK (0x80)
+#define UART_RSR_RE_OFST (7)
+
+#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 ))
+#define UART_RDS_BI_MSK (0x8)
+#define UART_RDS_BI_OFST (4)
+#define UART_RDS_FE_MSK (0x4)
+#define UART_RDS_FE_OFST (2)
+#define UART_RDS_PE_MSK (0x2)
+#define UART_RDS_PE_OFST (1)
+#define UART_RDS_OE_MSK (0x1)
+#define UART_RDS_OE_OFST (0)
+
+#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 ))
+#define UART_RD_RX_DATA_MSK (0xff)
+#define UART_RD_RX_DATA_OFST (0)
+
+#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c ))
+#define UART_TSR_TX_LEVEL_MSK (0x1f)
+#define UART_TSR_TX_LEVEL_OFST (0)
+#define UART_TSR_TXI_MSK (0x80)
+#define UART_TSR_TXI_OFST (7)
+
+#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 ))
+#define UART_TD_TX_DATA_MSK (0xff)
+#define UART_TD_TX_DATA_OFST (0)
+
+#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 ))
+#define UART_FCR_RX_THR_MSK (0xd0)
+#define UART_FCR_RX_THR_OFST (5)
+#define UART_FCR_RX_THR_1 (0x00)
+#define UART_FCR_RX_THR_2 (0x20)
+#define UART_FCR_RX_THR_4 (0x40)
+#define UART_FCR_RX_THR_6 (0x60)
+#define UART_FCR_RX_THR_8 (0x80)
+#define UART_FCR_RX_THR_10 (0xa0)
+#define UART_FCR_RX_THR_12 (0xc0)
+#define UART_FCR_RX_THR_14 (0xd0)
+#define UART_FCR_TX_THR_MSK (0x1c)
+#define UART_FCR_TX_THR_OFST (2)
+#define UART_FCR_TX_THR_0 (0x00)
+#define UART_FCR_TX_THR_2 (0x04)
+#define UART_FCR_TX_THR_4 (0x08)
+#define UART_FCR_TX_THR_8 (0x0c)
+#define UART_FCR_TX_THR_10 (0x10)
+#define UART_FCR_TX_THR_12 (0x14)
+#define UART_FCR_TX_THR_14 (0x18)
+#define UART_FCR_TX_THR_15 (0x1c)
+#define UART_FCR_RC_MSK (0x02)
+#define UART_FCR_RC_OFST (1)
+#define UART_FCR_TC_MSK (0x01)
+#define UART_FCR_TC_OFST (0)
+
+#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 ))
+#define UART_IES_ME_MSK (0x8)
+#define UART_IES_ME_OFST (3)
+#define UART_IES_TIE_MSK (0x4)
+#define UART_IES_TIE_OFST (2)
+#define UART_IES_TE_MSK (0x2)
+#define UART_IES_TE_OFST (1)
+#define UART_IES_RE_MSK (0x1)
+#define UART_IES_RE_OFST (0)
+
+#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c ))
+#define UART_IEC_ME_MSK (0x8)
+#define UART_IEC_ME_OFST (3)
+#define UART_IEC_TIE_MSK (0x4)
+#define UART_IEC_TIE_OFST (2)
+#define UART_IEC_TE_MSK (0x2)
+#define UART_IEC_TE_OFST (1)
+#define UART_IEC_RE_MSK (0x1)
+#define UART_IEC_RE_OFST (0)
+
+#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 ))
+#define UART_ISR_MI_MSK (0x8)
+#define UART_ISR_MI_OFST (3)
+#define UART_ISR_TII_MSK (0x4)
+#define UART_ISR_TII_OFST (2)
+#define UART_ISR_TI_MSK (0x2)
+#define UART_ISR_TI_OFST (1)
+#define UART_ISR_RI_MSK (0x1)
+#define UART_ISR_RI_OFST (0)
+
+#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 ))
+#define UART_IID_IID_MSK (0x7)
+#define UART_IID_IID_OFST (0)
+
+#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 ))
+#define UART_MC_OE_MSK (0x40)
+#define UART_MC_OE_OFST (6)
+#define UART_MC_SP_MSK (0x20)
+#define UART_MC_SP_OFST (5)
+#define UART_MC_EP_MSK (0x10)
+#define UART_MC_EP_OFST (4)
+#define UART_MC_PE_MSK (0x08)
+#define UART_MC_PE_OFST (3)
+#define UART_MC_ST_MSK (0x04)
+#define UART_MC_ST_ONE (0x0)
+#define UART_MC_ST_TWO (0x04)
+#define UART_MC_ST_OFST (2)
+#define UART_MC_CLS_MSK (0x03)
+#define UART_MC_CLS_OFST (0)
+#define UART_MC_CLS_CHARLEN_5 (0)
+#define UART_MC_CLS_CHARLEN_6 (1)
+#define UART_MC_CLS_CHARLEN_7 (2)
+#define UART_MC_CLS_CHARLEN_8 (3)
+
+#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c ))
+#define UART_MCR_AC_MSK (0x80)
+#define UART_MCR_AC_OFST (7)
+#define UART_MCR_AR_MSK (0x40)
+#define UART_MCR_AR_OFST (6)
+#define UART_MCR_BR_MSK (0x20)
+#define UART_MCR_BR_OFST (5)
+#define UART_MCR_LB_MSK (0x10)
+#define UART_MCR_LB_OFST (4)
+#define UART_MCR_DCD_MSK (0x08)
+#define UART_MCR_DCD_OFST (3)
+#define UART_MCR_RI_MSK (0x04)
+#define UART_MCR_RI_OFST (2)
+#define UART_MCR_DTR_MSK (0x02)
+#define UART_MCR_DTR_OFST (1)
+#define UART_MCR_RTS_MSK (0x01)
+#define UART_MCR_RTS_OFST (0)
+
+#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 ))
+#define UART_MSR_DCD_MSK (0x80)
+#define UART_MSR_DCD_OFST (7)
+#define UART_MSR_RI_MSK (0x40)
+#define UART_MSR_RI_OFST (6)
+#define UART_MSR_DSR_MSK (0x20)
+#define UART_MSR_DSR_OFST (5)
+#define UART_MSR_CTS_MSK (0x10)
+#define UART_MSR_CTS_OFST (4)
+#define UART_MSR_DDCD_MSK (0x08)
+#define UART_MSR_DDCD_OFST (3)
+#define UART_MSR_TERI_MSK (0x04)
+#define UART_MSR_TERI_OFST (2)
+#define UART_MSR_DDSR_MSK (0x02)
+#define UART_MSR_DDSR_OFST (1)
+#define UART_MSR_DCTS_MSK (0x01)
+#define UART_MSR_DCTS_OFST (0)
+
+#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 ))
+#define UART_DIV_LO_DIV_MSK (0xff)
+#define UART_DIV_LO_DIV_OFST (0)
+
+#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 ))
+#define UART_DIV_HI_DIV_MSK (0xff)
+#define UART_DIV_HI_DIV_OFST (0)
+
+#endif /* __UART00_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/uncompress.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include "asm/arch/platform.h"
+#include "asm/arch/hardware.h"
+#define UART00_TYPE (volatile unsigned int*)
+#include "asm/arch/uart00.h"
+
+/*
+ * This does not append a newline
+ */
+static void puts(const char *s)
+{
+ while (*s) {
+ while ((*UART_TSR(IO_ADDRESS(EXC_UART00_BASE)) & UART_TSR_TX_LEVEL_MSK)==15);
+
+ *UART_TD(IO_ADDRESS(EXC_UART00_BASE)) = *s;
+
+ if (*s == '\n') {
+ while ((*UART_TSR(IO_ADDRESS(EXC_UART00_BASE)) & UART_TSR_TX_LEVEL_MSK)==15);
+
+ *UART_TD(IO_ADDRESS(EXC_UART00_BASE)) = '\r';
+ }
+ s++;
+ }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-epxa10db/vmalloc.h
+ *
+ * Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
/*
* linux/include/asm-arm/arch-integrator/keyboard.h
*
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#define NR_SCANCODES 128
-extern unsigned char kmi_kbd_sysrq_xlate[NR_SCANCODES];
-
-extern int kmi_kbd_setkeycode(u_int scancode, u_int keycode);
-extern int kmi_kbd_getkeycode(u_int scancode);
-extern int kmi_kbd_translate(u_char scancode, u_char *keycode, char raw_mode);
-extern char kmi_kbd_unexpected_up(u_char keycode);
-extern void kmi_kbd_leds(u_char leds);
extern int kmi_kbd_init(void);
-#define kbd_setkeycode(sc,kc) kmi_kbd_setkeycode(sc,kc)
-#define kbd_getkeycode(sc) kmi_kbd_getkeycode(sc)
-
-#define kbd_translate(sc, kcp, rm) kmi_kbd_translate(sc,kcp,rm)
-#define kbd_unexpected_up(kc) kmi_kbd_unexpected_up(kc)
-#define kbd_leds(leds) kmi_kbd_leds(leds)
-#define kbd_init_hw() kmi_kbd_init()
-#define kbd_sysrq_xlate kmi_kbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KMIINT0)
-#define kbd_enable_irq() enable_irq(IRQ_KMIINT0)
-
-#define SYSRQ_KEY 0x54
+#define kbd_disable_irq() disable_irq(IRQ_KMIINT0)
+#define kbd_enable_irq() enable_irq(IRQ_KMIINT0)
+#define kbd_init_hw() kmi_kbd_init()
*/
#define HZ 128
+/*
+ * Define hz_to_std, since we have a non 100Hz define
+ * (see include/asm-arm/param.h)
+ */
+
+#if defined(__KERNEL__)
+#define hz_to_std(a) ((a * HZ)/100)
+#endif
+
#endif
*
* Driver definitions for PCI card dummy keyboard.
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* Copyright (C) 1998 Philip Blundell
*/
#define NR_SCANCODES 128
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-/* Prototype: int kbd_pretranslate(scancode, raw_mode)
- * Returns : 0 to ignore scancode
- */
-#define kbd_pretranslate(sc,rm) (1)
-
-/* Prototype: int kbd_translate(scancode, *keycode, *up_flag, raw_mode)
- * Returns : 0 to ignore scancode, *keycode set to keycode, *up_flag
- * set to 0200 if scancode indicates release
- */
-#define kbd_translate(sc, kcp, rm) 0
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) do { } while (0)
-#define kbd_init_hw() do { } while (0)
-#define kbd_disable_irq() do { } while (0)
-#define kbd_enable_irq() do { } while (0)
+#define kbd_init_hw() do { } while (0)
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
/*
* linux/include/asm-arm/arch-rpc/keyboard.h
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#define NR_SCANCODES 128
-extern void ps2kbd_leds(unsigned char leds);
-extern void ps2kbd_init_hw(void);
-extern unsigned char ps2kbd_sysrq_xlate[NR_SCANCODES];
+extern int ps2kbd_init_hw(void);
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) ps2kbd_leds(leds)
-#define kbd_init_hw() ps2kbd_init_hw()
-#define kbd_sysrq_xlate ps2kbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
-
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() ps2kbd_init_hw()
* architecture version 4). This file is based on the
* StrongARM SA-1100 data sheet version 2.2.
*
- * Language-specific definitions are selected by the
- * macro "LANGUAGE", which should be defined as either
- * "C" (default) or "Assembly".
*/
#error You must include hardware.h not SA-1100.h
#endif
-
-#ifndef LANGUAGE
-# ifdef __ASSEMBLY__
-# define LANGUAGE Assembly
-# else
-# define LANGUAGE C
-# endif
-#endif
-
-#ifndef io_p2v
-#define io_p2v(PhAdd) (PhAdd)
-#endif
-
-#include <asm/arch/bitfield.h>
-
-#define C 0
-#define Assembly 1
-
-
-#if LANGUAGE == C
-typedef unsigned short Word16 ;
-typedef unsigned int Word32 ;
-typedef Word32 Word ;
-typedef Word Quad [4] ;
-typedef void *Address ;
-typedef void (*ExcpHndlr) (void) ;
-#endif /* LANGUAGE == C */
-
-
-/*
- * Memory
- */
-
-#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
-
-#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
-#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
- /* [byte] */
-#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
- /* [byte] */
-#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
- /* [byte] */
-#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
- /* [byte] */
-
-#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
-#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
-#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
-#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
-#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
-
-#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
-
-#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
- (0x00000000 + (Nb)*StMemBnkSp)
-#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
-#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
-#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
-#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
-
-#if LANGUAGE == C
-typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
-#define StMemBnk /* Static Memory Bank [0..3] */ \
- ((StMemBnkType *) io_p2v (_StMemBnk (0)))
-#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
-#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
-#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
-#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
-#endif /* LANGUAGE == C */
-
-#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
- (0xC0000000 + (Nb)*DRAMBnkSp)
-#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
-#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
-#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
-#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
-
-#if LANGUAGE == C
-typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
-#define DRAMBnk /* DRAM Bank [0..3] */ \
- ((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
-#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
-#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
-#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
-#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
-#endif /* LANGUAGE == C */
-
-#define _ZeroMem 0xE0000000 /* Zero Memory bank */
-
-#if LANGUAGE == C
-typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
-#define ZeroMem /* Zero Memory bank */ \
- (*((ZeroMemType *) io_p2v (_ZeroMem)))
-#endif /* LANGUAGE == C */
+#include "bitfield.h"
/*
#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
-#if LANGUAGE == C
-
-typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
-typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
-
-#define PCMCIA0 /* PCMCIA 0 */ \
- (*((PCMCIAType *) io_p2v (_PCMCIA0)))
-#define PCMCIA0IO /* PCMCIA 0 I/O */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
-#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
-#define PCMCIA0Mem /* PCMCIA 0 Memory */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
-
-#define PCMCIA1 /* PCMCIA 1 */ \
- (*((PCMCIAType *) io_p2v (_PCMCIA1)))
-#define PCMCIA1IO /* PCMCIA 1 I/O */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
-#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
-#define PCMCIA1Mem /* PCMCIA 1 Memory */ \
- (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
-
-#endif /* LANGUAGE == C */
-
/*
* Universal Serial Bus (USB) Device Controller (UDC) control registers
* Controller (UDC) Status Register (read/write).
*/
-#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
-#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
-#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
- /* Packet size reg. */
-#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
- /* Packet size reg. */
-#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 0 */
-#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 1 (output) */
-#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 2 (input) */
-#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
- /* end-point 0 */
-#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
- /* reg. end-point 0 */
-#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
-#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
-
-#if LANGUAGE == C
-#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCCR)))
-#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCAR)))
-#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
- /* Packet size reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCOMP)))
-#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
- /* Packet size reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCIMP)))
-#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 0 */ \
- (*((volatile Word *) io_p2v (_Ser0UDCCS0)))
-#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 1 (output) */ \
- (*((volatile Word *) io_p2v (_Ser0UDCCS1)))
-#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 2 (input) */ \
- (*((volatile Word *) io_p2v (_Ser0UDCCS2)))
-#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
- /* end-point 0 */ \
- (*((volatile Word *) io_p2v (_Ser0UDCD0)))
-#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
- /* reg. end-point 0 */ \
- (*((volatile Word *) io_p2v (_Ser0UDCWC)))
-#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCDR)))
-#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
- (*((volatile Word *) io_p2v (_Ser0UDCSR)))
-#endif /* LANGUAGE == C */
+#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
+#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
+#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
+#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
+#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
+#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
+#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
+#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
+#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
+#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
+#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
#define UDCCR_UDD 0x00000001 /* UDC Disable */
#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
* fua, Tua Frequency, period of the UART communication.
*/
-#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
- (0x80010000 + ((Nb) - 1)*0x00020000)
-#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
- (0x80010004 + ((Nb) - 1)*0x00020000)
-#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
- (0x80010008 + ((Nb) - 1)*0x00020000)
-#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
- (0x8001000C + ((Nb) - 1)*0x00020000)
-#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
- (0x80010010 + ((Nb) - 1)*0x00020000)
-#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
- (0x80010014 + ((Nb) - 1)*0x00020000)
-#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
- (0x8001001C + ((Nb) - 1)*0x00020000)
-#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
- (0x80010020 + ((Nb) - 1)*0x00020000)
-
-#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
-#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
-#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
-#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
-#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
-#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
-#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
-
-#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
-#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
-#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
-#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
-#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
-#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
-#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
-#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
-
-#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
-#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
-#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
-#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
-#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
-#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
-#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
-
-/*
- * Register offsets
- */
+#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
+#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
+#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
+#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
+#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
+#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
+#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
+#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
+
+#define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
+#define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
+#define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
+#define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
+#define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
+#define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
+#define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
+
+#define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
+#define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
+#define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
+#define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
+#define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
+#define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
+#define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
+#define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
+
+#define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
+#define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
+#define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
+#define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
+#define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
+#define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
+#define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
+
+/* Those are still used in some places */
+#define _Ser1UTCR0 __PREG(Ser1UTCR0)
+#define _Ser2UTCR0 __PREG(Ser2UTCR0)
+#define _Ser3UTCR0 __PREG(Ser3UTCR0)
+
+/* Register offsets */
#define UTCR0 0x00
#define UTCR1 0x04
#define UTCR2 0x08
#define UTSR0 0x1c
#define UTSR1 0x20
-#if LANGUAGE == C
-
-#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser1UTCR0)))
-#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser1UTCR1)))
-#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_Ser1UTCR2)))
-#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
- (*((volatile Word *) io_p2v (_Ser1UTCR3)))
-#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser1UTDR)))
-#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser1UTSR0)))
-#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser1UTSR1)))
-
-#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser2UTCR0)))
-#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser2UTCR1)))
-#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_Ser2UTCR2)))
-#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
- (*((volatile Word *) io_p2v (_Ser2UTCR3)))
-#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
- (*((volatile Word *) io_p2v (_Ser2UTCR4)))
-#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser2UTDR)))
-#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser2UTSR0)))
-#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser2UTSR1)))
-
-#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser3UTCR0)))
-#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser3UTCR1)))
-#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_Ser3UTCR2)))
-#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
- (*((volatile Word *) io_p2v (_Ser3UTCR3)))
-#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser3UTDR)))
-#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser3UTSR0)))
-#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser3UTSR1)))
-
-#elif LANGUAGE == Assembly
-#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0))
-#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1))
-#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2))
-#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3))
-#define Ser1UTDR ( io_p2v (_Ser1UTDR))
-#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0))
-#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1))
-
-#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0))
-#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1))
-#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2))
-#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3))
-#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4))
-#define Ser2UTDR ( io_p2v (_Ser2UTDR))
-#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0))
-#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1))
-
-#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0))
-#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1))
-#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2))
-#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3))
-#define Ser3UTDR ( io_p2v (_Ser3UTDR))
-#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0))
-#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1))
-
-#endif /* LANGUAGE == C */
-
#define UTCR0_PE 0x00000001 /* Parity Enable */
#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
* fsd, Tsd Frequency, period of the SDLC communication.
*/
-#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
-#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
-#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
-#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
-#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
-#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
-#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
-#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
-
-#if LANGUAGE == C
-#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser1SDCR0)))
-#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser1SDCR1)))
-#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_Ser1SDCR2)))
-#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
- (*((volatile Word *) io_p2v (_Ser1SDCR3)))
-#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
- (*((volatile Word *) io_p2v (_Ser1SDCR4)))
-#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser1SDDR)))
-#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser1SDSR0)))
-#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser1SDSR1)))
-#endif /* LANGUAGE == C */
+#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
+#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
+#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
+#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
+#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
+#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
+#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
+#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
* SA-1100.]
*/
-#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
-#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
-#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
-#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
-#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
-#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
-
-#if LANGUAGE == C
-#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser2HSCR0)))
-#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser2HSCR1)))
-#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser2HSDR)))
-#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser2HSSR0)))
-#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser2HSSR1)))
-#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_Ser2HSCR2)))
-#endif /* LANGUAGE == C */
+#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
+#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
+#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
+#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
+#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
+#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
* ftcm, Ttcm Frequency, period of the telecom sampling.
*/
-#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
-#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
- /* (audio) */
-#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
- /* (telecom) */
-#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
- /* (CODEC reg.) */
-#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
-#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
-
-#if LANGUAGE == C
-#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser4MCCR0)))
-#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
- /* (audio) */ \
- (*((volatile Word *) io_p2v (_Ser4MCDR0)))
-#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
- /* (telecom) */ \
- (*((volatile Word *) io_p2v (_Ser4MCDR1)))
-#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
- /* (CODEC reg.) */ \
- (*((volatile Word *) io_p2v (_Ser4MCDR2)))
-#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
- (*((volatile Word *) io_p2v (_Ser4MCSR)))
-#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser4MCCR1)))
-#endif /* LANGUAGE == C */
+#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
+#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
+#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
+#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
+#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
+#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
/* [6..127] */
* fss, Tss Frequency, period of the SSP communication.
*/
-#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
-#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
-#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
-#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
-
-#if LANGUAGE == C
-#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_Ser4SSCR0)))
-#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_Ser4SSCR1)))
-#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
- (*((volatile Word *) io_p2v (_Ser4SSDR)))
-#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
- (*((volatile Word *) io_p2v (_Ser4SSSR)))
-#endif /* LANGUAGE == C */
+#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
+#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
+#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
+#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
* (read/write).
*/
-#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
- (0x90000000 + (Nb)*4)
-#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
-#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
-#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
-#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
-#define _OSCR 0x90000010 /* OS timer Counter Reg. */
-#define _OSSR 0x90000014 /* OS timer Status Reg. */
-#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
-#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
-
-#if LANGUAGE == C
-#define OSMR /* OS timer Match Reg. [0..3] */ \
- ((volatile Word *) io_p2v (_OSMR (0)))
-#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
-#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
-#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
-#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
-#define OSCR /* OS timer Counter Reg. */ \
- (*((volatile Word *) io_p2v (_OSCR)))
-#define OSSR /* OS timer Status Reg. */ \
- (*((volatile Word *) io_p2v (_OSSR)))
-#define OWER /* OS timer Watch-dog Enable Reg. */ \
- (*((volatile Word *) io_p2v (_OWER)))
-#define OIER /* OS timer Interrupt Enable Reg. */ \
- (*((volatile Word *) io_p2v (_OIER)))
-#endif /* LANGUAGE == C */
+#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
+#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
+#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
+#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
+#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
+#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
+#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
+#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
#define OSSR_M(Nb) /* Match detected [0..3] */ \
(0x00000001 << (Nb))
* (1 Hz nominal).
*/
-#define _RTAR 0x90010000 /* RTC Alarm Reg. */
-#define _RCNR 0x90010004 /* RTC CouNt Reg. */
-#define _RTTR 0x90010008 /* RTC Trim Reg. */
-#define _RTSR 0x90010010 /* RTC Status Reg. */
-
-#if LANGUAGE == C
-#define RTAR /* RTC Alarm Reg. */ \
- (*((volatile Word *) io_p2v (_RTAR)))
-#define RCNR /* RTC CouNt Reg. */ \
- (*((volatile Word *) io_p2v (_RCNR)))
-#define RTTR /* RTC Trim Reg. */ \
- (*((volatile Word *) io_p2v (_RTTR)))
-#define RTSR /* RTC Status Reg. */ \
- (*((volatile Word *) io_p2v (_RTSR)))
-#endif /* LANGUAGE == C */
+#define RTAR __REG(0x90010000) /* RTC Alarm Reg. */
+#define RCNR __REG(0x90010004) /* RTC CouNt Reg. */
+#define RTTR __REG(0x90010008) /* RTC Trim Reg. */
+#define RTSR __REG(0x90010010) /* RTC Status Reg. */
#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
#define RTTR_D Fld (10, 16) /* trim Delete count */
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
-#define _PMCR 0x90020000 /* PM Control Reg. */
-#define _PSSR 0x90020004 /* PM Sleep Status Reg. */
-#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
-#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
-#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
-#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
-#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
-#define _POSR 0x9002001C /* PM Oscillator Status Reg. */
-
-#if LANGUAGE == C
-#define PMCR /* PM Control Reg. */ \
- (*((volatile Word *) io_p2v (_PMCR)))
-#define PSSR /* PM Sleep Status Reg. */ \
- (*((volatile Word *) io_p2v (_PSSR)))
-#define PSPR /* PM Scratch-Pad Reg. */ \
- (*((volatile Word *) io_p2v (_PSPR)))
-#define PWER /* PM Wake-up Enable Reg. */ \
- (*((volatile Word *) io_p2v (_PWER)))
-#define PCFR /* PM general ConFiguration Reg. */ \
- (*((volatile Word *) io_p2v (_PCFR)))
-#define PPCR /* PM PLL Configuration Reg. */ \
- (*((volatile Word *) io_p2v (_PPCR)))
-#define PGSR /* PM GPIO Sleep state Reg. */ \
- (*((volatile Word *) io_p2v (_PGSR)))
-#define POSR /* PM Oscillator Status Reg. */ \
- (*((volatile Word *) io_p2v (_POSR)))
-
-#elif LANGUAGE == Assembly
-#define PMCR (io_p2v (_PMCR))
-#define PSSR (io_p2v (_PSSR))
-#define PSPR (io_p2v (_PSPR))
-#define PWER (io_p2v (_PWER))
-#define PCFR (io_p2v (_PCFR))
-#define PPCR (io_p2v (_PPCR))
-#define PGSR (io_p2v (_PGSR))
-#define POSR (io_p2v (_POSR))
-
-#endif /* LANGUAGE == C */
+#define PMCR __REG(0x90020000) /* PM Control Reg. */
+#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
+#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
+#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
+#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
+#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
+#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
+#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
* RCSR Reset Controller (RC) Status Register (read/write).
*/
-#define _RSRR 0x90030000 /* RC Software Reset Reg. */
-#define _RCSR 0x90030004 /* RC Status Reg. */
-
-#if LANGUAGE == C
-#define RSRR /* RC Software Reset Reg. */ \
- (*((volatile Word *) io_p2v (_RSRR)))
-#define RCSR /* RC Status Reg. */ \
- (*((volatile Word *) io_p2v (_RCSR)))
-#endif /* LANGUAGE == C */
+#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
+#define RCSR __REG(0x90030004) /* RC Status Reg. */
#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
* TUCR Test Unit Control Register (read/write).
*/
-#define _TUCR 0x90030008 /* Test Unit Control Reg. */
-
-#if LANGUAGE == C
-#define TUCR /* Test Unit Control Reg. */ \
- (*((volatile Word *) io_p2v (_TUCR)))
-#endif /* LANGUAGE == C */
+#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
#define TUCR_TIC 0x00000040 /* TIC mode */
#define TUCR_TTST 0x00000080 /* Trim TeST mode */
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
-#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
-#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
-#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
-#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
-#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
-#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
-#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
-#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
-
-#if LANGUAGE == C
-#define GPLR /* GPIO Pin Level Reg. */ \
- (*((volatile Word *) io_p2v (_GPLR)))
-#define GPDR /* GPIO Pin Direction Reg. */ \
- (*((volatile Word *) io_p2v (_GPDR)))
-#define GPSR /* GPIO Pin output Set Reg. */ \
- (*((volatile Word *) io_p2v (_GPSR)))
-#define GPCR /* GPIO Pin output Clear Reg. */ \
- (*((volatile Word *) io_p2v (_GPCR)))
-#define GRER /* GPIO Rising-Edge detect Reg. */ \
- (*((volatile Word *) io_p2v (_GRER)))
-#define GFER /* GPIO Falling-Edge detect Reg. */ \
- (*((volatile Word *) io_p2v (_GFER)))
-#define GEDR /* GPIO Edge Detect status Reg. */ \
- (*((volatile Word *) io_p2v (_GEDR)))
-#define GAFR /* GPIO Alternate Function Reg. */ \
- (*((volatile Word *) io_p2v (_GAFR)))
-#elif LANGUAGE == Assembly
-
-#define GPLR (io_p2v (_GPLR))
-#define GPDR (io_p2v (_GPDR))
-#define GPSR (io_p2v (_GPSR))
-#define GPCR (io_p2v (_GPCR))
-#define GRER (io_p2v (_GRER))
-#define GFER (io_p2v (_GFER))
-#define GEDR (io_p2v (_GEDR))
-#define GAFR (io_p2v (_GAFR))
-
-#endif /* LANGUAGE == C */
+#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
+#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
+#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
+#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
+#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
+#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
+#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
+#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
#define GPIO_MIN (0)
#define GPIO_MAX (27)
* versions 2.0 (rev. = 8) and higher.]
*/
-#define _ICIP 0x90050000 /* IC IRQ Pending reg. */
-#define _ICMR 0x90050004 /* IC Mask Reg. */
-#define _ICLR 0x90050008 /* IC Level Reg. */
-#define _ICCR 0x9005000C /* IC Control Reg. */
-#define _ICFP 0x90050010 /* IC FIQ Pending reg. */
-#define _ICPR 0x90050020 /* IC Pending Reg. */
-
-#if LANGUAGE == C
-#define ICIP /* IC IRQ Pending reg. */ \
- (*((volatile Word *) io_p2v (_ICIP)))
-#define ICMR /* IC Mask Reg. */ \
- (*((volatile Word *) io_p2v (_ICMR)))
-#define ICLR /* IC Level Reg. */ \
- (*((volatile Word *) io_p2v (_ICLR)))
-#define ICCR /* IC Control Reg. */ \
- (*((volatile Word *) io_p2v (_ICCR)))
-#define ICFP /* IC FIQ Pending reg. */ \
- (*((volatile Word *) io_p2v (_ICFP)))
-#define ICPR /* IC Pending Reg. */ \
- (*((volatile Word *) io_p2v (_ICPR)))
-#endif /* LANGUAGE == C */
+#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
+#define ICMR __REG(0x90050004) /* IC Mask Reg. */
+#define ICLR __REG(0x90050008) /* IC Level Reg. */
+#define ICCR __REG(0x9005000C) /* IC Control Reg. */
+#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
+#define ICPR __REG(0x90050020) /* IC Pending Reg. */
#define IC_GPIO(Nb) /* GPIO [0..10] */ \
(0x00000001 << (Nb))
* (read).
*/
-#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
-#define _PPSR 0x90060004 /* PPC Pin State Reg. */
-#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
-#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
- /* Reg. */
-#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
-
-#if LANGUAGE == C
-#define PPDR /* PPC Pin Direction Reg. */ \
- (*((volatile Word *) io_p2v (_PPDR)))
-#define PPSR /* PPC Pin State Reg. */ \
- (*((volatile Word *) io_p2v (_PPSR)))
-#define PPAR /* PPC Pin Assignment Reg. */ \
- (*((volatile Word *) io_p2v (_PPAR)))
-#define PSDR /* PPC Sleep-mode pin Direction */ \
- /* Reg. */ \
- (*((volatile Word *) io_p2v (_PSDR)))
-#define PPFR /* PPC Pin Flag Reg. */ \
- (*((volatile Word *) io_p2v (_PPFR)))
-#endif /* LANGUAGE == C */
+#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
+#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
+#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
+#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
+#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
(0x00000001 << (Nb))
* fcas, Tcas Frequency, period of the DRAM CAS shift registers.
*/
- /* Memory system: */
-#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
-#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
- (0xA0000004 + (Nb)*4)
-#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
-#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
-#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
-
-#if LANGUAGE == C
- /* Memory system: */
-#define MDCNFG /* DRAM CoNFiGuration reg. */ \
- (*((volatile Word *) io_p2v (_MDCNFG)))
-#define MDCAS /* DRAM CAS shift reg. [0..3] */ \
- ((volatile Word *) io_p2v (_MDCAS (0)))
-#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
-#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
-#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
-
-#elif LANGUAGE == Assembly
-
-#define MDCNFG (io_p2v(_MDCNFG))
-
-#endif /* LANGUAGE == C */
+#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
+#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
+#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
+#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
/* SA1100 MDCNFG values */
#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
*/
- /* Memory system: */
-#define _MSC(Nb) /* Static memory Control reg. */ \
- /* [0..1] */ \
- (0xA0000010 + (Nb)*4)
-#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
-#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
-#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
-
-#if LANGUAGE == C
- /* Memory system: */
-#define MSC /* Static memory Control reg. */ \
- /* [0..1] */ \
- ((volatile Word *) io_p2v (_MSC (0)))
-#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
-#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
-#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
-
-#elif LANGUAGE == Assembly
-
-#define MSC0 io_p2v(0xa0000010)
-#define MSC1 io_p2v(0xa0000014)
-#define MSC2 io_p2v(0xa000002c)
-
-#endif /* LANGUAGE == C */
+#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
+#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
+#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
Fld (16, ((Nb) Modulo 2)*16)
*/
/* Memory system: */
-#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
- /* Configuration Reg. */
-
-#if LANGUAGE == C
- /* Memory system: */
-#define MECR /* Expansion memory bus (PCMCIA) */ \
- /* Configuration Reg. */ \
- (*((volatile Word *) io_p2v (_MECR)))
-#endif /* LANGUAGE == C */
+#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
Fld (15, (Nb)*16)
* On SA1110 only
*/
-#define _MDREFR 0xA000001C
-
-#if LANGUAGE == C
- /* Memory system: */
-#define MDREFR \
- (*((volatile Word *) io_p2v (_MDREFR)))
-
-#elif LANGUAGE == Assembly
-
-#define MDREFR (io_p2v(_MDREFR))
-
-#endif /* LANGUAGE == C */
+#define MDREFR __REG(0xA000001C)
#define MDREFR_TRASR Fld (4, 0)
#define MDREFR_DRI Fld (12, 4)
#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
-#define _DDAR(Nb) /* DMA Device Address Reg. */ \
- /* channel [0..5] */ \
- (0xB0000000 + (Nb)*DMASp)
-#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
- /* channel [0..5] (write) */ \
- (0xB0000004 + (Nb)*DMASp)
-#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
- /* channel [0..5] (write) */ \
- (0xB0000008 + (Nb)*DMASp)
-#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
- /* channel [0..5] (read) */ \
- (0xB000000C + (Nb)*DMASp)
-#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
- /* channel [0..5] */ \
- (0xB0000010 + (Nb)*DMASp)
-#define _DBTA(Nb) /* DMA Buffer Transfer count */ \
- /* reg. A channel [0..5] */ \
- (0xB0000014 + (Nb)*DMASp)
-#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
- /* channel [0..5] */ \
- (0xB0000018 + (Nb)*DMASp)
-#define _DBTB(Nb) /* DMA Buffer Transfer count */ \
- /* reg. B channel [0..5] */ \
- (0xB000001C + (Nb)*DMASp)
-
-#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
- /* channel 0 */
-#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
- /* channel 0 (write) */
-#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
- /* channel 0 (write) */
-#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
- /* channel 0 (read) */
-#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
- /* channel 0 */
-#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
- /* reg. A channel 0 */
-#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
- /* channel 0 */
-#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
- /* reg. B channel 0 */
-
-#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
- /* channel 1 */
-#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
- /* channel 1 (write) */
-#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
- /* channel 1 (write) */
-#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
- /* channel 1 (read) */
-#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
- /* channel 1 */
-#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
- /* reg. A channel 1 */
-#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
- /* channel 1 */
-#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
- /* reg. B channel 1 */
-
-#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
- /* channel 2 */
-#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
- /* channel 2 (write) */
-#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
- /* channel 2 (write) */
-#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
- /* channel 2 (read) */
-#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
- /* channel 2 */
-#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
- /* reg. A channel 2 */
-#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
- /* channel 2 */
-#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
- /* reg. B channel 2 */
-
-#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
- /* channel 3 */
-#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
- /* channel 3 (write) */
-#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
- /* channel 3 (write) */
-#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
- /* channel 3 (read) */
-#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
- /* channel 3 */
-#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
- /* reg. A channel 3 */
-#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
- /* channel 3 */
-#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
- /* reg. B channel 3 */
-
-#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
- /* channel 4 */
-#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
- /* channel 4 (write) */
-#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
- /* channel 4 (write) */
-#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
- /* channel 4 (read) */
-#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
- /* channel 4 */
-#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
- /* reg. A channel 4 */
-#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
- /* channel 4 */
-#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
- /* reg. B channel 4 */
-
-#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
- /* channel 5 */
-#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
- /* channel 5 (write) */
-#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
- /* channel 5 (write) */
-#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
- /* channel 5 (read) */
-#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
- /* channel 5 */
-#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
- /* reg. A channel 5 */
-#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
- /* channel 5 */
-#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
- /* reg. B channel 5 */
-
-#if LANGUAGE == C
-
-#define DDAR0 /* DMA Device Address Reg. */ \
- /* channel 0 */ \
- (*((volatile Word *) io_p2v (_DDAR0)))
-#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR0)))
-#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR0)))
-#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
- /* channel 0 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR0)))
-#define DBSA0 /* DMA Buffer Start address reg. A */ \
- /* channel 0 */ \
- (*((volatile Address *) io_p2v (_DBSA0)))
-#define DBTA0 /* DMA Buffer Transfer count */ \
- /* reg. A channel 0 */ \
- (*((volatile Word *) io_p2v (_DBTA0)))
-#define DBSB0 /* DMA Buffer Start address reg. B */ \
- /* channel 0 */ \
- (*((volatile Address *) io_p2v (_DBSB0)))
-#define DBTB0 /* DMA Buffer Transfer count */ \
- /* reg. B channel 0 */ \
- (*((volatile Word *) io_p2v (_DBTB0)))
-
-#define DDAR1 /* DMA Device Address Reg. */ \
- /* channel 1 */ \
- (*((volatile Word *) io_p2v (_DDAR1)))
-#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR1)))
-#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR1)))
-#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
- /* channel 1 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR1)))
-#define DBSA1 /* DMA Buffer Start address reg. A */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DBSA1)))
-#define DBTA1 /* DMA Buffer Transfer count */ \
- /* reg. A channel 1 */ \
- (*((volatile Word *) io_p2v (_DBTA1)))
-#define DBSB1 /* DMA Buffer Start address reg. B */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DBSB1)))
-#define DBTB1 /* DMA Buffer Transfer count */ \
- /* reg. B channel 1 */ \
- (*((volatile Word *) io_p2v (_DBTB1)))
-
-#define DDAR2 /* DMA Device Address Reg. */ \
- /* channel 2 */ \
- (*((volatile Word *) io_p2v (_DDAR2)))
-#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR2)))
-#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR2)))
-#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
- /* channel 2 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR2)))
-#define DBSA2 /* DMA Buffer Start address reg. A */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DBSA2)))
-#define DBTA2 /* DMA Buffer Transfer count */ \
- /* reg. A channel 2 */ \
- (*((volatile Word *) io_p2v (_DBTA2)))
-#define DBSB2 /* DMA Buffer Start address reg. B */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DBSB2)))
-#define DBTB2 /* DMA Buffer Transfer count */ \
- /* reg. B channel 2 */ \
- (*((volatile Word *) io_p2v (_DBTB2)))
-
-#define DDAR3 /* DMA Device Address Reg. */ \
- /* channel 3 */ \
- (*((volatile Word *) io_p2v (_DDAR3)))
-#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR3)))
-#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR3)))
-#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
- /* channel 3 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR3)))
-#define DBSA3 /* DMA Buffer Start address reg. A */ \
- /* channel 3 */ \
- (*((volatile Address *) io_p2v (_DBSA3)))
-#define DBTA3 /* DMA Buffer Transfer count */ \
- /* reg. A channel 3 */ \
- (*((volatile Word *) io_p2v (_DBTA3)))
-#define DBSB3 /* DMA Buffer Start address reg. B */ \
- /* channel 3 */ \
- (*((volatile Address *) io_p2v (_DBSB3)))
-#define DBTB3 /* DMA Buffer Transfer count */ \
- /* reg. B channel 3 */ \
- (*((volatile Word *) io_p2v (_DBTB3)))
-
-#define DDAR4 /* DMA Device Address Reg. */ \
- /* channel 4 */ \
- (*((volatile Word *) io_p2v (_DDAR4)))
-#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR4)))
-#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR4)))
-#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
- /* channel 4 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR4)))
-#define DBSA4 /* DMA Buffer Start address reg. A */ \
- /* channel 4 */ \
- (*((volatile Address *) io_p2v (_DBSA4)))
-#define DBTA4 /* DMA Buffer Transfer count */ \
- /* reg. A channel 4 */ \
- (*((volatile Word *) io_p2v (_DBTA4)))
-#define DBSB4 /* DMA Buffer Start address reg. B */ \
- /* channel 4 */ \
- (*((volatile Address *) io_p2v (_DBSB4)))
-#define DBTB4 /* DMA Buffer Transfer count */ \
- /* reg. B channel 4 */ \
- (*((volatile Word *) io_p2v (_DBTB4)))
-
-#define DDAR5 /* DMA Device Address Reg. */ \
- /* channel 5 */ \
- (*((volatile Word *) io_p2v (_DDAR5)))
-#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR5)))
-#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR5)))
-#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
- /* channel 5 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR5)))
-#define DBSA5 /* DMA Buffer Start address reg. A */ \
- /* channel 5 */ \
- (*((volatile Address *) io_p2v (_DBSA5)))
-#define DBTA5 /* DMA Buffer Transfer count */ \
- /* reg. A channel 5 */ \
- (*((volatile Word *) io_p2v (_DBTA5)))
-#define DBSB5 /* DMA Buffer Start address reg. B */ \
- /* channel 5 */ \
- (*((volatile Address *) io_p2v (_DBSB5)))
-#define DBTB5 /* DMA Buffer Transfer count */ \
- /* reg. B channel 5 */ \
- (*((volatile Word *) io_p2v (_DBTB5)))
-
-#endif /* LANGUAGE == C */
+#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
+#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
+#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
+#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
+#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
+#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
+#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
+#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
#define DDAR_RW 0x00000001 /* device data Read/Write */
#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
(((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
+ DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
+ DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
+ DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
+ DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
+ DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
+ DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
+ DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
+ DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
+ DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
+ DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
+ DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
+ DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
+ DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
+ DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
/* (telecom) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
+ DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
/* (telecom) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
+ DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
+ DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
+ DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
#define DCSR_RUN 0x00000001 /* DMA RUNing */
#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
/* (Alternative) */
-#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
-#define _LCSR 0xB0100004 /* LCD Status Reg. */
-#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
- /* channel 1 */
-#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
- /* channel 1 */
-#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
- /* channel 2 */
-#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
- /* channel 2 */
-#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
-#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
-#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
-
-#if LANGUAGE == C
-#define LCCR0 /* LCD Control Reg. 0 */ \
- (*((volatile Word *) io_p2v (_LCCR0)))
-#define LCSR /* LCD Status Reg. */ \
- (*((volatile Word *) io_p2v (_LCSR)))
-#define DBAR1 /* LCD DMA Base Address Reg. */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DBAR1)))
-#define DCAR1 /* LCD DMA Current Address Reg. */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DCAR1)))
-#define DBAR2 /* LCD DMA Base Address Reg. */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DBAR2)))
-#define DCAR2 /* LCD DMA Current Address Reg. */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DCAR2)))
-#define LCCR1 /* LCD Control Reg. 1 */ \
- (*((volatile Word *) io_p2v (_LCCR1)))
-#define LCCR2 /* LCD Control Reg. 2 */ \
- (*((volatile Word *) io_p2v (_LCCR2)))
-#define LCCR3 /* LCD Control Reg. 3 */ \
- (*((volatile Word *) io_p2v (_LCCR3)))
-#endif /* LANGUAGE == C */
+#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
+#define LCSR __REG(0xB0100004) /* LCD Status Reg. */
+#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
+#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
+#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
+#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
+#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
+#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
+#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
#define LCCR0_LEN 0x00000001 /* LCD ENable */
#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
+#ifndef __ASSEMBLY__
+extern unsigned int processor_id;
+#endif
-#undef C
-#undef Assembly
-
+#define CPU_REVISION (processor_id & 15)
+#define CPU_SA1110_A0 (0)
+#define CPU_SA1110_B0 (4)
+#define CPU_SA1110_B1 (5)
+#define CPU_SA1110_B2 (6)
+#define CPU_SA1110_B4 (8)
+
+#define CPU_SA1100_ID (0x4401a110)
+#define CPU_SA1100_MASK (0xfffffff0)
+#define CPU_SA1110_ID (0x6901b110)
+#define CPU_SA1110_MASK (0xfffffff0)
#define SA1111_SAC_DMA_MIN_XFER (0x800)
+/*
+ * SA1111 register definitions.
+ */
+#define __CCREG(x) __REGP(SA1111_VBASE + (x))
+
/* System Bus Interface (SBI)
*
* Registers
* SKID ID Register
*/
-#define _SBI_SKCR _SA1111( 0x0000 )
-#define _SBI_SMCR _SA1111( 0x0004 )
-#define _SBI_SKID _SA1111( 0x0008 )
+#define _SBI_SKCR _SA1111(0x0000)
+#define _SBI_SMCR _SA1111(0x0004)
+#define _SBI_SKID _SA1111(0x0008)
#if LANGUAGE == C
-#define SBI_SKCR (*((volatile Word *) SA1111_p2v (_SBI_SKCR)))
-#define SBI_SMCR (*((volatile Word *) SA1111_p2v (_SBI_SMCR)))
-#define SBI_SKID (*((volatile Word *) SA1111_p2v (_SBI_SKID)))
+#define SBI_SKCR __CCREG(0x0000)
+#define SBI_SMCR __CCREG(0x0004)
+#define SBI_SKID __CCREG(0x0008)
#endif /* LANGUAGE == C */
#if LANGUAGE == C
-#define SKPCR (*((volatile Word *) SA1111_p2v (_SKPCR)))
-#define SKCDR (*((volatile Word *) SA1111_p2v (_SKCDR)))
-#define SKAUD (*((volatile Word *) SA1111_p2v (_SKAUD)))
-#define SKPMC (*((volatile Word *) SA1111_p2v (_SKPMC)))
-#define SKPTC (*((volatile Word *) SA1111_p2v (_SKPTC)))
-#define SKPEN0 (*((volatile Word *) SA1111_p2v (_SKPEN0)))
-#define SKPWM0 (*((volatile Word *) SA1111_p2v (_SKPWM0)))
-#define SKPEN1 (*((volatile Word *) SA1111_p2v (_SKPEN1)))
-#define SKPWM1 (*((volatile Word *) SA1111_p2v (_SKPWM1)))
+#define SKPCR __CCREG(0x0200)
+#define SKCDR __CCREG(0x0204)
+#define SKAUD __CCREG(0x0208)
+#define SKPMC __CCREG(0x020c)
+#define SKPTC __CCREG(0x0210)
+#define SKPEN0 __CCREG(0x0214)
+#define SKPWM0 __CCREG(0x0218)
+#define SKPEN1 __CCREG(0x021c)
+#define SKPWM1 __CCREG(0x0220)
#endif /* LANGUAGE == C */
#if LANGUAGE == C
-#define USB_OHCI_OP_BASE (*((volatile Word *) SA1111_p2v (_USB_OHCI_OP_BASE)))
-#define USB_STATUS (*((volatile Word *) SA1111_p2v (_USB_STATUS)))
-#define USB_RESET (*((volatile Word *) SA1111_p2v (_USB_RESET)))
-#define USB_INTERRUPTEST (*((volatile Word *) SA1111_p2v (_USB_INTERRUPTEST)))
+#define USB_OHCI_OP_BASE __CCREG(0x0400)
+#define USB_STATUS __CCREG(0x0518)
+#define USB_RESET __CCREG(0x051c)
+#define USB_INTERRUPTEST __CCReG(0x0520)
#endif /* LANGUAGE == C */
#if LANGUAGE == C
-#define SACR0 (*((volatile Word *) SA1111_p2v (_SACR0)))
-#define SACR1 (*((volatile Word *) SA1111_p2v (_SACR1)))
-#define SACR2 (*((volatile Word *) SA1111_p2v (_SACR2)))
-#define SASR0 (*((volatile Word *) SA1111_p2v (_SASR0)))
-#define SASR1 (*((volatile Word *) SA1111_p2v (_SASR1)))
-#define SASCR (*((volatile Word *) SA1111_p2v (_SASCR)))
-#define L3_CAR (*((volatile Word *) SA1111_p2v (_L3_CAR)))
-#define L3_CDR (*((volatile Word *) SA1111_p2v (_L3_CDR)))
-#define ACCAR (*((volatile Word *) SA1111_p2v (_ACCAR)))
-#define ACCDR (*((volatile Word *) SA1111_p2v (_ACCDR)))
-#define ACSAR (*((volatile Word *) SA1111_p2v (_ACSAR)))
-#define ACSDR (*((volatile Word *) SA1111_p2v (_ACSDR)))
-#define SADTCS (*((volatile Word *) SA1111_p2v (_SADTCS)))
-#define SADTSA (*((volatile Word *) SA1111_p2v (_SADTSA)))
-#define SADTCA (*((volatile Word *) SA1111_p2v (_SADTCA)))
-#define SADTSB (*((volatile Word *) SA1111_p2v (_SADTSB)))
-#define SADTCB (*((volatile Word *) SA1111_p2v (_SADTCB)))
-#define SADRCS (*((volatile Word *) SA1111_p2v (_SADRCS)))
-#define SADRSA (*((volatile Word *) SA1111_p2v (_SADRSA)))
-#define SADRCA (*((volatile Word *) SA1111_p2v (_SADRCA)))
-#define SADRSB (*((volatile Word *) SA1111_p2v (_SADRSB)))
-#define SADRCB (*((volatile Word *) SA1111_p2v (_SADRCB)))
-#define SAITR (*((volatile Word *) SA1111_p2v (_SAITR)))
-#define SADR (*((volatile Word *) SA1111_p2v (_SADR)))
+#define SACR0 __CCREG(0x0600)
+#define SACR1 __CCREG(0x0604)
+#define SACR2 __CCREG(0x0608)
+#define SASR0 __CCREG(0x060c)
+#define SASR1 __CCREG(0x0610)
+#define SASCR __CCREG(0x0618)
+#define L3_CAR __CCREG(0x061c)
+#define L3_CDR __CCREG(0x0620)
+#define ACCAR __CCREG(0x0624)
+#define ACCDR __CCREG(0x0628)
+#define ACSAR __CCREG(0x062c)
+#define ACSDR __CCREG(0x0630)
+#define SADTCS __CCREG(0x0634)
+#define SADTSA __CCREG(0x0638)
+#define SADTCA __CCREG(0x063c)
+#define SADTSB __CCREG(0x0640)
+#define SADTCB __CCREG(0x0644)
+#define SADRCS __CCREG(0x0648)
+#define SADRSA __CCREG(0x064c)
+#define SADRCA __CCREG(0x0650)
+#define SADRSB __CCREG(0x0654)
+#define SADRCB __CCREG(0x0658)
+#define SAITR __CCREG(0x065c)
+#define SADR __CCREG(0x0680)
#endif /* LANGUAGE == C */
#if LANGUAGE == C
-#define PA_DDR (*((volatile Word *) SA1111_p2v (_PA_DDR)))
-#define PA_DRR (*((volatile Word *) SA1111_p2v (_PA_DRR)))
-#define PA_DWR (*((volatile Word *) SA1111_p2v (_PA_DWR)))
-#define PA_SDR (*((volatile Word *) SA1111_p2v (_PA_SDR)))
-#define PA_SSR (*((volatile Word *) SA1111_p2v (_PA_SSR)))
-#define PB_DDR (*((volatile Word *) SA1111_p2v (_PB_DDR)))
-#define PB_DRR (*((volatile Word *) SA1111_p2v (_PB_DRR)))
-#define PB_DWR (*((volatile Word *) SA1111_p2v (_PB_DWR)))
-#define PB_SDR (*((volatile Word *) SA1111_p2v (_PB_SDR)))
-#define PB_SSR (*((volatile Word *) SA1111_p2v (_PB_SSR)))
-#define PC_DDR (*((volatile Word *) SA1111_p2v (_PC_DDR)))
-#define PC_DRR (*((volatile Word *) SA1111_p2v (_PC_DRR)))
-#define PC_DWR (*((volatile Word *) SA1111_p2v (_PC_DWR)))
-#define PC_SDR (*((volatile Word *) SA1111_p2v (_PC_SDR)))
-#define PC_SSR (*((volatile Word *) SA1111_p2v (_PC_SSR)))
+#define PA_DDR __CCREG(0x1000)
+#define PA_DRR __CCREG(0x1004)
+#define PA_DWR __CCREG(0x1004)
+#define PA_SDR __CCREG(0x1008)
+#define PA_SSR __CCREG(0x100c)
+#define PB_DDR __CCREG(0x1010)
+#define PB_DRR __CCREG(0x1014)
+#define PB_DWR __CCREG(0x1014)
+#define PB_SDR __CCREG(0x1018)
+#define PB_SSR __CCREG(0x101c)
+#define PC_DDR __CCREG(0x1020)
+#define PC_DRR __CCREG(0x1024)
+#define PC_DWR __CCREG(0x1024)
+#define PC_SDR __CCREG(0x1028)
+#define PC_SSR __CCREG(0x102c)
#endif /* LANGUAGE == C */
#if LANGUAGE == C
-#define INTTEST0 (*((volatile Word *) SA1111_p2v (_INTTEST0)))
-#define INTTEST1 (*((volatile Word *) SA1111_p2v (_INTTEST1)))
-#define INTEN0 (*((volatile Word *) SA1111_p2v (_INTEN0)))
-#define INTEN1 (*((volatile Word *) SA1111_p2v (_INTEN1)))
-#define INTPOL0 (*((volatile Word *) SA1111_p2v (_INTPOL0)))
-#define INTPOL1 (*((volatile Word *) SA1111_p2v (_INTPOL1)))
-#define INTTSTSEL (*((volatile Word *) SA1111_p2v (_INTTSTSEL)))
-#define INTSTATCLR0 (*((volatile Word *) SA1111_p2v (_INTSTATCLR0)))
-#define INTSTATCLR1 (*((volatile Word *) SA1111_p2v (_INTSTATCLR1)))
-#define INTSET0 (*((volatile Word *) SA1111_p2v (_INTSET0)))
-#define INTSET1 (*((volatile Word *) SA1111_p2v (_INTSET1)))
-#define WAKE_EN0 (*((volatile Word *) SA1111_p2v (_WAKE_EN0)))
-#define WAKE_EN1 (*((volatile Word *) SA1111_p2v (_WAKE_EN1)))
-#define WAKE_POL0 (*((volatile Word *) SA1111_p2v (_WAKE_POL0)))
-#define WAKE_POL1 (*((volatile Word *) SA1111_p2v (_WAKE_POL1)))
+#define INTTEST0 __CCREG(0x1600)
+#define INTTEST1 __CCREG(0x1604)
+#define INTEN0 __CCREG(0x1608)
+#define INTEN1 __CCREG(0x160c)
+#define INTPOL0 __CCREG(0x1610)
+#define INTPOL1 __CCREG(0x1614)
+#define INTTSTSEL __CCREG(0x1618)
+#define INTSTATCLR0 __CCREG(0x161c)
+#define INTSTATCLR1 __CCREG(0x1620)
+#define INTSET0 __CCREG(0x1624)
+#define INTSET1 __CCREG(0x1628)
+#define WAKE_EN0 __CCREG(0x162c)
+#define WAKE_EN1 __CCREG(0x1630)
+#define WAKE_POL0 __CCREG(0x1634)
+#define WAKE_POL1 __CCREG(0x1638)
#endif /* LANGUAGE == C */
#define _KBD( x ) _SA1111( 0x0A00 )
#define _MSE( x ) _SA1111( 0x0C00 )
-#define _KBDCR _SA1111( 0x0A00 )
+#define _KBDCR _SA1111( 0x0A00 )
#define _KBDSTAT _SA1111( 0x0A04 )
#define _KBDDATA _SA1111( 0x0A08 )
#define _KBDCLKDIV _SA1111( 0x0A0C )
#define _KBDPRECNT _SA1111( 0x0A10 )
-#define _MSECR _SA1111( 0x0C00 )
+#define _MSECR _SA1111( 0x0C00 )
#define _MSESTAT _SA1111( 0x0C04 )
#define _MSEDATA _SA1111( 0x0C08 )
#define _MSECLKDIV _SA1111( 0x0C0C )
#if ( LANGUAGE == C )
-#define KBDCR (*((volatile Word *) SA1111_p2v (_KBDCR)))
-#define KBDSTAT (*((volatile Word *) SA1111_p2v (_KBDSTAT)))
-#define KBDDATA (*((volatile Word *) SA1111_p2v (_KBDDATA)))
-#define KBDCLKDIV (*((volatile Word *) SA1111_p2v (_KBDCLKDIV)))
-#define KBDPRECNT (*((volatile Word *) SA1111_p2v (_KBDPRECNT)))
-#define KBDTEST1 (*((volatile Word *) SA1111_p2v (_KBDTEST1)))
-#define KBDTEST2 (*((volatile Word *) SA1111_p2v (_KBDTEST2)))
-#define KBDTEST3 (*((volatile Word *) SA1111_p2v (_KBDTEST3)))
-#define KBDTEST4 (*((volatile Word *) SA1111_p2v (_KBDTEST4)))
-#define MSECR (*((volatile Word *) SA1111_p2v (_MSECR)))
-#define MSESTAT (*((volatile Word *) SA1111_p2v (_MSESTAT)))
-#define MSEDATA (*((volatile Word *) SA1111_p2v (_MSEDATA)))
-#define MSECLKDIV (*((volatile Word *) SA1111_p2v (_MSECLKDIV)))
-#define MSEPRECNT (*((volatile Word *) SA1111_p2v (_MSEPRECNT)))
-#define MSETEST1 (*((volatile Word *) SA1111_p2v (_MSETEST1)))
-#define MSETEST2 (*((volatile Word *) SA1111_p2v (_MSETEST2)))
-#define MSETEST3 (*((volatile Word *) SA1111_p2v (_MSETEST3)))
-#define MSETEST4 (*((volatile Word *) SA1111_p2v (_MSETEST4)))
+#define KBDCR __CCREG(0x0a00)
+#define KBDSTAT __CCREG(0x0a04)
+#define KBDDATA __CCREG(0x0a08)
+#define KBDCLKDIV __CCREG(0x0a0c)
+#define KBDPRECNT __CCREG(0x0a10)
+#define MSECR __CCREG(0x0c00)
+#define MSESTAT __CCREG(0x0c04)
+#define MSEDATA __CCREG(0x0c08)
+#define MSECLKDIV __CCREG(0x0c0c)
+#define MSEPRECNT __CCREG(0x0c10)
#define KBDCR_ENA 0x08
#define KBDCR_FKD 0x02
#if LANGUAGE == C
-#define PCCR (*((volatile Word *) SA1111_p2v (_PCCR)))
-#define PCSSR (*((volatile Word *) SA1111_p2v (_PCSSR)))
-#define PCSR (*((volatile Word *) SA1111_p2v (_PCSR)))
+#define PCCR __CCREG(0x1800)
+#define PCSSR __CCREG(0x1804)
+#define PCSR __CCREG(0x1808)
#endif /* LANGUAGE == C */
* Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
*
* This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
*
* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
* Definitions for Neponset added.
*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "include <asm/hardware.h> instead"
-#endif
-
+#ifndef __ASM_ARCH_ASSABET_H
+#define __ASM_ARCH_ASSABET_H
/* System Configuration Register flags */
-#define SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
-#define SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
-#define SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
-#define SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
-#define SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
-#define SCR_SA1111 (1<<9) /* Neponset (0 = present) */
+#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
+#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
+#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
+#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
+#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
+#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */
-#define SCR_INIT -1
+#define ASSABET_SCR_INIT -1
/* Board Control Register */
-#define BCR_BASE 0xf1000000
-#define BCR (*(volatile unsigned int *)(BCR_BASE))
-
-#define BCR_DB1110 \
- (BCR_SPK_OFF | BCR_QMUTE | BCR_LED_GREEN | BCR_LED_RED | \
- BCR_RS232EN | BCR_LCD_12RGB | BCR_IRDA_MD0)
-
-#define BCR_DB1111 \
- (BCR_SPK_OFF | BCR_QMUTE | BCR_LED_GREEN | BCR_LED_RED | \
- BCR_RS232EN | BCR_LCD_12RGB | BCR_CF_BUS_OFF | BCR_STEREO_LB | \
- BCR_IRDA_MD0 | BCR_CF_RST)
-
-#define BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
-#define BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
-#define BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
-#define BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
-#define BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
-#define BCR_IRDA_MD0 (1<<4) /* Range/Power select */
-#define BCR_IRDA_MD1 (1<<5) /* Range/Power select */
-#define BCR_STEREO_LB (1<<6) /* Stereo Loopback */
-#define BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
-#define BCR_AUDIO_ON (1<<8) /* Audio power on */
-#define BCR_LIGHT_ON (1<<9) /* Backlight */
-#define BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
-#define BCR_LCD_ON (1<<11) /* LCD power on */
-#define BCR_RS232EN (1<<12) /* RS232 transceiver enable */
-#define BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
-#define BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
-#define BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
-#define BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
-#define BCR_COM_RTS (1<<17) /* COMport Request To Send */
-#define BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
-#define BCR_SMB_EN (1<<19) /* System management bus enable */
-#define BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable */
-#define BCR_QMUTE (1<<21) /* Quick Mute */
-#define BCR_RAD_ON (1<<22) /* Radio Power On */
-#define BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
-
-#ifndef __ASSEMBLY__
+#define ASSABET_BCR_BASE 0xf1000000
+#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
+
+#define ASSABET_BCR_DB1110 \
+ (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \
+ ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
+ ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
+ ASSABET_BCR_IRDA_MD0)
+
+#define ASSABET_BCR_DB1111 \
+ (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \
+ ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
+ ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
+ ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
+ ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
+
+#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
+#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
+#define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
+#define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
+#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
+#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
+#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
+#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */
+#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
+#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */
+#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */
+#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
+#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */
+#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */
+#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
+#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
+#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
+#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
+#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */
+#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
+#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */
+#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */
+#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */
+#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */
+#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
+
extern unsigned long SCR_value;
extern unsigned long BCR_value;
-#define BCR_set( x ) BCR = (BCR_value |= (x))
-#define BCR_clear( x ) BCR = (BCR_value &= ~(x))
-#endif
+#define ASSABET_BCR_set(x) ASSABET_BCR = (BCR_value |= (x))
+#define ASSABET_BCR_clear(x) ASSABET_BCR = (BCR_value &= ~(x))
-#define BSR_BASE 0xf1000000
-#define BSR (*(volatile unsigned int*)(BSR_BASE))
+#define ASSABET_BSR_BASE 0xf1000000
+#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
-#define BSR_RS232_VALID (1 << 24)
-#define BSR_COM_DCD (1 << 25)
-#define BSR_COM_CTS (1 << 26)
-#define BSR_COM_DSR (1 << 27)
-#define BSR_RAD_CTS (1 << 28)
-#define BSR_RAD_DSR (1 << 29)
-#define BSR_RAD_DCD (1 << 30)
-#define BSR_RAD_RI (1 << 31)
+#define ASSABET_BSR_RS232_VALID (1 << 24)
+#define ASSABET_BSR_COM_DCD (1 << 25)
+#define ASSABET_BSR_COM_CTS (1 << 26)
+#define ASSABET_BSR_COM_DSR (1 << 27)
+#define ASSABET_BSR_RAD_CTS (1 << 28)
+#define ASSABET_BSR_RAD_DSR (1 << 29)
+#define ASSABET_BSR_RAD_DCD (1 << 30)
+#define ASSABET_BSR_RAD_RI (1 << 31)
/* GPIOs for which the generic definition doesn't say much */
-#define GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
-#define GPIO_L3_I2C_SDA GPIO_GPIO (15) /* L3 and SMB control ports */
-#define GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
-#define GPIO_L3_MODE GPIO_GPIO (17) /* L3 mode signal with LED */
-#define GPIO_L3_I2C_SCL GPIO_GPIO (18) /* L3 and I2C control ports */
-#define GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
-#define GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
-#define GPIO_MBGNT GPIO_GPIO (21) /* 1111 MBGNT */
-#define GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
-#define GPIO_MBREQ GPIO_GPIO (22) /* 1111 MBREQ */
-#define GPIO_UCB1300_IRQ GPIO_GPIO (23) /* UCB GPIO and touchscreen */
-#define GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
-#define GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
-#define GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
-#define GPIO_NEP_IRQ GPIO_GPIO (25) /* Neponset IRQ */
-#define GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
-#define GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
-
-#define IRQ_GPIO_CF_IRQ IRQ_GPIO21
-#define IRQ_GPIO_CF_CD IRQ_GPIO22
-#define IRQ_GPIO_MBREQ IRQ_GPIO22
-#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO23
-#define IRQ_GPIO_CF_BVD2 IRQ_GPIO24
-#define IRQ_GPIO_CF_BVD1 IRQ_GPIO25
-#define IRQ_GPIO_NEP_IRQ IRQ_GPIO25
+#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
+#define ASSABET_GPIO_L3_I2C_SDA GPIO_GPIO (15) /* L3 and SMB control ports */
+#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
+#define ASSABET_GPIO_L3_MODE GPIO_GPIO (17) /* L3 mode signal with LED */
+#define ASSABET_GPIO_L3_I2C_SCL GPIO_GPIO (18) /* L3 and I2C control ports */
+#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
+#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
+#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
+#define ASSABET_GPIO_UCB1300_IRQ GPIO_GPIO (23) /* UCB GPIO and touchscreen */
+#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
+#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
+#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
+#define ASSABET_GPIO_NEP_IRQ GPIO_GPIO (25) /* Neponset IRQ */
+#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
+#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
+
+#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21
+#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22
+#define ASSABET_IRQ_GPIO_UCB1300_IRQ IRQ_GPIO23
+#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24
+#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25
+#define ASSABET_IRQ_GPIO_NEP_IRQ IRQ_GPIO25
/*
#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
-#ifndef __ASSEMBLY__
-
#define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
#define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
-#endif
-
#define IRR_ETHERNET (1<<0)
#define IRR_USAR (1<<1)
#define IRR_SA1111 (1<<2)
#define NCR_A0VPP (1<<5)
#define NCR_A1VPP (1<<6)
-#ifndef __ASSEMBLY__
#ifdef CONFIG_ASSABET_NEPONSET
-#define machine_has_neponset() ((SCR_value & SCR_SA1111) == 0)
+#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0)
#else
#define machine_has_neponset() (0)
#endif
-#endif
+#endif
-#ifndef BITFIELD
-#define BITFIELD
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
-#ifndef LANGUAGE
-#define LANGUAGE C
-#endif /* !defined (LANGUAGE) */
-
-#define C 0
-#define Assembly 1
-
-#if LANGUAGE == C
-#define UData(Data) ((unsigned int) (Data))
-#elif LANGUAGE == Assembly
+#ifndef __ASSEMBLY__
+#define UData(Data) ((unsigned long) (Data))
+#else
#define UData(Data) (Data)
-#endif /* LANGUAGE == C || LANGUAGE == Assembly */
+#endif
/*
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-#undef C
-#undef Assembly
-
-#endif /* !defined (BITFIELD) */
+#endif /* __BITFIELD_H */
#ifndef _INCLUDE_CERF_H_
#define _INCLUDE_CERF_H_
-/* GPIOs for CF+ slot lines */
-#define GPIO_CF_IRQ GPIO_GPIO (22) /* 1111 MBGNT _OR_ CF IRQ */
-#define GPIO_CF_CD GPIO_GPIO (23) /* 1111 MBREQ _OR_ CF CD */
-#define GPIO_CF_BVD2 GPIO_GPIO (19) /* Graphics IRQ _OR_ CF BVD */
-#define GPIO_CF_BVD1 GPIO_GPIO (20) /* 1111 IRQ _OR_ CF BVD */
+#ifdef CONFIG_SA1100_CERF_CPLD
-#define IRQ_GPIO_CF_IRQ IRQ_GPIO22
-#define IRQ_GPIO_CF_CD IRQ_GPIO23
-#define IRQ_GPIO_CF_BVD2 IRQ_GPIO19
-#define IRQ_GPIO_CF_BVD1 IRQ_GPIO20
-#define GPIO_UCB1200_IRQ GPIO_GPIO (18)
-#define IRQ_GPIO_UCB1200_IRQ IRQ_GPIO18
+// Map sa1100fb.c to sa1100_frontlight.c - Not pretty, but necessary.
+#define CERF_BACKLIGHT_ENABLE sa1100_fl_enable
+#define CERF_BACKLIGHT_DISABLE sa1100_fl_disable
-#endif
+//
+// IO Pins for devices
+//
+#define CERF_PDA_CPLD 0xf1000000
+#define CERF_PDA_CPLD_WRCLRINT (0x0)
+#define CERF_PDA_CPLD_BACKLIGHT (0x2)
+#define CERF_PDA_CPLD_SOUND_FREQ (0x4)
+#define CERF_PDA_CPLD_KEYPAD_A (0x6)
+#define CERF_PDA_CPLD_BATTFAULT (0x8)
+#define CERF_PDA_CPLD_KEYPAD_B (0xa)
+#define CERF_PDA_CPLD_SOUND_ENA (0xc)
+#define CERF_PDA_CPLD_SOUND_RESET (0xe)
+
+#define GPIO_CF_BVD2 GPIO_GPIO (5)
+#define GPIO_CF_BVD1 GPIO_GPIO (6)
+#define GPIO_CF_RESET GPIO_GPIO (7)
+#define GPIO_CF_IRQ GPIO_GPIO (8)
+#define GPIO_CF_CD GPIO_GPIO (9)
+
+#define GPIO_PWR_SHUTDOWN GPIO_GPIO (25)
+
+#define UCB1200_GPIO_CONT_CS 0x0001
+#define UCB1200_GPIO_CONT_DOWN 0x0002
+#define UCB1200_GPIO_CONT_INC 0x0004
+#define UCB1200_GPIO_CONT_ENA 0x0008
+#define UCB1200_GPIO_LCD_RESET 0x0010
+#define UCB1200_GPIO_IRDA_ENABLE 0x0020
+#define UCB1200_GPIO_BT_ENABLE 0x0040
+#define UCB1200_GPIO_L3_DATA 0x0080
+#define UCB1200_GPIO_L3_CLOCK 0x0100
+#define UCB1200_GPIO_L3_MODE 0x0200
+
+//
+// IRQ for devices
+//
+
+#define IRQ_UCB1200_CONT_CS IRQ_UCB1200_IO0
+#define IRQ_UCB1200_CONT_DOWN IRQ_UCB1200_IO1
+#define IRQ_UCB1200_CONT_INC IRQ_UCB1200_IO2
+#define IRQ_UCB1200_CONT_ENA IRQ_UCB1200_IO3
+#define IRQ_UCB1200_LCD_RESET IRQ_UCB1200_IO4
+#define IRQ_UCB1200_IRDA_ENABLE IRQ_UCB1200_IO5
+#define IRQ_UCB1200_BT_ENABLE IRQ_UCB1200_IO6
+#define IRQ_UCB1200_L3_DATA IRQ_UCB1200_IO7
+#define IRQ_UCB1200_L3_CLOCK IRQ_UCB1200_IO8
+#define IRQ_UCB1200_L3_MODE IRQ_UCB1200_IO9
+
+#define IRQ_GPIO_CF_BVD2 IRQ_GPIO5
+#define IRQ_GPIO_CF_BVD1 IRQ_GPIO6
+#define IRQ_GPIO_CF_IRQ IRQ_GPIO8
+#define IRQ_GPIO_CF_CD IRQ_GPIO9
+
+//
+// Device parameters
+//
+
+#define CERF_PDA_CPLD_SOUND_FREQ_8000 (0x01)
+#define CERF_PDA_CPLD_SOUND_FREQ_11025 (0x05)
+#define CERF_PDA_CPLD_SOUND_FREQ_16000 (0x02)
+#define CERF_PDA_CPLD_SOUND_FREQ_22050 (0x06)
+#define CERF_PDA_CPLD_SOUND_FREQ_32000 (0x03)
+#define CERF_PDA_CPLD_SOUND_FREQ_44100 (0x07)
+#define CERF_PDA_CPLD_SOUND_FREQ_48000 (0x0b)
+
+//
+// General Functions
+//
+
+#define CERF_PDA_CPLD_Get(x, y) (*((char*)(CERF_PDA_CPLD + (x))) & (y))
+#define CERF_PDA_CPLD_Set(x, y, z) (*((char*)(CERF_PDA_CPLD + (x))) = (*((char*)(CERF_PDA_CPLD + (x))) & ~(z)) | (y))
+#define CERF_PDA_CPLD_UnSet(x, y, z) (*((char*)(CERF_PDA_CPLD + (x))) = (*((char*)(CERF_PDA_CPLD + (x))) & ~(z)) & ~(y))
+
+
+#else // CONFIG_SA1100_CERF_CPLD
+
+
+#define GPIO_CF_BVD2 GPIO_GPIO (19)
+#define GPIO_CF_BVD1 GPIO_GPIO (20)
+#define GPIO_CF_RESET 0
+#define GPIO_CF_IRQ GPIO_GPIO (22)
+#define GPIO_CF_CD GPIO_GPIO (23)
+
+#define GPIO_LCD_RESET GPIO_GPIO (15)
+
+#define IRQ_GPIO_CF_BVD2 IRQ_GPIO19
+#define IRQ_GPIO_CF_BVD1 IRQ_GPIO20
+#define IRQ_GPIO_CF_IRQ IRQ_GPIO22
+#define IRQ_GPIO_CF_CD IRQ_GPIO23
+
+
+#endif // CONFIG_SA1100_CERF_CPLD
+
+
+#define GPIO_UCB1200_IRQ GPIO_GPIO (18)
+#define IRQ_GPIO_UCB1200_IRQ IRQ_GPIO18
+
+#endif // _INCLUDE_CERF_H_
#define _ADS_UARTC 0x10140000 /* UART C */
#define _ADS_UARTD 0x10160000 /* UART D */
+/* UART controll lines GPIOs */
+#define GPIO_GC_UART0_RTS GPIO_GPIO15
+#define GPIO_GC_UART1_RTS GPIO_GPIO17
+#define GPIO_GC_UART2_RTS GPIO_GPIO19
+#define GPIO_GC_UART0_CTS GPIO_GPIO14
+#define GPIO_GC_UART1_CTS GPIO_GPIO16
+#define GPIO_GC_UART2_CTS GPIO_GPIO17
+
+/* UART controll lines IRQs */
+#define IRQ_GC_UART0_CTS IRQ_GPIO14
+#define IRQ_GC_UART1_CTS IRQ_GPIO16
+#define IRQ_GC_UART2_CTS IRQ_GPIO17
+
+#ifndef __ASSEMBLY__
+struct gc_uart_ctrl_data_t {
+ int cts_gpio;
+ int cts_prev_state;
+ struct uart_info *info;
+ struct uart_port *port;
+};
+#endif /* __ASSEMBLY__ */
/* LEDs */
#define io_v2p( x ) \
( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
+#ifndef __ASSEMBLY__
+
+#if 0
+# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
+#else
+/*
+ * This __REG() version gives the same results as the one above, except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers. It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+typedef struct { volatile unsigned long offset[4096]; } __regbase;
+# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x) __REGP(io_p2v(x))
+#endif
+
+# define __PREG(x) (io_v2p((unsigned long)&(x)))
+
+#else
+
+# define __REG(x) io_p2v(x)
+# define __PREG(x) io_v2p(x)
+
+#endif
+
#include "SA-1100.h"
/*
- * Implementation specifics
+ * Implementation specifics.
+ *
+ * *** NOTE ***
+ * Any definitions in these files should be prefixed by an identifier -
+ * eg, ASSABET_UCB1300_IRQ This will allow us to eleminate these
+ * ifdefs, and lots of other preprocessor gunk elsewhere.
*/
#ifdef CONFIG_SA1100_PANGOLIN
#include "pangolin.h"
#endif
-#ifdef CONFIG_SA1100_ASSABET
-#include "assabet.h"
-#else
-#define machine_has_neponset() (0)
-#endif
-
-
#ifdef CONFIG_SA1100_HUW_WEBPANEL
#include "huw_webpanel.h"
#endif
#ifdef CONFIG_SA1111
-#define SA1111_p2v( x ) ((x) - SA1111_BASE + 0xf4000000)
-#define SA1111_v2p( x ) ((x) - 0xf4000000 + SA1111_BASE)
+/*
+ * The SA1111 is always located at virtual 0xf4000000.
+ */
+
+#define SA1111_VBASE 0xf4000000
+
+#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
+#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
#include "SA-1111.h"
* Created 16 Dec 1999 by Nicolas Pitre <nico@cam.org>
* This file contains the SA1100 architecture specific keyboard definitions
*/
-
#ifndef _SA1100_KEYBOARD_H
#define _SA1100_KEYBOARD_H
#include <linux/config.h>
#include <asm/mach-types.h>
-#include <asm/hardware.h>
-
-extern struct kbd_ops_struct *kbd_ops;
+#include <asm/arch/assabet.h>
#define kbd_disable_irq() do { } while(0);
#define kbd_enable_irq() do { } while(0);
-
-/*
- * SA1111 keyboard driver
- */
extern void sa1111_kbd_init_hw(void);
-
-/*
- * GraphicsClient keyboard driver
- */
extern void gc_kbd_init_hw(void);
+extern void smartio_kbd_init_hw(void);
+extern void cerf_kbd_init_hw(void);
static inline void kbd_init_hw(void)
{
- if (machine_is_assabet() && machine_has_neponset())
+ if ((machine_is_assabet() && machine_has_neponset()) ||
+ machine_is_graphicsmaster())
sa1111_kbd_init_hw();
-
if (machine_is_graphicsclient())
gc_kbd_init_hw();
-}
-
-
-
-#if 0 /* Brutus needs fixing */
-
-extern int Brutus_kbd_translate(unsigned char scancode, unsigned char *keycode,
- char raw_mode);
-extern void Brutus_kbd_leds(unsigned char leds);
-extern void Brutus_kbd_init_hw(void);
-extern void Brutus_kbd_enable_irq(void);
-extern void Brutus_kbd_disable_irq(void);
-extern unsigned char Brutus_kbd_sysrq_xlate[128];
-
-#define kbd_setkeycode(x...) (-ENOSYS)
-#define kbd_getkeycode(x...) (-ENOSYS)
-#define kbd_translate Brutus_kbd_translate
-#define kbd_unexpected_up(x...) (1)
-#define kbd_leds Brutus_kbd_leds
-#define kbd_init_hw Brutus_kbd_init_hw
-#define kbd_enable_irq Brutus_kbd_enable_irq
-#define kbd_disable_irq Brutus_kbd_disable_irq
-#define kbd_sysrq_xlate Brutus_kbd_sysrq_xlate
-
-#define SYSRQ_KEY 0x54
-
-#elif 0 // CONFIG_SA1100_GRAPHICSCLIENT
-extern int gc_kbd_setkeycode(unsigned int scancode, unsigned int keycode);
-extern int gc_kbd_getkeycode(unsigned int scancode);
-extern int gc_kbd_translate(unsigned char scancode, unsigned char *keycode, char raw_mode);
-extern void gc_kbd_leds(unsigned char leds);
-extern void gc_kbd_init_hw(void);
-extern void gc_kbd_enable_irq(void);
-extern void gc_kbd_disable_irq(void);
-extern unsigned char gc_kbd_sysrq_xlate[128];
-
-#define kbd_setkeycode(x...) gc_kbd_setkeycode //(-ENOSYS)
-#define kbd_getkeycode(x...) gc_kbd_getkeycode //(-ENOSYS)
-#define kbd_translate gc_kbd_translate
-#define kbd_unexpected_up(x...) (1)
-#define kbd_leds gc_kbd_leds
-#define kbd_init_hw gc_kbd_init_hw
-#define kbd_enable_irq gc_kbd_enable_irq
-#define kbd_disable_irq gc_kbd_disable_irq
-#define kbd_sysrq_xlate (1)
-
+ if (machine_is_adsbitsy())
+ smartio_kbd_init_hw();
+#ifdef CONFIG_SA1100_CERF_CPLD
+ if (machine_is_cerf())
+ cerf_kbd_init_hw();
#endif
+}
#endif /* _SA1100_KEYBOARD_H */
-
/*
- * linux/include/asm-arm/arch-sa1100/trizeps.h
+ * linux/include/asm-arm/arch-sa1100/simpad.h
*
* based of assabet.h same as HUW_Webpanel
*
- * This file contains the hardware specific definitions for Trizeps
+ * This file contains the hardware specific definitions for SIMpad
*
- * 2001/03/14 Peter Lueg <peter.lueg@dsa-ac.de>
+ * 2001/05/14 Juergen Messerer <juergen.messerer@siemens.ch>
*/
#ifndef SIMPAD_H
#error "include <asm/hardware.h> instead"
#endif
-/* System Configuration Register flags */
-
-#define SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
-#define SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
-#define SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
-#define SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
-#define SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
-#define SCR_SA1111 (1<<9) /* Neponset (0 = present) */
-
-#define SCR_INIT -1
-
#define GPIO_UART1_RTS GPIO_GPIO14
#define GPIO_UART1_DTR GPIO_GPIO7
#define GPIO_UART1_CTS GPIO_GPIO8
#define GPIO_UART3_DCD GPIO_GPIO18
#define GPIO_UART3_DSR GPIO_GPIO17
+#define GPIO_UCB1300_IRQ GPIO_GPIO (22) /* UCB GPIO and touchscreen */
+
#define IRQ_UART1_CTS IRQ_GPIO15
#define IRQ_UART1_DCD GPIO_GPIO23
#define IRQ_UART1_DSR GPIO_GPIO6
#define IRQ_UART3_DCD GPIO_GPIO18
#define IRQ_UART3_DSR GPIO_GPIO17
-#define GPIO_UCB1300_IRQ GPIO_GPIO (22) /* UCB GPIO and touchscreen */
-#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
-
-#define SA1100_UART1_EXT \
- (struct huw_irq_desc){GPIO_UART1_CTS, IRQ_UART1_CTS, \
- GPIO_UART1_DCD, IRQ_UART1_DCD, \
- GPIO_UART1_DSR, IRQ_UART1_DSR}
-#define SA1100_UART3_EXT \
- (struct huw_irq_desc){GPIO_UART3_CTS, IRQ_UART3_CTS, \
- GPIO_UART3_DCD, IRQ_UART3_DCD, \
- GPIO_UART3_DSR, IRQ_UART3_DSR}
+#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
/*--- PCMCIA ---*/
#define GPIO_CF_CD GPIO_GPIO24
-#define GPIO_CF_IRQ GPIO_GPIO1
+#define GPIO_CF_IRQ GPIO_GPIO1
#define IRQ_GPIO_CF_IRQ IRQ_GPIO1
-#define IRQ_GPIO_CF_CD IRQ_GPIO24
+#define IRQ_GPIO_CF_CD IRQ_GPIO24
-// CS3 Latch is write only, a shadow is neccessary
+// CS3 Latch is write only, a shadow is neccessary
-#define CS3BUSTYPE unsigned volatile long
+#define CS3BUSTYPE unsigned volatile long
#define CS3_BASE 0xf1000000
-#define VCC_5V_EN 0x0001
-#define VCC_3V_EN 0x0002
-#define EN1 0x0004
-#define EN0 0x0008
+#define VCC_5V_EN 0x0001 // For 5V PCMCIA
+#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA
+#define EN1 0x0004 // This is only for EPROM's
+#define EN0 0x0008 // Both should be enable for 3.3V or 5V
#define DISPLAY_ON 0x0010
#define PCMCIA_BUFF_DIS 0x0020
#define MQ_RESET 0x0040
#define PCMCIA_RESET 0x0080
#define DECT_POWER_ON 0x0100
-#define IRDA_SD 0x0200
+#define IRDA_SD 0x0200 // Shutdown for powersave
#define RS232_ON 0x0400
-#define SD_MEDIAQ 0x0800
-#define LED2_ON 0x1000
-#define IRDA_MODE 0x2000
-#define ENABLE_5V 0x4000
+#define SD_MEDIAQ 0x0800 // Shutdown for powersave
+#define LED2_ON 0x1000
+#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode
+#define ENABLE_5V 0x4000 // Enable 5V circuit
#define RESET_SIMCARD 0x8000
#define RS232_ENABLE 0x0440
-#define PCMCIAMASK 0x402f
-
-#ifndef __ASSEMBLY__
-static long cs3_shadow;
-void init_simpad_cs3();
-void PCMCIA_setbit(int value);
-void PCMCIA_clearbit(int value);
-#endif
+#define PCMCIAMASK 0x402f
#endif // SIMPAD_H
static inline void arch_idle(void)
{
- if (!hlt_counter)
- cpu_do_idle(0);
+ if (!hlt_counter) {
+ int flags;
+ local_irq_save(flags);
+ if (!current->need_resched)
+ cpu_do_idle(0);
+ local_irq_restore(flags);
+ }
}
#ifdef CONFIG_SA1100_VICTOR
/*
* linux/include/asm-arm/arch-shark/dma.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
/*
* linux/include/asm-arm/arch-shark/hardware.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/hardware.h
/*
* linux/include/asm-arm/arch-shark/ide.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa285/ide.h
/*
* linux/include/asm-arm/arch-shark/io.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/io.h
/*
* linux/include/asm-arm/arch-shark/irq.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from linux/arch/ppc/kernel/i8259.c and:
* include/asm-arm/arch-ebsa110/irq.h
/*
* linux/include/asm-arm/arch-shark/irqs.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*/
#define NR_IRQS 16
/*
* linux/include/asm-arm/arch-shark/keyboard.h
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* Derived from linux/include/asm-arm/arch-ebsa285/keyboard.h
* (C) 1998 Russell King
#include <asm/io.h>
#include <asm/system.h>
+#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
+#define NR_SCANCODES 128
+
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
+
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
extern void pckbd_init_hw(void);
extern unsigned char pckbd_sysrq_xlate[128];
-#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
-
-#define NR_SCANCODES 128
+static inline void kbd_init_hw(void)
+{
+ if (have_isa_bridge) {
+ k_setkeycode = pckbd_setkeycode;
+ k_getkeycode = pckbd_getkeycode;
+ k_translate = pckbd_translate;
+ k_unexpected_up = pckbd_unexpected_up;
+ k_leds = pckbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+ k_sysrq_key = 0x54;
+ k_sysrq_xlate = pckbd_sysrq_xlate;
+#endif
+ pckbd_init_hw();
+ }
+}
-#define kbd_setkeycode(sc,kc) pckbd_setkeycode(sc,kc)
-#define kbd_getkeycode(sc) pckbd_getkeycode(sc)
-#define kbd_translate(sc, kcp, rm) pckbd_translate(sc, kcp, rm)
-#define kbd_unexpected_up pckbd_unexpected_up
-#define kbd_leds(leds) pckbd_leds(leds)
-#define kbd_init_hw() pckbd_init_hw()
-#define kbd_sysrq_xlate pckbd_sysrq_xlate
-
-#define kbd_disable_irq()
-#define kbd_enable_irq()
-
-#define SYSRQ_KEY 0x54
+/*
+ * PC Keyboard specifics
+ */
/* resource allocation */
#define kbd_request_region() request_region(0x60, 16, "keyboard")
/*
* linux/include/asm-arm/arch-shark/memory.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/memory.h
/*
* linux/include/asm-arm/arch-shark/param.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*/
/* This must be a power of 2 because the RTC
* can't use anything else.
*/
#define HZ 64
+
+#define hz_to_std(a) ((a * HZ)/100)
/*
* linux/include/asm-arm/arch-shark/system.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
/*
* linux/include/asm-arm/arch-shark/time.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* Uses the real time clock because you can't run
* the timer with level triggered interrupts and
/*
* linux/include/asm-arm/arch-shark/timex.h
*
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*/
/*
* linux/include/asm-arm/arch-shark/uncompress.h
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa285/uncompress.h
*
* Driver definitions for Tbox dummy keyboard.
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* Copyright (C) 1998 Philip Blundell
*/
#define NR_SCANCODES 128
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-/* Prototype: int kbd_pretranslate(scancode, raw_mode)
- * Returns : 0 to ignore scancode
- */
-#define kbd_pretranslate(sc,rm) (1)
-
-/* Prototype: int kbd_translate(scancode, *keycode, *up_flag, raw_mode)
- * Returns : 0 to ignore scancode, *keycode set to keycode, *up_flag
- * set to 0200 if scancode indicates release
- */
-#define kbd_translate(sc, kcp, rm) 0
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) do { } while (0)
-#define kbd_init_hw() do { } while (0)
-#define kbd_disable_irq() do { } while (0)
-#define kbd_enable_irq() do { } while (0)
+#define kbd_init_hw() do { } while (0)
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/ep7211.h
+ *
+ * This file contains the hardware definitions of the EP7211 internal
+ * registers.
+ *
+ * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_HARDWARE_EP7211_H
+#define __ASM_HARDWARE_EP7211_H
+
+#include <asm/hardware/clps7111.h>
+
+/*
+ * define EP7211_BASE to be the base address of the region
+ * you want to access.
+ */
+
+#define EP7211_PHYS_BASE (0x80000000)
+
+/*
+ * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
+ * present in 7212) here.
+ */
+
+#endif /* __ASM_HARDWARE_EP7211_H */
#ifndef __ASM_HARDWARE_EP7212_H
#define __ASM_HARDWARE_EP7212_H
+#include <linux/config.h>
+
/*
* define EP7212_BASE to be the base address of the region
* you want to access.
#define INTSR3 0x2240
#define INTMR3 0x2280
#define LEDFLSH 0x22c0
+#if defined (CONFIG_ARCH_CDB89712)
+#define SDCONF 0x2300
+#define SDRFPR 0x2340
+#endif
#define DAIR_DAIEN (1 << 16)
#define DAIR_ECS (1 << 17)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
+#if defined (CONFIG_ARCH_CDB89712)
+#define SDCONF_ACTIVE (1 << 10)
+#define SDCONF_CLKCTL (1 << 9)
+#define SDCONF_WIDTH_4 (0 << 7)
+#define SDCONF_WIDTH_8 (1 << 7)
+#define SDCONF_WIDTH_16 (2 << 7)
+#define SDCONF_WIDTH_32 (3 << 7)
+#define SDCONF_SIZE_16 (0 << 5)
+#define SDCONF_SIZE_64 (1 << 5)
+#define SDCONF_SIZE_128 (2 << 5)
+#define SDCONF_SIZE_256 (3 << 5)
+#define SDCONF_CASLAT_2 (2)
+#define SDCONF_CASLAT_3 (3)
+#endif
#endif /* __ASM_HARDWARE_EP7212_H */
#ifndef __ASM_ARM_KEYBOARD_H
#define __ASM_ARM_KEYBOARD_H
+#include <linux/kd.h>
+#include <linux/pm.h>
+
/*
* We provide a unified keyboard interface when in VC_MEDIUMRAW
* mode. This means that all keycodes must be common between
*/
#ifdef __KERNEL__
-#include <asm/arch/keyboard.h>
+extern int (*k_setkeycode)(unsigned int, unsigned int);
+extern int (*k_getkeycode)(unsigned int);
+extern int (*k_translate)(unsigned char, unsigned char *, char);
+extern char (*k_unexpected_up)(unsigned char);
+extern void (*k_leds)(unsigned char);
+
+
+static inline int kbd_setkeycode(unsigned int sc, unsigned int kc)
+{
+ int ret = -EINVAL;
+
+ if (k_setkeycode)
+ ret = k_setkeycode(sc, kc);
+
+ return ret;
+}
-#ifndef kbd_rate
-struct kbd_repeat;
+static inline int kbd_getkeycode(unsigned int sc)
+{
+ int ret = -EINVAL;
-extern int kbd_rate(struct kbd_repeat *rate) __attribute__((weak));
-#endif
+ if (k_getkeycode)
+ ret = k_getkeycode(sc);
+
+ return ret;
+}
+
+static inline void kbd_leds(unsigned char leds)
+{
+ if (k_leds)
+ k_leds(leds);
+}
+
+extern int k_sysrq_key;
+extern unsigned char *k_sysrq_xlate;
+
+#define SYSRQ_KEY k_sysrq_key
+#define kbd_sysrq_xlate k_sysrq_xlate
+#define kbd_translate k_translate
+#define kbd_unexpected_up k_unexpected_up
+
+#include <asm/arch/keyboard.h>
#endif /* __KERNEL__ */
#define clean_dcache_entry(_s) cpu_dcache_clean_entry((unsigned long)(_s))
/*
- * I cache only
+ * I cache coherency stuff.
+ *
+ * This *is not* just icache. It is to make data written to memory
+ * consistent such that instructions fetched from the region are what
+ * we expect.
+ *
+ * This generally means that we have to clean out the Dcache and write
+ * buffers, and maybe flush the Icache in the specified range.
*/
#define flush_icache_range(_s,_e) \
do { \
#define __put_user_asm_half(x,addr,err) \
({ \
unsigned long __temp = (unsigned long)(x); \
- __put_user_asm_byte(__temp, addr, err); \
- __put_user_asm_byte(__temp >> 8, (int)(addr) + 1, err); \
+ unsigned long __ptr = (unsigned long)(addr); \
+ __put_user_asm_byte(__temp, __ptr, err); \
+ __put_user_asm_byte(__temp >> 8, __ptr + 1, err); \
})
#define __put_user_asm_word(x,addr,err) \
#define __get_user_asm_half(x,addr,err) \
({ \
- unsigned long __b1, __b2; \
- __get_user_asm_byte(__b1, addr, err); \
- __get_user_asm_byte(__b2, (int)(addr) + 1, err); \
+ unsigned long __b1, __b2, __ptr = (unsigned long)addr; \
+ __get_user_asm_byte(__b1, __ptr, err); \
+ __get_user_asm_byte(__b2, __ptr + 1, err); \
(x) = __b1 | (__b2 << 8); \
})
};
/* it is allowed to have multiple ATAG_MEM nodes */
-#define ATAG_MEM 0x54410002
+#define ATAG_MEM 0x54410002
struct tag_mem32 {
u32 size;
#define put_user(x,p) \
({ \
- const register typeof(*(p)) *__p asm("r0") = (p); \
const register typeof(*(p)) __r1 asm("r1") = (x); \
+ const register typeof(*(p)) *__p asm("r0") = (p); \
register int __e asm("r0"); \
switch (sizeof(*(p))) { \
case 1: \
#define AUTO_DMA
+#define EXTRA_FLOPPY_PARAMS
#endif /* __ASM_I386_FLOPPY_H */
return retval;
}
+/*
+ * Cache management
+ *
+ * This needed for two cases
+ * 1. Out of order aware processors
+ * 2. Accidentally out of order processors (PPro errata #51)
+ */
+
+#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
+
+static inline void flush_write_buffers(void)
+{
+ __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory");
+}
+
+#define dma_cache_inv(_start,_size) flush_write_buffers()
+#define dma_cache_wback(_start,_size) flush_write_buffers()
+#define dma_cache_wback_inv(_start,_size) flush_write_buffers()
+
+#else
+
/* Nothing to do */
#define dma_cache_inv(_start,_size) do { } while (0)
#define dma_cache_wback(_start,_size) do { } while (0)
#define dma_cache_wback_inv(_start,_size) do { } while (0)
+#define flush_write_buffers()
+
+#endif
#endif /* __KERNEL__ */
/*
* This works. Despite all the confusion.
+ * (except on PPro SMP or if we are using OOSTORE)
+ * (PPro errata 66, 92)
*/
+
+#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
+
+#define spin_unlock_string \
+ "movb $1,%0" \
+ :"=m" (lock->lock) : : "memory"
+
+
+static inline void spin_unlock(spinlock_t *lock)
+{
+#if SPINLOCK_DEBUG
+ if (lock->magic != SPINLOCK_MAGIC)
+ BUG();
+ if (!spin_is_locked(lock))
+ BUG();
+#endif
+ __asm__ __volatile__(
+ spin_unlock_string
+ );
+}
+
+#else
+
#define spin_unlock_string \
- "movb $1,%0"
+ "xchgb %b0, %1" \
+ :"=q" (oldval), "=m" (lock->lock) \
+ :"0" (oldval) : "memory"
+
+static inline void spin_unlock(spinlock_t *lock)
+{
+ char oldval = 1;
+#if SPINLOCK_DEBUG
+ if (lock->magic != SPINLOCK_MAGIC)
+ BUG();
+ if (!spin_is_locked(lock))
+ BUG();
+#endif
+ __asm__ __volatile__(
+ spin_unlock_string
+ );
+}
+
+#endif
static inline int spin_trylock(spinlock_t *lock)
{
:"=m" (lock->lock) : : "memory");
}
-static inline void spin_unlock(spinlock_t *lock)
-{
-#if SPINLOCK_DEBUG
- if (lock->magic != SPINLOCK_MAGIC)
- BUG();
- if (!spin_is_locked(lock))
- BUG();
-#endif
- __asm__ __volatile__(
- spin_unlock_string
- :"=m" (lock->lock) : : "memory");
-}
/*
* Read-write spinlocks, allowing multiple readers
#include <linux/types.h>
#include <asm/bootinfo.h>
+#include <asm/raw_io.h>
extern u_long atari_mch_cookie;
extern u_long atari_mch_type;
* DMA reads (i.e., writes to memory).
*/
+
+#define atari_readb raw_inb
+#define atari_writeb raw_outb
+
+#define atari_inb_p raw_inb
+#define atari_outb_p raw_outb
+
+
+
#include <linux/mm.h>
#include <asm/pgalloc.h>
__constant_set_bit(nr, vaddr) : \
__generic_set_bit(nr, vaddr))
+#define __set_bit(nr,vaddr) set_bit(nr,vaddr)
+
extern __inline__ void __constant_set_bit(int nr, volatile void * vaddr)
{
__asm__ __volatile__ ("bset %1,%0"
__constant_test_and_clear_bit(nr, vaddr) : \
__generic_test_and_clear_bit(nr, vaddr))
+#define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr)
+
extern __inline__ int __constant_test_and_clear_bit(int nr, volatile void * vaddr)
{
char retval;
/* basically PC init + set use_virtual_dma */
#define FDC1 m68k_floppy_init()
-static int FDC2 = -1;
-
#define N_FDC 1
#define N_DRIVE 8
{
if(MACH_IS_Q40)
return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT,
- "floppy", NULL);
+ "floppy", floppy_hardint);
else if(MACH_IS_SUN3X)
return sun3xflop_request_irq();
static void fd_free_irq(void)
{
if(MACH_IS_Q40)
- free_irq(FLOPPY_IRQ, NULL);
+ free_irq(FLOPPY_IRQ, floppy_hardint);
}
#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
#endif
}
-
-
+#define EXTRA_FLOPPY_PARAMS
/* entry.S is sensitive to the offsets of these fields */
typedef struct {
- unsigned int __softirq_active;
- unsigned int __softirq_mask;
+ unsigned int __softirq_pending;
unsigned int __local_irq_count;
unsigned int __local_bh_count;
unsigned int __syscall_count;
+ struct task_struct * __ksoftirqd_task;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
-#define MACH_HAS_ISA 1
+#define MULTI_ISA 0
#endif /* Q40 */
/* GG-II Zorro to ISA bridge */
#define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff))
#define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff))
-#ifndef MACH_HAS_ISA
-#define MACH_HAS_ISA 1
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
#else
-#undef MACH_HAS_ISA
-#define MACH_HAS_ISA m
+#undef MULTI_ISA
+#define MULTI_ISA 1
#endif
#endif /* GG2 */
#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
-#ifndef MACH_HAS_ISA
-#define MACH_HAS_ISA 1
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
#else
-#undef MACH_HAS_ISA
-#define MACH_HAS_ISA m
+#undef MULTI_ISA
+#define MULTI_ISA 1
#endif
#endif /* AMIGA_PCMCIA */
-#ifdef MACH_HAS_ISA
+#ifdef CONFIG_ISA
+
+#if MULTI_ISA == 0
+#undef MULTI_ISA
+#endif
#define Q40_ISA (1)
#define GG2_ISA (2)
#define AG_ISA (3)
-#if defined(CONFIG_Q40) && MACH_HAS_ISA==1
+#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
#define ISA_TYPE Q40_ISA
#define ISA_SEX 0
#endif
-#if defined(CONFIG_AMIGA_PCMCIA) && MACH_HAS_ISA==1
+#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE AG_ISA
#define ISA_SEX 1
#endif
-#if defined(CONFIG_GG2) && MACH_HAS_ISA==1
+#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
#define ISA_TYPE GG2_ISA
#define ISA_SEX 0
#endif
-#ifdef CONFIG_ISA
+#ifdef MULTI_ISA
extern int isa_type;
extern int isa_sex;
#define isa_writeb(val,p) out_8(isa_mtb(p),(val))
#define isa_writew(val,p) out_le16(isa_mtw(p),(val))
-#define isa_inb_p(p) ({unsigned char v=isa_inb(p);isa_outb(0,0x80);v;})
-#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_outb(0,0x80);})
+static inline void isa_delay(void)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case Q40_ISA: isa_outb(0,0x80); break;
+#endif
+#ifdef CONFIG_GG2
+ case GG2_ISA: break;
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case AG_ISA: break;
+#endif
+ default: break; /* avoid warnings */
+ }
+}
+
+#define isa_inb_p(p) ({unsigned char v=isa_inb(p);isa_delay();v;})
+#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (buf), (nr))
#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (buf), (nr))
#define isa_outsw(port, buf, nr) \
(ISA_SEX ? raw_outsw(isa_itw(port), (buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (buf), (nr)))
-#endif /* MACH_HAS_ISA */
+#endif /* CONFIG_ISA */
#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
#define insw isa_insw
#define outsb isa_outsb
#define outsw isa_outsw
-#endif /* MACH_HAS_ISA */
-
+#define readb isa_readb
+#define readw isa_readw
+#define writeb isa_writeb
+#define writew isa_writeb
+#endif /* CONFIG_ISA */
#if defined(CONFIG_PCI)
-#define inl(port) in_le32(port)
-#define outl(val,port) out_le32((port),(val))
-
-#define readb(addr) in_8(addr)
-#define readw(addr) in_le16(addr)
-#define readl(addr) in_le32(addr)
+#define inl(port) in_le32(port)
+#define outl(val,port) out_le32((port),(val))
+#define readl(addr) in_le32(addr)
+#define writel(val,addr) out_le32((addr),(val))
+/* those can be defined for both ISA and PCI - it wont work though */
+#define readb(addr) in_8(addr)
+#define readw(addr) in_le16(addr)
#define writeb(val,addr) out_8((addr),(val))
#define writew(val,addr) out_le16((addr),(val))
-#define writel(val,addr) out_le32((addr),(val))
-
#ifndef CONFIG_ISA
#define inb(port) in_8(port)
/*
* kernel with both ISA and PCI compiled in, those have
* conflicting defs for in/out. Simply consider port < 1024
- * ISA and everything else PCI
+ * ISA and everything else PCI. read,write not defined
+ * in this case
*/
#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
-extern void iounmap(void *addr);
-/* Nothing to do */
+/* m68k caches aren't DMA coherent */
+extern void dma_cache_wback_inv(unsigned long start, unsigned long size);
+extern void dma_cache_wback(unsigned long start, unsigned long size);
+extern void dma_cache_inv(unsigned long start, unsigned long size);
-#define dma_cache_inv(_start,_size) do { } while (0)
-#define dma_cache_wback(_start,_size) do { } while (0)
-#define dma_cache_wback_inv(_start,_size) do { } while (0)
#ifndef CONFIG_SUN3
#define IO_SPACE_LIMIT 0xffff
#define _ASM_MC146818RTC_H
#include <linux/config.h>
+#include <asm/atarihw.h>
#ifdef CONFIG_ATARI
/* RTC in Atari machines */
#define RTC_MINYEAR epoch
#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
+atari_outb_p((addr),RTC_PORT(0)); \
+atari_inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
+atari_outb_p((addr),RTC_PORT(0)); \
+atari_outb_p((val),RTC_PORT(1)); \
})
#endif /* CONFIG_ATARI */
}
#define flush_dcache_page(page) do { } while (0)
+#define flush_icache_page(vma,pg) do { } while (0)
/* Push n pages at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
}
}
-#define flush_icache_page(vma,pg) do { } while (0)
+
#ifdef CONFIG_SUN3
#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define swp_entry_to_pte(x) ((pte_t) { (x).val })
-#endif CONFIG_SUN3
+#endif /* CONFIG_SUN3 */
#endif /* !__ASSEMBLY__ */
#include <asm-generic/pgtable.h>
#endif /* !__ASSEMBLY__ */
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
+
#endif /* _M68K_PGTABLE_H */
/*
- * linux/include/asm-m68k/io_native.h
+ * linux/include/asm-m68k/raw_io.h
*
* 10/20/00 RZ: - created from bits of io.h and ide.h to cleanup namespace
*
".previous"
: "=d" (result)
: "a" (sem1)
- : "%d0", "memory");
+ : "memory");
return result;
}
".previous"
: "=d" (result)
: "a" (sem1)
- : "%d0", "memory");
+ : "memory");
return result;
}
* include/asm-m68k/serial.h
*
* currently this seems useful only for a Q40,
- * its an almost exact copy of ../asm/alpha/serial.h
+ * its an almost exact copy of ../asm-alpha/serial.h
*
*/
#define local_bh_disable() cpu_bh_disable(smp_processor_id())
#define local_bh_enable() cpu_bh_enable(smp_processor_id())
+#define __local_bh_enable() local_bh_enable()
#define in_softirq() (local_bh_count(smp_processor_id()) != 0)
struct stat64 {
unsigned char __pad0[6];
unsigned short st_dev;
- unsigned char __pad1[4];
+ unsigned char __pad1[2];
#define STAT64_HAS_BROKEN_ST_INO 1
unsigned long __st_ino;
unsigned char __pad2[6];
unsigned short st_rdev;
- unsigned char __pad3[4];
+ unsigned char __pad3[2];
long long st_size;
unsigned long st_blksize;
__memset_g((s),(c),(count)))
#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, size_t );
/*
* __builtin_memcpy() does not handle page-sized memcpys very well,
* thus following the same assumptions as for page-sized memsets, this
}
#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void * ,const void * ,size_t );
#define memcmp(cs, ct, n) \
(__builtin_constant_p(n) ? \
__builtin_memcmp((cs),(ct),(n)) : \
for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
-// st=fd_inb(virtual_dma_port+4) & 0x80 ;
+/* st=fd_inb(virtual_dma_port+4) & 0x80 ; */
st = *(sun3x_fdc.status_r);
-// if(st != 0xa0)
-// break;
+/* if(st != 0xa0) */
+/* break; */
if((st & 0x80) == 0) {
virtual_dma_count = lcount;
break;
if(virtual_dma_mode)
-// fd_outb(*lptr, virtual_dma_port+5);
+/* fd_outb(*lptr, virtual_dma_port+5); */
*(sun3x_fdc.data_r) = *lptr;
else
-// *lptr = fd_inb(virtual_dma_port+5);
+/* *lptr = fd_inb(virtual_dma_port+5); */
*lptr = *(sun3x_fdc.data_r);
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
-// st = fd_inb(virtual_dma_port+4);
+/* st = fd_inb(virtual_dma_port+4); */
st = *(sun3x_fdc.status_r);
}
register void *_last __asm__ ("d1"); \
__asm__ __volatile__("jbsr " SYMBOL_NAME_STR(resume) \
: "=d" (_last) : "a" (_prev), "a" (_next) \
- : "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
+ : "d0", /* "d1", */ "d2", "d3", "d4", "d5", "a0", "a1"); \
(last) = _last; \
}
case 4: \
__put_user_asm(__pu_err, __pu_val, ptr, l); \
break; \
+ case 8: \
+ __pu_err = __constant_copy_to_user(ptr, &__pu_val, 8); \
+ break; \
default: \
__pu_err = __put_user_bad(); \
break; \
case 4: \
__get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \
break; \
+ case 8: \
+ __gu_err = __constant_copy_from_user(&__gu_val, ptr, 8); \
+ break; \
default: \
__gu_val = 0; \
__gu_err = __get_user_bad(); \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
__asm__ __volatile__ ("trap #0" \
- : "=g" (__res) \
- : "0" (__res) \
- : "%d0"); \
+ : "+d" (__res) ); \
__syscall_return(type,__res); \
}
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
__asm__ __volatile__ ("trap #0" \
- : "=d" (__res) \
- : "0" (__res), "d" (__a) \
- : "%d0"); \
+ : "+d" (__res) \
+ : "d" (__a) ); \
__syscall_return(type,__res); \
}
register long __a __asm__ ("%d1") = (long)(a); \
register long __b __asm__ ("%d2") = (long)(b); \
__asm__ __volatile__ ("trap #0" \
- : "=d" (__res) \
- : "0" (__res), "d" (__a), "d" (__b) \
- : "%d0"); \
+ : "+d" (__res) \
+ : "d" (__a), "d" (__b) \
+ ); \
__syscall_return(type,__res); \
}
register long __b __asm__ ("%d2") = (long)(b); \
register long __c __asm__ ("%d3") = (long)(c); \
__asm__ __volatile__ ("trap #0" \
- : "=d" (__res) \
- : "0" (__res), "d" (__a), "d" (__b), \
+ : "+d" (__res) \
+ : "d" (__a), "d" (__b), \
"d" (__c) \
- : "%d0"); \
+ ); \
__syscall_return(type,__res); \
}
register long __c __asm__ ("%d3") = (long)(c); \
register long __d __asm__ ("%d4") = (long)(d); \
__asm__ __volatile__ ("trap #0" \
- : "=d" (__res) \
- : "0" (__res), "d" (__a), "d" (__b), \
+ : "+d" (__res) \
+ : "d" (__a), "d" (__b), \
"d" (__c), "d" (__d) \
- : "%d0"); \
+ ); \
__syscall_return(type,__res); \
}
register long __d __asm__ ("%d4") = (long)(d); \
register long __e __asm__ ("%d5") = (long)(e); \
__asm__ __volatile__ ("trap #0" \
- : "=d" (__res) \
- : "0" (__res), "d" (__a), "d" (__b), \
+ : "+d" (__res) \
+ : "d" (__a), "d" (__b), \
"d" (__c), "d" (__d), "d" (__e) \
- : "%d0"); \
+ ); \
__syscall_return(type,__res); \
}
-#ifndef _ASM_ZORRO_H
-#define _ASM_ZORRO_H
+#ifndef _ASM_M68K_ZORRO_H
+#define _ASM_M68K_ZORRO_H
#include <asm/raw_io.h>
#define z_readb raw_inb
#define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+/* Values for nocacheflag and cmode */
+#ifndef IOMAP_FULL_CACHING
+#define IOMAP_FULL_CACHING 0
+#define IOMAP_NOCACHE_SER 1
+#define IOMAP_NOCACHE_NONSER 2
+#define IOMAP_WRITETHROUGH 3
+#endif
+
+extern void iounmap(void *addr);
+
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+ int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+
+
+extern inline void *z_remap_nocache_ser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+extern inline void *z_remap_nocache_nonser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_NONSER);
+}
+
+extern inline void *z_remap_writethrough(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *z_remap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+#define z_unmap iounmap
+#define z_iounmap iounmap
+#define z_ioremap z_remap_nocache_ser
+
#endif /* _ASM_ZORRO_H */
#define FDC1 fd_ops->fd_getfdaddr1();
-/*
- * Hack: The floppy drivrer defines this, before including fdreg.h. We use
- * to define FDC2 only one and keep it a static variable in floppy.c.
- */
-#ifdef FDPATCHES
-static int FDC2 = -1;
-#endif
-
#define N_FDC 1 /* do you *really* want a second controller? */
#define N_DRIVE 8
*/
#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* _ASM_FLOPPY_H */
#define FDC1 fd_ops->fd_getfdaddr1();
-/*
- * Hack: The floppy drivrer defines this, before including fdreg.h. We use
- * to define FDC2 only one and keep it a static variable in floppy.c.
- */
-#ifdef FDPATCHES
-static int FDC2=-1;
-#endif
-
#define N_FDC 1 /* do you *really* want a second controller? */
#define N_DRIVE 8
*/
#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* _ASM_FLOPPY_H */
#define CROSS_64KB(a,s) (0)
#endif /* __ASM_PPC_FLOPPY_H */
+
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* __KERNEL__ */
*/
#define FDC1 sun_floppy_init()
-static int FDC2=-1;
-
#define N_FDC 1
#define N_DRIVE 8
#define fd_eject(drive) sparc_eject()
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* !(__ASM_SPARC_FLOPPY_H) */
#define FLOPPY1_TYPE sun_floppy_types[1]
#define FDC1 ((unsigned long)sun_fdc)
-static int FDC2 = -1;
#define N_FDC 1
#define N_DRIVE 8
return sun_floppy_types[0];
}
+#define EXTRA_FLOPPY_PARAMS
+
#endif /* !(__ASM_SPARC64_FLOPPY_H) */
int (*ioctl) (struct inode *, struct file *, unsigned, unsigned long);
int (*check_media_change) (kdev_t);
int (*revalidate) (kdev_t);
+ struct module *owner;
};
/*
char extent[4]; /* 731 */
char parent[2]; /* 721 */
char name[0];
-};
+} __attribute__((packed));
/* high sierra is identical to iso, except that the date is only 6 bytes, and
there is an extra reserved byte after the flags */
char volume_sequence_number [ISODCL (29, 32)]; /* 723 */
unsigned char name_len [ISODCL (33, 33)]; /* 711 */
char name [0];
-};
+} __attribute__((packed));
#define ISOFS_BLOCK_BITS 11
#define ISOFS_BLOCK_SIZE 2048
}
extern int iso_date(char *, int);
+struct inode; /* To make gcc happy */
+
extern int parse_rock_ridge_inode(struct iso_directory_record *, struct inode *);
extern int get_rock_ridge_filename(struct iso_directory_record *, char *, struct inode *);
extern int isofs_name_translate(struct iso_directory_record *, char *, struct inode *);
extern struct dentry *isofs_lookup(struct inode *, struct dentry *);
extern struct buffer_head *isofs_bread(struct inode *, unsigned int, unsigned int);
+extern int isofs_get_blocks(struct inode *, long, struct buffer_head **, unsigned long);
extern struct inode_operations isofs_dir_inode_operations;
extern struct file_operations isofs_dir_operations;
#ifndef _ISO_FS_I
#define _ISO_FS_I
+enum isofs_file_format {
+ isofs_file_normal = 0,
+ isofs_file_sparse = 1,
+ isofs_file_compressed = 2,
+};
+
/*
* iso fs inode data in memory
*/
struct iso_inode_info {
unsigned int i_first_extent;
unsigned char i_file_format;
+ unsigned char i_format_parm[3];
unsigned long i_next_section_ino;
off_t i_section_size;
};
unsigned char s_unhide;
unsigned char s_nosuid;
unsigned char s_nodev;
+ unsigned char s_nocompress;
+
mode_t s_mode;
gid_t s_gid;
uid_t s_uid;
#define PCI_DEVICE_ID_NS_87415 0x0002
#define PCI_DEVICE_ID_NS_87560_LIO 0x000e
#define PCI_DEVICE_ID_NS_87560_USB 0x0012
+#define PCI_DEVICE_ID_NS_83815 0x0020
+#define PCI_DEVICE_ID_NS_83820 0x0022
#define PCI_DEVICE_ID_NS_87410 0xd001
#define PCI_VENDOR_ID_TSENG 0x100c
#define PCI_VENDOR_ID_NETGEAR 0x1385
#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
+#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a
#define PCI_VENDOR_ID_APPLICOM 0x1389
#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
} else {
// printk("VM: __lru_cache_del, found unknown page ?!\n");
}
- DEBUG_LRU_PAGE(page);
}
/**
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