struct cg3_par {
spinlock_t lock;
- struct cg3_regs *regs;
+ struct cg3_regs __iomem *regs;
u32 sw_cmap[((256 * 3) + 3) / 4];
u32 flags;
unsigned transp, struct fb_info *info)
{
struct cg3_par *par = (struct cg3_par *) info->par;
- struct bt_regs *bt = &par->regs->cmap;
+ struct bt_regs __iomem *bt = &par->regs->cmap;
unsigned long flags;
u32 *p32;
u8 *p8;
cg3_blank(int blank, struct fb_info *info)
{
struct cg3_par *par = (struct cg3_par *) info->par;
- struct cg3_regs *regs = par->regs;
+ struct cg3_regs __iomem *regs = par->regs;
unsigned long flags;
u8 val;
}
for (p = cg3_regvals[type]; *p; p += 2) {
- u8 *regp = &((u8 *)par->regs)[p[0]];
+ u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
sbus_writeb(p[1], regp);
}
for (p = cg3_dacvals; *p; p += 2) {
- volatile u8 *regp;
+ volatile u8 __iomem *regp;
- regp = (volatile u8 *)&par->regs->cmap.addr;
+ regp = (volatile u8 __iomem *)&par->regs->cmap.addr;
sbus_writeb(p[0], regp);
- regp = (volatile u8 *)&par->regs->cmap.control;
+ regp = (volatile u8 __iomem *)&par->regs->cmap.control;
sbus_writeb(p[1], regp);
}
}
all->info.var.xres);
all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
- all->par.regs = (struct cg3_regs *)
- sbus_ioremap(&sdev->resource[0], CG3_REGS_OFFSET,
+ all->par.regs = sbus_ioremap(&sdev->resource[0], CG3_REGS_OFFSET,
sizeof(struct cg3_regs), "cg3 regs");
all->info.flags = FBINFO_DEFAULT;
all->info.fbops = &cg3_ops;
#ifdef CONFIG_SPARC32
- all->info.screen_base = (char *)
+ all->info.screen_base = (char __iomem *)
prom_getintdefault(sdev->prom_node, "address", 0);
#endif
if (!all->info.screen_base)
- all->info.screen_base = (char *)
+ all->info.screen_base =
sbus_ioremap(&sdev->resource[0], CG3_RAM_OFFSET,
all->par.fbsize, "cg3 ram");
all->info.par = &all->par;