[PATCH] Add new cache descriptors, as found on P4-M (Centrino)

diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 82abff3c68226966abc746339e4af89e09730bea..69aa8304f79721ab8875ebee9ab96ed4d9584e3b 100644 (file)
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -93,15 +93,17 @@ static struct _cache_table cache_table[] __initdata =
 {
        { 0x06, LVL_1_INST, 8 },
        { 0x08, LVL_1_INST, 16 },
-       { 0x0A, LVL_1_DATA, 8 },
-       { 0x0C, LVL_1_DATA, 16 },
+       { 0x0a, LVL_1_DATA, 8 },
+       { 0x0c, LVL_1_DATA, 16 },
        { 0x22, LVL_3,      512 },
        { 0x23, LVL_3,      1024 },
        { 0x25, LVL_3,      2048 },
        { 0x29, LVL_3,      4096 },
+       { 0x2c, LVL_1_DATA, 32 },
+       { 0x30, LVL_1_INST, 32 },
        { 0x39, LVL_2,      128 },
        { 0x3b, LVL_2,      128 },
-       { 0x3C, LVL_2,      256 },
+       { 0x3c, LVL_2,      256 },
        { 0x41, LVL_2,      128 },
        { 0x42, LVL_2,      256 },
        { 0x43, LVL_2,      512 },
@@ -114,13 +116,15 @@ static struct _cache_table cache_table[] __initdata =
        { 0x71, LVL_TRACE,  16 },
        { 0x72, LVL_TRACE,  32 },
        { 0x79, LVL_2,      128 },
-       { 0x7A, LVL_2,      256 },
-       { 0x7B, LVL_2,      512 },
-       { 0x7C, LVL_2,      1024 },
+       { 0x7a, LVL_2,      256 },
+       { 0x7b, LVL_2,      512 },
+       { 0x7c, LVL_2,      1024 },
        { 0x82, LVL_2,      256 },
        { 0x83, LVL_2,      512 },
        { 0x84, LVL_2,      1024 },
        { 0x85, LVL_2,      2048 },
+       { 0x86, LVL_2,      512 },
+       { 0x87, LVL_2,      1024 },
        { 0x00, 0, 0}
 };