#include <linux/device.h>
#include <asm/hardware.h>
+#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
omap_map_io();
}
-MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
+MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610/1710")
MAINTAINER("Tony Lindgren <tony@atomide.com>")
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
+#include <linux/delay.h>
#include <asm/hardware.h>
+#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc innovator1510_io_desc[] __initdata = {
-{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE,
+{ OMAP1510_FPGA_BASE, OMAP1510_FPGA_START, OMAP1510_FPGA_SIZE,
MT_DEVICE },
};
static struct resource innovator1510_smc91x_resources[] = {
[0] = {
- .start = OMAP1510P1_FPGA_ETHR_START, /* Physical */
- .end = OMAP1510P1_FPGA_ETHR_START + 16,
+ .start = OMAP1510_FPGA_ETHR_START, /* Physical */
+ .end = OMAP1510_FPGA_ETHR_START + 16,
.flags = IORESOURCE_MEM,
},
[1] = {
#ifdef CONFIG_ARCH_OMAP1510
if (cpu_is_omap1510()) {
iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
+ udelay(10); /* Delay needed for FPGA */
/* Dump the Innovator FPGA rev early - useful info for support. */
printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
- fpga_read(OMAP1510P1_FPGA_REV_HIGH),
- fpga_read(OMAP1510P1_FPGA_REV_LOW),
- fpga_read(OMAP1510P1_FPGA_BOARD_REV));
+ fpga_read(OMAP1510_FPGA_REV_HIGH),
+ fpga_read(OMAP1510_FPGA_REV_LOW),
+ fpga_read(OMAP1510_FPGA_BOARD_REV));
}
#endif
#ifdef CONFIG_ARCH_OMAP1610
#include <linux/device.h>
#include <asm/hardware.h>
+#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
*
* Modified from board-generic.c
*
+ * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
+ * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
#include <linux/device.h>
#include <asm/hardware.h>
+#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
- MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
+ MAINTAINER("Kevin Hilman <kjh@hilman.org>")
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_perseus2_map_io)
#include <linux/spinlock.h>
#include <asm/hardware.h>
+#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
}
}
-module_init(omap_bus_init);
+postcore_initcall(omap_bus_init);
module_exit(omap_bus_exit);
MODULE_DESCRIPTION("Virtual bus for OMAP");
}, {
.name = "ck_gen1",
.flags = CK_RATEF | CK_IDLEF,
- .rate_reg = CK_DPLL1,
+ .rate_reg = DPLL_CTL,
.idle_reg = ARM_IDLECT1,
.idle_shift = IDLDPLL_ARM,
.parent = OMAP_CLKIN,
omap_writew(0x1000, ARM_SYSST);
#if defined(CONFIG_OMAP_ARM_30MHZ)
omap_writew(0x1555, ARM_CKCTL);
- omap_writew(0x2290, DPLL_CTL_REG);
+ omap_writew(0x2290, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_60MHZ)
omap_writew(0x1005, ARM_CKCTL);
- omap_writew(0x2290, DPLL_CTL_REG);
+ omap_writew(0x2290, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_96MHZ)
omap_writew(0x1005, ARM_CKCTL);
- omap_writew(0x2410, DPLL_CTL_REG);
+ omap_writew(0x2410, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_120MHZ)
omap_writew(0x110a, ARM_CKCTL);
- omap_writew(0x2510, DPLL_CTL_REG);
+ omap_writew(0x2510, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_168MHZ)
omap_writew(0x110f, ARM_CKCTL);
- omap_writew(0x2710, DPLL_CTL_REG);
+ omap_writew(0x2710, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_182MHZ) && defined(CONFIG_ARCH_OMAP730)
omap_writew(0x250E, ARM_CKCTL);
- omap_writew(0x2710, DPLL_CTL_REG);
+ omap_writew(0x2710, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_192MHZ) && (defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912))
omap_writew(0x150f, ARM_CKCTL);
if (crystal_type == 2) {
source_clock = 13; /* MHz */
- omap_writew(0x2510, DPLL_CTL_REG);
+ omap_writew(0x2510, DPLL_CTL);
} else
- omap_writew(0x2810, DPLL_CTL_REG);
+ omap_writew(0x2810, DPLL_CTL);
#elif defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730)
omap_writew(0x250E, ARM_CKCTL);
- omap_writew(0x2790, DPLL_CTL_REG);
+ omap_writew(0x2790, DPLL_CTL);
#else
#error "OMAP MHZ not set, please run make xconfig"
#endif
#ifdef CONFIG_MACH_OMAP_PERSEUS2
/* Select slicer output as OMAP input clock */
- omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL_REG) & ~0x1, OMAP730_PCC_UPLD_CTRL_REG);
+ omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off some other junk the bootloader might have turned on */
#include <asm/arch/board.h>
#include <asm/io.h>
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP revision check
+ *
+ * Since we use the cpu_is_omapnnnn() macros, there's a chance that a board
+ * switches to an updated core. We want to print out the OMAP revision early.
+ *
+ * We use the system_serial registers for the revision information so we
+ * can see it in /proc/cpuinfo.
+ *
+ * If the OMAP detection gets more complicated, we may want to expand this
+ * to store the OMAP version and replace the current cpu_is_omapnnnn() macros.
+ *
+ * ----------------------------------------------------------------------------
+ */
+static void __init omap_check_revision(void)
+{
+ system_serial_high = omap_readl(OMAP_ID_BASE);
+ system_serial_low = OMAP_ID_REG;
+ system_rev = (OMAP_ID_REG >> ID_SHIFT) & ID_MASK;
+
+ printk("OMAP revision: %d.%d (0x%08x) id: 0x%08x detected as OMAP-",
+ (system_serial_high >> 20) & 0xf,
+ (system_serial_high >> 16) & 0xf,
+ system_serial_high, system_serial_low);
+
+ switch (system_rev) {
+ case OMAP_ID_730:
+ printk("730\n");
+ system_rev = 0x730;
+ break;
+ case OMAP_ID_1510:
+ printk("1510\n");
+ system_rev = 0x1510;
+ break;
+ case OMAP_ID_1610:
+ printk("1610\n");
+ system_rev = 0x1610;
+ break;
+ case OMAP_ID_1710:
+ printk("1710\n");
+ system_rev = 0x1710;
+ break;
+ case OMAP_ID_5912:
+ printk("5912/1611B\n");
+ system_rev = 0x5912;
+ break;
+ default:
+ printk("unknown, please add support!\n");
+ }
+}
+
/*
* ----------------------------------------------------------------------------
* OMAP I/O mapping
static struct map_desc omap5912_io_desc[] __initdata = {
{ OMAP5912_DSP_BASE, OMAP5912_DSP_START, OMAP5912_DSP_SIZE, MT_DEVICE },
{ OMAP5912_DSPREG_BASE, OMAP5912_DSPREG_START, OMAP5912_DSPREG_SIZE, MT_DEVICE },
- { OMAP5912_SRAM_BASE, OMAP5912_SRAM_START, OMAP5912_SRAM_SIZE, MT_DEVICE }
+/*
+ * The OMAP5912 has 250kByte internal SRAM. Because the mapping is baseed on page
+ * size (4kByte), it seems that the last 2kByte (=0x800) of the 250kByte are not mapped.
+ * Add additional 2kByte (0x800) so that the last page is mapped and the last 2kByte
+ * can be used.
+ */
+ { OMAP5912_SRAM_BASE, OMAP5912_SRAM_START, OMAP5912_SRAM_SIZE + 0x800, MT_DEVICE }
};
#endif
/* We have to initialize the IO space mapping before we can run
* cpu_is_omapxxx() macros. */
iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
+ omap_check_revision();
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
* on a Posted Write in the TIPB Bridge".
*/
- omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG);
- omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG);
+ omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
+ omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
/* Must init clocks early to assure that timer interrupt works
*/
{
u16 w;
- w = omap_readw(OMAP_DMA_CSDP_REG(lch));
+ w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~0x03;
w |= data_type;
- omap_writew(w, OMAP_DMA_CSDP_REG(lch));
+ omap_writew(w, OMAP_DMA_CSDP(lch));
- w = omap_readw(OMAP_DMA_CCR_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
w |= 1 << 5;
- omap_writew(w, OMAP_DMA_CCR_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR(lch));
- w = omap_readw(OMAP_DMA_CCR2_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR2(lch));
w &= ~(1 << 2);
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
w |= 1 << 2;
- omap_writew(w, OMAP_DMA_CCR2_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR2(lch));
- omap_writew(elem_count, OMAP_DMA_CEN_REG(lch));
- omap_writew(frame_count, OMAP_DMA_CFN_REG(lch));
+ omap_writew(elem_count, OMAP_DMA_CEN(lch));
+ omap_writew(frame_count, OMAP_DMA_CFN(lch));
}
+void omap_set_dma_constant_fill(int lch, u32 color)
+{
+ u16 w;
+
+#ifdef CONFIG_DEBUG_KERNEL
+ if (omap_dma_in_1510_mode) {
+ printk(KERN_ERR "OMAP DMA constant fill not available in 1510 mode.");
+ BUG();
+ return;
+ }
+#endif
+ w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
+ w |= 0x01;
+ omap_writew(w, OMAP_DMA_CCR2(lch));
+
+ omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
+ omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
+
+ w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
+ w |= 1; /* Channel type G */
+ omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
+}
+
+void omap_set_dma_transparent_copy(int lch, u32 color)
+{
+ u16 w;
+
+#ifdef CONFIG_DEBUG_KERNEL
+ if (omap_dma_in_1510_mode) {
+ printk(KERN_ERR "OMAP DMA transparent copy not available in 1510 mode.");
+ BUG();
+ }
+#endif
+ w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
+ w |= 0x02;
+ omap_writew(w, OMAP_DMA_CCR2(lch));
+
+ omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
+ omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
+
+ w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
+ w |= 1; /* Channel type G */
+ omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
+}
void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start)
{
u16 w;
- w = omap_readw(OMAP_DMA_CSDP_REG(lch));
+ w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~(0x1f << 2);
w |= src_port << 2;
- omap_writew(w, OMAP_DMA_CSDP_REG(lch));
+ omap_writew(w, OMAP_DMA_CSDP(lch));
- w = omap_readw(OMAP_DMA_CCR_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(0x03 << 12);
w |= src_amode << 12;
- omap_writew(w, OMAP_DMA_CCR_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR(lch));
+
+ omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
+ omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
+}
+
+void omap_set_dma_src_index(int lch, int eidx, int fidx)
+{
+ omap_writew(eidx, OMAP_DMA_CSEI(lch));
+ omap_writew(fidx, OMAP_DMA_CSFI(lch));
+}
+
+void omap_set_dma_src_data_pack(int lch, int enable)
+{
+ u16 w;
+
+ w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
+ w |= enable ? (1 << 6) : 0;
+ omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+void omap_set_dma_src_burst_mode(int lch, int burst_mode)
+{
+ u16 w;
- omap_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch));
- omap_writew(src_start, OMAP_DMA_CSSA_L_REG(lch));
+ w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
+ switch (burst_mode) {
+ case OMAP_DMA_DATA_BURST_4:
+ w |= (0x01 << 7);
+ break;
+ case OMAP_DMA_DATA_BURST_8:
+ w |= (0x03 << 7);
+ break;
+ default:
+ printk(KERN_ERR "Invalid DMA burst mode\n");
+ BUG();
+ return;
+ }
+ omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
{
u16 w;
- w = omap_readw(OMAP_DMA_CSDP_REG(lch));
+ w = omap_readw(OMAP_DMA_CSDP(lch));
w &= ~(0x1f << 9);
w |= dest_port << 9;
- omap_writew(w, OMAP_DMA_CSDP_REG(lch));
+ omap_writew(w, OMAP_DMA_CSDP(lch));
- w = omap_readw(OMAP_DMA_CCR_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~(0x03 << 14);
w |= dest_amode << 14;
- omap_writew(w, OMAP_DMA_CCR_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR(lch));
+
+ omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
+ omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
+}
+
+void omap_set_dma_dest_index(int lch, int eidx, int fidx)
+{
+ omap_writew(eidx, OMAP_DMA_CDEI(lch));
+ omap_writew(fidx, OMAP_DMA_CDFI(lch));
+}
+
+void omap_set_dma_dest_data_pack(int lch, int enable)
+{
+ u16 w;
- omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch));
- omap_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch));
+ w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
+ w |= enable ? (1 << 13) : 0;
+ omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+void omap_set_dma_dest_burst_mode(int lch, int burst_mode)
+{
+ u16 w;
+
+ w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
+ switch (burst_mode) {
+ case OMAP_DMA_DATA_BURST_4:
+ w |= (0x01 << 14);
+ break;
+ case OMAP_DMA_DATA_BURST_8:
+ w |= (0x03 << 14);
+ break;
+ default:
+ printk(KERN_ERR "Invalid DMA burst mode\n");
+ BUG();
+ return;
+ }
+ omap_writew(w, OMAP_DMA_CSDP(lch));
}
void omap_start_dma(int lch)
/* Enable the queue, if needed so. */
if (next_lch != -1) {
/* Clear the STOP_LNK bits */
- w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
+ w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
w &= ~(1 << 14);
- omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
- w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
+ omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
+ w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
w &= ~(1 << 14);
- omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
+ omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
/* And set the ENABLE_LNK bits */
omap_writew(next_lch | (1 << 15),
- OMAP_DMA_CLNK_CTRL_REG(lch));
+ OMAP_DMA_CLNK_CTRL(lch));
/* The loop case */
if (dma_chan[next_lch].next_lch == lch)
omap_writew(lch | (1 << 15),
- OMAP_DMA_CLNK_CTRL_REG(next_lch));
+ OMAP_DMA_CLNK_CTRL(next_lch));
/* Read CSR to make sure it's cleared. */
- w = omap_readw(OMAP_DMA_CSR_REG(next_lch));
+ w = omap_readw(OMAP_DMA_CSR(next_lch));
/* Enable some nice interrupts. */
omap_writew(dma_chan[next_lch].enabled_irqs,
- OMAP_DMA_CICR_REG(next_lch));
+ OMAP_DMA_CICR(next_lch));
dma_chan[next_lch].flags |= OMAP_DMA_ACTIVE;
}
}
/* Read CSR to make sure it's cleared. */
- w = omap_readw(OMAP_DMA_CSR_REG(lch));
+ w = omap_readw(OMAP_DMA_CSR(lch));
/* Enable some nice interrupts. */
- omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch));
+ omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
- w = omap_readw(OMAP_DMA_CCR_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR(lch));
w |= OMAP_DMA_CCR_EN;
- omap_writew(w, OMAP_DMA_CCR_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
int next_lch;
/* Disable all interrupts on the channel */
- omap_writew(0, OMAP_DMA_CICR_REG(lch));
+ omap_writew(0, OMAP_DMA_CICR(lch));
if (omap_dma_in_1510_mode()) {
- w = omap_readw(OMAP_DMA_CCR_REG(lch));
+ w = omap_readw(OMAP_DMA_CCR(lch));
w &= ~OMAP_DMA_CCR_EN;
- omap_writew(w, OMAP_DMA_CCR_REG(lch));
+ omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
return;
}
* According to thw HW spec, enabling the STOP_LNK bit
* resets the CCR_EN bit at the same time.
*/
- w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
+ w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
w |= (1 << 14);
- w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
+ w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
if (next_lch != -1) {
- omap_writew(0, OMAP_DMA_CICR_REG(next_lch));
- w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
+ omap_writew(0, OMAP_DMA_CICR(next_lch));
+ w = omap_readw(OMAP_DMA_CLNK_CTRL(next_lch));
w |= (1 << 14);
- w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
+ w = omap_writew(w, OMAP_DMA_CLNK_CTRL(next_lch));
dma_chan[next_lch].flags &= ~OMAP_DMA_ACTIVE;
}
}
csr = dma_chan[ch].saved_csr;
dma_chan[ch].saved_csr = 0;
} else
- csr = omap_readw(OMAP_DMA_CSR_REG(ch));
+ csr = omap_readw(OMAP_DMA_CSR(ch));
if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
dma_chan[ch + 6].saved_csr = csr >> 7;
csr &= 0x7f;
}
/* Disable the 1510 compatibility mode and set the sync device
* id. */
- omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch));
+ omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
} else {
- omap_writew(dev_id, OMAP_DMA_CCR_REG(free_ch));
+ omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
}
*dma_ch_out = free_ch;
spin_unlock_irqrestore(&dma_chan_lock, flags);
/* Disable all DMA interrupts for the channel. */
- omap_writew(0, OMAP_DMA_CICR_REG(ch));
+ omap_writew(0, OMAP_DMA_CICR(ch));
/* Make sure the DMA transfer is stopped. */
- omap_writew(0, OMAP_DMA_CCR_REG(ch));
+ omap_writew(0, OMAP_DMA_CCR(ch));
}
int omap_dma_in_1510_mode(void)
enable_1510_mode = 1;
} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
printk(KERN_INFO "OMAP DMA hardware version %d\n",
- omap_readw(OMAP_DMA_HW_ID_REG));
+ omap_readw(OMAP_DMA_HW_ID));
printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
- (omap_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_0_L_REG),
- (omap_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_1_L_REG),
- omap_readw(OMAP_DMA_CAPS_2_REG), omap_readw(OMAP_DMA_CAPS_3_REG),
- omap_readw(OMAP_DMA_CAPS_4_REG));
+ (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L),
+ (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L),
+ omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
+ omap_readw(OMAP_DMA_CAPS_4));
if (!enable_1510_mode) {
u16 w;
/* Disable OMAP 3.0/3.1 compatibility mode. */
- w = omap_readw(OMAP_DMA_GSCR_REG);
+ w = omap_readw(OMAP_DMA_GSCR);
w |= 1 << 3;
- omap_writew(w, OMAP_DMA_GSCR_REG);
+ omap_writew(w, OMAP_DMA_GSCR);
dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
} else
dma_chan_count = 9;
EXPORT_SYMBOL(omap_free_dma);
EXPORT_SYMBOL(omap_start_dma);
EXPORT_SYMBOL(omap_stop_dma);
+
EXPORT_SYMBOL(omap_set_dma_transfer_params);
+EXPORT_SYMBOL(omap_set_dma_constant_fill);
+EXPORT_SYMBOL(omap_set_dma_transparent_copy);
+
EXPORT_SYMBOL(omap_set_dma_src_params);
+EXPORT_SYMBOL(omap_set_dma_src_index);
+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
+
EXPORT_SYMBOL(omap_set_dma_dest_params);
+EXPORT_SYMBOL(omap_set_dma_dest_index);
+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
+
EXPORT_SYMBOL(omap_dma_link_lch);
EXPORT_SYMBOL(omap_dma_unlink_lch);
irq -= IH_FPGA_BASE;
if (irq < 8)
- __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO)
- & ~(1 << irq)), OMAP1510P1_FPGA_IMR_LO);
+ __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
+ & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
else if (irq < 16)
- __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
- & ~(1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
+ __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
+ & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
else
__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
& ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
static inline u32 get_fpga_unmasked_irqs(void)
{
return
- ((__raw_readb(OMAP1510P1_FPGA_ISR_LO) &
- __raw_readb(OMAP1510P1_FPGA_IMR_LO))) |
- ((__raw_readb(OMAP1510P1_FPGA_ISR_HI) &
- __raw_readb(OMAP1510P1_FPGA_IMR_HI)) << 8) |
+ ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
+ __raw_readb(OMAP1510_FPGA_IMR_LO))) |
+ ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
+ __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
((__raw_readb(INNOVATOR_FPGA_ISR2) &
__raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
}
irq -= IH_FPGA_BASE;
if (irq < 8)
- __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO) | (1 << irq)),
- OMAP1510P1_FPGA_IMR_LO);
+ __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
+ OMAP1510_FPGA_IMR_LO);
else if (irq < 16)
- __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
- | (1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
+ __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
+ | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
else
__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
| (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
{
int i;
- __raw_writeb(0, OMAP1510P1_FPGA_IMR_LO);
- __raw_writeb(0, OMAP1510P1_FPGA_IMR_HI);
+ __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
+ __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
__raw_writeb(0, INNOVATOR_FPGA_IMR2);
for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/pm.h>
#include <asm/mach/irq.h>
#include <asm/io.h>
#define OMAP730_GPIO_INT_MASK 0x10
#define OMAP730_GPIO_INT_STATUS 0x14
-#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
+#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
struct gpio_bank {
u32 base;
reg += OMAP730_GPIO_DIR_CONTROL;
break;
}
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (is_input)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
void omap_set_gpio_direction(int gpio, int is_input)
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT_REG;
- l = omap_readl(reg);
+ reg += OMAP_MPUIO_OUTPUT;
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DATA_OUTPUT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
BUG();
return;
}
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
void omap_set_gpio_dataout(int gpio, int enable)
BUG();
return -1;
}
- return (omap_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+ return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}
static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE_REG;
- l = omap_readl(reg);
+ reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_1610:
edge &= 0x03;
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
gpio &= 0x07;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
l |= edge << (gpio << 1);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_CONTROL;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
default:
BUG();
switch (bank->method) {
case METHOD_MPUIO:
- l = omap_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG);
+ l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1510:
- l = omap_readl(reg + OMAP1510_GPIO_INT_CONTROL);
+ l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_EDGE_CTRL2;
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
- return (omap_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
+ return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
case METHOD_GPIO_730:
- l = omap_readl(reg + OMAP730_GPIO_INT_CONTROL);
+ l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
default:
BUG();
return;
}
- omap_writel(1 << get_gpio_index(gpio), reg);
+ __raw_writel(1 << get_gpio_index(gpio), reg);
}
static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_MASKIT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_MASK;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_MASK;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
BUG();
return;
}
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
int omap_request_gpio(int gpio)
/* Claim the pin for the ARM */
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
- omap_writel(omap_readl(reg) | (1 << get_gpio_index(gpio)), reg);
+ __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
}
#endif
spin_unlock(&bank->lock);
isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
#endif
for (;;) {
- u32 isr = omap_readl(isr_reg);
+ u32 isr = __raw_readl(isr_reg);
unsigned int gpio_irq;
if (!isr)
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510)
- omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
+ __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610)
- omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
+ __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730)
- omap_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
+ __raw_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
#endif
}
bank = &gpio_bank[i];
bank->reserved_map = 0;
+ bank->base = IO_ADDRESS(bank->base);
spin_lock_init(&bank->lock);
if (bank->method == METHOD_MPUIO) {
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
}
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510) {
- omap_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
- omap_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
+ __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
+ __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
}
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610) {
- omap_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
- omap_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+ __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
+ __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
}
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730) {
- omap_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
- omap_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
+ __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
+ __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
gpio_count = 32; /* 730 has 32-bit GPIOs */
}
}
/* Enable system clock for GPIO module.
- * The CAM_CLK_CTRL_REG *is* really the right place. */
+ * The CAM_CLK_CTRL *is* really the right place. */
if (cpu_is_omap1610())
- omap_writel(omap_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG);
+ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
return 0;
}
return 0;
}
-EXPORT_SYMBOL(omap_gpio_init);
EXPORT_SYMBOL(omap_request_gpio);
EXPORT_SYMBOL(omap_free_gpio);
+EXPORT_SYMBOL(omap_set_gpio_direction);
+EXPORT_SYMBOL(omap_set_gpio_dataout);
+EXPORT_SYMBOL(omap_get_gpio_datain);
+EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
arch_initcall(omap_gpio_init);
static void omap_ack_irq(unsigned int irq)
{
if (irq > 31)
- omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG);
+ omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
- omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG);
+ omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}
static void omap_mask_irq(unsigned int irq)
int bank = IRQ_BANK(irq);
u32 l;
- l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
+ l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l |= 1 << IRQ_BIT(irq);
- omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
+ omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_unmask_irq(unsigned int irq)
int bank = IRQ_BANK(irq);
u32 l;
- l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
+ l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(irq));
- omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
+ omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_mask_ack_irq(unsigned int irq)
/* FIQ is only available on bank 0 interrupts */
fiq = bank ? 0 : (fiq & 0x1);
val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
- offset = IRQ_ILR0 + IRQ_BIT(irq) * 0x4;
+ offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
irq_bank_writel(val, bank, offset);
}
/* Mask and clear all interrupts */
for (i = 0; i < irq_bank_count; i++) {
- irq_bank_writel(~0x0, i, IRQ_MIR);
- irq_bank_writel(0x0, i, IRQ_ITR);
+ irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
+ irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
}
/* Clear any pending interrupts */
- irq_bank_writel(0x03, 0, IRQ_CONTROL_REG);
- irq_bank_writel(0x03, 1, IRQ_CONTROL_REG);
+ irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
+ irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
val &= ~0xff;
omap_writel(val, OCPI_SEC);
- val = omap_readl(OCPI_SEC);
- val |= 0;
- omap_writel(val, OCPI_SEC);
-
- val = omap_readl(OCPI_SINT0);
- val |= 0;
- omap_writel(val, OCPI_SINT1);
-
return 0;
}
EXPORT_SYMBOL(ocpi_enable);
projects / history.git / commitdiff