#define E1000_RXBUFFER_16384 16384
/* How many Tx Descriptors do we need to call netif_wake_queue ? */
-#define E1000_TX_QUEUE_WAKE 16
+#define E1000_TX_QUEUE_WAKE 16
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
+#define E1000_RX_BUFFER_WRITE 16
#define E1000_JUMBO_PBA 0x00000028
#define E1000_DEFAULT_PBA 0x00000030
uint16_t link_duplex;
spinlock_t stats_lock;
atomic_t irq_sem;
- boolean_t rx_csum;
/* TX */
struct e1000_desc_ring tx_ring;
uint64_t hw_csum_err;
uint64_t hw_csum_good;
uint32_t rx_int_delay;
+ boolean_t rx_csum;
/* OS defined structs */
struct net_device *netdev;
{
uint32_t rctl;
- /* Setup the Receive Control Register */
- rctl = E1000_RCTL_EN | E1000_RCTL_BAM |
- E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
- (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
+ rctl = E1000_READ_REG(&adapter->hw, RCTL);
+
+ rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
+
+ rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
+ E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
+ (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
if(adapter->hw.tbi_compatibility_on == 1)
rctl |= E1000_RCTL_SBP;
+ else
+ rctl &= ~E1000_RCTL_SBP;
+ rctl &= ~(E1000_RCTL_SZ_4096);
switch (adapter->rx_buffer_len) {
case E1000_RXBUFFER_2048:
default:
rctl |= E1000_RCTL_SZ_2048;
+ rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
break;
case E1000_RXBUFFER_4096:
rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
- /* move tail */
- E1000_WRITE_REG(&adapter->hw, RDT, i);
+ if(!(i % E1000_RX_BUFFER_WRITE))
+ E1000_WRITE_REG(&adapter->hw, RDT, i);
i = (i + 1) % rx_ring->count;
}