Update starfire and tulip net drivers to use new PCI API functions

pci_set_mwi and pci_clear_mwi.

diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index bb1d20a923595b2006327e8ec29b199fce5c3807..36d6ff62f074d44219d24318e7c05bf5c2f7b0ee 100644 (file)
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -96,9 +96,10 @@
        LK1.3.5 (jgarzik)
        - ethtool NWAY_RST, GLINK, [GS]MSGLVL support
 
-       LK1.3.6 (Ion Badulescu)
-       - Sparc64 support and fixes
-       - Better stats and error handling
+       LK1.3.6:
+       - Sparc64 support and fixes (Ion Badulescu)
+       - Better stats and error handling (Ion Badulescu)
+       - Use new pci_set_mwi() PCI API function (jgarzik)
 
 TODO:
        - implement tx_timeout() properly
@@ -107,7 +108,7 @@ TODO:
 
 #define DRV_NAME       "starfire"
 #define DRV_VERSION    "1.03+LK1.3.6"
-#define DRV_RELDATE    "March 6, 2002"
+#define DRV_RELDATE    "March 7, 2002"
 
 #include <linux/version.h>
 #include <linux/module.h>
@@ -617,8 +618,10 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
        long ioaddr;
        int drv_flags, io_size;
        int boguscnt;
+#ifndef HAVE_PCI_SET_MWI
        u16 cmd;
        u8 cache;
+#endif
 
 /* when built into the kernel, we only print version if device is found */
 #ifndef MODULE
@@ -665,6 +668,9 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
 
        pci_set_master(pdev);
 
+#ifdef HAVE_PCI_SET_MWI
+       pci_set_mwi(pdev);
+#else
        /* enable MWI -- it vastly improves Rx performance on sparc64 */
        pci_read_config_word(pdev, PCI_COMMAND, &cmd);
        cmd |= PCI_COMMAND_INVALIDATE;
@@ -679,6 +685,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
                                      SMP_CACHE_BYTES >> 2);
        }
+#endif
 
 #ifdef ZEROCOPY
        /* Starfire can do SG and TCP/UDP checksumming */

diff --git a/drivers/net/tulip/ChangeLog b/drivers/net/tulip/ChangeLog
index 3111685c2da476caffe22da4e009b56d5d664b65..67b4289c3ceed6b817ad7c21f26ddc753bfcb942 100644 (file)
--- a/drivers/net/tulip/ChangeLog
+++ b/drivers/net/tulip/ChangeLog
@@ -1,3 +1,10 @@
+2002-03-07  Jeff Garzik  <jgarzik@mandrakesoft.com>
+
+       * tulip_core (tulip_mwi_config): Use new PCI API functions
+       for enabling and disabled Memory-Write-Invalidate
+       PCI transaction.
+       Fix bugs in tulip MWI config also.
+
 2002-01-28  Stefan Rompf  <srompf@isg.de>,
             Jeff Garzik  <jgarzik@mandrakesoft.com>
 

diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index b414978d22e80da25ac27ff5376e558398792775..7b0a44f48e8d6665ae5c7c56c008447d8b2b6f23 100644 (file)
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -15,8 +15,8 @@
 */
 
 #define DRV_NAME       "tulip"
-#define DRV_VERSION    "1.1.11"
-#define DRV_RELDATE    "Feb 08, 2002"
+#define DRV_VERSION    "1.1.12"
+#define DRV_RELDATE    "Mar 07, 2002"
 
 #include <linux/config.h>
 #include <linux/module.h>
@@ -1164,7 +1164,7 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
 {
        struct tulip_private *tp = dev->priv;
        u8 cache;
-       u16 pci_command, new_command;
+       u16 pci_command;
        u32 csr0;
 
        if (tulip_debug > 3)
@@ -1172,24 +1172,6 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
 
        tp->csr0 = csr0 = 0;
 
-       /* check for sane cache line size. from acenic.c. */
-       pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
-       if ((cache << 2) != SMP_CACHE_BYTES) {
-               printk(KERN_WARNING "%s: PCI cache line size set incorrectly "
-                      "(%i bytes) by BIOS/FW, correcting to %i\n",
-                      pdev->slot_name, (cache << 2), SMP_CACHE_BYTES);
-               pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
-                                     SMP_CACHE_BYTES >> 2);
-               udelay(5);
-       }
-
-       /* read cache line size again, hardware may not have accepted
-        * our cache line size change
-        */
-       pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
-       if (!cache)
-               goto out;
-
        /* if we have any cache line size at all, we can do MRM */
        csr0 |= MRM;
 
@@ -1200,15 +1182,19 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
        /* set or disable MWI in the standard PCI command bit.
         * Check for the case where  mwi is desired but not available
         */
+       if (csr0 & MWI) pci_set_mwi(pdev);
+       else            pci_clear_mwi(pdev);
+
+       /* read result from hardware (in case bit refused to enable) */
        pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
-       if (csr0 & MWI) new_command = pci_command | PCI_COMMAND_INVALIDATE;
-       else            new_command = pci_command & ~PCI_COMMAND_INVALIDATE;
-       if (new_command != pci_command) {
-               pci_write_config_word(pdev, PCI_COMMAND, new_command);
-               udelay(5);
-               pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
-               if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
-                       csr0 &= ~MWI;
+       if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
+               csr0 &= ~MWI;
+
+       /* if cache line size hardwired to zero, no MWI */
+       pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
+       if ((csr0 & MWI) && (cache == 0)) {
+               csr0 &= ~MWI;
+               pci_clear_mwi(pdev);
        }
 
        /* assign per-cacheline-size cache alignment and
@@ -1225,20 +1211,29 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
                csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
                break;
        default:
-               goto out;
+               cache = 0;
+               break;
        }
 
-       tp->csr0 = csr0;
-       goto out;
+       /* if we have a good cache line size, we by now have a good
+        * csr0, so save it and exit
+        */
+       if (cache)
+               goto out;
 
+       /* we don't have a good csr0 or cache line size, disable MWI */
        if (csr0 & MWI) {
-               pci_command &= ~PCI_COMMAND_INVALIDATE;
-               pci_write_config_word(pdev, PCI_COMMAND, pci_command);
+               pci_clear_mwi(pdev);
                csr0 &= ~MWI;
        }
-       tp->csr0 = csr0 | (8 << BurstLenShift) | (1 << CALShift);
+
+       /* sane defaults for burst length and cache alignment
+        * originally from de4x5 driver
+        */
+       csr0 |= (8 << BurstLenShift) | (1 << CALShift);
 
 out:
+       tp->csr0 = csr0;
        if (tulip_debug > 2)
                printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
                       pdev->slot_name, cache, csr0);