mov out3 = in3 // copy arg3
;;
mov loc3 = psr // save psr
- ;;
+ ;;
mov loc4=ar.rsc // save RSE configuration
dep.z loc2=loc2,0,61 // convert pal entry point to physical
;;
*/
identify_cpu(my_cpu_info);
+#ifdef CONFIG_MCKINLEY
+ {
+#define FEATURE_SET 16
+ struct ia64_pal_retval iprv;
+
+ if (my_cpu_data->family == 0x1f) {
+
+ PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
+
+ if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) {
+
+ PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
+ (iprv.v1 | 0x80), FEATURE_SET, 0);
+ }
+ }
+ }
+#endif
+
/* Clear the stack memory reserved for pt_regs: */
memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
* shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
* be fine).
*/
- ia64_set_dcr( IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
+ ia64_set_dcr( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC);
#ifndef CONFIG_SMP
ia64_set_fpu_owner(0);
{
if (!access_ok(VERIFY_WRITE, to, sizeof(siginfo_t)))
return -EFAULT;
- if (from->si_code < 0)
- return __copy_to_user(to, from, sizeof(siginfo_t));
- else {
+ if (from->si_code < 0) {
+ if (__copy_to_user(to, from, sizeof(siginfo_t)))
+ return -EFAULT;
+ } else {
int err;
/*
#define __NR_futex 1230
#define __NR_sched_setaffinity 1231
#define __NR_sched_getaffinity 1232
+#define __NR_security 1233
#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)