[PATCH] Add AMD K8 support to 2.5.53.

Add support for the AMD Opteron/Athlon64/Hammer/K8 line to the 32bit
kernel.

Mostly just reusing Athlon code with some changed CPU model checks.
The Hammer has model number 15.

I also fixed rmb()/mb() to use the SSE2 mfence/lfence instructions
on P4 and Hammer. They are somewhat cheaper than the locked cycle.

diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig
index 514b8ce72a5dcc371a233d414009d35c77f88f15..68a522c910b8f7bbcc7fc3d356e91db1d09e529f 100644 (file)
--- a/arch/i386/Kconfig
+++ b/arch/i386/Kconfig
@@ -140,6 +140,13 @@ config MK7
          some extended instructions, and passes appropriate optimization
          flags to GCC.
 
+config MK8
+       bool "Opteron/Athlon64/Hammer/K8"
+       help
+         Select this for an AMD Opteron or Athlon64 Hammer-family processor.  Enables
+         use of some extended instructions, and passes appropriate optimization
+         flags to GCC.
+
 config MELAN
        bool "Elan"
 
@@ -200,7 +207,7 @@ config X86_L1_CACHE_SHIFT
        int
        default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MCYRIXIII || MK6 || MPENTIUMIII || M686 || M586MMX || M586TSC || M586
        default "4" if MELAN || M486 || M386
-       default "6" if MK7
+       default "6" if MK7 || MK8
        default "7" if MPENTIUM4
 
 config RWSEM_GENERIC_SPINLOCK
@@ -255,12 +262,12 @@ config X86_ALIGNMENT_16
 
 config X86_TSC
        bool
-       depends on MWINCHIP3D || MWINCHIP2 || MCRUSOE || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || M686 || M586MMX || M586TSC
+       depends on MWINCHIP3D || MWINCHIP2 || MCRUSOE || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || M686 || M586MMX || M586TSC || MK8
        default y
 
 config X86_GOOD_APIC
        bool
-       depends on MK7 || MPENTIUM4 || MPENTIUMIII || M686 || M586MMX
+       depends on MK7 || MPENTIUM4 || MPENTIUMIII || M686 || M586MMX || MK8
        default y
 
 config X86_INTEL_USERCOPY
@@ -270,7 +277,7 @@ config X86_INTEL_USERCOPY
 
 config X86_USE_PPRO_CHECKSUM
        bool
-       depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || M686
+       depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || M686 || MK8
        default y
 
 config X86_USE_3DNOW
@@ -288,6 +295,11 @@ config X86_PREFETCH
        depends on MPENTIUMIII || MP4
        default y
 
+config X86_SSE2
+        bool
+       depends on MK8 || MPENTIUM4
+       default y
+
 config HUGETLB_PAGE
        bool "Huge TLB Page Support"
        help

diff --git a/arch/i386/Makefile b/arch/i386/Makefile
index 383bc1dfec295cd3aa026dccb436da0dd519af05..889ceb717e3a1a9f1ec39f014b5645728b21746c 100644 (file)
--- a/arch/i386/Makefile
+++ b/arch/i386/Makefile
@@ -38,6 +38,7 @@ cflags-$(CONFIG_MPENTIUMIII)  += $(call check_gcc,-march=pentium3,-march=i686)
 cflags-$(CONFIG_MPENTIUM4)     += $(call check_gcc,-march=pentium4,-march=i686)
 cflags-$(CONFIG_MK6)           += $(call check_gcc,-march=k6,-march=i586)
 cflags-$(CONFIG_MK7)           += $(call check_gcc,-march=athlon,-march=i686 -malign-functions=4)
+cflags-$(CONFIG_MK8)           += $(call check_gcc,-march=k8,$(call check_gcc,-march=athlon,-march=i686 -malign-functions=4))
 cflags-$(CONFIG_MCRUSOE)       += -march=i686 -malign-functions=0 -malign-jumps=0 -malign-loops=0
 cflags-$(CONFIG_MWINCHIPC6)    += $(call check_gcc,-march=winchip-c6,-march=i586)
 cflags-$(CONFIG_MWINCHIP2)     += $(call check_gcc,-march=winchip2,-march=i586)

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index 98936e86c9b8931d60a9588c9cd44196a6cd771c..73d1bbdbf43ccee6ae081f2016e1a1af1ac209f2 100644 (file)
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -614,7 +614,8 @@ static int __init detect_init_APIC (void)
 
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-               if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1)
+               if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
+                   (boot_cpu_data.x86 == 15))      
                        break;
                goto no_apic;
        case X86_VENDOR_INTEL:

diff --git a/arch/i386/kernel/cpu/mcheck/k7.c b/arch/i386/kernel/cpu/mcheck/k7.c
index 294c78c9b53434d045bc91b61ec6ff3430eaebb2..1df54f5a7087750b4b3318e38125e0764d588513 100644 (file)
--- a/arch/i386/kernel/cpu/mcheck/k7.c
+++ b/arch/i386/kernel/cpu/mcheck/k7.c
@@ -1,5 +1,5 @@
 /*
- * Athlon specific Machine Check Exception Reporting
+ * Athlon/Hammer specific Machine Check Exception Reporting
  */
 
 #include <linux/init.h>
@@ -82,6 +82,9 @@ void __init amd_mcheck_init(struct cpuinfo_x86 *c)
        nr_mce_banks = l & 0xff;
 
        for (i=0; i<nr_mce_banks; i++) {
+               /* Don't enable northbridge MCE by default on Hammer */
+               if (boot_cpu_data.x86_model == 15 && i == 4) 
+                       continue;
                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
        }

diff --git a/arch/i386/kernel/cpu/mtrr/main.c b/arch/i386/kernel/cpu/mtrr/main.c
index 46caa93519aab823d5c03bee9a46a07944fd55c1..5b82d52983db6073e7aacdf91bb34223f90e648b 100644 (file)
--- a/arch/i386/kernel/cpu/mtrr/main.c
+++ b/arch/i386/kernel/cpu/mtrr/main.c
@@ -574,7 +574,7 @@ static int __init mtrr_init(void)
                           query the width (in bits) of the physical
                           addressable memory on the Hammer family.
                         */
-                       if (boot_cpu_data.x86 >= 7 
+                       if (boot_cpu_data.x86 == 15
                            && (cpuid_eax(0x80000000) >= 0x80000008)) {
                                u32 phys_addr;
                                phys_addr = cpuid_eax(0x80000008) & 0xff;

diff --git a/arch/i386/kernel/nmi.c b/arch/i386/kernel/nmi.c
index fbae2c8deeaf5247d6da6d58ce2567cd4fb1301d..9eeaca1be2a12f8e05421347b811bb95add05d7b 100644 (file)
--- a/arch/i386/kernel/nmi.c
+++ b/arch/i386/kernel/nmi.c
@@ -123,7 +123,7 @@ static int __init setup_nmi_watchdog(char *str)
                nmi_watchdog = nmi;
        if ((nmi == NMI_LOCAL_APIC) &&
                        (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
-                       (boot_cpu_data.x86 == 6))
+                       (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
                nmi_watchdog = nmi;
        /*
         * We can enable the IO-APIC watchdog
@@ -294,7 +294,7 @@ void __pminit setup_apic_nmi_watchdog (void)
 {
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-               if (boot_cpu_data.x86 != 6)
+               if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
                        return;
                setup_k7_watchdog();
                break;

diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h
index f236e21749ab1fe5afc3e127185ceb2dfb02f5eb..5410e84760e687fda5dbc1f6bbbf5f9e8cafdbda 100644 (file)
--- a/include/asm-i386/bugs.h
+++ b/include/asm-i386/bugs.h
@@ -193,6 +193,11 @@ static void __init check_config(void)
            && (boot_cpu_data.x86_mask < 6 || boot_cpu_data.x86_mask == 11))
                panic("Kernel compiled for PMMX+, assumes a local APIC without the read-before-write bug!");
 #endif
+
+#ifdef CONFIG_X86_SSE2
+       if (!cpu_has_sse2)
+               panic("Kernel compiled for SSE2, CPU doesn't have it.");
+#endif
 }
 
 static void __init check_bugs(void)

diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 92ff7f79dee4eb5c57fd5d5621f5d694bb409c9f..5f019713fa4cc1e9bbfa856c992fc048e7c16c94 100644 (file)
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -75,6 +75,7 @@
 #define cpu_has_tsc            boot_cpu_has(X86_FEATURE_TSC)
 #define cpu_has_pae            boot_cpu_has(X86_FEATURE_PAE)
 #define cpu_has_pge            boot_cpu_has(X86_FEATURE_PGE)
+#define cpu_has_sse2           boot_cpu_has(X86_FEATURE_XMM2)
 #define cpu_has_apic           boot_cpu_has(X86_FEATURE_APIC)
 #define cpu_has_sep            boot_cpu_has(X86_FEATURE_SEP)
 #define cpu_has_mtrr           boot_cpu_has(X86_FEATURE_MTRR)

diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index fc8f116430bc6376abc373b0d84ed0af9f975682..e085e51e9d251ae7563d1260f583a5b203ae6413 100644 (file)
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -288,9 +288,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
  * nop for these.
  */
  
+#ifdef CONFIG_X86_SSE2
+#define mb()   asm volatile("mfence" ::: "memory")
+#define rmb()  asm volatile("lfence" ::: "memory")
+#else
 #define mb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
 #define rmb()  mb()
-
+#endif
 /**
  * read_barrier_depends - Flush all pending reads that subsequents reads
  * depend on.