0xc8000, 0xd8000, 0xe8000};
static int si_probe_addrs[]= {0xc0000, 0xd0000, 0xe0000,
0xc8000, 0xd8000, 0xe8000, 0xa0000};
+static int si1_probe_addrs[]= { 0xd0000};
#define NR_SX_ADDRS (sizeof(sx_probe_addrs)/sizeof (int))
#define NR_SI_ADDRS (sizeof(si_probe_addrs)/sizeof (int))
+#define NR_SI1_ADDRS (sizeof(si1_probe_addrs)/sizeof (int))
/* Set the mask to all-ones. This alas, only supports 32 interrupts.
}
} else if (IS_EISA_BOARD(board)) {
outb(board->irq<<4, board->eisa_base+0xc02);
+ } else if (IS_SI1_BOARD(board)) {
+ write_sx_byte (board, SI1_ISA_RESET, 0); // value does not matter
} else {
/* Gory details of the SI/ISA board */
write_sx_byte (board, SI2_ISA_RESET, SI2_ISA_RESET_SET);
} else if (IS_EISA_BOARD(board)) {
write_sx_byte(board, SI2_EISA_OFF, SI2_EISA_VAL);
outb((board->irq<<4)|4, board->eisa_base+0xc02);
+ } else if (IS_SI1_BOARD(board)) {
+ write_sx_byte (board, SI1_ISA_RESET_CLEAR, 0);
+ write_sx_byte (board, SI1_ISA_INTCL, 0);
} else {
/* Don't bug me about the clear_set.
I haven't the foggiest idea what it's about -- REW */
SX_CONF_HOSTIRQ);
} else if (IS_EISA_BOARD(board)) {
inb(board->eisa_base+0xc03);
+ } else if (IS_SI1_BOARD(board)) {
+ write_sx_byte (board, SI1_ISA_INTCL,0);
+ write_sx_byte (board, SI1_ISA_INTCL_CLEAR,0);
} else {
switch (board->irq) {
case 11:write_sx_byte (board, SI2_ISA_IRQ11, SI2_ISA_IRQ11_SET);break;
if (IS_SX_BOARD (board)) rc = SX_TYPE_SX;
if (IS_CF_BOARD (board)) rc = SX_TYPE_CF;
if (IS_SI_BOARD (board)) rc = SX_TYPE_SI;
+ if (IS_SI1_BOARD (board)) rc = SX_TYPE_SI;
if (IS_EISA_BOARD (board)) rc = SX_TYPE_SI;
sx_dprintk (SX_DEBUG_FIRMWARE, "returning type= %d\n", rc);
break;
int i;
func_enter();
- sx_dprintk (SX_DEBUG_PROBE, "Going to verify SI signature %lx.\n",
+ sx_dprintk (SX_DEBUG_PROBE, "Going to verify SI signature hw %lx at %lx.\n", board->hw_base,
board->base + SI2_ISA_ID_BASE);
if (sx_debug & SX_DEBUG_PROBE)
my_hd ((char *)(board->base + SI2_ISA_ID_BASE), 0x8);
if (!IS_EISA_BOARD(board)) {
+ if( IS_SI1_BOARD(board) )
+ {
+ for (i=0;i<8;i++) {
+ write_sx_byte (board, SI2_ISA_ID_BASE+7-i,i);
+
+ }
+ }
for (i=0;i<8;i++) {
if ((read_sx_byte (board, SI2_ISA_ID_BASE+7-i) & 7) != i) {
return 0;
my_iounmap (board->hw_base, board->base);
}
}
+ for (i=0;i<NR_SI1_ADDRS;i++) {
+ board = &boards[found];
+ board->hw_base = si1_probe_addrs[i];
+ board->base2 =
+ board->base = (ulong) ioremap(board->hw_base, SI1_ISA_WINDOW_LEN);
+ board->flags &= ~SX_BOARD_TYPE;
+ board->flags |= SI1_ISA_BOARD;
+ board->irq = sx_irqmask ?-1:0;
+
+ if (probe_si (board)) {
+ found++;
+ } else {
+ my_iounmap (board->hw_base, board->base);
+ }
+ }
sx_dprintk(SX_DEBUG_PROBE, "Probing for EISA cards\n");
for(eisa_slot=0x1000; eisa_slot<0x10000; eisa_slot+=0x1000)
#define CARD_BUS(type) ((type>>4)&0xF)
#define CARD_PHASE(type) (type&0xF)
+#define TYPE_SI1_ISA CARD_TYPE(BUS_ISA,SI1_Z280)
#define TYPE_SI2_ISA CARD_TYPE(BUS_ISA,SI2_Z280)
#define TYPE_SI2_EISA CARD_TYPE(BUS_EISA,SI2_Z280)
#define TYPE_SI2_PCI CARD_TYPE(BUS_PCI,SI2_Z280)
#define TYPE_SX_ISA CARD_TYPE(BUS_ISA,SI3_T225)
#define TYPE_SX_PCI CARD_TYPE(BUS_PCI,SI3_T225)
+/*****************************************************************************
+****************************** ******************************
+****************************** Phase 1 Z280 ******************************
+****************************** ******************************
+*****************************************************************************/
+
+/* ISA board details... */
+#define SI1_ISA_WINDOW_LEN 0x10000 /* 64 Kbyte shared memory window */
+//#define SI1_ISA_MEMORY_LEN 0x8000 /* Usable memory - unused define*/
+//#define SI1_ISA_ADDR_LOW 0x0A0000 /* Lowest address = 640 Kbyte */
+//#define SI1_ISA_ADDR_HIGH 0xFF8000 /* Highest address = 16Mbyte - 32Kbyte */
+//#define SI2_ISA_ADDR_STEP SI2_ISA_WINDOW_LEN/* ISA board address step */
+//#define SI2_ISA_IRQ_MASK 0x9800 /* IRQs 15,12,11 */
+
+/* ISA board, register definitions... */
+//#define SI2_ISA_ID_BASE 0x7FF8 /* READ: Board ID string */
+#define SI1_ISA_RESET 0x8000 /* WRITE: Host Reset */
+#define SI1_ISA_RESET_CLEAR 0xc000 /* WRITE: Host Reset clear*/
+#define SI1_ISA_WAIT 0x9000 /* WRITE: Host wait */
+#define SI1_ISA_WAIT_CLEAR 0xd000 /* WRITE: Host wait clear */
+#define SI1_ISA_INTCL 0xa000 /* WRITE: Host Reset */
+#define SI1_ISA_INTCL_CLEAR 0xe000 /* WRITE: Host Reset */
+
/*****************************************************************************
****************************** ******************************