[PATCH] FEC driver updates to support the ColdFire 5282 CPU (header)

For reasons only Motorola will ever know they decided to use a
substantially different register layout for the FEC ethernet device on
the 5282 ColdFire silicon.  This defines an appropriate access structure
for it.

diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index e8f04e8d2474438b03cf07248671fb0b83db3a3f..3bdb0d78b75a2f574b16fe049af3cf32c4c01455 100644 (file)
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -1,9 +1,10 @@
 /****************************************************************************/
 
 /*
- *     fec.h  --  Fast Ethernet Controller for Motorola ColdFire 5272.
+ *     fec.h  --  Fast Ethernet Controller for Motorola ColdFire 5272
+ *                and 5282..
  *
- *     (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
+ *     (C) Copyright 2000-2003, Greg Ungerer (gerg@snapgear.com)
  *     (C) Copyright 2000-2001, Lineo (www.lineo.com)
  */
 
@@ -12,6 +13,52 @@
 #define        FEC_H
 /****************************************************************************/
 
+#ifdef CONFIG_M5282
+/*
+ *     Just figures, Motorola would have to change the offsets for
+ *     registers in the same peripheral device on different models
+ *     of the ColdFire!
+ */
+typedef struct fec {
+       unsigned long   fec_reserved0;
+       unsigned long   fec_ievent;             /* Interrupt event reg */
+       unsigned long   fec_imask;              /* Interrupt mask reg */
+       unsigned long   fec_reserved1;
+       unsigned long   fec_r_des_active;       /* Receive descriptor reg */
+       unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
+       unsigned long   fec_reserved2[3];
+       unsigned long   fec_ecntrl;             /* Ethernet control reg */
+       unsigned long   fec_reserved3[6];
+       unsigned long   fec_mii_data;           /* MII manage frame reg */
+       unsigned long   fec_mii_speed;          /* MII speed control reg */
+       unsigned long   fec_reserved4[7];
+       unsigned long   fec_mib_ctrlstat;       /* MIB control/status reg */
+       unsigned long   fec_reserved5[7];
+       unsigned long   fec_r_cntrl;            /* Receive control reg */
+       unsigned long   fec_reserved6[15];
+       unsigned long   fec_x_cntrl;            /* Transmit Control reg */
+       unsigned long   fec_reserved7[7];
+       unsigned long   fec_addr_low;           /* Low 32bits MAC address */
+       unsigned long   fec_addr_high;          /* High 16bits MAC address */
+       unsigned long   fec_opd;                /* Opcode + Pause duration */
+       unsigned long   fec_reserved8[10];
+       unsigned long   fec_hash_table_high;    /* High 32bits hash table */
+       unsigned long   fec_hash_table_low;     /* Low 32bits hash table */
+       unsigned long   fec_grp_hash_table_high;/* High 32bits hash table */
+       unsigned long   fec_grp_hash_table_low; /* Low 32bits hash table */
+       unsigned long   fec_reserved9[7];
+       unsigned long   fec_x_wmrk;             /* FIFO transmit water mark */
+       unsigned long   fec_reserved10;
+       unsigned long   fec_r_bound;            /* FIFO receive bound reg */
+       unsigned long   fec_r_fstart;           /* FIFO receive start reg */
+       unsigned long   fec_reserved11[11];
+       unsigned long   fec_r_des_start;        /* Receive descriptor ring */
+       unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
+       unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
+} fec_t;
+
+#else
+
 /*
  *     Define device register set address map.
  */
@@ -49,6 +96,8 @@ typedef struct fec {
        unsigned long   fec_fifo_ram[112];      /* FIFO RAM buffer */
 } fec_t;
 
+#endif /* CONFIG_M5272 */
+
 
 /*
  *     Define the buffer descriptor structure.