return -EFAULT;
return(0);
}
- case HDIO_GETGEO_BIG:
- {
- struct hd_big_geometry driver_geo;
- if (hba[ctlr]->drv[dsk].cylinders) {
- driver_geo.heads = hba[ctlr]->drv[dsk].heads;
- driver_geo.sectors = hba[ctlr]->drv[dsk].sectors;
- driver_geo.cylinders = hba[ctlr]->drv[dsk].cylinders;
- } else {
- driver_geo.heads = 0xff;
- driver_geo.sectors = 0x3f;
- driver_geo.cylinders = hba[ctlr]->drv[dsk].nr_blocks / (0xff*0x3f);
- }
- driver_geo.start=
- hba[ctlr]->hd[minor(inode->i_rdev)].start_sect;
- if (copy_to_user((void *) arg, &driver_geo,
- sizeof( struct hd_big_geometry)))
- return -EFAULT;
- return(0);
- }
+
case BLKRRPART:
return revalidate_logvol(inode->i_rdev, 1);
case BLKGETSIZE:
-/*
- * linux/drivers/ide/aec62xx.c Version 0.09 June. 9, 2000
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
+ * Version 0.09 June. 9, 2000
*
* Copyright (C) 1999-2000 Andre Hedrick (andre@linux-ide.org)
* May be copied or modified under the terms of the GNU General Public License
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
#undef DISPLAY_AEC62XX_TIMINGS
return 0x00;
}
-static int aec6210_tune_chipset (ide_drive_t *drive, byte speed)
+static int aec6210_tune_chipset(struct ata_device *drive, byte speed)
{
struct ata_channel *hwif = drive->channel;
struct pci_dev *dev = hwif->pci_dev;
return(err);
}
-static int aec6260_tune_chipset (ide_drive_t *drive, byte speed)
+static int aec6260_tune_chipset(struct ata_device *drive, byte speed)
{
struct ata_channel *hwif = drive->channel;
struct pci_dev *dev = hwif->pci_dev;
}
-static int aec62xx_tune_chipset (ide_drive_t *drive, byte speed)
+static int aec62xx_tune_chipset(struct ata_device *drive, byte speed)
{
if (drive->channel->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
return ((int) aec6210_tune_chipset(drive, speed));
}
#ifdef CONFIG_BLK_DEV_IDEDMA
-static int config_aec6210_chipset_for_dma (ide_drive_t *drive, byte ultra)
+static int config_aec6210_chipset_for_dma(struct ata_device *drive, byte ultra)
{
struct hd_driveid *id = drive->id;
struct ata_channel *hwif = drive->channel;
0);
}
-static int config_aec6260_chipset_for_dma (ide_drive_t *drive, byte ultra)
+static int config_aec6260_chipset_for_dma(struct ata_device *drive, byte ultra)
{
struct hd_driveid *id = drive->id;
struct ata_channel *hwif = drive->channel;
0);
}
-static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
+static int config_chipset_for_dma(struct ata_device *drive, byte ultra)
{
switch(drive->channel->pci_dev->device) {
case PCI_DEVICE_ID_ARTOP_ATP850UF:
#endif /* CONFIG_BLK_DEV_IDEDMA */
-static void aec62xx_tune_drive (ide_drive_t *drive, byte pio)
+static void aec62xx_tune_drive(struct ata_device *drive, byte pio)
{
byte speed;
}
#ifdef CONFIG_BLK_DEV_IDEDMA
-static int config_drive_xfer_rate (ide_drive_t *drive)
+static int config_drive_xfer_rate(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
int on = 1;
#endif
#endif
-unsigned int __init pci_init_aec62xx (struct pci_dev *dev)
+static unsigned int __init aec62xx_init_chipset(struct pci_dev *dev)
{
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
return dev->irq;
}
-unsigned int __init ata66_aec62xx(struct ata_channel *hwif)
+static unsigned int __init aec62xx_ata66_check(struct ata_channel *ch)
{
- byte mask = hwif->unit ? 0x02 : 0x01;
- byte ata66 = 0;
+ u8 mask = ch->unit ? 0x02 : 0x01;
+ u8 ata66 = 0;
+
+ pci_read_config_byte(ch->pci_dev, 0x49, &ata66);
- pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
return ((ata66 & mask) ? 0 : 1);
}
-void __init ide_init_aec62xx(struct ata_channel *hwif)
+static void __init aec62xx_init_channel(struct ata_channel *hwif)
{
#ifdef CONFIG_AEC62XX_TUNING
hwif->tuneproc = aec62xx_tune_drive;
#endif
}
-void __init ide_dmacapable_aec62xx(struct ata_channel *hwif, unsigned long dmabase)
+static void __init aec62xx_init_dma(struct ata_channel *hwif, unsigned long dmabase)
{
#ifdef CONFIG_AEC62XX_TUNING
- unsigned long flags;
- byte reg54h = 0;
-
- __save_flags(flags); /* local CPU only */
- __cli(); /* local CPU only */
+ u8 reg54h = 0;
pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
pci_write_config_byte(hwif->pci_dev, 0x54, reg54h & ~(hwif->unit ? 0xF0 : 0x0F));
+#endif
+ ata_init_dma(hwif, dmabase);
+}
- __restore_flags(flags); /* local CPU only */
-#endif /* CONFIG_AEC62XX_TUNING */
- ide_setup_dma(hwif, dmabase, 8);
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_ARTOP,
+ device: PCI_DEVICE_ID_ARTOP_ATP850UF,
+ init_chipset: aec62xx_init_chipset,
+ init_channel: aec62xx_init_channel,
+ init_dma: aec62xx_init_dma,
+ enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
+ bootable: OFF_BOARD,
+ flags: ATA_F_SER | ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_ARTOP,
+ device: PCI_DEVICE_ID_ARTOP_ATP860,
+ init_chipset: aec62xx_init_chipset,
+ ata66_check: aec62xx_ata66_check,
+ init_channel: aec62xx_init_channel,
+ enablebits: { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
+ bootable: NEVER_BOARD,
+ flags: ATA_F_IRQ | ATA_F_NOADMA | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_ARTOP,
+ device: PCI_DEVICE_ID_ARTOP_ATP860R,
+ init_chipset: aec62xx_init_chipset,
+ ata66_check: aec62xx_ata66_check,
+ init_channel: aec62xx_init_channel,
+ enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+};
+
+int __init init_aec62xx(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
+#include <linux/init.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
-#include <linux/init.h>
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#undef DISPLAY_ALI_TIMINGS
byte ali_proc = 0;
static struct pci_dev *isa_dev;
-static void ali15x3_tune_drive (ide_drive_t *drive, byte pio)
+static void ali15x3_tune_drive(struct ata_device *drive, byte pio)
{
struct ata_timing *t;
struct ata_channel *hwif = drive->channel;
__restore_flags(flags);
}
-static int ali15x3_tune_chipset (ide_drive_t *drive, byte speed)
+static int ali15x3_tune_chipset(struct ata_device *drive, byte speed)
{
struct ata_channel *hwif = drive->channel;
struct pci_dev *dev = hwif->pci_dev;
return (err);
}
-static void config_chipset_for_pio (ide_drive_t *drive)
+static void config_chipset_for_pio(struct ata_device *drive)
{
ali15x3_tune_drive(drive, 5);
}
#ifdef CONFIG_BLK_DEV_IDEDMA
-static int config_chipset_for_dma (ide_drive_t *drive, byte ultra33)
+static int config_chipset_for_dma(struct ata_device *drive, byte ultra33)
{
struct hd_driveid *id = drive->id;
byte speed = 0x00;
return rval;
}
-static byte ali15x3_can_ultra (ide_drive_t *drive)
+static byte ali15x3_can_ultra(struct ata_device *drive)
{
#ifndef CONFIG_WDC_ALI15X3
struct hd_driveid *id = drive->id;
}
}
-static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
+static int ali15x3_config_drive_for_dma(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
struct ata_channel *hwif = drive->channel;
}
#endif
-unsigned int __init pci_init_ali15x3(struct pci_dev *dev)
+static unsigned int __init ali15x3_init_chipset(struct pci_dev *dev)
{
unsigned long fixdma_base = pci_resource_start(dev, 4);
* of UDMA66 transfers. It doesn't check the drives.
* But see note 2 below!
*/
-unsigned int __init ata66_ali15x3(struct ata_channel *hwif)
+static unsigned int __init ali15x3_ata66_check(struct ata_channel *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
unsigned int ata66 = 0;
return(ata66);
}
-void __init ide_init_ali15x3(struct ata_channel *hwif)
+static void __init ali15x3_init_channel(struct ata_channel *hwif)
{
#ifndef CONFIG_SPARC64
byte ideic, inmir;
hwif->autodma = 0;
#else
hwif->autodma = 0;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+#endif
}
-void __init ide_dmacapable_ali15x3(struct ata_channel *hwif, unsigned long dmabase)
+static void __init ali15x3_init_dma(struct ata_channel *ch, unsigned long dmabase)
{
- if ((dmabase) && (m5229_revision < 0x20)) {
+ if ((dmabase) && (m5229_revision < 0x20))
return;
- }
- ide_setup_dma(hwif, dmabase, 8);
+
+ ata_init_dma(ch, dmabase);
+}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_AL,
+ device: PCI_DEVICE_ID_AL_M5229,
+ init_chipset: ali15x3_init_chipset,
+ ata66_check: ali15x3_ata66_check,
+ init_channel: ali15x3_init_channel,
+ init_dma: ali15x3_init_dma,
+ enablebits: { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
+ bootable: ON_BOARD
+};
+
+int __init init_ali15x3(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* $Id: amd74xx.c,v 2.8 2002/03/14 11:52:20 vojtech Exp $
*
* Copyright (c) 2000-2002 Vojtech Pavlik
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
+
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#define AMD_IDE_ENABLE (0x00 + amd_config->base)
#define AMD_IDE_CONFIG (0x01 + amd_config->base)
* and initialize its drive independent registers.
*/
-unsigned int __init pci_init_amd74xx(struct pci_dev *dev, const char *name)
+static unsigned int __init amd74xx_init_chipset(struct pci_dev *dev)
{
unsigned char t;
unsigned int u;
return 0;
}
-unsigned int __init ata66_amd74xx(struct ata_channel *hwif)
+static unsigned int __init amd74xx_ata66_check(struct ata_channel *hwif)
{
return ((amd_enabled & amd_80w) >> hwif->unit) & 1;
}
-void __init ide_init_amd74xx(struct ata_channel *hwif)
+static void __init amd74xx_init_channel(struct ata_channel *hwif)
{
int i;
/*
* We allow the BM-DMA driver only work on enabled interfaces.
*/
+static void __init amd74xx_init_dma(struct ata_channel *ch, unsigned long dmabase)
+{
+ if ((amd_enabled >> ch->unit) & 1)
+ ata_init_dma(ch, dmabase);
+}
+
-void __init ide_dmacapable_amd74xx(struct ata_channel *hwif, unsigned long dmabase)
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_AMD,
+ device: PCI_DEVICE_ID_AMD_COBRA_7401,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_AMD,
+ device: PCI_DEVICE_ID_AMD_VIPER_7409,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_AMD,
+ device: PCI_DEVICE_ID_AMD_VIPER_7411,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_AMD,
+ device: PCI_DEVICE_ID_AMD_OPUS_7441,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_AMD,
+ device: PCI_DEVICE_ID_AMD_8111_IDE,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x40,0x01,0x01}, {0x40,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_NVIDIA,
+ device: PCI_DEVICE_ID_NVIDIA_NFORCE_IDE,
+ init_chipset: amd74xx_init_chipset,
+ ata66_check: amd74xx_ata66_check,
+ init_channel: amd74xx_init_channel,
+ init_dma: amd74xx_init_dma,
+ enablebits: {{0x50,0x01,0x01}, {0x50,0x02,0x02}},
+ bootable: ON_BOARD
+ },
+};
+
+int __init init_amd74xx(void)
{
- if ((amd_enabled >> hwif->unit) & 1)
- ide_setup_dma(hwif, dmabase, 8);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
-/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
+ * $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
*
* linux/drivers/ide/cmd64x.c Version 1.22 June 9, 2000
*
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
-#include <linux/ide.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#ifndef SPLIT_BYTE
#define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
bmide_dev = dev;
cmd64x_display_info = &cmd64x_get_info;
}
-#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
+#endif
return 0;
}
-unsigned int __init pci_init_cmd64x(struct pci_dev *dev)
+static unsigned int __init cmd64x_init_chipset(struct pci_dev *dev)
{
if (dev->device == PCI_DEVICE_ID_CMD_680)
return cmd680_pci_init (dev);
return cmd64x_pci_init (dev);
}
-unsigned int cmd680_ata66(struct ata_channel *hwif)
+static unsigned int cmd680_ata66(struct ata_channel *hwif)
{
byte ata66 = 0;
byte addr_mask = (hwif->unit) ? 0xB0 : 0xA0;
return (ata66 & 0x01) ? 1 : 0;
}
-unsigned int cmd64x_ata66(struct ata_channel *hwif)
+static unsigned int cmd64x_ata66(struct ata_channel *hwif)
{
byte ata66 = 0;
byte mask = (hwif->unit) ? 0x02 : 0x01;
return (ata66 & mask) ? 1 : 0;
}
-unsigned int __init ata66_cmd64x(struct ata_channel *hwif)
+static unsigned int __init cmd64x_ata66_check(struct ata_channel *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
if (dev->device == PCI_DEVICE_ID_CMD_680)
return cmd64x_ata66(hwif);
}
-void __init ide_init_cmd64x(struct ata_channel *hwif)
+static void __init cmd64x_init_channel(struct ata_channel *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
unsigned int class_rev;
}
hwif->highmem = 1;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+#endif
+}
+
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_643,
+ init_chipset: cmd64x_init_chipset,
+ init_channel: cmd64x_init_channel,
+ bootable: ON_BOARD,
+ },
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_646,
+ init_chipset: cmd64x_init_chipset,
+ init_channel: cmd64x_init_channel,
+ enablebits: {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_648,
+ init_chipset: cmd64x_init_chipset,
+ ata66_check: cmd64x_ata66_check,
+ init_channel: cmd64x_init_channel,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_649,
+ init_chipset: cmd64x_init_chipset,
+ ata66_check: cmd64x_ata66_check,
+ init_channel: cmd64x_init_channel,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_680,
+ init_chipset: cmd64x_init_chipset,
+ ata66_check: cmd64x_ata66_check,
+ init_channel: cmd64x_init_channel,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+ },
+};
+
+int __init init_cmd64x(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/cs5530.c Version 0.6 Mar. 18, 2000
*
* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
+
#include <asm/io.h>
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
#undef DISPLAY_CS5530_TIMINGS
/*
* Initialize the cs5530 bridge for reliable IDE DMA operation.
*/
-unsigned int __init pci_init_cs5530(struct pci_dev *dev)
+static unsigned int __init pci_init_cs5530(struct pci_dev *dev)
{
struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
unsigned short pcicmd = 0;
* This gets invoked by the IDE driver once for each channel,
* and performs channel-specific pre-initialization before drive probing.
*/
-void __init ide_init_cs5530(struct ata_channel *hwif)
+static void __init ide_init_cs5530(struct ata_channel *hwif)
{
hwif->serialized = 1;
if (!hwif->dma_base) {
}
}
}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_CYRIX,
+ device: PCI_DEVICE_ID_CYRIX_5530_IDE,
+ init_chipset: pci_init_cs5530,
+ init_channel: ide_init_cs5530,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+};
+
+int __init init_cs5530(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/cy82c693.c Version 0.34 Dec. 13, 1999
*
* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
-#include <linux/ide.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
/* the current version */
#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
* the device prior to INIT.
*/
-unsigned int __init pci_init_cy82c693(struct pci_dev *dev)
+static unsigned int __init pci_init_cy82c693(struct pci_dev *dev)
{
#ifdef CY82C693_SETDMA_CLOCK
byte data;
OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
OUT_BYTE(data, CY82_DATA_PORT);
-#if CY82C693_DEBUG_INFO
+# if CY82C693_DEBUG_INFO
printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", dev->name, data);
-#endif /* CY82C693_DEBUG_INFO */
+# endif
-#endif /* CY82C693_SETDMA_CLOCK */
+#endif
return 0;
}
/*
* the init function - called for each ide channel once
*/
-void __init ide_init_cy82c693(struct ata_channel *hwif)
+static void __init ide_init_cy82c693(struct ata_channel *hwif)
{
hwif->chipset = ide_cy82c693;
hwif->tuneproc = cy82c693_tune_drive;
if (!noautodma)
hwif->autodma = 1;
}
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+#endif
+}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_CONTAQ,
+ device: PCI_DEVICE_ID_CONTAQ_82C693,
+ init_chipset: pci_init_cy82c693,
+ init_channel: ide_init_cy82c693,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+};
+
+int __init init_cy82c693(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/hpt34x.c Version 0.31 June. 9, 2000
*
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
#include <asm/io.h>
#include <asm/irq.h>
+
#include "ata-timing.h"
+#include "pcihost.h"
#ifndef SPLIT_BYTE
-#define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
+# define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
#endif
#define HPT343_DEBUG_DRIVE_INFO 0
*/
#define HPT34X_PCI_INIT_REG 0x80
-unsigned int __init pci_init_hpt34x(struct pci_dev *dev)
+static unsigned int __init pci_init_hpt34x(struct pci_dev *dev)
{
int i = 0;
unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
bmide_dev = dev;
hpt34x_display_info = &hpt34x_get_info;
}
-#endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
+#endif
return dev->irq;
}
-void __init ide_init_hpt34x(struct ata_channel *hwif)
+static void __init ide_init_hpt34x(struct ata_channel *hwif)
{
- hwif->tuneproc = &hpt34x_tune_drive;
- hwif->speedproc = &hpt34x_tune_chipset;
+ hwif->tuneproc = hpt34x_tune_drive;
+ hwif->speedproc = hpt34x_tune_chipset;
#ifdef CONFIG_BLK_DEV_IDEDMA
if (hwif->dma_base) {
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
}
-#else /* !CONFIG_BLK_DEV_IDEDMA */
+#else
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
hwif->autodma = 0;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+#endif
+}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_TTI,
+ device: PCI_DEVICE_ID_TTI_HPT343,
+ init_chipset: pci_init_hpt34x,
+ init_channel: ide_init_hpt34x,
+ bootable: NEVER_BOARD,
+ extra: 16,
+ flags: ATA_F_NOADMA | ATA_F_DMA
+};
+
+int __init init_hpt34x(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/hpt366.c Version 0.22 20 Sep 2001
*
* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
* Note that final HPT370 support was done by force extraction of GPL.
*
* - add function for getting/setting power status of drive
- * - the HPT370's state machine can get confused. reset it before each dma
+ * - the HPT370's state machine can get confused. reset it before each dma
* xfer to prevent that from happening.
* - reset state engine whenever we get an error.
- * - check for busmaster state at end of dma.
+ * - check for busmaster state at end of dma.
* - use new highpoint timings.
* - detect bus speed using highpoint register.
* - use pll if we don't have a clock table. added a 66MHz table that's
* pci clocks as the chip can glitch in those cases. the highpoint
* approved workaround slows everything down too much to be useful. in
* addition, we would have to serialize access to each chip.
- * Adrian Sun <a.sun@sun.com>
+ * Adrian Sun <a.sun@sun.com>
*
* add drive timings for 66MHz PCI bus,
* fix ATA Cable signal detection, fix incorrect /proc info
* add /proc display for per-drive PIO/DMA/UDMA mode and
* per-channel ATA-33/66 Cable detect.
- * Duncan Laurie <void@sun.com>
+ * Duncan Laurie <void@sun.com>
*
* fixup /proc output for multiple controllers
* Tim Hockin <thockin@sun.com>
*
- * On hpt366:
+ * On hpt366:
* Reset the hpt366 on error, reset on dma
* Fix disabling Fast Interrupt hpt366.
- * Mike Waychison <crlf@sun.com>
+ * Mike Waychison <crlf@sun.com>
*
* 02 May 2002 - HPT374 support (Andre Hedrick <andre@linux-ide.org>)
*/
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
+
#undef DISPLAY_HPT366_TIMINGS
#include <linux/proc_fs.h>
#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
-const char *quirk_drives[] = {
+static const char *quirk_drives[] = {
"QUANTUM FIREBALLlct08 08",
"QUANTUM FIREBALLP KA6.4",
"QUANTUM FIREBALLP LM20.4",
NULL
};
-const char *bad_ata100_5[] = {
+static const char *bad_ata100_5[] = {
"IBM-DTLA-307075",
"IBM-DTLA-307060",
"IBM-DTLA-307045",
NULL
};
-const char *bad_ata66_4[] = {
+static const char *bad_ata66_4[] = {
"IBM-DTLA-307075",
"IBM-DTLA-307060",
"IBM-DTLA-307045",
NULL
};
-const char *bad_ata66_3[] = {
+static const char *bad_ata66_3[] = {
"WDC AC310200R",
NULL
};
-const char *bad_ata33[] = {
+static const char *bad_ata33[] = {
"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
};
struct chipset_bus_clock_list_entry {
- byte xfer_speed;
+ u8 xfer_speed;
unsigned int chipset_settings;
};
* PIO.
* 31 FIFO enable.
*/
-struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
+static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
{ XFER_UDMA_4, 0x900fd943 },
{ XFER_UDMA_3, 0x900ad943 },
{ XFER_UDMA_2, 0x900bd943 },
{ 0, 0x0120d9d9 }
};
-struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
{ XFER_UDMA_4, 0x90c9a731 },
{ XFER_UDMA_3, 0x90cfa731 },
{ XFER_UDMA_2, 0x90caa731 },
{ 0, 0x0120a7a7 }
};
-struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
+static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
{ XFER_UDMA_4, 0x90c98521 },
{ XFER_UDMA_3, 0x90cf8521 },
#if 1
/* these are the current (4 sep 2001) timings from highpoint */
-struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
{ XFER_UDMA_5, 0x12446231 },
{ XFER_UDMA_4, 0x12446231 },
{ XFER_UDMA_3, 0x126c6231 },
};
/* 2x 33MHz timings */
-struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
{ XFER_UDMA_5, 0x1488e673 },
{ XFER_UDMA_4, 0x1488e673 },
{ XFER_UDMA_3, 0x1498e673 },
{ XFER_UDMA_0, 0x14a0e73f },
{ XFER_MW_DMA_2, 0x2480fa73 },
- { XFER_MW_DMA_1, 0x2480fa77 },
+ { XFER_MW_DMA_1, 0x2480fa77 },
{ XFER_MW_DMA_0, 0x2480fb3f },
{ XFER_PIO_4, 0x0c82be73 },
};
#else
/* from highpoint documentation. these are old values */
-struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
{ XFER_UDMA_5, 0x16454e31 },
{ XFER_UDMA_4, 0x16454e31 },
{ XFER_UDMA_3, 0x166d4e31 },
{ 0, 0x06514e57 }
};
-struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
{ XFER_UDMA_5, 0x14846231 },
{ XFER_UDMA_4, 0x14886231 },
{ XFER_UDMA_3, 0x148c6231 },
{ XFER_UDMA_2, 0x148c6231 },
{ XFER_UDMA_1, 0x14906231 },
{ XFER_UDMA_0, 0x14986231 },
-
+
{ XFER_MW_DMA_2, 0x26514e21 },
{ XFER_MW_DMA_1, 0x26514e33 },
{ XFER_MW_DMA_0, 0x26514e97 },
-
+
{ XFER_PIO_4, 0x06514e21 },
{ XFER_PIO_3, 0x06514e22 },
{ XFER_PIO_2, 0x06514e33 },
};
#endif
-struct chipset_bus_clock_list_entry fifty_base_hpt370[] = {
+static struct chipset_bus_clock_list_entry fifty_base_hpt370[] = {
{ XFER_UDMA_5, 0x12848242 },
{ XFER_UDMA_4, 0x12ac8242 },
{ XFER_UDMA_3, 0x128c8242 },
{ 0, 0x0ac1f48a }
};
-struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
{ XFER_UDMA_6, 0x1c81dc62 },
{ XFER_UDMA_5, 0x1c6ddc62 },
{ XFER_UDMA_4, 0x1c8ddc62 },
{ 0, 0x0d029d5e }
};
-struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
+static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
{ XFER_UDMA_5, 0x12848242 },
{ XFER_UDMA_4, 0x12ac8242 },
{ XFER_UDMA_3, 0x128c8242 },
{ 0, 0x0a81f443 }
};
-struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
{ XFER_UDMA_6, 0x1c869c62 },
{ XFER_UDMA_5, 0x1cae9c62 },
{ XFER_UDMA_4, 0x1c8a9c62 },
{ 0, 0x0d029d26 }
};
-struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
+static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
{ XFER_UDMA_6, 0x12808242 },
{ XFER_UDMA_5, 0x12848242 },
{ XFER_UDMA_4, 0x12ac8242 },
};
#if 0
-struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
+static struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
{ XFER_UDMA_6, },
{ XFER_UDMA_5, },
{ XFER_UDMA_4, },
};
#endif
#if 0
-struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
+static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
{ XFER_UDMA_6, 0x12406231 }, /* checkme */
{ XFER_UDMA_5, 0x12446231 },
0x14846231
static unsigned int pci_rev5_check_hpt3xx(struct pci_dev *dev);
static unsigned int pci_rev7_check_hpt3xx(struct pci_dev *dev);
-byte hpt366_proc = 0;
-extern char *ide_xfer_verbose (byte xfer_rate);
+static u8 hpt366_proc = 0;
+extern char *ide_xfer_verbose(u8 xfer_rate);
#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
static int hpt366_get_info(char *, char **, off_t, int);
{
u8 c2, c3;
- /* older revs don't have these registers mapped
+ /* older revs don't have these registers mapped
* into io space */
pci_read_config_byte(dev, 0x43, &c0);
pci_read_config_byte(dev, 0x47, &c1);
p += sprintf(p, "Mode: %s %s"
" %s %s\n",
- (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
+ (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
(c0 & 0x80) ? "PIO " : "off ",
(c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
(c1 & 0x80) ? "PIO " : "off ",
}
}
p += sprintf(p, "\n");
-
+
return p-buffer;/* => must be less than 4k! */
}
#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
return ((int) (class_rev > 0x06) ? 1 : 0);
}
-static int check_in_drive_lists (ide_drive_t *drive, const char **list)
+static int check_in_drive_lists(struct ata_device *drive, const char **list)
{
struct hd_driveid *id = drive->id;
return 0;
}
-static unsigned int pci_bus_clock_list (byte speed, struct chipset_bus_clock_list_entry * chipset_table)
+static unsigned int pci_bus_clock_list(byte speed, struct chipset_bus_clock_list_entry * chipset_table)
{
for ( ; chipset_table->xfer_speed ; chipset_table++)
if (chipset_table->xfer_speed == speed) {
return chipset_table->chipset_settings;
}
-static void hpt366_tune_chipset (ide_drive_t *drive, byte speed)
+static void hpt366_tune_chipset(struct ata_device *drive, byte speed)
{
struct pci_dev *dev = drive->channel->pci_dev;
byte regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
byte drive_fast = 0;
/*
- * Disable the "fast interrupt" prediction.
+ * Disable the "fast interrupt" prediction.
*/
pci_read_config_byte(dev, regfast, &drive_fast);
if (drive_fast & 0x02)
reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
} else {
reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
- }
+ }
reg2 &= ~0x80000000;
pci_write_config_dword(dev, regtime, reg2);
}
-static void hpt368_tune_chipset (ide_drive_t *drive, byte speed)
+static void hpt368_tune_chipset(struct ata_device *drive, byte speed)
{
hpt366_tune_chipset(drive, speed);
}
-static void hpt370_tune_chipset (ide_drive_t *drive, byte speed)
+static void hpt370_tune_chipset(struct ata_device *drive, byte speed)
{
byte regfast = (drive->channel->unit) ? 0x55 : 0x51;
unsigned int list_conf = 0;
/*
* Disable the "fast interrupt" prediction.
- * don't holdoff on interrupts. (== 0x01 despite what the docs say)
+ * don't holdoff on interrupts. (== 0x01 despite what the docs say)
*/
pci_read_config_byte(dev, regfast, &drive_fast);
new_fast = drive_fast;
if (new_fast != drive_fast)
pci_write_config_byte(drive->channel->pci_dev, regfast, new_fast);
- list_conf = pci_bus_clock_list(speed,
+ list_conf = pci_bus_clock_list(speed,
(struct chipset_bus_clock_list_entry *)
dev->sysdata);
pci_read_config_dword(dev, drive_pci, &drive_conf);
list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
-
+
if (speed < XFER_MW_DMA_0) {
list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
}
pci_write_config_dword(dev, drive_pci, list_conf);
}
-static void hpt372_tune_chipset (ide_drive_t *drive, byte speed)
+static void hpt372_tune_chipset(struct ata_device *drive, byte speed)
{
byte regfast = (drive->channel->unit) ? 0x55 : 0x51;
unsigned int list_conf = 0;
pci_read_config_byte(dev, regfast, &drive_fast);
drive_fast &= ~0x07;
pci_write_config_byte(drive->channel->pci_dev, regfast, drive_fast);
-
+
list_conf = pci_bus_clock_list(speed,
(struct chipset_bus_clock_list_entry *)
dev->sysdata);
pci_write_config_dword(dev, drive_pci, list_conf);
}
-static void hpt374_tune_chipset (ide_drive_t *drive, byte speed)
+static void hpt374_tune_chipset(struct ata_device *drive, byte speed)
{
hpt372_tune_chipset(drive, speed);
}
-static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed)
+static int hpt3xx_tune_chipset(struct ata_device *drive, byte speed)
{
if ((drive->type != ATA_DISK) && (speed < XFER_SW_DMA_0))
return -1;
return ((int) ide_config_drive_speed(drive, speed));
}
-static void config_chipset_for_pio (ide_drive_t *drive)
+static void config_chipset_for_pio(struct ata_device *drive)
{
unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
unsigned short xfer_pio = drive->id->eide_pio_modes;
(void) hpt3xx_tune_chipset(drive, speed);
}
-static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio)
+static void hpt3xx_tune_drive(struct ata_device *drive, byte pio)
{
byte speed;
switch(pio) {
* check_in_drive_lists(drive, bad_ata33)
*
*/
-static int config_chipset_for_dma (ide_drive_t *drive)
+static int config_chipset_for_dma(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
byte speed = 0x00;
return rval;
}
-int hpt3xx_quirkproc (ide_drive_t *drive)
+static int hpt3xx_quirkproc(struct ata_device *drive)
{
return ((int) check_in_drive_lists(drive, quirk_drives));
}
-void hpt3xx_intrproc (ide_drive_t *drive)
+static void hpt3xx_intrproc(struct ata_device *drive)
{
if (drive->quirk_list) {
/* drives in the quirk_list may not like intr setups/cleanups */
}
}
-void hpt3xx_maskproc (ide_drive_t *drive, int mask)
+static void hpt3xx_maskproc(struct ata_device *drive, int mask)
{
struct pci_dev *dev = drive->channel->pci_dev;
}
}
-static int config_drive_xfer_rate (ide_drive_t *drive)
+static int config_drive_xfer_rate(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
int on = 1;
* this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
* HOTSWAP ATA Infrastructure.
*/
-void hpt3xx_reset (ide_drive_t *drive)
+static void hpt3xx_reset(struct ata_device *drive)
{
#if 0
unsigned long high_16 = pci_resource_start(drive->channel->pci_dev, 4);
}
#if 0
-static int hpt3xx_tristate (ide_drive_t * drive, int state)
+static int hpt3xx_tristate(struct ata_device * drive, int state)
{
- struct ata_channel *hwif = drive->channel;
- struct pci_dev *dev = hwif->pci_dev;
- byte reset = (hwif->unit) ? 0x80 : 0x40;
- byte state_reg = (hwif->unit) ? 0x57 : 0x53;
+ struct ata_channel *ch = drive->channel;
+ struct pci_dev *dev = ch->pci_dev;
+ byte reset = (ch->unit) ? 0x80 : 0x40;
+ byte state_reg = (ch->unit) ? 0x57 : 0x53;
byte reg59h = 0;
byte regXXh = 0;
- if (!hwif)
+ if (!ch)
return -EINVAL;
-// hwif->bus_state = state;
+// ch->bus_state = state;
pci_read_config_byte(dev, 0x59, ®59h);
pci_read_config_byte(dev, state_reg, ®XXh);
}
#endif
-/*
+/*
* set/get power state for a drive.
* turning the power off does the following things:
* 1) soft-reset the drive
* when we turn things back on, we need to re-initialize things.
*/
#define TRISTATE_BIT 0x8000
-static int hpt370_busproc(ide_drive_t * drive, int state)
+static int hpt370_busproc(struct ata_device * drive, int state)
{
- struct ata_channel *hwif = drive->channel;
- byte tristate, resetmask, bus_reg;
+ struct ata_channel *ch = drive->channel;
+ u8 tristate, resetmask, bus_reg;
u16 tri_reg;
- if (!hwif)
+ if (!ch)
return -EINVAL;
- hwif->bus_state = state;
+ ch->bus_state = state;
- if (hwif->unit) {
+ if (ch->unit) {
/* secondary channel */
tristate = 0x56;
- resetmask = 0x80;
- } else {
+ resetmask = 0x80;
+ } else {
/* primary channel */
tristate = 0x52;
resetmask = 0x40;
}
/* grab status */
- pci_read_config_word(hwif->pci_dev, tristate, &tri_reg);
- pci_read_config_byte(hwif->pci_dev, 0x59, &bus_reg);
+ pci_read_config_word(ch->pci_dev, tristate, &tri_reg);
+ pci_read_config_byte(ch->pci_dev, 0x59, &bus_reg);
/* set the state. we don't set it if we don't need to do so.
* make sure that the drive knows that it has failed if it's off */
switch (state) {
case BUSSTATE_ON:
- hwif->drives[0].failures = 0;
- hwif->drives[1].failures = 0;
+ ch->drives[0].failures = 0;
+ ch->drives[1].failures = 0;
if ((bus_reg & resetmask) == 0)
return 0;
tri_reg &= ~TRISTATE_BIT;
bus_reg &= ~resetmask;
break;
case BUSSTATE_OFF:
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
+ ch->drives[0].failures = ch->drives[0].max_failures + 1;
+ ch->drives[1].failures = ch->drives[1].max_failures + 1;
if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
return 0;
tri_reg &= ~TRISTATE_BIT;
bus_reg |= resetmask;
break;
case BUSSTATE_TRISTATE:
- hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
- hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
+ ch->drives[0].failures = ch->drives[0].max_failures + 1;
+ ch->drives[1].failures = ch->drives[1].max_failures + 1;
if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
return 0;
tri_reg |= TRISTATE_BIT;
bus_reg |= resetmask;
break;
}
- pci_write_config_byte(hwif->pci_dev, 0x59, bus_reg);
- pci_write_config_word(hwif->pci_dev, tristate, tri_reg);
+ pci_write_config_byte(ch->pci_dev, 0x59, bus_reg);
+ pci_write_config_word(ch->pci_dev, tristate, tri_reg);
return 0;
}
-static void __init init_hpt37x(struct pci_dev *dev)
+static void __init hpt37x_init(struct pci_dev *dev)
{
int adjust, i;
u16 freq;
u32 pll;
- byte reg5bh;
+ u8 reg5bh;
/*
* default to pci clock. make sure MA15/16 are set to output
pci_write_config_byte(dev, 0x5b, 0x23);
/*
- * set up the PLL. we need to adjust it so that it's stable.
+ * set up the PLL. we need to adjust it so that it's stable.
* freq = Tpll * 192 / Tpci
*/
pci_read_config_word(dev, 0x78, &freq);
}
printk("HPT37X: using 66MHz PCI clock\n");
}
-
+
/*
* only try the pll if we don't have a table for the clock
* speed that we're running at. NOTE: the internal PLL will
* don't like to use the PLL because it will cause glitches
* on PRST/SRST when the HPT state engine gets reset.
*/
- if (dev->sysdata)
+ if (dev->sysdata)
goto init_hpt37X_done;
-
+
/*
* adjust PLL based upon PCI clock, enable it, and wait for
* stabilization.
if (reg5bh & 0x80) {
/* spin looking for the clock to destabilize */
for (i = 0; i < 0x1000; ++i) {
- pci_read_config_byte(dev, 0x5b,
+ pci_read_config_byte(dev, 0x5b,
®5bh);
if ((reg5bh & 0x80) == 0)
goto pll_recal;
}
pci_read_config_dword(dev, 0x5c, &pll);
- pci_write_config_dword(dev, 0x5c,
+ pci_write_config_dword(dev, 0x5c,
pll & ~0x100);
pci_write_config_byte(dev, 0x5b, 0x21);
if (pci_rev7_check_hpt3xx(dev)) {
pll -= (adjust >> 1);
else
pll += (adjust >> 1);
- }
+ }
init_hpt37X_done:
/* reset state engine */
- pci_write_config_byte(dev, 0x50, 0x37);
- pci_write_config_byte(dev, 0x54, 0x37);
+ pci_write_config_byte(dev, 0x50, 0x37);
+ pci_write_config_byte(dev, 0x54, 0x37);
udelay(100);
}
-static void __init init_hpt366 (struct pci_dev *dev)
+static void __init hpt366_init(struct pci_dev *dev)
{
unsigned int reg1 = 0;
- byte drive_fast = 0;
+ u8 drive_fast = 0;
/*
* Disable the "fast interrupt" prediction.
if (drive_fast & 0x80)
pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
pci_read_config_dword(dev, 0x40, ®1);
-
+
/* detect bus speed by looking at control reg timing: */
switch((reg1 >> 8) & 7) {
case 5:
}
}
-unsigned int __init pci_init_hpt366(struct pci_dev *dev)
+static unsigned int __init hpt366_init_chipset(struct pci_dev *dev)
{
- byte test = 0;
+ u8 test = 0;
if (dev->resource[PCI_ROM_RESOURCE].start)
pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
if (pci_rev3_check_hpt3xx(dev))
- init_hpt37x(dev);
+ hpt37x_init(dev);
else
- init_hpt366(dev);
+ hpt366_init(dev);
if (n_hpt_devs < HPT366_MAX_DEVS)
hpt_devs[n_hpt_devs++] = dev;
return dev->irq;
}
-unsigned int __init ata66_hpt366(struct ata_channel *hwif)
+static unsigned int __init hpt366_ata66_check(struct ata_channel *ch)
{
- byte ata66 = 0;
- byte regmask = (hwif->unit) ? 0x01 : 0x02;
+ u8 ata66 = 0;
+ u8 regmask = (ch->unit) ? 0x01 : 0x02;
- pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
+ pci_read_config_byte(ch->pci_dev, 0x5a, &ata66);
#ifdef DEBUG
printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
ata66, (ata66 & regmask) ? "33" : "66",
- PCI_FUNC(hwif->pci_dev->devfn));
+ PCI_FUNC(ch->pci_dev->devfn));
#endif
return ((ata66 & regmask) ? 0 : 1);
}
-void __init ide_init_hpt366(struct ata_channel *hwif)
+static void __init hpt366_init_channel(struct ata_channel *ch)
{
- hwif->tuneproc = &hpt3xx_tune_drive;
- hwif->speedproc = &hpt3xx_tune_chipset;
- hwif->quirkproc = &hpt3xx_quirkproc;
- hwif->intrproc = &hpt3xx_intrproc;
- hwif->maskproc = &hpt3xx_maskproc;
+ ch->tuneproc = hpt3xx_tune_drive;
+ ch->speedproc = hpt3xx_tune_chipset;
+ ch->quirkproc = hpt3xx_quirkproc;
+ ch->intrproc = hpt3xx_intrproc;
+ ch->maskproc = hpt3xx_maskproc;
#ifdef HPT_SERIALIZE_IO
/* serialize access to this device */
- if (hwif->mate)
- hwif->serialized = hwif->mate->serialized = 1;
+ if (ch->mate)
+ ch->serialized = ch->mate->serialized = 1;
#endif
#ifdef CONFIG_BLK_DEV_IDEDMA
- if (hwif->dma_base) {
- if (pci_rev3_check_hpt3xx(hwif->pci_dev)) {
+ if (ch->dma_base) {
+ if (pci_rev3_check_hpt3xx(ch->pci_dev)) {
byte reg5ah = 0;
- pci_read_config_byte(hwif->pci_dev, 0x5a, ®5ah);
+ pci_read_config_byte(ch->pci_dev, 0x5a, ®5ah);
if (reg5ah & 0x10) /* interrupt force enable */
- pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10);
+ pci_write_config_byte(ch->pci_dev, 0x5a, reg5ah & ~0x10);
/*
* set up ioctl for power status.
* note: power affects both
* drives on each channel
*/
- hwif->resetproc = hpt3xx_reset;
- hwif->busproc = hpt370_busproc;
-
- if (pci_rev7_check_hpt3xx(hwif->pci_dev)) {
- hwif->udma_stop = hpt374_udma_stop;
- hwif->XXX_udma = hpt374_dmaproc;
- } else if (pci_rev5_check_hpt3xx(hwif->pci_dev)) {
- hwif->udma_stop = hpt374_udma_stop;
- hwif->XXX_udma = hpt374_dmaproc;
- } else if (hwif->pci_dev->device == PCI_DEVICE_ID_TTI_HPT372) {
- hwif->udma_stop = hpt374_udma_stop;
- hwif->XXX_udma = hpt374_dmaproc;
- } else if (pci_rev3_check_hpt3xx(hwif->pci_dev)) {
- hwif->udma_start = hpt370_udma_start;
- hwif->udma_stop = hpt370_udma_stop;
- hwif->udma_timeout = hpt370_udma_timeout;
- hwif->udma_irq_lost = hpt370_udma_irq_lost;
- hwif->XXX_udma = hpt370_dmaproc;
+ ch->resetproc = hpt3xx_reset;
+ ch->busproc = hpt370_busproc;
+
+ if (pci_rev7_check_hpt3xx(ch->pci_dev)) {
+ ch->udma_stop = hpt374_udma_stop;
+ ch->XXX_udma = hpt374_dmaproc;
+ } else if (pci_rev5_check_hpt3xx(ch->pci_dev)) {
+ ch->udma_stop = hpt374_udma_stop;
+ ch->XXX_udma = hpt374_dmaproc;
+ } else if (ch->pci_dev->device == PCI_DEVICE_ID_TTI_HPT372) {
+ ch->udma_stop = hpt374_udma_stop;
+ ch->XXX_udma = hpt374_dmaproc;
+ } else if (pci_rev3_check_hpt3xx(ch->pci_dev)) {
+ ch->udma_start = hpt370_udma_start;
+ ch->udma_stop = hpt370_udma_stop;
+ ch->udma_timeout = hpt370_udma_timeout;
+ ch->udma_irq_lost = hpt370_udma_irq_lost;
+ ch->XXX_udma = hpt370_dmaproc;
}
- } else if (pci_rev2_check_hpt3xx(hwif->pci_dev)) {
- hwif->udma_irq_lost = hpt366_udma_irq_lost;
-// hwif->resetproc = hpt3xx_reset;
-// hwif->busproc = hpt3xx_tristate;
- hwif->XXX_udma = hpt366_dmaproc;
+ } else if (pci_rev2_check_hpt3xx(ch->pci_dev)) {
+ ch->udma_irq_lost = hpt366_udma_irq_lost;
+// ch->resetproc = hpt3xx_reset;
+// ch->busproc = hpt3xx_tristate;
+ ch->XXX_udma = hpt366_dmaproc;
} else {
- hwif->udma_irq_lost = hpt366_udma_irq_lost;
-// hwif->resetproc = hpt3xx_reset;
-// hwif->busproc = hpt3xx_tristate;
- hwif->XXX_udma = hpt366_dmaproc;
+ ch->udma_irq_lost = hpt366_udma_irq_lost;
+// ch->resetproc = hpt3xx_reset;
+// ch->busproc = hpt3xx_tristate;
+ ch->XXX_udma = hpt366_dmaproc;
}
if (!noautodma)
- hwif->autodma = 1;
+ ch->autodma = 1;
else
- hwif->autodma = 0;
- hwif->highmem = 1;
+ ch->autodma = 0;
+ ch->highmem = 1;
} else {
- hwif->autodma = 0;
- hwif->drives[0].autotune = 1;
- hwif->drives[1].autotune = 1;
+ ch->autodma = 0;
+ ch->drives[0].autotune = 1;
+ ch->drives[1].autotune = 1;
}
-#else /* !CONFIG_BLK_DEV_IDEDMA */
- hwif->drives[0].autotune = 1;
- hwif->drives[1].autotune = 1;
- hwif->autodma = 0;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+#else
+ ch->drives[0].autotune = 1;
+ ch->drives[1].autotune = 1;
+ ch->autodma = 0;
+#endif
}
-void __init ide_dmacapable_hpt366(struct ata_channel *hwif, unsigned long dmabase)
+static void __init hpt366_init_dma(struct ata_channel *ch, unsigned long dmabase)
{
- byte masterdma = 0, slavedma = 0;
- byte dma_new = 0, dma_old = inb(dmabase+2);
- byte primary = hwif->unit ? 0x4b : 0x43;
- byte secondary = hwif->unit ? 0x4f : 0x47;
- unsigned long flags;
-
- __save_flags(flags); /* local CPU only */
- __cli(); /* local CPU only */
+ u8 masterdma = 0;
+ u8 slavedma = 0;
+ u8 dma_new = 0;
+ u8 dma_old = inb(dmabase+2);
+ u8 primary = ch->unit ? 0x4b : 0x43;
+ u8 secondary = ch->unit ? 0x4f : 0x47;
dma_new = dma_old;
- pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
- pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
+ pci_read_config_byte(ch->pci_dev, primary, &masterdma);
+ pci_read_config_byte(ch->pci_dev, secondary, &slavedma);
+
+ if (masterdma & 0x30)
+ dma_new |= 0x20;
+ if (slavedma & 0x30)
+ dma_new |= 0x40;
+ if (dma_new != dma_old)
+ outb(dma_new, dmabase+2);
- if (masterdma & 0x30) dma_new |= 0x20;
- if (slavedma & 0x30) dma_new |= 0x40;
- if (dma_new != dma_old) outb(dma_new, dmabase+2);
+ ata_init_dma(ch, dmabase);
+}
+
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_TTI,
+ device: PCI_DEVICE_ID_TTI_HPT366,
+ init_chipset: hpt366_init_chipset,
+ ata66_check: hpt366_ata66_check,
+ init_channel: hpt366_init_channel,
+ init_dma: hpt366_init_dma,
+ bootable: OFF_BOARD,
+ extra: 240,
+ flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_TTI,
+ device: PCI_DEVICE_ID_TTI_HPT372,
+ init_chipset: hpt366_init_chipset,
+ ata66_check: hpt366_ata66_check,
+ init_channel: hpt366_init_channel,
+ init_dma: hpt366_init_dma,
+ bootable: OFF_BOARD,
+ extra: 0,
+ flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_TTI,
+ device: PCI_DEVICE_ID_TTI_HPT374,
+ init_chipset: hpt366_init_chipset,
+ ata66_check: hpt366_ata66_check,
+ init_channel: hpt366_init_channel,
+ init_dma: hpt366_init_dma,
+ bootable: OFF_BOARD,
+ extra: 0,
+ flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
+ },
+};
- __restore_flags(flags); /* local CPU only */
+int __init init_hpt366(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
- ide_setup_dma(hwif, dmabase, 8);
+ return 0;
}
return 0;
}
- case HDIO_GETGEO_BIG:
- {
- struct hd_big_geometry *loc = (struct hd_big_geometry *) arg;
- unsigned int bios_cyl;
- if (!loc) return -EINVAL;
- val = 255;
- if (put_user(val, (byte *) &loc->heads)) return -EFAULT;
- val = 63;
- if (put_user(val, (byte *) &loc->sectors)) return -EFAULT;
- bios_cyl = raid[minor].sectors/63/255;
- if (put_user(bios_cyl, (unsigned int *) &loc->cylinders)) return -EFAULT;
- if (put_user((unsigned)ataraid_gendisk.part[minor(inode->i_rdev)].start_sect,
- (unsigned long *) &loc->start)) return -EFAULT;
- return 0;
- }
-
case BLKROSET:
case BLKROGET:
case BLKSSZGET:
-/***** vi:set ts=8 sts=8 sw=8:************************************************
+/**** vi:set ts=8 sts=8 sw=8:************************************************
*
* Copyright (C) 1994-1998,2002 Linus Torvalds and authors:
*
/*
* This can be called for a dynamically installed interface. Don't __init it
*/
-void ide_setup_dma(struct ata_channel *ch, unsigned long dma_base, unsigned int num_ports)
+void ata_init_dma(struct ata_channel *ch, unsigned long dma_base)
{
- printk(" %s: BM-DMA at 0x%04lx-0x%04lx", ch->name, dma_base, dma_base + num_ports - 1);
- if (check_region(dma_base, num_ports)) {
- printk(" -- ERROR, PORT ADDRESSES ALREADY IN USE\n");
+ if (!request_region(dma_base, 8, ch->name)) {
+ printk(KERN_ERR "ATA: ERROR: BM DMA portst already in use!\n");
+
return;
}
- request_region(dma_base, num_ports, ch->name);
+ printk(KERN_INFO" %s: BM-DMA at 0x%04lx-0x%04lx", ch->name, dma_base, dma_base + 7);
ch->dma_base = dma_base;
ch->dmatable_cpu = pci_alloc_consistent(ch->pci_dev,
PRD_ENTRIES * PRD_BYTES,
* linux/drivers/ide/ide-geometry.c
*
* Sun Feb 24 23:13:03 CET 2002: Patch by Andries Brouwer to remove the
- * confused CMOS probe applied. This is solving more problems then it my
+ * confused CMOS probe applied. This is solving more problems than it may
* (unexpectedly) introduce.
*/
#include <asm/io.h>
#include <asm/irq.h>
+#include "pcihost.h"
+
/* Missing PCI device IDs: */
#define PCI_VENDOR_ID_HINT 0x3388
#define PCI_DEVICE_ID_HINT 0x8013
/*
- * Some combi chips, which can be used on the PCI bus or the VL bus can be in
- * some systems acessed either through the PCI config space or through the
- * hosts IO bus. If the corresponding initialization driver is using the host
- * IO space to deal with them please define the following.
+ * This is the list of registered PCI chipset driver data structures.
*/
+static struct ata_pci_device *ata_pci_device_list = NULL;
-#define ATA_PCI_IGNORE ((void *)-1)
-#define IDE_NO_DRIVER ((void *)-2)
-
-#ifdef CONFIG_BLK_DEV_AEC62XX
-extern unsigned int pci_init_aec62xx(struct pci_dev *);
-extern unsigned int ata66_aec62xx(struct ata_channel *);
-extern void ide_init_aec62xx(struct ata_channel *);
-extern void ide_dmacapable_aec62xx(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_ALI15X3
-extern unsigned int pci_init_ali15x3(struct pci_dev *);
-extern unsigned int ata66_ali15x3(struct ata_channel *);
-extern void ide_init_ali15x3(struct ata_channel *);
-extern void ide_dmacapable_ali15x3(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_AMD74XX
-extern unsigned int pci_init_amd74xx(struct pci_dev *);
-extern unsigned int ata66_amd74xx(struct ata_channel *);
-extern void ide_init_amd74xx(struct ata_channel *);
-extern void ide_dmacapable_amd74xx(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_CMD64X
-extern unsigned int pci_init_cmd64x(struct pci_dev *);
-extern unsigned int ata66_cmd64x(struct ata_channel *);
-extern void ide_init_cmd64x(struct ata_channel *);
-extern void ide_dmacapable_cmd64x(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_CY82C693
-extern unsigned int pci_init_cy82c693(struct pci_dev *);
-extern void ide_init_cy82c693(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_CS5530
-extern unsigned int pci_init_cs5530(struct pci_dev *);
-extern void ide_init_cs5530(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_HPT34X
-extern unsigned int pci_init_hpt34x(struct pci_dev *);
-extern void ide_init_hpt34x(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_HPT366
-extern unsigned int pci_init_hpt366(struct pci_dev *);
-extern unsigned int ata66_hpt366(struct ata_channel *);
-extern void ide_init_hpt366(struct ata_channel *);
-extern void ide_dmacapable_hpt366(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_NS87415
-extern void ide_init_ns87415(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_OPTI621
-extern void ide_init_opti621(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_PDC_ADMA
-extern unsigned int pci_init_pdcadma(struct pci_dev *);
-extern unsigned int ata66_pdcadma(struct ata_channel *);
-extern void ide_init_pdcadma(struct ata_channel *);
-extern void ide_dmacapable_pdcadma(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_PDC202XX
-extern unsigned int pci_init_pdc202xx(struct pci_dev *);
-extern unsigned int ata66_pdc202xx(struct ata_channel *);
-extern void ide_init_pdc202xx(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_PIIX
-extern unsigned int pci_init_piix(struct pci_dev *);
-extern unsigned int ata66_piix(struct ata_channel *);
-extern void ide_init_piix(struct ata_channel *);
-extern void ide_dmacapable_piix(struct ata_channel *, unsigned long);
-#endif
-
-#ifdef CONFIG_BLK_DEV_IT8172
-extern unsigned int pci_init_it8172(struct pci_dev *);
-extern void ide_init_it8172(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_RZ1000
-extern void ide_init_rz1000(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_SVWKS
-extern unsigned int pci_init_svwks(struct pci_dev *);
-extern unsigned int ata66_svwks(struct ata_channel *);
-extern void ide_init_svwks(struct ata_channel *);
-#endif
-
-#ifdef CONFIG_BLK_DEV_SIS5513
-extern unsigned int pci_init_sis5513(struct pci_dev *);
-extern unsigned int ata66_sis5513(struct ata_channel *);
-extern void ide_init_sis5513(struct ata_channel *);
-#endif
+/*
+ * This function supplies the data necessary to detect the particular chipset.
+ *
+ * Please note that we don't copy data over. We are just linking it in to the
+ * list.
+ */
+void ata_register_chipset(struct ata_pci_device *d)
+{
+ struct ata_pci_device *tmp;
-#ifdef CONFIG_BLK_DEV_SL82C105
-extern unsigned int pci_init_sl82c105(struct pci_dev *);
-extern void dma_init_sl82c105(struct ata_channel *, unsigned long);
-extern void ide_init_sl82c105(struct ata_channel *);
-#endif
+ if (!d)
+ return;
-#ifdef CONFIG_BLK_DEV_TRM290
-extern void ide_init_trm290(struct ata_channel *);
-#endif
+ d->next = NULL;
-#ifdef CONFIG_BLK_DEV_VIA82CXXX
-extern unsigned int pci_init_via82cxxx(struct pci_dev *);
-extern unsigned int ata66_via82cxxx(struct ata_channel *);
-extern void ide_init_via82cxxx(struct ata_channel *);
-extern void ide_dmacapable_via82cxxx(struct ata_channel *, unsigned long);
-#endif
+ if (!ata_pci_device_list) {
+ ata_pci_device_list = d;
-typedef struct ide_pci_enablebit_s {
- u8 reg; /* pci configuration register holding the enable-bit */
- u8 mask; /* mask used to isolate the enable-bit */
- u8 val; /* expected value of masked register when "enabled" */
-} ide_pci_enablebit_t;
+ return;
+ }
-/* Flags used to untangle quirk handling.
- */
-#define ATA_F_DMA 0x01
-#define ATA_F_NODMA 0x02 /* no DMA mode supported at all */
-#define ATA_F_NOADMA 0x04 /* DMA has to be enabled explicitely */
-#define ATA_F_FIXIRQ 0x08 /* fixed irq wiring */
-#define ATA_F_SER 0x10 /* serialize on first and second channel interrupts */
-#define ATA_F_IRQ 0x20 /* trust IRQ information from config */
-#define ATA_F_PHACK 0x40 /* apply PROMISE hacks */
-#define ATA_F_HPTHACK 0x80 /* apply HPT366 hacks */
-
-struct ata_pci_device {
- unsigned short vendor;
- unsigned short device;
- unsigned int (*init_chipset)(struct pci_dev *dev);
- unsigned int (*ata66_check)(struct ata_channel *hwif);
- void (*init_channel)(struct ata_channel *hwif);
- void (*dma_init)(struct ata_channel *hwif, unsigned long dmabase);
- ide_pci_enablebit_t enablebits[2];
- unsigned int bootable;
- unsigned int extra;
- unsigned int flags;
-};
+ tmp = ata_pci_device_list;
+ while (tmp->next) {
+ tmp = tmp->next;
+ }
-static struct ata_pci_device pci_chipsets[] __initdata = {
-#ifdef CONFIG_BLK_DEV_PIIX
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_9, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, pci_init_piix, ata66_piix, ide_init_piix, ide_dmacapable_piix, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_VIA82CXXX
- {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, pci_init_via82cxxx, ata66_via82cxxx, ide_init_via82cxxx, ide_dmacapable_via82cxxx, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0, ATA_F_NOADMA },
- {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, pci_init_via82cxxx, ata66_via82cxxx, ide_init_via82cxxx, ide_dmacapable_via82cxxx, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0, ATA_F_NOADMA },
-#endif
-#ifdef CONFIG_BLK_DEV_PDC202XX
-# ifdef CONFIG_PDC202XX_FORCE
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, pci_init_pdc202xx, NULL, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 16, ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48, ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA},
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 48, ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA},
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48, ATA_F_IRQ | ATA_F_DMA },
-# else
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, pci_init_pdc202xx, NULL, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16, ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48, ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48, ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48, ATA_F_IRQ | ATA_F_DMA },
-# endif
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
- /* Promise used a different PCI identification for the raid card
- * apparently to try and prevent Linux detecting it and using our own
- * raid code. We want to detect it for the ataraid drivers, so we have
- * to list both here.. */
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268R, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_RZ1000
- {PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000, NULL, NULL, ide_init_rz1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001, NULL, NULL, ide_init_rz1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_SIS5513
- {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_init_sis5513, ata66_sis5513, ide_init_sis5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0, ATA_F_NOADMA },
-#endif
-#ifdef CONFIG_BLK_DEV_CMD64X
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, pci_init_cmd64x, NULL, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, pci_init_cmd64x, NULL, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0, ATA_F_DMA },
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_680, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_OPTI621
- {PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621, NULL, NULL, ide_init_opti621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825, NULL, NULL, ide_init_opti621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_TRM290
- {PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, NULL, NULL, ide_init_trm290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_NS87415
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, NULL, NULL, ide_init_ns87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_AEC62XX
- {PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, pci_init_aec62xx, NULL, ide_init_aec62xx, ide_dmacapable_aec62xx, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0, ATA_F_SER | ATA_F_IRQ | ATA_F_DMA },
- {PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, pci_init_aec62xx, ata66_aec62xx, ide_init_aec62xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0, ATA_F_IRQ | ATA_F_NOADMA | ATA_F_DMA },
- {PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, pci_init_aec62xx, ata66_aec62xx, ide_init_aec62xx, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_SL82C105
- {PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, pci_init_sl82c105, NULL, ide_init_sl82c105, dma_init_sl82c105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_HPT34X
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, pci_init_hpt34x, NULL, ide_init_hpt34x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16, ATA_F_NOADMA | ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_HPT366
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, pci_init_hpt366, ata66_hpt366, ide_init_hpt366, ide_dmacapable_hpt366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240, ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA },
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, pci_init_hpt366, ata66_hpt366, ide_init_hpt366, ide_dmacapable_hpt366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA },
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, pci_init_hpt366, ata66_hpt366, ide_init_hpt366, ide_dmacapable_hpt366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_ALI15X3
- {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, pci_init_ali15x3, ata66_ali15x3, ide_init_ali15x3, ide_dmacapable_ali15x3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_CY82C693
- {PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_init_cy82c693, NULL, ide_init_cy82c693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_CS5530
- {PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, pci_init_cs5530, NULL, ide_init_cs5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
-#endif
-#ifdef CONFIG_BLK_DEV_AMD74XX
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x50,0x01,0x01}, {0x50,0x02,0x02}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_PDC_ADMA
- {PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841, pci_init_pdcadma, ata66_pdcadma, ide_init_pdcadma, ide_dmacapable_pdcadma, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_NODMA },
-#endif
-#ifdef CONFIG_BLK_DEV_SVWKS
- {PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, pci_init_svwks, ata66_svwks, ide_init_svwks, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
- {PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, pci_init_svwks, ata66_svwks, ide_init_svwks, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-#endif
-#ifdef CONFIG_BLK_DEV_IT8172
- {PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, pci_init_it8172, NULL, ide_init_it8172, NULL, {{0x00,0x00,0x00}, {0x40,0x00,0x01}}, ON_BOARD, 0, 0 },
-#endif
- /* Those are id's of chips we don't deal currently with,
- * but which still need some generic quirk handling.
- */
- {PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640, NULL, NULL, ATA_PCI_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, NULL, NULL, NULL, NULL, {{0x6D,0x80,0x80}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_NODMA },
- {PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_FIXIRQ },
- {PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_FIXIRQ },
- {PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_FIXIRQ },
- {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_NOADMA },
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, NULL, NULL, IDE_NO_DRIVER, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240, ATA_F_IRQ | ATA_F_HPTHACK },
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, NULL, NULL, IDE_NO_DRIVER, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_HPTHACK },
- {PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, NULL, NULL, IDE_NO_DRIVER, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_IRQ | ATA_F_HPTHACK },
- {0, 0, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
+ tmp->next = d;
+}
/*
* This allows off board ide-pci cards the enable a BIOS, verify interrupt
* Match a PCI IDE port against an entry in ide_hwifs[],
* based on io_base port if possible.
*/
-static struct ata_channel __init *lookup_hwif (unsigned long io_base, int bootable, const char *name)
+static struct ata_channel __init *lookup_channel(unsigned long io_base, int bootable, const char *name)
{
int h;
struct ata_channel *hwif;
/*
* Setup DMA transfers on a channel.
*/
-static void __init setup_channel_dma(struct ata_channel *hwif, struct pci_dev *dev,
+static void __init setup_channel_dma(struct ata_channel *ch,
+ struct pci_dev *dev,
struct ata_pci_device *d,
int port,
u8 class_rev,
autodma = 0;
if (autodma)
- hwif->autodma = 1;
+ ch->autodma = 1;
if (!((d->flags & ATA_F_DMA) || ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))))
return;
- dma_base = get_dma_base(hwif, ((port == ATA_PRIMARY) && d->extra) ? d->extra : 0, dev->name);
+ dma_base = get_dma_base(ch, ((port == ATA_PRIMARY) && d->extra) ? d->extra : 0, dev->name);
if (!dma_base) {
- printk("%s: %s Bus-Master DMA was disabled by BIOS\n", hwif->name, dev->name);
+ printk("%s: %s Bus-Master DMA was disabled by BIOS\n",
+ ch->name, dev->name);
return;
}
* Set up BM-DMA capability (PnP BIOS should have done this already)
*/
if (!(d->vendor == PCI_VENDOR_ID_CYRIX && d->device == PCI_DEVICE_ID_CYRIX_5530_IDE))
- hwif->autodma = 0; /* default DMA off if we had to configure it here */
+ ch->autodma = 0; /* default DMA off if we had to configure it here */
pci_write_config_word(dev, PCI_COMMAND, *pcicmd | PCI_COMMAND_MASTER);
if (pci_read_config_word(dev, PCI_COMMAND, pcicmd) || !(*pcicmd & PCI_COMMAND_MASTER)) {
- printk("%s: %s error updating PCICMD\n", hwif->name, dev->name);
+ printk("%s: %s error updating PCICMD\n",
+ ch->name, dev->name);
dma_base = 0;
}
}
- if (d->dma_init)
- d->dma_init(hwif, dma_base);
+ if (d->init_dma)
+ d->init_dma(ch, dma_base);
else
- ide_setup_dma(hwif, dma_base, 8);
+ ata_init_dma(ch, dma_base);
}
#endif
if (!base)
base = port ? 0x170 : 0x1f0;
- if ((ch = lookup_hwif(base, d->bootable, dev->name)) == NULL)
+ if ((ch = lookup_channel(base, d->bootable, dev->name)) == NULL)
return -ENOMEM; /* no room in ide_hwifs[] */
if (ch->io_ports[IDE_DATA_OFFSET] != base) {
autodma = 1;
#endif
- if (d->init_channel == IDE_NO_DRIVER) {
- printk(KERN_WARNING "%s: detected chipset, but driver not compiled in!\n", dev->name);
- d->init_channel = NULL;
- }
-
if (pci_enable_device(dev)) {
printk(KERN_WARNING "%s: Could not enable PCI device.\n", dev->name);
return;
}
}
- printk("%s: IDE controller on PCI bus %02x dev %02x\n", dev->name, dev->bus->number, dev->devfn);
+ printk("ATA: %s: controller on PCI bus %02x dev %02x\n",
+ dev->name, dev->bus->number, dev->devfn);
setup_pci_device(dev, d);
if (!dev2)
return;
d2 = d;
- printk("%s: IDE controller on PCI bus %02x dev %02x\n", dev2->name, dev2->bus->number, dev2->devfn);
+ printk("ATA: %s: controller on PCI bus %02x dev %02x\n",
+ dev2->name, dev2->bus->number, dev2->devfn);
setup_pci_device(dev2, d2);
}
vendor = dev->vendor;
device = dev->device;
+
+
/* Look up the chipset information.
+ * We expect only one match.
*/
- d = pci_chipsets;
- while (d->vendor && !(d->vendor == vendor && d->device == device))
- ++d;
+ for (d = ata_pci_device_list; d; d = d->next) {
+ if (d->vendor == vendor && d->device == device)
+ break;
+ }
+
+ if (!d) {
+ if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
+ printk(KERN_INFO "ATA: unknown interface: %s, on PCI slot %s\n",
+ dev->name, dev->slot_name);
+ }
+ return;
+ }
if (d->init_channel == ATA_PCI_IGNORE)
printk(KERN_INFO "ATA: %s: ignored by PCI bus scan\n", dev->name);
hpt366_device_order_fixup(dev, d);
if (d->device == PCI_DEVICE_ID_TTI_HPT374)
hpt374_device_order_fixup(dev, d);
- }
- else if (d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20268R)
+ } else if (d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20268R)
pdc20270_device_order_fixup(dev, d);
- else if (!(d->vendor == 0 && d->device == 0) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
- if (d->vendor == 0 && d->device == 0)
- printk(KERN_INFO "ATA: unknown interface: %s (%04x:%04x) on PCI slot %s\n",
- dev->name, vendor, device, dev->slot_name);
- else
- printk(KERN_INFO "ATA: interface: %s, on PCI slot %s\n", dev->name, dev->slot_name);
+ else if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
+ printk(KERN_INFO "ATA: %s (%04x:%04x) on PCI slot %s\n",
+ dev->name, vendor, device, dev->slot_name);
setup_pci_device(dev, d);
}
}
}
}
}
+
+/* known chips without particular chipset driver module data table */
+/* Those are id's of chips we don't deal currently with, but which still need
+ * some generic quirk handling.
+ */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_PCTECH,
+ device: PCI_DEVICE_ID_PCTECH_SAMURAI_IDE,
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_CMD,
+ device: PCI_DEVICE_ID_CMD_640,
+ init_channel: ATA_PCI_IGNORE,
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_NS,
+ device: PCI_DEVICE_ID_NS_87410,
+ enablebits: {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_HINT,
+ device: PCI_DEVICE_ID_HINT,
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_HOLTEK,
+ device: PCI_DEVICE_ID_HOLTEK_6565,
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82371MX,
+ enablebits: {{0x6D,0x80,0x80}, {0x00,0x00,0x00}},
+ bootable: ON_BOARD, 0,
+ flags: ATA_F_NODMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_UMC,
+ device: PCI_DEVICE_ID_UMC_UM8673F,
+ bootable: ON_BOARD,
+ flags: ATA_F_FIXIRQ
+ },
+ {
+ vendor: PCI_VENDOR_ID_UMC,
+ device: PCI_DEVICE_ID_UMC_UM8886A,
+ bootable: ON_BOARD,
+ flags: ATA_F_FIXIRQ
+ },
+ {
+ vendor: PCI_VENDOR_ID_UMC,
+ device: PCI_DEVICE_ID_UMC_UM8886BF,
+ bootable: ON_BOARD,
+ flags: ATA_F_FIXIRQ
+ },
+ {
+ vendor: PCI_VENDOR_ID_VIA,
+ device: PCI_DEVICE_ID_VIA_82C561,
+ bootable: ON_BOARD,
+ flags: ATA_F_NOADMA
+ }
+};
+
+int __init init_ata_pci_misc(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
+}
if (!noautodma)
ide_hwifs[ix].autodma = 1;
#endif
+ ide_hwifs[ix].unmask = 1;
}
}
#include <asm/bitops.h>
#include "ata-timing.h"
+#include "pcihost.h"
/*
* Those will be moved into separate header files eventually.
*/
-#ifdef CONFIG_BLK_DEV_RZ1000
-extern void ide_probe_for_rz100x(void);
-#endif
#ifdef CONFIG_ETRAX_IDE
extern void init_e100_ide(void);
#endif
return ide_started; /* continue polling */
}
ch->poll_timeout = 0; /* end of polling */
- printk("%s: ATAPI reset timed-out, status=0x%02x\n", drive->name, stat);
+ printk("%s: ATAPI reset timed out, status=0x%02x\n", drive->name, stat);
return do_reset1 (drive, 1); /* do it the old fashioned way */
}
ch->poll_timeout = 0; /* done polling */
ide_set_handler(drive, reset_pollfunc, HZ/20, NULL);
return ide_started; /* continue polling */
}
- printk("%s: reset timed-out, status=0x%02x\n", ch->name, stat);
+ printk("%s: reset timed out, status=0x%02x\n", ch->name, stat);
drive->failures++;
} else {
printk("%s: reset: ", ch->name);
return 0;
}
- case HDIO_GETGEO_BIG:
- {
- struct hd_big_geometry *loc = (struct hd_big_geometry *) arg;
-
- if (!loc || (drive->type != ATA_DISK && drive->type != ATA_FLOPPY))
- return -EINVAL;
-
- if (put_user(drive->bios_head, (byte *) &loc->heads)) return -EFAULT;
- if (put_user(drive->bios_sect, (byte *) &loc->sectors)) return -EFAULT;
- if (put_user(drive->bios_cyl, (unsigned int *) &loc->cylinders)) return -EFAULT;
- if (put_user((unsigned)drive->part[minor(inode->i_rdev)&PARTN_MASK].start_sect,
- (unsigned long *) &loc->start)) return -EFAULT;
- return 0;
- }
-
case HDIO_GETGEO_BIG_RAW:
{
struct hd_big_geometry *loc = (struct hd_big_geometry *) arg;
if (!loc || (drive->type != ATA_DISK && drive->type != ATA_FLOPPY))
return -EINVAL;
- if (put_user(drive->head, (byte *) &loc->heads)) return -EFAULT;
- if (put_user(drive->sect, (byte *) &loc->sectors)) return -EFAULT;
+ if (put_user(drive->head, (u8 *) &loc->heads)) return -EFAULT;
+ if (put_user(drive->sect, (u8 *) &loc->sectors)) return -EFAULT;
if (put_user(drive->cyl, (unsigned int *) &loc->cylinders)) return -EFAULT;
if (put_user((unsigned)drive->part[minor(inode->i_rdev)&PARTN_MASK].start_sect,
(unsigned long *) &loc->start)) return -EFAULT;
init_pdc4030();
goto done;
}
-#endif /* CONFIG_BLK_DEV_PDC4030 */
+#endif
#ifdef CONFIG_BLK_DEV_ALI14XX
case -17: /* "ali14xx" */
{
initializing = 1;
+#ifdef CONFIG_PCI
+ /*
+ * Register the host chip drivers.
+ */
+# ifdef CONFIG_BLK_DEV_PIIX
+ init_piix();
+# endif
+# ifdef CONFIG_BLK_DEV_VIA82CXXX
+ init_via82cxxx();
+# endif
+# ifdef CONFIG_BLK_DEV_PDC202XX
+ init_pdc202xx();
+# endif
+# ifdef CONFIG_BLK_DEV_RZ1000
+ init_rz1000();
+# endif
+# ifdef CONFIG_BLK_DEV_SIS5513
+ init_sis5513();
+# endif
+# ifdef CONFIG_BLK_DEV_CMD64X
+ init_cmd64x();
+# endif
+# ifdef CONFIG_BLK_DEV_OPTI621
+ init_opti621();
+# endif
+# ifdef CONFIG_BLK_DEV_TRM290
+ init_trm290();
+# endif
+# ifdef CONFIG_BLK_DEV_NS87415
+ init_ns87415();
+# endif
+# ifdef CONFIG_BLK_DEV_AEC62XX
+ init_aec62xx();
+# endif
+# ifdef CONFIG_BLK_DEV_SL82C105
+ init_sl82c105();
+# endif
+# ifdef CONFIG_BLK_DEV_HPT34X
+ init_hpt34x();
+# endif
+# ifdef CONFIG_BLK_DEV_HPT366
+ init_hpt366();
+# endif
+# ifdef CONFIG_BLK_DEV_ALI15X3
+ init_ali15x3();
+# endif
+# ifdef CONFIG_BLK_DEV_CY82C693
+ init_cy82c693();
+# endif
+# ifdef CONFIG_BLK_DEV_CS5530
+ init_cs5530();
+# endif
+# ifdef CONFIG_BLK_DEV_AMD74XX
+ init_amd74xx();
+# endif
+# ifdef CONFIG_BLK_DEV_PDC_ADMA
+ init_pdcadma();
+# endif
+# ifdef CONFIG_BLK_DEV_SVWKS
+ init_svwks();
+# endif
+# ifdef CONFIG_BLK_DEV_IT8172
+ init_it8172();
+# endif
+
+ init_ata_pci_misc();
+
/*
* Detect and initialize "known" IDE host chip types.
*/
-#ifdef CONFIG_PCI
if (pci_present()) {
# ifdef CONFIG_PCI
ide_scan_pcibus(ide_scan_direction);
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/io.h>
#include <asm/it8172/it8172_int.h>
#include "ata-timing.h"
+#include "pcihost.h"
/*
* Prototypes
#endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_IT8172_TUNING) */
-unsigned int __init pci_init_it8172 (struct pci_dev *dev)
+static unsigned int __init pci_init_it8172 (struct pci_dev *dev)
{
unsigned char progif;
-
+
/*
* Place both IDE interfaces into PCI "native" mode
*/
(void)pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
- (void)pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
+ (void)pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
return IT8172_IDE_IRQ;
}
-void __init ide_init_it8172(struct ata_channel *hwif)
+static void __init ide_init_it8172(struct ata_channel *hwif)
{
struct pci_dev* dev = hwif->pci_dev;
unsigned long cmdBase, ctrlBase;
-
+
hwif->tuneproc = &it8172_tune_drive;
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
#ifndef CONFIG_BLK_DEV_IDEDMA
hwif->autodma = 0;
#else /* CONFIG_BLK_DEV_IDEDMA */
-#ifdef CONFIG_IT8172_TUNING
+# ifdef CONFIG_IT8172_TUNING
hwif->autodma = 1;
hwif->dmaproc = &it8172_dmaproc;
hwif->speedproc = &it8172_tune_chipset;
-#endif /* CONFIG_IT8172_TUNING */
-#endif /* !CONFIG_BLK_DEV_IDEDMA */
+# endif
+#endif
cmdBase = dev->resource[0].start;
ctrlBase = dev->resource[1].start;
-
+
ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
hwif->noprobe = 0;
}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_ITE,
+ device: PCI_DEVICE_ID_ITE_IT8172G,
+ init_chipset: pci_init_it8172,
+ init_channel: ide_init_it8172,
+ exnablebits: {{0x00,0x00,0x00}, {0x40,0x00,0x01} },
+ bootable: ON_BOARD
+};
+
+int __init init_it8172(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
-#include <linux/ide.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/io.h>
+#include "pcihost.h"
+
static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
/*
}
#endif
-void __init ide_init_ns87415(struct ata_channel *hwif)
+static void __init ide_init_ns87415(struct ata_channel *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
unsigned int ctrl, using_inta;
hwif->selectproc = &ns87415_selectproc;
}
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_NS,
+ device: PCI_DEVICE_ID_NS_87415,
+ init_channel: ide_init_ns87415,
+ bootable: ON_BOARD,
+};
+
+int __init init_ns87415(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
*
* Authors:
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
+#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#define OPTI621_MAX_PIO 3
/* In fact, I do not have any PIO 4 drive
/*
* ide_init_opti621() is called once for each hwif found at boot.
*/
-void __init ide_init_opti621(struct ata_channel *hwif)
+static void __init ide_init_opti621(struct ata_channel *hwif)
{
hwif->drives[0].drive_data = PIO_DONT_KNOW;
hwif->drives[1].drive_data = PIO_DONT_KNOW;
hwif->tuneproc = &opti621_tune_drive;
}
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_OPTI,
+ device: PCI_DEVICE_ID_OPTI_82C621,
+ init_channel: ide_init_opti621,
+ enablebits: {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_OPTI,
+ device: PCI_DEVICE_ID_OPTI_82C825,
+ init_channel: ide_init_opti621,
+ enablebits: {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
+ bootable: ON_BOARD
+ },
+};
+
+int __init init_opti621(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
+}
--- /dev/null
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
+ * Copyright (C) 2002 Marcin Dalecki <martin@dalecki.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Declarations needed for the handling of PCI (mostly) based host chip set
+ * interfaces.
+ */
+
+#ifdef CONFIG_BLK_DEV_PIIX
+extern int init_piix(void);
+#endif
+#ifdef CONFIG_BLK_DEV_VIA82CXXX
+extern int init_via82cxxx(void);
+#endif
+#ifdef CONFIG_BLK_DEV_PDC202XX
+extern int init_pdc202xx(void);
+#endif
+#ifdef CONFIG_BLK_DEV_RZ1000
+extern int init_rz1000(void);
+#endif
+#ifdef CONFIG_BLK_DEV_SIS5513
+extern int init_sis5513(void);
+#endif
+#ifdef CONFIG_BLK_DEV_CMD64X
+extern int init_cmd64x(void);
+#endif
+#ifdef CONFIG_BLK_DEV_OPTI621
+extern int init_opti621(void);
+#endif
+#ifdef CONFIG_BLK_DEV_TRM290
+extern int init_trm290(void);
+#endif
+#ifdef CONFIG_BLK_DEV_NS87415
+extern int init_ns87415(void);
+#endif
+#ifdef CONFIG_BLK_DEV_AEC62XX
+extern int init_aec62xx(void);
+#endif
+#ifdef CONFIG_BLK_DEV_SL82C105
+extern int init_sl82c105(void);
+#endif
+#ifdef CONFIG_BLK_DEV_HPT34X
+extern int init_hpt34x(void);
+#endif
+#ifdef CONFIG_BLK_DEV_HPT366
+extern int init_hpt366(void);
+#endif
+#ifdef CONFIG_BLK_DEV_ALI15X3
+extern int init_ali15x3(void);
+#endif
+#ifdef CONFIG_BLK_DEV_CY82C693
+extern int init_cy82c693(void);
+#endif
+#ifdef CONFIG_BLK_DEV_CS5530
+extern int init_cs5530(void);
+#endif
+#ifdef CONFIG_BLK_DEV_AMD74XX
+extern int init_amd74xx(void);
+#endif
+#ifdef CONFIG_BLK_DEV_PDC_ADMA
+extern int init_pdcadma(void);
+#endif
+#ifdef CONFIG_BLK_DEV_SVWKS
+extern int init_svwks(void);
+#endif
+#ifdef CONFIG_BLK_DEV_IT8172
+extern int init_it8172(void);
+#endif
+extern int init_ata_pci_misc(void);
+
+/*
+ * Some combi chips, which can be used on the PCI bus or the VL bus can be in
+ * some systems acessed either through the PCI config space or through the
+ * hosts IO bus. If the corresponding initialization driver is using the host
+ * IO space to deal with them please define the following.
+ */
+
+#define ATA_PCI_IGNORE ((void *)-1)
+
+/*
+ * Just to prevent us from having too many tinny headers we have consolidated
+ * all those declarations here.
+ */
+
+#ifdef CONFIG_BLK_DEV_RZ1000
+extern void ide_probe_for_rz100x(void);
+#endif
+
+typedef struct ide_pci_enablebit_s {
+ u8 reg; /* pci configuration register holding the enable-bit */
+ u8 mask; /* mask used to isolate the enable-bit */
+ u8 val; /* expected value of masked register when "enabled" */
+} ide_pci_enablebit_t;
+
+/* Flags used to untangle quirk handling.
+ */
+#define ATA_F_DMA 0x01
+#define ATA_F_NODMA 0x02 /* no DMA mode supported at all */
+#define ATA_F_NOADMA 0x04 /* DMA has to be enabled explicitely */
+#define ATA_F_FIXIRQ 0x08 /* fixed irq wiring */
+#define ATA_F_SER 0x10 /* serialize on first and second channel interrupts */
+#define ATA_F_IRQ 0x20 /* trust IRQ information from config */
+#define ATA_F_PHACK 0x40 /* apply PROMISE hacks */
+#define ATA_F_HPTHACK 0x80 /* apply HPT366 hacks */
+
+
+struct ata_pci_device {
+ unsigned short vendor;
+ unsigned short device;
+ unsigned int (*init_chipset)(struct pci_dev *);
+ unsigned int (*ata66_check)(struct ata_channel *);
+ void (*init_channel)(struct ata_channel *);
+ void (*init_dma)(struct ata_channel *, unsigned long);
+ ide_pci_enablebit_t enablebits[2];
+ unsigned int bootable;
+ unsigned int extra;
+ unsigned int flags;
+ struct ata_pci_device *next; /* beware we link the netries in pleace */
+};
+
+extern void ata_register_chipset(struct ata_pci_device *d);
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/pdc202xx.c Version 0.30 Mar. 18, 2000
*
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
#define PDC202XX_DEBUG_DRIVE_INFO 0
#define PDC202XX_DECODE_REGISTER_INFO 0
#endif /* PDC202XX_DECODE_REGISTER_INFO */
-static int check_in_drive_lists (ide_drive_t *drive, const char **list)
+static int check_in_drive_lists(struct ata_device *drive, const char **list)
{
struct hd_driveid *id = drive->id;
return 0;
}
-static int pdc202xx_tune_chipset (ide_drive_t *drive, byte speed)
+static int pdc202xx_tune_chipset(struct ata_device *drive, byte speed)
{
struct ata_channel *hwif = drive->channel;
struct pci_dev *dev = hwif->pci_dev;
return err;
}
-static int pdc202xx_new_tune_chipset (ide_drive_t *drive, byte speed)
+static int pdc202xx_new_tune_chipset(struct ata_device *drive, byte speed)
{
struct ata_channel *hwif = drive->channel;
#ifdef CONFIG_BLK_DEV_IDEDMA
* 180, 120, 90, 90, 90, 60, 30
* 11, 5, 4, 3, 2, 1, 0
*/
-static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
+static int config_chipset_for_pio(struct ata_device *drive, byte pio)
{
byte speed = 0x00;
return ((int) pdc202xx_tune_chipset(drive, speed));
}
-static void pdc202xx_tune_drive (ide_drive_t *drive, byte pio)
+static void pdc202xx_tune_drive(struct ata_device *drive, byte pio)
{
(void) config_chipset_for_pio(drive, pio);
}
#ifdef CONFIG_BLK_DEV_IDEDMA
-static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
+static int config_chipset_for_dma(struct ata_device *drive, byte ultra)
{
struct hd_driveid *id = drive->id;
struct ata_channel *hwif = drive->channel;
0);
}
-static int config_drive_xfer_rate (ide_drive_t *drive)
+static int config_drive_xfer_rate(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
struct ata_channel *hwif = drive->channel;
return 0;
}
-int pdc202xx_quirkproc (ide_drive_t *drive)
+int pdc202xx_quirkproc(struct ata_device *drive)
{
return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
}
}
#endif
-void pdc202xx_new_reset (ide_drive_t *drive)
+void pdc202xx_new_reset(struct ata_device *drive)
{
OUT_BYTE(0x04,IDE_CONTROL_REG);
mdelay(1000);
drive->channel->unit ? "Secondary" : "Primary");
}
-void pdc202xx_reset (ide_drive_t *drive)
+void pdc202xx_reset(struct ata_device *drive)
{
unsigned long high_16 = pci_resource_start(drive->channel->pci_dev, 4);
byte udma_speed_flag = IN_BYTE(high_16 + 0x001f);
* this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
* HOTSWAP ATA Infrastructure.
*/
-static int pdc202xx_tristate (ide_drive_t * drive, int state)
+static int pdc202xx_tristate(struct ata_device * drive, int state)
{
#if 0
struct ata_channel *hwif = drive->channel;
return 0;
}
-unsigned int __init pci_init_pdc202xx(struct pci_dev *dev)
+static unsigned int __init pdc202xx_init_chipset(struct pci_dev *dev)
{
unsigned long high_16 = pci_resource_start(dev, 4);
byte udma_speed_flag = IN_BYTE(high_16 + 0x001f);
OUT_BYTE(secondary_mode|1, high_16 + 0x001b);
printk("%s\n", (IN_BYTE(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
}
-#endif /* CONFIG_PDC202XX_MASTER */
+#endif
fttk_tx_series:
bmide_dev = dev;
pdc202xx_display_info = &pdc202xx_get_info;
}
-#endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
+#endif
return dev->irq;
}
-unsigned int __init ata66_pdc202xx(struct ata_channel *hwif)
+static unsigned int __init ata66_pdc202xx(struct ata_channel *hwif)
{
unsigned short mask = (hwif->unit) ? (1<<11) : (1<<10);
unsigned short CIS;
}
}
-void __init ide_init_pdc202xx(struct ata_channel *hwif)
+static void __init ide_init_pdc202xx(struct ata_channel *hwif)
{
hwif->tuneproc = &pdc202xx_tune_drive;
hwif->quirkproc = &pdc202xx_quirkproc;
hwif->autodma = 0;
#endif
}
+
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+#ifdef CONFIG_PDC202XX_FORCE
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20246,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: NULL,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ extra: 16,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20262,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20265,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: ON_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20267,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+#else
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20246,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: NULL,
+ init_channel: ide_init_pdc202xx,
+ enablebits: {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
+ bootable: OFF_BOARD,
+ extra: 16,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20262,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ enablebits: {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
+ bootable: OFF_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20265,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ enablebits: {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
+ bootable: OFF_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_PHACK | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20267,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ exnablebits: {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
+ bootable: OFF_BOARD,
+ extra: 48,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+#endif
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20268,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ /* Promise used a different PCI identification for the raid card
+ * apparently to try and prevent Linux detecting it and using our own
+ * raid code. We want to detect it for the ataraid drivers, so we have
+ * to list both here.. */
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20268R,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20269,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20275,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_PROMISE,
+ device: PCI_DEVICE_ID_PROMISE_20276,
+ init_chipset: pdc202xx_init_chipset,
+ ata66_check: ata66_pdc202xx,
+ init_channel: ide_init_pdc202xx,
+ bootable: OFF_BOARD,
+ flags: ATA_F_IRQ | ATA_F_DMA
+ },
+};
+
+int __init init_pdc202xx(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
+}
return ide_started; /* continue polling... */
}
ch->poll_timeout = 0;
- printk(KERN_ERR "%s: write timed-out!\n",drive->name);
+ printk(KERN_ERR "%s: write timed out!\n",drive->name);
return ide_error(drive, "write timeout", GET_STAT());
}
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
#undef DISPLAY_PDCADMA_TIMINGS
}
#endif
-unsigned int __init pci_init_pdcadma(struct pci_dev *dev)
+static unsigned int __init pci_init_pdcadma(struct pci_dev *dev)
{
#if defined(DISPLAY_PDCADMA_TIMINGS) && defined(CONFIG_PROC_FS)
if (!pdcadma_proc) {
return 0;
}
-unsigned int __init ata66_pdcadma(struct ata_channel *channel)
+static unsigned int __init ata66_pdcadma(struct ata_channel *channel)
{
return 1;
}
-void __init ide_init_pdcadma(struct ata_channel *hwif)
+static void __init ide_init_pdcadma(struct ata_channel *hwif)
{
hwif->autodma = 0;
hwif->dma_base = 0;
// }
}
-void __init ide_dmacapable_pdcadma(struct ata_channel *hwif, unsigned long dmabase)
+static void __init ide_dmacapable_pdcadma(struct ata_channel *hwif, unsigned long dmabase)
{
// ide_setup_dma(hwif, dmabase, 8);
}
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841,
+ pci_init_pdcadma,
+ ata66_pdcadma,
+ ide_init_pdcadma,
+ ide_dmacapable_pdcadma,
+ {
+ {0x00,0x00,0x00},
+ {0x00,0x00,0x00}
+ },
+ OFF_BOARD,
+ 0,
+ ATA_F_NODMA
+};
+
+int __init init_pdcadma(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
return 0;
}
- case HDIO_GETGEO_BIG:
- {
- struct hd_big_geometry *loc = (struct hd_big_geometry *) arg;
- if (!loc) return -EINVAL;
- if (put_user(raid[minor].geom.heads, (byte *) &loc->heads)) return -EFAULT;
- if (put_user(raid[minor].geom.sectors, (byte *) &loc->sectors)) return -EFAULT;
- if (put_user(raid[minor].geom.cylinders, (unsigned int *) &loc->cylinders)) return -EFAULT;
- if (put_user((unsigned)ataraid_gendisk.part[minor(inode->i_rdev)].start_sect,
- (unsigned long *) &loc->start)) return -EFAULT;
- return 0;
- }
-
-
case BLKROSET:
case BLKROGET:
case BLKSSZGET:
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* $Id: piix.c,v 1.3 2002/03/29 16:06:06 vojtech Exp $
*
* Copyright (c) 2000-2002 Vojtech Pavlik
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
+
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#define PIIX_IDETIM0 0x40
#define PIIX_IDETIM1 0x42
* The initialization callback. Here we determine the IDE chip type
* and initialize its drive independent registers.
*/
-
-unsigned int __init pci_init_piix(struct pci_dev *dev, const char *name)
+static unsigned int __init piix_init_chipset(struct pci_dev *dev)
{
unsigned int u;
unsigned short w;
return 0;
}
-unsigned int __init ata66_piix(struct ata_channel *hwif)
+static unsigned int __init piix_ata66_check(struct ata_channel *hwif)
{
return ((piix_enabled & piix_80w) >> hwif->unit) & 1;
}
-void __init ide_init_piix(struct ata_channel *hwif)
+static void __init piix_init_channel(struct ata_channel *hwif)
{
int i;
* We allow the BM-DMA driver only work on enabled interfaces,
* and only if DMA is safe with the chip and bridge.
*/
-
-void __init ide_dmacapable_piix(struct ata_channel *hwif, unsigned long dmabase)
+static void __init piix_init_dma(struct ata_channel *hwif, unsigned long dmabase)
{
if (((piix_enabled >> hwif->unit) & 1)
&& !(piix_config->flags & PIIX_NODMA))
- ide_setup_dma(hwif, dmabase, 8);
+ ata_init_dma(hwif, dmabase);
+}
+
+
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82371FB_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82371SB_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82371AB,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82443MX_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82372FB_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801AA_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801AB_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801BA_9,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801BA_8,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801E_9,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801CA_10,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801CA_11,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_INTEL,
+ device: PCI_DEVICE_ID_INTEL_82801DB_9,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_EFAR,
+ device: PCI_DEVICE_ID_EFAR_SLC90E66_1,
+ init_chipset: piix_init_chipset,
+ ata66_check: piix_ata66_check,
+ init_channel: piix_init_channel,
+ init_dma: piix_init_dma,
+ enablebits: {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
+ bootable: ON_BOARD
+ },
+};
+
+int __init init_piix(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* Copyright (C) 1995-1998 Linus Torvalds & author (see below)
*
* Principal Author: mlord@pobox.com (Mark Lord)
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
-#include <linux/ide.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/io.h>
#ifdef CONFIG_PCI
-void __init ide_init_rz1000(struct ata_channel *hwif) /* called from ide-pci.c */
+#include "pcihost.h"
+
+static void __init rz1000_init_channel(struct ata_channel *hwif)
{
unsigned short reg;
struct pci_dev *dev = hwif->pci_dev;
}
}
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_PCTECH,
+ device: PCI_DEVICE_ID_PCTECH_RZ1000,
+ init_channel: rz1000_init_channel,
+ bootable: ON_BOARD
+ },
+ {
+ vendor: PCI_VENDOR_ID_PCTECH,
+ device: PCI_DEVICE_ID_PCTECH_RZ1001,
+ init_channel: rz1000_init_channel,
+ bootable: ON_BOARD
+ },
+};
+
+int __init init_rz1000(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
+}
+
#else
static void __init init_rz1000 (struct pci_dev *dev, const char *name)
struct pci_dev *dev = NULL;
while ((dev = pci_find_device(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000, dev))!=NULL)
- init_rz1000 (dev, "RZ1000");
+ rz1000_init (dev, "RZ1000");
while ((dev = pci_find_device(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001, dev))!=NULL)
- init_rz1000 (dev, "RZ1001");
+ rz1000_init (dev, "RZ1001");
}
#endif
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/serverworks.c Version 0.3 26 Oct 2001
*
* May be copied or modified under the terms of the GNU General Public License
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
-#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>
+#include <linux/ide.h>
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#undef DISPLAY_SVWKS_TIMINGS
#undef SVWKS_DEBUG_DRIVE_INFO
static struct pci_dev *isa_dev;
-static int svwks_tune_chipset (ide_drive_t *drive, byte speed)
+static int svwks_tune_chipset(struct ata_device *drive, byte speed)
{
byte udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
byte dma_modes[] = { 0x77, 0x21, 0x20 };
pci_write_config_byte(dev, drive_pci2, dma_timing);
pci_write_config_byte(dev, drive_pci3, ultra_timing);
pci_write_config_byte(dev, 0x54, ultra_enable);
-
+
if (speed > XFER_PIO_4)
outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
else
return err;
}
-static void config_chipset_for_pio (ide_drive_t *drive)
+static void config_chipset_for_pio(struct ata_device *drive)
{
unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
unsigned short xfer_pio = drive->id->eide_pio_modes;
drive->current_speed = speed;
}
-static void svwks_tune_drive (ide_drive_t *drive, byte pio)
+static void svwks_tune_drive(struct ata_device *drive, byte pio)
{
byte speed;
switch(pio) {
}
#ifdef CONFIG_BLK_DEV_IDEDMA
-static int config_chipset_for_dma (ide_drive_t *drive)
+static int config_chipset_for_dma(struct ata_device *drive)
{
struct hd_driveid *id = drive->id;
struct pci_dev *dev = drive->channel->pci_dev;
}
#endif
-unsigned int __init pci_init_svwks(struct pci_dev *dev)
+static unsigned int __init svwks_init_chipset(struct pci_dev *dev)
{
unsigned int reg;
byte btr;
return 0;
}
-unsigned int __init ata66_svwks(struct ata_channel *hwif)
+static unsigned int __init svwks_ata66_check(struct ata_channel *hwif)
{
struct pci_dev *dev = hwif->pci_dev;
return 0;
}
-void __init ide_init_svwks(struct ata_channel *hwif)
+static void __init ide_init_svwks(struct ata_channel *hwif)
{
if (!hwif->irq)
hwif->irq = hwif->unit ? 15 : 14;
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
hwif->autodma = 0;
-#else /* CONFIG_BLK_DEV_IDEDMA */
+#else
if (hwif->dma_base) {
#ifdef CONFIG_IDEDMA_AUTO
if (!noautodma)
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
}
-#endif /* !CONFIG_BLK_DEV_IDEDMA */
+#endif
+}
+
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_SERVERWORKS,
+ device: PCI_DEVICE_ID_SERVERWORKS_OSB4IDE,
+ init_chipset: svwks_init_chipset,
+ ata66_check: svwks_ata66_check,
+ init_channel: ide_init_svwks,
+ bootable: ON_BOARD,
+ flags: ATA_F_DMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_SERVERWORKS,
+ device: PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,
+ init_chipset: svwks_init_chipset,
+ ata66_check: svwks_ata66_check,
+ init_channel: ide_init_svwks,
+ bootable: ON_BOARD
+ },
+};
+
+int __init init_svwks(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
-#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
+#include <linux/hdreg.h>
#include <asm/io.h>
#include <asm/irq.h>
#include "ata-timing.h"
+#include "pcihost.h"
/* When DEBUG is defined it outputs initial PCI config register
values and changes made to them by the driver */
#endif
/* Chip detection and general config */
-unsigned int __init pci_init_sis5513(struct pci_dev *dev)
+static unsigned int __init pci_init_sis5513(struct pci_dev *dev)
{
struct pci_dev *host;
int i = 0;
return 0;
}
-unsigned int __init ata66_sis5513(struct ata_channel *hwif)
+static unsigned int __init ata66_sis5513(struct ata_channel *hwif)
{
byte reg48h = 0, ata66 = 0;
byte mask = hwif->unit ? 0x20 : 0x10;
return ata66;
}
-void __init ide_init_sis5513(struct ata_channel *hwif)
+static void __init ide_init_sis5513(struct ata_channel *hwif)
{
hwif->irq = hwif->unit ? 15 : 14;
}
return;
}
+
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_SI,
+ device: PCI_DEVICE_ID_SI_5513,
+ init_chipset: pci_init_sis5513,
+ ata66_check: ata66_sis5513,
+ init_channel: ide_init_sis5513,
+ enablebits: {{0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
+ bootable: ON_BOARD,
+ flags: ATA_F_NOADMA
+};
+
+int __init init_sis5513(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
#include <asm/dma.h>
#include "ata-timing.h"
+#include "pcihost.h"
extern char *ide_xfer_verbose (byte xfer_rate);
/*
* Enable the PCI device
*/
-unsigned int __init pci_init_sl82c105(struct pci_dev *dev)
+static unsigned int __init sl82c105_init_chipset(struct pci_dev *dev)
{
unsigned char ctrl_stat;
return dev->irq;
}
-void __init dma_init_sl82c105(struct ata_channel *hwif, unsigned long dma_base)
+static void __init sl82c105_init_dma(struct ata_channel *hwif, unsigned long dma_base)
{
unsigned int rev;
byte dma_state;
outb(dma_state, dma_base + 2);
hwif->XXX_udma = NULL;
- ide_setup_dma(hwif, dma_base, 8);
+ ata_init_dma(hwif, dma_base);
if (hwif->XXX_udma)
hwif->XXX_udma = sl82c105_dmaproc;
}
/*
* Initialise the chip
*/
-void __init ide_init_sl82c105(struct ata_channel *hwif)
+static void __init sl82c105_init_channel(struct ata_channel *hwif)
{
hwif->tuneproc = tune_sl82c105;
}
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_WINBOND,
+ device: PCI_DEVICE_ID_WINBOND_82C105,
+ init_chipset: sl82c105_init_chipset,
+ init_channel: sl82c105_init_channel,
+ init_dma: sl82c105_init_dma,
+ enablebits: { {0x40,0x01,0x01}, {0x40,0x10,0x10} },
+ bootable: ON_BOARD
+};
+
+int __init init_sl82c105(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* linux/drivers/ide/trm290.c Version 1.02 Mar. 18, 2000
*
* Copyright (c) 1997-1998 Mark Lord
#include <asm/io.h>
+#include "pcihost.h"
+
static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
struct ata_channel *hwif = drive->channel;
/*
* Invoked from ide-dma.c at boot time.
*/
-void __init ide_init_trm290(struct ata_channel *hwif)
+static void __init trm290_init_channel(struct ata_channel *hwif)
{
unsigned int cfgbase = 0;
unsigned long flags;
hwif->irq = primary_irq;
}
- ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->unit ? 0x0080 : 0x0000), 3);
+ ata_init_dma(hwif, (hwif->config_data + 4) ^ (hwif->unit ? 0x0080 : 0x0000));
#ifdef CONFIG_BLK_DEV_IDEDMA
hwif->udma_start = trm290_udma_start;
}
#endif
}
+
+/* module data table */
+static struct ata_pci_device chipset __initdata = {
+ vendor: PCI_VENDOR_ID_TEKRAM,
+ device: PCI_DEVICE_ID_TEKRAM_DC290,
+ init_channel: trm290_init_channel,
+ bootable: ON_BOARD
+};
+
+int __init init_trm290(void)
+{
+ ata_register_chipset(&chipset);
+
+ return 0;
+}
-/*
+/**** vi:set ts=8 sts=8 sw=8:************************************************
+ *
* $Id: via82cxxx.c,v 3.34 2002/02/12 11:26:11 vojtech Exp $
*
* Copyright (c) 2000-2001 Vojtech Pavlik
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
+
#include <asm/io.h>
#include "ata-timing.h"
+#include "pcihost.h"
#define VIA_IDE_ENABLE 0x40
#define VIA_IDE_CONFIG 0x41
* and initialize its drive independent registers.
*/
-unsigned int __init pci_init_via82cxxx(struct pci_dev *dev)
+static unsigned int __init via82cxxx_init_chipset(struct pci_dev *dev)
{
struct pci_dev *isa = NULL;
unsigned char t, v;
return 0;
}
-unsigned int __init ata66_via82cxxx(struct ata_channel *hwif)
+static unsigned int __init via82cxxx_ata66_check(struct ata_channel *hwif)
{
return ((via_enabled & via_80w) >> hwif->unit) & 1;
}
-void __init ide_init_via82cxxx(struct ata_channel *hwif)
+static void __init via82cxxx_init_channel(struct ata_channel *hwif)
{
int i;
* We allow the BM-DMA driver to only work on enabled interfaces.
*/
-void __init ide_dmacapable_via82cxxx(struct ata_channel *hwif, unsigned long dmabase)
+static void __init via82cxxx_init_dma(struct ata_channel *hwif, unsigned long dmabase)
{
if ((via_enabled >> hwif->unit) & 1)
- ide_setup_dma(hwif, dmabase, 8);
+ ata_init_dma(hwif, dmabase);
+}
+
+/* module data table */
+static struct ata_pci_device chipsets[] __initdata = {
+ {
+ vendor: PCI_VENDOR_ID_VIA,
+ device: PCI_DEVICE_ID_VIA_82C576_1,
+ init_chipset: via82cxxx_init_chipset,
+ ata66_check: via82cxxx_ata66_check,
+ init_channel: via82cxxx_init_channel,
+ init_dma: via82cxxx_init_dma,
+ enablebits: {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
+ bootable: ON_BOARD,
+ flags: ATA_F_NOADMA
+ },
+ {
+ vendor: PCI_VENDOR_ID_VIA,
+ device: PCI_DEVICE_ID_VIA_82C586_1,
+ init_chipset: via82cxxx_init_chipset,
+ ata66_check: via82cxxx_ata66_check,
+ init_channel: via82cxxx_init_channel,
+ init_dma: via82cxxx_init_dma,
+ enablebits: {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
+ bootable: ON_BOARD,
+ flags: ATA_F_NOADMA
+ },
+};
+
+int __init init_via82cxxx(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
+ ata_register_chipset(&chipsets[i]);
+ }
+
+ return 0;
}
if (rq) kfree (rq);
cmd->result = DID_ERROR << 16;
done(cmd);
+
return 0;
}
-int idescsi_abort (Scsi_Cmnd *cmd)
+/* FIXME: This needs further investigation.
+ */
+int idescsi_device_reset (Scsi_Cmnd *cmd)
{
- return SCSI_ABORT_SNOOZE;
-}
+#if 0
+ ide_drive_t *drive = idescsi_drives[cmd->target];
+ struct request req;
-int idescsi_reset (Scsi_Cmnd *cmd, unsigned int resetflags)
-{
- return SCSI_RESET_SUCCESS;
+ ide_init_drive_cmd(&req);
+ req.flags = REQ_SPECIAL;
+
+ /* FIX ME, the next executable line causes on oops in lk 2.5.10-dj1
+ * [code copied from ide-cd's ide_cdrom_reset(), does it work?]
+ */
+ ide_do_drive_cmd(drive, &req, ide_wait);
+#endif
+ return SUCCESS;
}
int idescsi_bios (Disk *disk, kdev_t dev, int *parm)
info: idescsi_info,
ioctl: idescsi_ioctl,
queuecommand: idescsi_queue,
- abort: idescsi_abort,
- reset: idescsi_reset,
+ eh_device_reset_handler:
+ idescsi_device_reset,
bios_param: idescsi_bios,
can_queue: 10,
this_id: -1,
return -EFAULT;
return 0;
}
- case HDIO_GETGEO_BIG:
- {
- struct hd_big_geometry *loc =
- (struct hd_big_geometry *) arg;
-
- if(!loc)
- return -EINVAL;
- host = sdp->host;
-
- /* default to most commonly used values */
- diskinfo[0] = 0x40;
- diskinfo[1] = 0x20;
- diskinfo[2] = sdkp->capacity >> 11;
-
- /* override with calculated, extended default,
- or driver values */
- if(host->hostt->bios_param != NULL)
- host->hostt->bios_param(sdkp, dev,
- &diskinfo[0]);
- else
- scsicam_bios_param(sdkp, dev, &diskinfo[0]);
- if (put_user(diskinfo[0], &loc->heads) ||
- put_user(diskinfo[1], &loc->sectors) ||
- put_user(diskinfo[2],
- (unsigned int *) &loc->cylinders) ||
- put_user((unsigned)
- get_start_sect(inode->i_rdev),
- (unsigned long *)&loc->start))
- return -EFAULT;
- return 0;
- }
case BLKGETSIZE:
case BLKGETSIZE64:
case BLKROSET:
unsigned long start;
};
-/* BIG GEOMETRY */
+/* BIG GEOMETRY - dying, used only by HDIO_GETGEO_BIG_RAW */
struct hd_big_geometry {
unsigned char heads;
unsigned char sectors;
};
/* hd/ide ctl's that pass (arg) ptrs to user space are numbered 0x033n/0x033n */
-#define HDIO_GETGEO_BIG 0x0330 /* */
+/* 0x330 is reserved - used to be HDIO_GETGEO_BIG */
#define HDIO_GETGEO_BIG_RAW 0x0331 /* */
#define __NEW_HD_DRIVE_ID
extern int ide_unregister_subdriver(struct ata_device *drive);
#ifdef CONFIG_PCI
-# define ON_BOARD 1
-# define NEVER_BOARD 0
+# define ON_BOARD 0
+# define NEVER_BOARD 1
# ifdef CONFIG_BLK_DEV_OFFBOARD
# define OFF_BOARD ON_BOARD
# else
extern int check_drive_lists(struct ata_device *, int good_bad);
extern int XXX_ide_dmaproc(struct ata_device *);
extern void ide_release_dma(struct ata_channel *);
-extern void ide_setup_dma(struct ata_channel *, unsigned long, unsigned int) __init;
extern int ata_start_dma(struct ata_device *, struct request *rq);
+
+extern void ata_init_dma(struct ata_channel *, unsigned long) __init;
#endif
extern spinlock_t ide_lock;
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