[ARM PATCH] 2538/1: S3C2410 - ADC IRQ correct edge handling

Patch from Ben Dooks

The S3C2410 ADC+TC interrupt where being registrered as
edge-sensitive IRQs, but the code was handling them as
if they where level-sensitive.

Signed-off-by: Ben Dooks
Signed-off-by: Russell King

diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 48cc5ef82b35ab02024bbc1f0f8df439c88a328b..b668c48f43990f3648f248f8c17399f884568b4f 100644 (file)
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -39,6 +39,9 @@
  *
  *   04-Nov-2004  Ben Dooks
  *               Fix standard IRQ wake for EINT0..4 and RTC
+ *
+ *   22-Feb-2004  Ben Dooks
+ *               Fixed edge-triggering on ADC IRQ
 */
 
 #include <linux/init.h>
@@ -426,6 +429,23 @@ s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int gro
        }
 }
 
+static inline void
+s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
+{
+       unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
+
+       __raw_writel(bit, S3C2410_SUBSRCPND);
+
+       /* only ack parent if we've got all the irqs (seems we must
+        * ack, all and hope that the irq system retriggers ok when
+        * the interrupt goes off again)
+        */
+
+       if (1) {
+               __raw_writel(parentmask, S3C2410_SRCPND);
+               __raw_writel(parentmask, S3C2410_INTPND);
+       }
+}
 
 /* UART0 */
 
@@ -522,7 +542,7 @@ s3c_irq_adc_unmask(unsigned int irqno)
 static void
 s3c_irq_adc_ack(unsigned int irqno)
 {
-       s3c_irqsub_maskack(irqno, INTMSK_ADCPARENT, 3 << 9);
+       s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
 }
 
 static struct irqchip s3c_irq_adc = {