DRIVERS := $(DRIVERS) drivers/fc4/fc4.a
endif
+ifdef CONFIG_PPC
+DRIVERS := $(DRIVERS) drivers/macintosh/macintosh.a
+endif
+
ifdef CONFIG_MAC
DRIVERS := $(DRIVERS) drivers/macintosh/macintosh.a
endif
O_TARGET := kernel.o
O_OBJS := entry.o traps.o process.o osf_sys.o irq.o signal.o setup.o \
- ptrace.o time.o semaphore.o i8259.o rtc_irq.o
+ ptrace.o time.o semaphore.o i8259.o
OX_OBJS := alpha_ksyms.o
#define MCPCIA_MAX_HOSES 4
-/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. Durango adds
- PCI2 and PCI3 at MID 6 and 7 respectively. */
-
-#define hose2mid(h) ((h) + 4)
-
-
/*
* Given a bus, device, and function number, compute resulting
* configuration space address and setup the MCPCIA_HAXR2 register
struct pci_controler *hose)
{
unsigned long flags;
- unsigned long mid = hose2mid(hose->index);
+ unsigned long mid = MCPCIA_HOSE2MID(hose->index);
unsigned int stat0, value, temp, cpu;
cpu = smp_processor_id();
struct pci_controler *hose)
{
unsigned long flags;
- unsigned long mid = hose2mid(hose->index);
+ unsigned long mid = MCPCIA_HOSE2MID(hose->index);
unsigned int stat0, temp, cpu;
cpu = smp_processor_id();
mcpcia_pci_tbi(struct pci_controler *hose, dma_addr_t start, dma_addr_t end)
{
wmb();
- BUG();
+ *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;
mb();
}
\f
mcpcia_probe_hose(int h)
{
int cpu = smp_processor_id();
- int mid = hose2mid(h);
+ int mid = MCPCIA_HOSE2MID(h);
unsigned int pci_rev;
/* Gotta be REAL careful. If hose is absent, we get an mcheck. */
{
struct pci_controler *hose;
struct resource *io, *mem, *hae_mem;
- int mid = hose2mid(h);
+ int mid = MCPCIA_HOSE2MID(h);
hose = alloc_pci_controler();
io = alloc_resource();
static void __init
mcpcia_startup_hose(struct pci_controler *hose)
{
- int mid = hose2mid(hose->index);
+ int mid = MCPCIA_HOSE2MID(hose->index);
unsigned int tmp;
mcpcia_pci_clr_err(mid);
error was on? */
struct pci_controler *hose;
for (hose = hose_head; hose; hose = hose->next)
- mcpcia_pci_clr_err(hose2mid(hose->index));
+ mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index));
break;
}
case 1:
return PCIBIOS_SUCCESSFUL;
}
-static int
+int
polaris_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
unsigned long pci_addr;
return PCIBIOS_SUCCESSFUL;
}
-static int
+int
polaris_write_config_dword(struct pci_dev *dev, int where, u32 value)
{
unsigned long pci_addr;
#include <asm/system.h>
#include "proto.h"
+#include "irq_impl.h"
#include "pci_impl.h"
write_dword: pyxis_write_config_dword
};
\f
+/* Note mask bit is true for ENABLED irqs. */
+static unsigned long cached_irq_mask;
+
+static inline void
+pyxis_update_irq_hw(unsigned long mask)
+{
+ *(vulp)PYXIS_INT_MASK = mask;
+ mb();
+ *(vulp)PYXIS_INT_MASK;
+}
+
+static inline void
+pyxis_enable_irq(unsigned int irq)
+{
+ pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+}
+
+static inline void
+pyxis_disable_irq(unsigned int irq)
+{
+ pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+}
+
+static unsigned int
+pyxis_startup_irq(unsigned int irq)
+{
+ pyxis_enable_irq(irq);
+ return 0;
+}
+
+static void
+pyxis_mask_and_ack_irq(unsigned int irq)
+{
+ unsigned long bit = 1UL << (irq - 16);
+ unsigned long mask = cached_irq_mask &= ~bit;
+
+ /* Disable the interrupt. */
+ *(vulp)PYXIS_INT_MASK = mask;
+ wmb();
+ /* Ack PYXIS PCI interrupt. */
+ *(vulp)PYXIS_INT_REQ = bit;
+ mb();
+ /* Re-read to force both writes. */
+ *(vulp)PYXIS_INT_MASK;
+}
+
+static struct hw_interrupt_type pyxis_irq_type = {
+ typename: "PYXIS",
+ startup: pyxis_startup_irq,
+ shutdown: pyxis_disable_irq,
+ enable: pyxis_enable_irq,
+ disable: pyxis_disable_irq,
+ ack: pyxis_mask_and_ack_irq,
+ end: pyxis_enable_irq,
+};
+
+void
+pyxis_device_interrupt(unsigned long vector, struct pt_regs *regs)
+{
+ unsigned long pld;
+ unsigned int i;
+
+ /* Read the interrupt summary register of PYXIS */
+ pld = *(vulp)PYXIS_INT_REQ;
+ pld &= cached_irq_mask;
+
+ /*
+ * Now for every possible bit set, work through them and call
+ * the appropriate interrupt handler.
+ */
+ while (pld) {
+ i = ffz(~pld);
+ pld &= pld - 1; /* clear least bit set */
+ if (i == 7)
+ isa_device_interrupt(vector, regs);
+ else
+ handle_irq(16+i, regs);
+ }
+}
+
+void __init
+init_pyxis_irqs(unsigned long ignore_mask)
+{
+ long i;
+
+ *(vulp)PYXIS_INT_MASK = 0; /* disable all */
+ *(vulp)PYXIS_INT_REQ = -1; /* flush all */
+ mb();
+
+ /* Send -INTA pulses to clear any pending interrupts ...*/
+ *(vuip) PYXIS_IACK_SC;
+
+ for (i = 16; i < 48; ++i) {
+ if ((ignore_mask >> i) & 1)
+ continue;
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &pyxis_irq_type;
+ }
+
+ setup_irq(16+7, &isa_cascade_irqaction);
+}
+\f
void
pyxis_pci_tbi(struct pci_controler *hose, dma_addr_t start, dma_addr_t end)
{
__restore_flags(flags);
}
-static void
+static void __init
pyxis_enable_broken_tbi(struct pci_iommu_arena *arena)
{
void *page;
}
\f
#ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
-static long
+static long __init
tsunami_probe_read(volatile unsigned long *vaddr)
{
long dont_care, probe_result;
return probe_result;
}
-static long
+static long __init
tsunami_probe_write(volatile unsigned long *vaddr)
{
long true_contents, probe_result = 1;
-/* started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c */
+/*
+ * linux/arch/alpha/kernel/i8259.c
+ *
+ * This is the 'legacy' 8259A Programmable Interrupt Controller,
+ * present in the majority of PC/AT boxes.
+ *
+ * Started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c.
+ */
#include <linux/init.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <asm/io.h>
-#include <asm/delay.h>
-
-/*
- * This is the 'legacy' 8259A Programmable Interrupt Controller,
- * present in the majority of PC/AT boxes.
- */
-static void enable_8259A_irq(unsigned int irq);
-static void disable_8259A_irq(unsigned int irq);
+#include "proto.h"
+#include "irq_impl.h"
-/* shutdown is same as "disable" */
-#define end_8259A_irq enable_8259A_irq
-#define shutdown_8259A_irq disable_8259A_irq
-static void mask_and_ack_8259A(unsigned int);
+/* Note mask bit is true for DISABLED irqs. */
+static unsigned int cached_irq_mask = 0xffff;
-static unsigned int startup_8259A_irq(unsigned int irq)
+static inline void
+i8259_update_irq_hw(unsigned int irq, unsigned long mask)
{
- enable_8259A_irq(irq);
- return 0; /* never anything pending */
+ int port = 0x21;
+ if (irq & 8) mask >>= 8;
+ if (irq & 8) port = 0xA1;
+ outb(mask, port);
}
-static struct hw_interrupt_type i8259A_irq_type = {
- "XT-PIC",
- startup_8259A_irq,
- shutdown_8259A_irq,
- enable_8259A_irq,
- disable_8259A_irq,
- mask_and_ack_8259A,
- end_8259A_irq
-};
-
-/*
- * 8259A PIC functions to handle ISA devices:
- */
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- */
-static unsigned int cached_irq_mask = 0xffff;
-
-#define __byte(x,y) (((unsigned char *)&(y))[x])
-#define cached_21 (__byte(0,cached_irq_mask))
-#define cached_A1 (__byte(1,cached_irq_mask))
-
-/*
- * These have to be protected by the irq controller spinlock
- * before being called.
- */
-static void disable_8259A_irq(unsigned int irq)
+inline void
+i8259a_enable_irq(unsigned int irq)
{
- unsigned int mask = 1 << irq;
- cached_irq_mask |= mask;
- if (irq & 8)
- outb(cached_A1,0xA1);
- else
- outb(cached_21,0x21);
+ i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
}
-static void enable_8259A_irq(unsigned int irq)
+inline void
+i8259a_disable_irq(unsigned int irq)
{
- unsigned int mask = ~(1 << irq);
- cached_irq_mask &= mask;
- if (irq & 8)
- outb(cached_A1,0xA1);
- else
- outb(cached_21,0x21);
+ i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
}
-static void mask_and_ack_8259A(unsigned int irq)
+void
+i8259a_mask_and_ack_irq(unsigned int irq)
{
- disable_8259A_irq(irq);
+ i8259a_disable_irq(irq);
- /* Ack the interrupt making it the lowest priority */
- /* First the slave .. */
- if (irq > 7) {
- outb(0xE0 | (irq - 8), 0xa0);
+ /* Ack the interrupt making it the lowest priority. */
+ if (irq >= 8) {
+ outb(0xE0 | (irq - 8), 0xa0); /* ack the slave */
irq = 2;
}
- /* .. then the master */
- outb(0xE0 | irq, 0x20);
+ outb(0xE0 | irq, 0x20); /* ack the master */
}
-static void init_8259A(void)
+unsigned int
+i8259a_startup_irq(unsigned int irq)
{
- outb(0xff, 0x21); /* mask all of 8259A-1 */
- outb(0xff, 0xA1); /* mask all of 8259A-2 */
+ i8259a_enable_irq(irq);
+ return 0; /* never anything pending */
}
-/*
- * IRQ2 is cascade interrupt to second interrupt controller
- */
-static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
+struct hw_interrupt_type i8259a_irq_type = {
+ typename: "XT-PIC",
+ startup: i8259a_startup_irq,
+ shutdown: i8259a_disable_irq,
+ enable: i8259a_enable_irq,
+ disable: i8259a_disable_irq,
+ ack: i8259a_mask_and_ack_irq,
+ end: i8259a_enable_irq,
+};
void __init
-init_ISA_irqs (void)
+init_i8259a_irqs(void)
{
- int i;
+ static struct irqaction cascade = {
+ handler: no_action,
+ name: "cascade",
+ };
+
+ long i;
+
+ outb(0xff, 0x21); /* mask all of 8259A-1 */
+ outb(0xff, 0xA1); /* mask all of 8259A-2 */
- for (i = 0; i < NR_IRQS; i++) {
- if (i == RTC_IRQ)
- continue;
- if (i >= 16)
- break;
+ for (i = 0; i < 16; i++) {
irq_desc[i].status = IRQ_DISABLED;
- /*
- * 16 old-style INTA-cycle interrupts:
- */
- irq_desc[i].handler = &i8259A_irq_type;
+ irq_desc[i].handler = &i8259a_irq_type;
}
- init_8259A();
- setup_irq(2, &irq2);
+ setup_irq(2, &cascade);
}
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
-#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/delay.h>
-#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
+#include <asm/dma.h>
#include <asm/bitops.h>
#include <asm/machvec.h>
#include "proto.h"
+#include "irq_impl.h"
#define vulp volatile unsigned long *
#define vuip volatile unsigned int *
/* Only uniprocessor needs this IRQ/BH locking depth, on SMP it lives
in the per-cpu structure for cache reasons. */
-#ifndef __SMP__
+#ifndef CONFIG_SMP
int __local_irq_count;
int __local_bh_count;
unsigned long __irq_attempt[NR_IRQS];
#endif
-#if NR_IRQS > 128
-# error Unable to handle more than 128 irq levels.
-#endif
-
#ifdef CONFIG_ALPHA_GENERIC
#define ACTUAL_NR_IRQS alpha_mv.nr_irqs
#else
#define ACTUAL_NR_IRQS NR_IRQS
#endif
-/* Reserved interrupts. These must NEVER be requested by any driver!
- IRQ 2 used by hw cascade */
-#define IS_RESERVED_IRQ(irq) ((irq)==2)
-
-
/*
- * The ack_irq routine used by 80% of the systems.
+ * Performance counter hook. A module can override this to
+ * do something useful.
*/
-void
-common_ack_irq(unsigned long irq)
-{
- if (irq < 16) {
- /* Ack the interrupt making it the lowest priority */
- /* First the slave .. */
- if (irq > 7) {
- outb(0xE0 | (irq - 8), 0xa0);
- irq = 2;
- }
- /* .. then the master */
- outb(0xE0 | irq, 0x20);
- }
-}
-
-
-
-static void dummy_perf(unsigned long vector, struct pt_regs *regs)
+static void
+dummy_perf(unsigned long vector, struct pt_regs *regs)
{
printk(KERN_CRIT "Performance counter interrupt!\n");
}
* Dispatch device interrupts.
*/
-/* Handle ISA interrupt via the PICs. */
+/*
+ * Handle ISA interrupt via the PICs.
+ */
#if defined(CONFIG_ALPHA_GENERIC)
# define IACK_SC alpha_mv.iack_sc
# define IACK_SC POLARIS_IACK_SC
#elif defined(CONFIG_ALPHA_IRONGATE)
# define IACK_SC IRONGATE_IACK_SC
-#else
- /* This is bogus but necessary to get it to compile on all platforms. */
-# define IACK_SC 1L
#endif
+#if defined(IACK_SC)
void
-isa_device_interrupt(unsigned long vector, struct pt_regs * regs)
+isa_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
-#if 1
/*
* Generate a PCI interrupt acknowledge cycle. The PIC will
* respond with the interrupt vector of the highest priority
}
}
handle_irq(j, regs);
-#else
+}
+#endif
+#if defined(CONFIG_ALPHA_GENERIC) || !defined(IACK_SC)
+void
+isa_no_iack_sc_device_interrupt(unsigned long vector, struct pt_regs *regs)
+{
unsigned long pic;
/*
* write only. This is not true.
*/
pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */
- pic &= ~alpha_irq_mask; /* apply mask */
pic &= 0xFFFB; /* mask out cascade & hibits */
while (pic) {
int j = ffz(~pic);
pic &= pic - 1;
- handle_irq(j, j, regs);
+ handle_irq(j, regs);
}
+}
#endif
+
+/*
+ * Handle interrupts from the SRM, assuming no additional weirdness.
+ */
+
+static inline void
+srm_enable_irq(unsigned int irq)
+{
+ cserve_ena(irq - 16);
+}
+
+static void
+srm_disable_irq(unsigned int irq)
+{
+ cserve_dis(irq - 16);
+}
+
+static unsigned int
+srm_startup_irq(unsigned int irq)
+{
+ srm_enable_irq(irq);
+ return 0;
}
-/* Handle interrupts from the SRM, assuming no additional weirdness. */
+static struct hw_interrupt_type srm_irq_type = {
+ typename: "SRM",
+ startup: srm_startup_irq,
+ shutdown: srm_disable_irq,
+ enable: srm_enable_irq,
+ disable: srm_disable_irq,
+ ack: srm_disable_irq,
+ end: srm_enable_irq,
+};
void
srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
- int irq;
-
- irq = (vector - 0x800) >> 4;
+ int irq = (vector - 0x800) >> 4;
handle_irq(irq, regs);
}
+void __init
+init_srm_irqs(long max, unsigned long ignore_mask)
+{
+ long i;
+
+ for (i = 16; i < max; ++i) {
+ if (i < 64 && ((ignore_mask >> i) & 1))
+ continue;
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &srm_irq_type;
+ }
+}
/*
- * Special irq handlers.
+ * The not-handled irq handler.
+ */
+
+static void
+noirq_enable_disable(unsigned int irq)
+{
+}
+
+static unsigned int
+noirq_startup(unsigned int irq)
+{
+ return 0;
+}
+
+static void
+noirq_ack(unsigned int irq)
+{
+ printk(KERN_CRIT "Unexpected IRQ %u\n", irq);
+}
+
+static struct hw_interrupt_type no_irq_type = {
+ typename: "none",
+ startup: noirq_startup,
+ shutdown: noirq_enable_disable,
+ enable: noirq_enable_disable,
+ disable: noirq_enable_disable,
+ ack: noirq_ack,
+ end: noirq_enable_disable,
+};
+
+/*
+ * The special RTC interrupt type. The interrupt itself was
+ * processed by PALcode, and comes in via entInt vector 1.
*/
-void no_action(int cpl, void *dev_id, struct pt_regs *regs) { }
+static struct hw_interrupt_type rtc_irq_type = {
+ typename: "RTC",
+ startup: noirq_startup,
+ shutdown: noirq_enable_disable,
+ enable: noirq_enable_disable,
+ disable: noirq_enable_disable,
+ ack: noirq_enable_disable,
+ end: noirq_enable_disable,
+};
+
+void __init
+init_rtc_irq(void)
+{
+ irq_desc[RTC_IRQ].status = IRQ_DISABLED;
+ irq_desc[RTC_IRQ].handler = &rtc_irq_type;
+}
/*
- * Initial irq handlers.
+ * Special irq handlers.
*/
-static void enable_none(unsigned int irq) { }
-static unsigned int startup_none(unsigned int irq) { return 0; }
-static void disable_none(unsigned int irq) { }
-static void ack_none(unsigned int irq)
+void
+no_action(int cpl, void *dev_id, struct pt_regs *regs)
{
- printk("unexpected IRQ trap at vector %02x\n", irq);
}
-/* startup is the same as "enable", shutdown is same as "disable" */
-#define shutdown_none disable_none
-#define end_none enable_none
-
-struct hw_interrupt_type no_irq_type = {
- "none",
- startup_none,
- shutdown_none,
- enable_none,
- disable_none,
- ack_none,
- end_none
+/*
+ * Common irq handlers.
+ */
+
+struct irqaction isa_cascade_irqaction = {
+ handler: no_action,
+ name: "isa-cascade"
};
+struct irqaction timer_cascade_irqaction = {
+ handler: no_action,
+ name: "timer-cascade"
+};
+
+struct irqaction halt_switch_irqaction = {
+ handler: no_action,
+ name: "halt-switch"
+};
+
+
spinlock_t irq_controller_lock = SPIN_LOCK_UNLOCKED;
-irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned =
- { [0 ... NR_IRQS-1] = { 0, &no_irq_type, }};
+irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = {
+ [0 ... NR_IRQS-1] = { 0, &no_irq_type, }
+};
-int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action)
+int
+handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
+ struct irqaction *action)
{
- int status;
- int cpu = smp_processor_id();
+ int status, cpu = smp_processor_id();
+ unsigned long ipl;
kstat.irqs[cpu][irq]++;
irq_enter(cpu, irq);
status = 1; /* Force the "do bottom halves" bit */
+ ipl = rdps() & 7;
do {
- if (!(action->flags & SA_INTERRUPT))
- __sti();
- else
- __cli();
+ unsigned long newipl = (action->flags & SA_INTERRUPT ? 7 : 0);
+ if (newipl != ipl) {
+ swpipl(newipl);
+ ipl = newipl;
+ }
status |= action->flags;
action->handler(irq, action->dev_id, regs);
} while (action);
if (status & SA_SAMPLE_RANDOM)
add_interrupt_randomness(irq);
- __cli();
+ if (ipl == 0)
+ __cli();
irq_exit(cpu, irq);
spin_lock_irqsave(&irq_controller_lock, flags);
switch (irq_desc[irq].depth) {
- case 1: {
+ case 1:
+ {
unsigned int status = irq_desc[irq].status & ~IRQ_DISABLED;
irq_desc[irq].status = status;
if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
irq_desc[irq].status = status | IRQ_REPLAY;
- hw_resend_irq(irq_desc[irq].handler,irq); /* noop */
+
+ /* ??? We can't re-send on (most?) alpha hw.
+ hw_resend_irq(irq_desc[irq].handler,irq); */
}
irq_desc[irq].handler->enable(irq);
/* fall-through */
- }
+ }
default:
irq_desc[irq].depth--;
break;
case 0:
- printk("enable_irq() unbalanced from %p\n",
+ printk(KERN_ERR "enable_irq() unbalanced from %p\n",
__builtin_return_address(0));
}
spin_unlock_irqrestore(&irq_controller_lock, flags);
if (irq >= ACTUAL_NR_IRQS)
return -EINVAL;
- if (IS_RESERVED_IRQ(irq))
- return -EINVAL;
if (!handler)
return -EINVAL;
* to figure out which interrupt is which (messes up the
* interrupt freeing logic etc).
*/
- if (irqflags & SA_SHIRQ) {
- if (!dev_id)
- printk("Bad boy: %s (at %p) called us without a dev_id!\n",
- devname, __builtin_return_address(0));
+ if ((irqflags & SA_SHIRQ) && !dev_id) {
+ printk(KERN_ERR
+ "Bad boy: %s (at %p) called us without a dev_id!\n",
+ devname, __builtin_return_address(0));
}
#endif
unsigned long flags;
if (irq >= ACTUAL_NR_IRQS) {
- printk("Trying to free IRQ%d\n",irq);
- return;
- }
- if (IS_RESERVED_IRQ(irq)) {
- printk("Trying to free reserved IRQ %d\n", irq);
+ printk(KERN_CRIT "Trying to free IRQ%d\n", irq);
return;
}
+
spin_lock_irqsave(&irq_controller_lock,flags);
p = &irq_desc[irq].action;
for (;;) {
if (action->dev_id != dev_id)
continue;
- /* Found it - now remove it from the list of entries */
+ /* Found - now remove it from the list of entries. */
*pp = action->next;
if (!irq_desc[irq].action) {
irq_desc[irq].status |= IRQ_DISABLED;
}
spin_unlock_irqrestore(&irq_controller_lock,flags);
- /* Wait to make sure it's not being used on another CPU */
+ /* Wait to make sure it's not being used on
+ another CPU. */
while (irq_desc[irq].status & IRQ_INPROGRESS)
barrier();
kfree(action);
return;
}
- printk("Trying to free free IRQ%d\n",irq);
+ printk(KERN_ERR "Trying to free free IRQ%d\n",irq);
spin_unlock_irqrestore(&irq_controller_lock,flags);
return;
}
struct irqaction * action;
char *p = buf;
-#ifdef __SMP__
+#ifdef CONFIG_SMP
p += sprintf(p, " ");
for (i = 0; i < smp_num_cpus; i++)
p += sprintf(p, "CPU%d ", i);
if (!action)
continue;
p += sprintf(p, "%3d: ",i);
-#ifndef __SMP__
+#ifndef CONFIG_SMP
p += sprintf(p, "%10u ", kstat_irqs(i));
#else
for (j = 0; j < smp_num_cpus; j++)
return p - buf;
}
-#ifdef __SMP__
+#ifdef CONFIG_SMP
/* Who has global_irq_lock. */
int global_irq_holder = NO_PROC_ID;
__sti();
break;
default:
- printk("global_restore_flags: %08lx (%p)\n",
+ printk(KERN_ERR "global_restore_flags: %08lx (%p)\n",
flags, __builtin_return_address(0));
}
}
}
#endif
}
-#endif /* __SMP__ */
+#endif /* CONFIG_SMP */
/*
* do_IRQ handles all normal device IRQ's (the special
unsigned int status;
if ((unsigned) irq > ACTUAL_NR_IRQS) {
- printk("device_interrupt: illegal interrupt %d\n", irq);
+ printk(KERN_CRIT "device_interrupt: illegal interrupt %d\n",
+ irq);
return;
}
desc = irq_desc + irq;
spin_lock_irq(&irq_controller_lock); /* mask also the RTC */
desc->handler->ack(irq);
+
/*
- REPLAY is when Linux resends an IRQ that was dropped earlier
- WAITING is used by probe to mark irqs that are being tested
- */
+ * REPLAY is when Linux resends an IRQ that was dropped earlier.
+ * WAITING is used by probe to mark irqs that are being tested.
+ */
status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
status |= IRQ_PENDING; /* we _want_ to handle it */
/*
* If there is no IRQ handler or it was disabled, exit early.
- Since we set PENDING, if another processor is handling
- a different instance of this same irq, the other processor
- will take care of it.
+ * Since we set PENDING, if another processor is handling
+ * a different instance of this same irq, the other processor
+ * will take care of it.
*/
if (!action)
return;
/*
- * Edge triggered interrupts need to remember
- * pending events.
+ * Edge triggered interrupts need to remember pending events.
* This applies to any hw interrupts that allow a second
* instance of the same irq to arrive while we are in do_IRQ
* or in the handler. But the code here only handles the _second_
{
switch (type) {
case 0:
-#ifdef __SMP__
+#ifdef CONFIG_SMP
handle_ipi(®s);
return;
#else
- printk("Interprocessor interrupt? You must be kidding\n");
+ printk(KERN_CRIT "Interprocessor interrupt? "
+ "You must be kidding!\n");
#endif
break;
case 1:
-#ifdef __SMP__
+#ifdef CONFIG_SMP
cpu_data[smp_processor_id()].smp_local_irq_count++;
smp_percpu_timer_interrupt(®s);
if (smp_processor_id() == smp_boot_cpuid)
perf_irq(vector, ®s);
return;
default:
- printk("Hardware intr %ld %lx? Huh?\n", type, vector);
+ printk(KERN_CRIT "Hardware intr %ld %lx? Huh?\n",
+ type, vector);
}
printk("PC = %016lx PS=%04lx\n", regs.pc, regs.ps);
}
+void __init
+common_init_isa_dma(void)
+{
+ outb(0, DMA1_RESET_REG);
+ outb(0, DMA2_RESET_REG);
+ outb(0, DMA1_CLR_MASK_REG);
+ outb(0, DMA2_CLR_MASK_REG);
+}
+
void __init
init_IRQ(void)
{
#define MCHK_K_OS_BUGCHECK 0x008A
#define MCHK_K_PAL_BUGCHECK 0x0090
-#ifndef __SMP__
+#ifndef CONFIG_SMP
struct mcheck_info __mcheck_info;
#endif
--- /dev/null
+/*
+ * linux/arch/alpha/kernel/irq_impl.h
+ *
+ * Copyright (C) 1995 Linus Torvalds
+ * Copyright (C) 1998, 2000 Richard Henderson
+ *
+ * This file contains declarations and inline functions for interfacing
+ * with the IRQ handling routines in irq.c.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+
+#define RTC_IRQ 8
+
+extern void isa_device_interrupt(unsigned long, struct pt_regs *);
+extern void isa_no_iack_sc_device_interrupt(unsigned long, struct pt_regs *);
+extern void srm_device_interrupt(unsigned long, struct pt_regs *);
+extern void pyxis_device_interrupt(unsigned long, struct pt_regs *);
+
+extern struct irqaction isa_cascade_irqaction;
+extern struct irqaction timer_cascade_irqaction;
+extern struct irqaction halt_switch_irqaction;
+
+extern void init_srm_irqs(long, unsigned long);
+extern void init_pyxis_irqs(unsigned long);
+extern void init_rtc_irq(void);
+
+extern void common_init_isa_dma(void);
+
+extern void i8259a_enable_irq(unsigned int);
+extern void i8259a_disable_irq(unsigned int);
+extern void i8259a_mask_and_ack_irq(unsigned int);
+extern unsigned int i8259a_startup_irq(unsigned int);
+extern struct hw_interrupt_type i8259a_irq_type;
+extern void init_i8259a_irqs(void);
+
+extern void no_action(int cpl, void *dev_id, struct pt_regs *regs);
+extern void handle_irq(int irq, struct pt_regs * regs);
+
+static inline void
+alpha_do_profile(unsigned long pc)
+{
+ if (prof_buffer && current->pid) {
+ extern char _stext;
+
+ pc -= (unsigned long) &_stext;
+ pc >>= prof_shift;
+ /*
+ * Don't ignore out-of-bounds PC values silently,
+ * put them into the last histogram slot, so if
+ * present, they will show up as a sharp peak.
+ */
+ if (pc > prof_len - 1)
+ pc = prof_len - 1;
+ atomic_inc((atomic_t *)&prof_buffer[pc]);
+ }
+}
void
pcibios_align_resource(void *data, struct resource *res, unsigned long size)
{
- struct pci_dev * dev = data;
+ struct pci_dev *dev = data;
unsigned long alignto;
unsigned long start = res->start;
#include <linux/reboot.h>
#include <linux/console.h>
-#if 0
-#ifdef CONFIG_RTC
-#include <linux/mc146818rtc.h>
-#endif
-#endif
-
#include <asm/reg.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#endif
}
-#if 0
-#ifdef CONFIG_RTC
- /* Reset rtc to defaults. */
- rtc_kill_pit();
-#endif
-#endif
-
if (alpha_mv.kill_arch)
alpha_mv.kill_arch(mode);
struct task_struct;
struct pci_dev;
struct pci_controler;
+struct irqaction;
/* core_apecs.c */
extern struct pci_ops apecs_pci_ops;
/* core_polaris.c */
extern struct pci_ops polaris_pci_ops;
+extern int polaris_read_config_dword(struct pci_dev *, int, u32 *);
+extern int polaris_write_config_dword(struct pci_dev *, int, u32);
extern void polaris_init_arch(void);
extern void polaris_machine_check(u64, u64, struct pt_regs *);
#define polaris_pci_tbi ((void *)0)
/* time.c */
extern void timer_interrupt(int irq, void *dev, struct pt_regs * regs);
-extern void rtc_init_pit(void);
-extern void rtc_kill_pit(void);
-extern void common_init_pit(void);
+extern void common_init_rtc(struct irqaction *);
extern unsigned long est_cycle_freq;
/* smc37c93x.c */
/* ns87312.c */
extern void ns87312_enable_ide(long ide_base);
-/* fpregs.c */
+/* ../lib/fpreg.c */
extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
extern unsigned long alpha_read_fp_reg (unsigned long reg);
/* ../mm/init.c */
void srm_paging_stop(void);
-/* irq.h */
+/* irq.c */
#ifdef __SMP__
#define mcheck_expected(cpu) (cpu_data[cpu].mcheck_expected)
+++ /dev/null
-/* RTC irq callbacks, 1999 Andrea Arcangeli <andrea@suse.de> */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/irq.h>
-
-static void enable_rtc(unsigned int irq) { }
-static unsigned int startup_rtc(unsigned int irq) { return 0; }
-#define shutdown_rtc enable_rtc
-#define end_rtc enable_rtc
-#define ack_rtc enable_rtc
-#define disable_rtc enable_rtc
-
-void __init
-init_RTC_irq(void)
-{
- static struct hw_interrupt_type rtc_irq_type = { "RTC",
- startup_rtc,
- shutdown_rtc,
- enable_rtc,
- disable_rtc,
- ack_rtc,
- end_rtc };
- irq_desc[RTC_IRQ].status = IRQ_DISABLED;
- irq_desc[RTC_IRQ].handler = &rtc_irq_type;
-}
#include <linux/ioport.h>
#include <linux/bootmem.h>
-#if 0
-#ifdef CONFIG_RTC
-#include <linux/timex.h>
-#endif
-#endif
#ifdef CONFIG_BLK_DEV_INITRD
#include <linux/blk.h>
#endif
/* Reserve standard resources. */
reserve_std_resources();
-#if 0
- /* Initialize the timers. */
- /* ??? There is some circumstantial evidence that this needs
- to be done now rather than later in time_init, which would
- be more natural. Someone please explain or refute. */
-#if defined(CONFIG_RTC)
- rtc_init_pit();
-#else
- alpha_mv.init_pit();
-#endif
-#endif
-
/*
* Give us a default console. TGA users will see nothing until
* chr_dev_init is called, rather late in the boot sequence.
#include <asm/unistd.h>
#include "proto.h"
+#include "irq_impl.h"
#define DEBUG_SMP 0
/* We need to make like a normal interrupt -- otherwise
timer interrupts ignore the global interrupt lock,
which would be a Bad Thing. */
- irq_enter(cpu, TIMER_IRQ);
+ irq_enter(cpu, RTC_IRQ);
update_one_process(current, 1, user, !user, cpu);
if (current->pid) {
}
data->prof_counter = data->prof_multiplier;
- irq_exit(cpu, TIMER_IRQ);
+ irq_exit(cpu, RTC_IRQ);
}
}
}
static void
-ipi_imb(void)
+ipi_imb(void *ignored)
{
imb();
}
#include <asm/core_cia.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-alcor_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+/* Note mask bit is true for ENABLED irqs. */
+static unsigned long cached_irq_mask;
+
+static inline void
+alcor_update_irq_hw(unsigned long mask)
{
- if (irq >= 16) {
- /* On Alcor, at least, lines 20..30 are not connected and can
- generate spurrious interrupts if we turn them on while IRQ
- probing. So explicitly mask them out. */
- mask |= 0x7ff000000000UL;
-
- /* Note inverted sense of mask bits: */
- *(vuip)GRU_INT_MASK = ~(mask >> 16);
- mb();
- }
- else if (irq >= 8)
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else
- outb(mask, 0x21); /* ISA PIC1 */
+ *(vuip)GRU_INT_MASK = mask;
+ mb();
+}
+
+static inline void
+alcor_enable_irq(unsigned int irq)
+{
+ alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+}
+
+static inline void
+alcor_disable_irq(unsigned int irq)
+{
+ alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
}
static void
-alcor_ack_irq(unsigned long irq)
+alcor_mask_and_ack_irq(unsigned int irq)
{
- if (irq < 16) {
- /* Ack the interrupt making it the lowest priority */
- /* First the slave .. */
- if (irq > 7) {
- outb(0xE0 | (irq - 8), 0xa0);
- irq = 2;
- }
- /* .. then the master */
- outb(0xE0 | irq, 0x20);
+ alcor_disable_irq(irq);
- /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
- *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
- *(vuip)GRU_INT_CLEAR = 0x00000000; mb();
- }
+ /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
+ *(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
+ *(vuip)GRU_INT_CLEAR = 0; mb();
}
+static unsigned int
+alcor_startup_irq(unsigned int irq)
+{
+ alcor_enable_irq(irq);
+ return 0;
+}
+
+static void
+alcor_isa_mask_and_ack_irq(unsigned int irq)
+{
+ i8259a_mask_and_ack_irq(irq);
+
+ /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
+ *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
+ *(vuip)GRU_INT_CLEAR = 0; mb();
+}
+
+static struct hw_interrupt_type alcor_irq_type = {
+ typename: "ALCOR",
+ startup: alcor_startup_irq,
+ shutdown: alcor_disable_irq,
+ enable: alcor_enable_irq,
+ disable: alcor_disable_irq,
+ ack: alcor_mask_and_ack_irq,
+ end: alcor_enable_irq,
+};
+
static void
alcor_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
if (i == 31) {
isa_device_interrupt(vector, regs);
} else {
- handle_irq(16 + i, 16 + i, regs);
+ handle_irq(16 + i, regs);
}
}
}
-static void
+static void __init
alcor_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ long i;
if (alpha_using_srm)
alpha_mv.device_interrupt = srm_device_interrupt;
- *(vuip)GRU_INT_MASK = ~(alpha_irq_mask >> 16); mb(); /* invert */
- *(vuip)GRU_INT_EDGE = 0U; mb(); /* all are level */
+ *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */
+ *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */
*(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */
- *(vuip)GRU_INT_CLEAR = 0UL; mb(); /* all clear */
+ *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */
+
+ for (i = 16; i < 48; ++i) {
+ /* On Alcor, at least, lines 20..30 are not connected
+ and can generate spurrious interrupts if we turn them
+ on while IRQ probing. */
+ if (i >= 16+20 && i <= 16+30)
+ continue;
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &alcor_irq_type;
+ }
+ i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
- enable_irq(16 + 31); /* enable (E)ISA PIC cascade */
- enable_irq(2); /* enable cascade */
+ setup_irq(16+31, &isa_cascade_irqaction);
}
min_mem_address: CIA_DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: ALCOR_PROBE_MASK,
- update_irq_hw: alcor_update_irq_hw,
- ack_irq: alcor_ack_irq,
device_interrupt: alcor_device_interrupt,
init_arch: cia_init_arch,
init_irq: alcor_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: alcor_kill_arch,
pci_map_irq: alcor_map_irq,
min_mem_address: CIA_DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: ALCOR_PROBE_MASK,
- update_irq_hw: alcor_update_irq_hw,
- ack_irq: alcor_ack_irq,
device_interrupt: alcor_device_interrupt,
init_arch: cia_init_arch,
init_irq: alcor_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: alcor_kill_arch,
pci_map_irq: alcor_map_irq,
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/core_pyxis.h>
#include "proto.h"
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void enable_cabriolet_irq(unsigned int irq);
-static void disable_cabriolet_irq(unsigned int irq);
-
-static void enable_cabriolet_srm_irq(unsigned int irq);
-static void disable_cabriolet_srm_irq(unsigned int irq);
-
-#define end_cabriolet_irq enable_cabriolet_irq
-#define shutdown_cabriolet_irq disable_cabriolet_irq
-#define mask_and_ack_cabriolet_irq disable_cabriolet_irq
-
-#define end_cabriolet_srm_irq enable_cabriolet_srm_irq
-#define shutdown_cabriolet_srm_irq disable_cabriolet_srm_irq
-#define mask_and_ack_cabriolet_srm_irq disable_cabriolet_srm_irq
-
-static unsigned int
-startup_cabriolet_irq(unsigned int irq)
-{
- enable_cabriolet_irq(irq);
- return 0; /* never anything pending */
-}
-
-static unsigned int
-startup_cabriolet_srm_irq(unsigned int irq)
-{
- enable_cabriolet_srm_irq(irq);
- return 0; /* never anything pending */
-}
-
-static struct hw_interrupt_type cabriolet_irq_type = {
- "CABRIOLET",
- startup_cabriolet_irq,
- shutdown_cabriolet_irq,
- enable_cabriolet_irq,
- disable_cabriolet_irq,
- mask_and_ack_cabriolet_irq,
- end_cabriolet_irq,
-};
-
-static struct hw_interrupt_type cabriolet_srm_irq_type = {
- "CABRIOLET-SRM",
- startup_cabriolet_srm_irq,
- shutdown_cabriolet_srm_irq,
- enable_cabriolet_srm_irq,
- disable_cabriolet_srm_irq,
- mask_and_ack_cabriolet_srm_irq,
- end_cabriolet_srm_irq,
-};
-
+/* Note mask bit is true for DISABLED irqs. */
static unsigned long cached_irq_mask = ~0UL;
static inline void
-cabriolet_flush_irq_mask(unsigned long mask)
-{
- outl(mask >> 16, 0x804);
-}
-
-static void
-enable_cabriolet_irq(unsigned int irq)
+cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
{
- cached_irq_mask &= ~(1UL << irq);
- cabriolet_flush_irq_mask(cached_irq_mask);
+ int ofs = (irq - 16) / 8;
+ outb(mask >> (16 + ofs*3), 0x804 + ofs);
}
-static void
-disable_cabriolet_irq(unsigned int irq)
+static inline void
+cabriolet_enable_irq(unsigned int irq)
{
- cached_irq_mask |= 1UL << irq;
- cabriolet_flush_irq_mask(cached_irq_mask);
+ cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
}
-
-
-/* Under SRM console, we must use the CSERVE PALcode routine to manage
- the interrupt mask for us. Otherwise, the kernel/HW get out of
- sync with what the PALcode thinks it needs to deliver/ignore. */
-
static void
-enable_cabriolet_srm_irq(unsigned int irq)
+cabriolet_disable_irq(unsigned int irq)
{
- cserve_ena(irq - 16);
+ cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
}
-static void
-disable_cabriolet_srm_irq(unsigned int irq)
-{
- cserve_dis(irq - 16);
+static unsigned int
+cabriolet_startup_irq(unsigned int irq)
+{
+ cabriolet_enable_irq(irq);
+ return 0; /* never anything pending */
}
+static struct hw_interrupt_type cabriolet_irq_type = {
+ typename: "CABRIOLET",
+ startup: cabriolet_startup_irq,
+ shutdown: cabriolet_disable_irq,
+ enable: cabriolet_enable_irq,
+ disable: cabriolet_disable_irq,
+ ack: cabriolet_disable_irq,
+ end: cabriolet_enable_irq,
+};
static void
cabriolet_device_interrupt(unsigned long v, struct pt_regs *r)
}
}
-static void __init
-init_TSUNAMI_irqs(struct hw_interrupt_type * ops)
-{
- int i;
-
- for (i = 0; i < NR_IRQS; i++) {
- if (i == RTC_IRQ)
- continue;
- if (i < 16)
- continue;
- if (i >= 35)
- break;
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].handler = ops;
- }
-}
-
static void __init
cabriolet_init_irq(void)
{
- static struct irqaction cascade = { no_action, 0, 0, "sio-cascade", NULL, NULL};
-
- STANDARD_INIT_IRQ_PROLOG;
+ init_i8259a_irqs();
+ init_rtc_irq();
- init_ISA_irqs();
- init_RTC_irq();
if (alpha_using_srm) {
alpha_mv.device_interrupt = srm_device_interrupt;
- init_TSUNAMI_irqs(&cabriolet_srm_irq_type);
+ init_srm_irqs(35, 0);
}
else {
- init_TSUNAMI_irqs(&cabriolet_irq_type);
- cabriolet_flush_irq_mask(~0UL);
+ long i;
+
+ outb(0xff, 0x804);
+ outb(0xff, 0x805);
+ outb(0xff, 0x806);
+
+ for (i = 16; i < 35; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &cabriolet_irq_type;
+ }
}
- setup_irq(16 + 4, &cascade); /* enable SIO cascade */
+ common_init_isa_dma();
+ setup_irq(16+4, &isa_cascade_irqaction);
}
init_arch: apecs_init_arch,
init_irq: cabriolet_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: cabriolet_init_pci,
kill_arch: NULL,
pci_map_irq: cabriolet_map_irq,
init_arch: cia_init_arch,
init_irq: cabriolet_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: cabriolet_init_pci,
pci_map_irq: cabriolet_map_irq,
pci_swizzle: common_swizzle,
init_arch: lca_init_arch,
init_irq: cabriolet_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: cabriolet_init_pci,
pci_map_irq: eb66p_map_irq,
pci_swizzle: common_swizzle,
init_arch: pyxis_init_arch,
init_irq: cabriolet_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: alphapc164_init_pci,
pci_map_irq: alphapc164_map_irq,
pci_swizzle: common_swizzle,
init_arch: cia_init_arch,
init_irq: cabriolet_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: alphapc164_init_pci,
pci_map_irq: alphapc164_map_irq,
pci_swizzle: common_swizzle,
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
-#include <linux/irq.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/hwrpb.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-/*
- * HACK ALERT! only the boot cpu is used for interrupts.
- */
-
-static void enable_tsunami_irq(unsigned int irq);
-static void disable_tsunami_irq(unsigned int irq);
-static void enable_clipper_irq(unsigned int irq);
-static void disable_clipper_irq(unsigned int irq);
-
-#define end_tsunami_irq enable_tsunami_irq
-#define shutdown_tsunami_irq disable_tsunami_irq
-#define mask_and_ack_tsunami_irq disable_tsunami_irq
-
-#define end_clipper_irq enable_clipper_irq
-#define shutdown_clipper_irq disable_clipper_irq
-#define mask_and_ack_clipper_irq disable_clipper_irq
-
-
-static unsigned int
-startup_tsunami_irq(unsigned int irq)
-{
- enable_tsunami_irq(irq);
- return 0; /* never anything pending */
-}
-
-static unsigned int
-startup_clipper_irq(unsigned int irq)
-{
- enable_clipper_irq(irq);
- return 0; /* never anything pending */
-}
-
-static struct hw_interrupt_type tsunami_irq_type = {
- "TSUNAMI",
- startup_tsunami_irq,
- shutdown_tsunami_irq,
- enable_tsunami_irq,
- disable_tsunami_irq,
- mask_and_ack_tsunami_irq,
- end_tsunami_irq
-};
-
-static struct hw_interrupt_type clipper_irq_type = {
- "CLIPPER",
- startup_clipper_irq,
- shutdown_clipper_irq,
- enable_clipper_irq,
- disable_clipper_irq,
- mask_and_ack_clipper_irq,
- end_clipper_irq
-};
-
static unsigned long cached_irq_mask;
+
#define TSUNAMI_SET_IRQ_MASK(cpu, value) \
do { \
volatile unsigned long *csr; \
- \
csr = &TSUNAMI_cchip->dim##cpu##.csr; \
*csr = (value); \
mb(); \
static inline void
do_flush_irq_mask(unsigned long value)
{
- switch (TSUNAMI_bootcpu)
- {
+ switch (TSUNAMI_bootcpu) {
case 0:
TSUNAMI_SET_IRQ_MASK(0, value);
break;
do_flush_irq_mask(value);
}
-static void
-enable_tsunami_irq(unsigned int irq)
-{
- cached_irq_mask |= 1UL << irq;
- dp264_flush_irq_mask(cached_irq_mask);
-}
-
-static void
-disable_tsunami_irq(unsigned int irq)
-{
- cached_irq_mask &= ~(1UL << irq);
- dp264_flush_irq_mask(cached_irq_mask);
-}
-
static void
clipper_flush_irq_mask(unsigned long mask)
{
do_flush_irq_mask(value);
}
+static inline void
+dp264_enable_irq(unsigned int irq)
+{
+ cached_irq_mask |= 1UL << irq;
+ dp264_flush_irq_mask(cached_irq_mask);
+}
+
static void
-enable_clipper_irq(unsigned int irq)
+dp264_disable_irq(unsigned int irq)
+{
+ cached_irq_mask &= ~(1UL << irq);
+ dp264_flush_irq_mask(cached_irq_mask);
+}
+
+static unsigned int
+dp264_startup_irq(unsigned int irq)
+{
+ dp264_enable_irq(irq);
+ return 0; /* never anything pending */
+}
+
+static inline void
+clipper_enable_irq(unsigned int irq)
{
cached_irq_mask |= 1UL << irq;
clipper_flush_irq_mask(cached_irq_mask);
}
static void
-disable_clipper_irq(unsigned int irq)
+clipper_disable_irq(unsigned int irq)
{
cached_irq_mask &= ~(1UL << irq);
clipper_flush_irq_mask(cached_irq_mask);
}
+static unsigned int
+clipper_startup_irq(unsigned int irq)
+{
+ clipper_enable_irq(irq);
+ return 0; /* never anything pending */
+}
+
+static struct hw_interrupt_type dp264_irq_type = {
+ typename: "DP264",
+ startup: dp264_startup_irq,
+ shutdown: dp264_disable_irq,
+ enable: dp264_enable_irq,
+ disable: dp264_disable_irq,
+ ack: dp264_disable_irq,
+ end: dp264_enable_irq,
+};
+
+static struct hw_interrupt_type clipper_irq_type = {
+ typename: "CLIPPER",
+ startup: clipper_startup_irq,
+ shutdown: clipper_disable_irq,
+ enable: clipper_enable_irq,
+ disable: clipper_disable_irq,
+ ack: clipper_disable_irq,
+ end: clipper_enable_irq,
+};
+
static void
dp264_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
}
static void __init
-init_TSUNAMI_irqs(struct hw_interrupt_type * ops)
+init_tsunami_irqs(struct hw_interrupt_type * ops)
{
- int i;
-
- for (i = 0; i < NR_IRQS; i++) {
- if (i == RTC_IRQ)
- continue;
- if (i < 16)
- continue;
- /* only irqs between 16 and 47 are tsunami irqs */
- if (i >= 48)
- break;
+ long i;
+
+ /* Only irqs between 16 and 47 are tsunami irqs. */
+ for (i = 16; i < 48; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
irq_desc[i].handler = ops;
}
if (alpha_using_srm)
alpha_mv.device_interrupt = dp264_srm_device_interrupt;
- init_ISA_irqs();
- init_RTC_irq();
- init_TSUNAMI_irqs(&tsunami_irq_type);
-
dp264_flush_irq_mask(0UL);
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ init_tsunami_irqs(&dp264_irq_type);
}
static void __init
if (alpha_using_srm)
alpha_mv.device_interrupt = clipper_srm_device_interrupt;
- init_ISA_irqs();
- init_RTC_irq();
- init_TSUNAMI_irqs(&clipper_irq_type);
-
clipper_flush_irq_mask(0UL);
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ init_tsunami_irqs(&clipper_irq_type);
}
init_arch: tsunami_init_arch,
init_irq: dp264_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: dp264_init_pci,
kill_arch: tsunami_kill_arch,
pci_map_irq: dp264_map_irq,
init_arch: tsunami_init_arch,
init_irq: dp264_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: monet_init_pci,
kill_arch: tsunami_kill_arch,
pci_map_irq: monet_map_irq,
init_arch: tsunami_init_arch,
init_irq: dp264_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: tsunami_kill_arch,
pci_map_irq: webbrick_map_irq,
init_arch: tsunami_init_arch,
init_irq: clipper_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: tsunami_kill_arch,
pci_map_irq: clipper_map_irq,
#include <asm/core_lca.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-eb64p_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+/* Note mask bit is true for DISABLED irqs. */
+static unsigned int cached_irq_mask = -1;
+
+static inline void
+eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
{
- if (irq >= 16)
- if (irq >= 24)
- outb(mask >> 24, 0x27);
- else
- outb(mask >> 16, 0x26);
- else if (irq >= 8)
- outb(mask >> 8, 0xA1);
- else
- outb(mask, 0x21);
+ outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26));
}
+static inline void
+eb64p_enable_irq(unsigned int irq)
+{
+ eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+}
+
+static inline void
+eb64p_disable_irq(unsigned int irq)
+{
+ eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
+}
+
+static unsigned int
+eb64p_startup_irq(unsigned int irq)
+{
+ eb64p_enable_irq(irq);
+ return 0; /* never anything pending */
+}
+
+static struct hw_interrupt_type eb64p_irq_type = {
+ typename: "EB64P",
+ startup: eb64p_startup_irq,
+ shutdown: eb64p_disable_irq,
+ enable: eb64p_enable_irq,
+ disable: eb64p_disable_irq,
+ ack: eb64p_disable_irq,
+ end: eb64p_enable_irq,
+};
+
static void
eb64p_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
/* Read the interrupt summary registers */
pld = inb(0x26) | (inb(0x27) << 8);
+
/*
* Now, for every possible bit set, work through
* them and call the appropriate interrupt handler.
if (i == 5) {
isa_device_interrupt(vector, regs);
} else {
- handle_irq(16 + i, 16 + i, regs);
+ handle_irq(16 + i, regs);
}
}
}
static void __init
eb64p_init_irq(void)
{
+ long i;
+
#ifdef CONFIG_ALPHA_GENERIC
/*
* CABRIO SRM may not set variation correctly, so here we test
*/
if (inw(0x806) != 0xffff) {
extern struct alpha_machine_vector cabriolet_mv;
-#if 1
- printk("eb64p_init_irq: resetting for CABRIO\n");
-#endif
alpha_mv = cabriolet_mv;
alpha_mv.init_irq();
return;
}
#endif /* GENERIC */
- STANDARD_INIT_IRQ_PROLOG;
+ outb(0xff, 0x26);
+ outb(0xff, 0x27);
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+
+ for (i = 16; i < 32; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &eb64p_irq_type;
+ }
- outb(alpha_irq_mask >> 16, 0x26);
- outb(alpha_irq_mask >> 24, 0x27);
- enable_irq(16 + 5); /* enable SIO cascade */
- enable_irq(2); /* enable cascade */
+ common_init_isa_dma();
+ setup_irq(16+5, &isa_cascade_irqaction);
}
/*
* 3 Interrupt Line B from slot 1
* 4 Interrupt Line C from slot 0
* 5 Interrupt line from the two ISA PICs
- * 6 Tulip (slot
+ * 6 Tulip
* 7 NCR SCSI
*
* Summary @ 0x27
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 32,
- irq_probe_mask: _PROBE_MASK(32),
- update_irq_hw: eb64p_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: eb64p_device_interrupt,
init_arch: apecs_init_arch,
init_irq: eb64p_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: eb64p_map_irq,
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 32,
- irq_probe_mask: _PROBE_MASK(32),
- update_irq_hw: eb64p_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: eb64p_device_interrupt,
init_arch: lca_init_arch,
init_irq: eb64p_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
pci_map_irq: eb64p_map_irq,
pci_swizzle: common_swizzle,
#include <asm/hwrpb.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
* HACK ALERT! only the boot cpu is used for interrupts.
*/
-static void
-eiger_update_irq_hw(unsigned long irq, unsigned long unused, int unmask_p)
+/* Note that this interrupt code is identical to TAKARA. */
+
+/* Note mask bit is true for DISABLED irqs. */
+static unsigned long cached_irq_mask[2] = { -1, -1 };
+
+static inline void
+eiger_update_irq_hw(unsigned long irq, unsigned long mask)
{
- unsigned int regaddr;
- unsigned long mask;
+ int regaddr;
- if (irq <= 15) {
- if (irq <= 7)
- outb(alpha_irq_mask, 0x21); /* ISA PIC1 */
- else
- outb(alpha_irq_mask >> 8, 0xA1); /* ISA PIC2 */
- } else {
- if (irq > 63)
- mask = _alpha_irq_masks[1] << 16;
- else
- mask = _alpha_irq_masks[0] >> ((irq - 16) & 0x30);
+ mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
+ regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
+ outl(mask & 0xffff0000UL, regaddr);
+}
- regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
+static inline void
+eiger_enable_irq(unsigned int irq)
+{
+ unsigned long mask;
+ mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
+ eiger_update_irq_hw(irq, mask);
+}
- outl(mask & 0xffff0000UL, regaddr);
- }
+static void
+eiger_disable_irq(unsigned int irq)
+{
+ unsigned long mask;
+ mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
+ eiger_update_irq_hw(irq, mask);
+}
+
+static unsigned int
+eiger_startup_irq(unsigned int irq)
+{
+ eiger_enable_irq(irq);
+ return 0; /* never anything pending */
}
+static struct hw_interrupt_type eiger_irq_type = {
+ typename: "EIGER",
+ startup: eiger_startup_irq,
+ shutdown: eiger_disable_irq,
+ enable: eiger_enable_irq,
+ disable: eiger_disable_irq,
+ ack: eiger_disable_irq,
+ end: eiger_enable_irq,
+};
+
static void
eiger_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
* despatch an interrupt if it's set.
*/
- if (intstatus & 8) handle_irq(16+3, 16+3, regs);
- if (intstatus & 4) handle_irq(16+2, 16+2, regs);
- if (intstatus & 2) handle_irq(16+1, 16+1, regs);
- if (intstatus & 1) handle_irq(16+0, 16+0, regs);
+ if (intstatus & 8) handle_irq(16+3, regs);
+ if (intstatus & 4) handle_irq(16+2, regs);
+ if (intstatus & 2) handle_irq(16+1, regs);
+ if (intstatus & 1) handle_irq(16+0, regs);
} else {
- isa_device_interrupt (vector, regs);
+ isa_device_interrupt(vector, regs);
}
}
static void
eiger_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
- int irq = (vector - 0x800) >> 4;
- handle_irq(irq, irq, regs);
+ int irq = (vector - 0x800) >> 4;
+ handle_irq(irq, regs);
}
static void __init
eiger_init_irq(void)
{
+ long i;
+
outb(0, DMA1_RESET_REG);
outb(0, DMA2_RESET_REG);
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
if (alpha_using_srm)
alpha_mv.device_interrupt = eiger_srm_device_interrupt;
- eiger_update_irq_hw(16, alpha_irq_mask, 0);
+ for (i = 16; i < 128; i += 16)
+ eiger_update_irq_hw(i, -1);
- enable_irq(2);
+ init_i8259a_irqs();
+ init_rtc_irq();
+
+ for (i = 16; i < 128; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &eiger_irq_type;
+ }
}
static int __init
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 128,
- irq_probe_mask: TSUNAMI_PROBE_MASK,
- update_irq_hw: eiger_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: eiger_device_interrupt,
init_arch: tsunami_init_arch,
init_irq: eiger_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: tsunami_kill_arch,
pci_map_irq: eiger_map_irq,
#include <asm/pgtable.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "machvec_impl.h"
-static void
-jensen_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
-{
- if (irq >= 8)
- outb(mask >> 8, 0xA1);
- else
- outb(mask, 0x21);
-}
-
/*
* Jensen is special: the vector is 0x8X0 for EISA interrupt X, and
* 0x9X0 for the local motherboard interrupts..
*/
static void
-handle_nmi(struct pt_regs * regs)
+jensen_local_ack(unsigned int irq)
{
- printk("Whee.. NMI received. Probable hardware error\n");
- printk("61=%02x, 461=%02x\n", inb(0x61), inb(0x461));
+ /* irq1 is supposed to be the keyboard, silly Jensen. */
+ if (irq == 7)
+ i8259a_mask_and_ack_irq(1);
}
+static struct hw_interrupt_type jensen_local_irq_type = {
+ typename: "LOCAL",
+ startup: i8259a_startup_irq,
+ shutdown: i8259a_disable_irq,
+ enable: i8259a_enable_irq,
+ disable: i8259a_disable_irq,
+ ack: jensen_local_ack,
+ end: i8259a_enable_irq,
+};
+
static void
jensen_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
- int irq, ack;
-
- ack = irq = (vector - 0x800) >> 4;
+ int irq;
switch (vector) {
- case 0x660: handle_nmi(regs); return;
+ case 0x660:
+ printk("Whee.. NMI received. Probable hardware error\n");
+ printk("61=%02x, 461=%02x\n", inb(0x61), inb(0x461));
+ return;
/* local device interrupts: */
- case 0x900: irq = 4, ack = -1; break; /* com1 -> irq 4 */
- case 0x920: irq = 3, ack = -1; break; /* com2 -> irq 3 */
- case 0x980: irq = 1, ack = -1; break; /* kbd -> irq 1 */
- case 0x990: irq = 9, ack = -1; break; /* mouse -> irq 9 */
+ case 0x900: irq = 4; break; /* com1 -> irq 4 */
+ case 0x920: irq = 3; break; /* com2 -> irq 3 */
+ case 0x980: irq = 1; break; /* kbd -> irq 1 */
+ case 0x990: irq = 9; break; /* mouse -> irq 9 */
+
default:
if (vector > 0x900) {
printk("Unknown local interrupt %lx\n", vector);
+ return;
}
- /* irq1 is supposed to be the keyboard, silly Jensen
- (is this really needed??) */
+ irq = (vector - 0x800) >> 4;
if (irq == 1)
irq = 7;
break;
}
- handle_irq(irq, ack, regs);
+ handle_irq(irq, regs);
}
-static void
+static void __init
jensen_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ init_i8259a_irqs();
+ init_rtc_irq();
- enable_irq(2); /* enable cascade */
+ irq_desc[1].handler = &jensen_local_irq_type;
+ irq_desc[4].handler = &jensen_local_irq_type;
+ irq_desc[3].handler = &jensen_local_irq_type;
+ irq_desc[7].handler = &jensen_local_irq_type;
+ irq_desc[9].handler = &jensen_local_irq_type;
+
+ common_init_isa_dma();
}
-static void
+static void __init
jensen_init_arch(void)
{
__direct_map_base = 0;
rtc_port: 0x170,
nr_irqs: 16,
- irq_probe_mask: _PROBE_MASK(16),
- update_irq_hw: jensen_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: jensen_device_interrupt,
init_arch: jensen_init_arch,
init_irq: jensen_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: NULL,
kill_arch: NULL,
};
#include <asm/core_pyxis.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-miata_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
-{
- if (irq >= 16) {
- /* Make CERTAIN none of the bogus ints get enabled... */
- *(vulp)PYXIS_INT_MASK =
- ~((long)mask >> 16) & ~0x400000000000063bUL;
- mb();
- /* ... and read it back to make sure it got written. */
- *(vulp)PYXIS_INT_MASK;
- }
- else if (irq >= 8)
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else
- outb(mask, 0x21); /* ISA PIC1 */
-}
-
-static void
-miata_device_interrupt(unsigned long vector, struct pt_regs *regs)
-{
- unsigned long pld, tmp;
- unsigned int i;
-
- /* Read the interrupt summary register of PYXIS */
- pld = *(vulp)PYXIS_INT_REQ;
-
- /*
- * For now, AND off any bits we are not interested in:
- * HALT (2), timer (6), ISA Bridge (7), 21142/3 (8)
- * then all the PCI slots/INTXs (12-31).
- */
- /* Maybe HALT should only be used for SRM console boots? */
- pld &= 0x00000000fffff9c4UL;
-
- /*
- * Now for every possible bit set, work through them and call
- * the appropriate interrupt handler.
- */
- while (pld) {
- i = ffz(~pld);
- pld &= pld - 1; /* clear least bit set */
- if (i == 7) {
- isa_device_interrupt(vector, regs);
- } else if (i == 6) {
- continue;
- } else {
- /* if not timer int */
- handle_irq(16 + i, 16 + i, regs);
- }
- *(vulp)PYXIS_INT_REQ = 1UL << i; mb();
- tmp = *(vulp)PYXIS_INT_REQ;
- }
-}
-
static void
miata_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
- int irq, ack;
+ int irq;
- ack = irq = (vector - 0x800) >> 4;
+ irq = (vector - 0x800) >> 4;
/*
* I really hate to do this, but the MIATA SRM console ignores the
* So, here's this grotty hack... :-(
*/
if (irq >= 16)
- ack = irq = irq + 8;
+ irq = irq + 8;
- handle_irq(irq, ack, regs);
+ handle_irq(irq, regs);
}
static void __init
miata_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
-
if (alpha_using_srm)
alpha_mv.device_interrupt = miata_srm_device_interrupt;
- /* Note invert on MASK bits. */
- *(vulp)PYXIS_INT_MASK =
- ~((long)alpha_irq_mask >> 16) & ~0x400000000000063bUL; mb();
#if 0
/* These break on MiataGL so we'll try not to do it at all. */
*(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */
*(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */
#endif
- /* Clear upper timer. */
- *(vulp)PYXIS_INT_REQ = 0x4000000000000180UL; mb();
- enable_irq(16 + 2); /* enable HALT switch - SRM only? */
- enable_irq(16 + 6); /* enable timer */
- enable_irq(16 + 7); /* enable ISA PIC cascade */
- enable_irq(2); /* enable cascade */
+ init_i8259a_irqs();
+ init_rtc_irq();
+
+ /* Not interested in the bogus interrupts (3,10), Fan Fault (0),
+ NMI (1), or EIDE (9).
+
+ We also disable the risers (4,5), since we don't know how to
+ route the interrupts behind the bridge. */
+ init_pyxis_irqs(0x63b0000);
+
+ common_init_isa_dma();
+ setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */
+ setup_irq(16+6, &timer_cascade_irqaction);
}
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: _PROBE_MASK(48),
- update_irq_hw: miata_update_irq_hw,
- ack_irq: common_ack_irq,
- device_interrupt: miata_device_interrupt,
+ device_interrupt: pyxis_device_interrupt,
init_arch: pyxis_init_arch,
init_irq: miata_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: miata_init_pci,
kill_arch: miata_kill_arch,
pci_map_irq: miata_map_irq,
#include <asm/core_cia.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-mikasa_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+
+/* Note mask bit is true for ENABLED irqs. */
+static int cached_irq_mask;
+
+static inline void
+mikasa_update_irq_hw(int mask)
+{
+ outw(mask, 0x536);
+}
+
+static inline void
+mikasa_enable_irq(unsigned int irq)
+{
+ mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
+}
+
+static inline void
+mikasa_disable_irq(unsigned int irq)
{
- if (irq >= 16)
- outw(~(mask >> 16), 0x536); /* note invert */
- else if (irq >= 8)
- outb(mask >> 8, 0xA1);
- else
- outb(mask, 0x21);
+ mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
}
+static unsigned int
+mikasa_startup_irq(unsigned int irq)
+{
+ mikasa_enable_irq(irq);
+ return 0;
+}
+
+static struct hw_interrupt_type mikasa_irq_type = {
+ typename: "MIKASA",
+ startup: mikasa_startup_irq,
+ shutdown: mikasa_disable_irq,
+ enable: mikasa_enable_irq,
+ disable: mikasa_disable_irq,
+ ack: mikasa_disable_irq,
+ end: mikasa_enable_irq,
+};
+
static void
mikasa_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
unsigned int i;
/* Read the interrupt summary registers */
- pld = (((unsigned long) (~inw(0x534)) & 0x0000ffffUL) << 16) |
- (((unsigned long) inb(0xa0)) << 8) |
- ((unsigned long) inb(0x20));
+ pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
+ | (((unsigned long) inb(0xa0)) << 8)
+ | inb(0x20));
/*
* Now for every possible bit set, work through them and call
if (i < 16) {
isa_device_interrupt(vector, regs);
} else {
- handle_irq(i, i, regs);
+ handle_irq(i, regs);
}
}
}
static void __init
mikasa_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ long i;
if (alpha_using_srm)
alpha_mv.device_interrupt = srm_device_interrupt;
- outw(~(alpha_irq_mask >> 16), 0x536); /* note invert */
- enable_irq(2); /* enable cascade */
+ mikasa_update_irq_hw(0);
+
+ for (i = 16; i < 32; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &mikasa_irq_type;
+ }
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
}
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 32,
- irq_probe_mask: _PROBE_MASK(32),
- update_irq_hw: mikasa_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: mikasa_device_interrupt,
init_arch: apecs_init_arch,
init_irq: mikasa_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: mikasa_map_irq,
min_mem_address: CIA_DEFAULT_MEM_BASE,
nr_irqs: 32,
- irq_probe_mask: _PROBE_MASK(32),
- update_irq_hw: mikasa_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: mikasa_device_interrupt,
init_arch: cia_init_arch,
init_irq: mikasa_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
pci_map_irq: mikasa_map_irq,
pci_swizzle: common_swizzle,
#include <asm/hwrpb.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-#define dev2hose(d) (bus2hose[(d)->bus->number]->pci_hose_index)
-
-static void
-nautilus_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
-{
- /* The timer is connected to PIC interrupt line also on Nautilus.
- The timer interrupt handler enables the PIC line, so in order
- not to get multiple timer interrupt sources, we mask it out
- at all times. */
-
- mask |= 0x100;
- if (irq >= 8)
- outb(mask >> 8, 0xA1);
- else
- outb(mask, 0x21);
-}
static void __init
nautilus_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
-
- enable_irq(2); /* enable cascade */
- disable_irq(8);
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
}
static int __init
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: (_PROBE_MASK(16) & ~0x101UL),
- update_irq_hw: nautilus_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: isa_device_interrupt,
init_arch: irongate_init_arch,
init_irq: nautilus_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: nautilus_kill_arch,
pci_map_irq: nautilus_map_irq,
#include <asm/core_cia.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
+/* Note mask bit is true for ENABLED irqs. */
+static int cached_irq_mask;
-static void
-noritake_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+static inline void
+noritake_update_irq_hw(int irq, int mask)
{
- if (irq <= 15)
- if (irq <= 7)
- outb(mask, 0x21); /* ISA PIC1 */
- else
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else if (irq <= 31)
- outw(~(mask >> 16), 0x54a);
- else
- outw(~(mask >> 32), 0x54c);
+ int port = 0x54a;
+ if (irq >= 16) mask >>= 16;
+ if (irq >= 16) port = 0x54c;
+ outw(mask, port);
+}
+
+static inline void
+noritake_enable_irq(unsigned int irq)
+{
+ noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
+}
+
+static inline void
+noritake_disable_irq(unsigned int irq)
+{
+ noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
}
+static unsigned int
+noritake_startup_irq(unsigned int irq)
+{
+ noritake_enable_irq(irq);
+ return 0;
+}
+
+static struct hw_interrupt_type noritake_irq_type = {
+ typename: "NORITAKE",
+ startup: noritake_startup_irq,
+ shutdown: noritake_disable_irq,
+ enable: noritake_enable_irq,
+ disable: noritake_disable_irq,
+ ack: noritake_disable_irq,
+ end: noritake_enable_irq,
+};
+
static void
noritake_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
unsigned int i;
/* Read the interrupt summary registers of NORITAKE */
- pld = ((unsigned long) inw(0x54c) << 32) |
- ((unsigned long) inw(0x54a) << 16) |
- ((unsigned long) inb(0xa0) << 8) |
- ((unsigned long) inb(0x20));
+ pld = (((unsigned long) inw(0x54c) << 32)
+ | ((unsigned long) inw(0x54a) << 16)
+ | ((unsigned long) inb(0xa0) << 8)
+ | inb(0x20));
/*
* Now for every possible bit set, work through them and call
if (i < 16) {
isa_device_interrupt(vector, regs);
} else {
- handle_irq(i, i, regs);
+ handle_irq(i, regs);
}
}
}
static void
noritake_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
- int irq, ack;
+ int irq;
- ack = irq = (vector - 0x800) >> 4;
+ irq = (vector - 0x800) >> 4;
/*
* I really hate to do this, too, but the NORITAKE SRM console also
- * reports PCI vectors *lower* than I expected from the bit numbers
- * in the documentation.
+ * reports PCI vectors *lower* than I expected from the bit numbers
+ * in the documentation.
* But I really don't want to change the fixup code for allocation
- * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
- * look nice and clean now.
+ * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
+ * look nice and clean now.
* So, here's this additional grotty hack... :-(
*/
if (irq >= 16)
- ack = irq = irq + 1;
+ irq = irq + 1;
- handle_irq(irq, ack, regs);
+ handle_irq(irq, regs);
}
static void __init
noritake_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ long i;
if (alpha_using_srm)
alpha_mv.device_interrupt = noritake_srm_device_interrupt;
- outw(~(alpha_irq_mask >> 16), 0x54a); /* note invert */
- outw(~(alpha_irq_mask >> 32), 0x54c); /* note invert */
- enable_irq(2); /* enable cascade */
+ outw(0, 0x54a);
+ outw(0, 0x54c);
+
+ for (i = 16; i < 48; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &noritake_irq_type;
+ }
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
}
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: _PROBE_MASK(48),
- update_irq_hw: noritake_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: noritake_device_interrupt,
init_arch: apecs_init_arch,
init_irq: noritake_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: noritake_map_irq,
min_mem_address: CIA_DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: _PROBE_MASK(48),
- update_irq_hw: noritake_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: noritake_device_interrupt,
init_arch: cia_init_arch,
init_irq: noritake_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
pci_map_irq: noritake_map_irq,
pci_swizzle: noritake_swizzle,
#include <asm/core_mcpcia.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
+
+/*
+ * HACK ALERT! only the boot cpu is used for interrupts.
+ */
+
+
+/* Note mask bit is true for ENABLED irqs. */
+
static unsigned int hose_irq_masks[4] = {
0xff0000, 0xfe0000, 0xff0000, 0xff0000
};
+static unsigned int cached_irq_masks[4];
+static inline void
+rawhide_update_irq_hw(int hose, int mask)
+{
+ *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
+ mb();
+ *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
+}
+
+static void
+rawhide_enable_irq(unsigned int irq)
+{
+ unsigned int mask, hose;
-/* Note that `mask' initially contains only the low 64 bits. */
+ irq -= 16;
+ hose = irq / 24;
+ irq -= hose * 24;
-static void
-rawhide_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+ mask = cached_irq_masks[hose] |= 1 << irq;
+ mask |= hose_irq_masks[hose];
+ rawhide_update_irq_hw(hose, mask);
+}
+
+static void
+rawhide_disable_irq(unsigned int irq)
{
- unsigned int saddle, hose, new_irq;
-
- if (irq < 16) {
- if (irq < 8)
- outb(mask, 0x21); /* ISA PIC1 */
- else
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- return;
- }
+ unsigned int mask, hose;
- saddle = (irq > 63);
- mask = _alpha_irq_masks[saddle];
+ irq -= 16;
+ hose = irq / 24;
+ irq -= hose * 24;
- if (saddle == 0) {
- /* Saddle 0 includes EISA interrupts. */
- mask >>= 16;
- new_irq = irq - 16;
- } else {
- new_irq = irq - 64;
- }
+ mask = cached_irq_masks[hose] &= ~(1 << irq);
+ mask |= hose_irq_masks[hose];
+ rawhide_update_irq_hw(hose, mask);
+}
- hose = saddle << 1;
- if (new_irq >= 24) {
- mask >>= 24;
- hose += 1;
- }
- *(vuip)MCPCIA_INT_MASK0(hose) =
- (~mask & 0x00ffffff) | hose_irq_masks[hose];
- mb();
- *(vuip)MCPCIA_INT_MASK0(hose);
+static unsigned int
+rawhide_startup_irq(unsigned int irq)
+{
+ rawhide_enable_irq(irq);
+ return 0;
}
+static struct hw_interrupt_type rawhide_irq_type = {
+ typename: "RAWHIDE",
+ startup: rawhide_startup_irq,
+ shutdown: rawhide_disable_irq,
+ enable: rawhide_enable_irq,
+ disable: rawhide_disable_irq,
+ ack: rawhide_disable_irq,
+ end: rawhide_enable_irq,
+};
+
static void
rawhide_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
/* Adjust by which hose it is from. */
irq -= ((irq + 16) >> 2) & 0x38;
- handle_irq(irq, irq, regs);
+ handle_irq(irq, regs);
}
static void __init
rawhide_init_irq(void)
{
struct pci_controler *hose;
+ long i;
mcpcia_init_hoses();
- STANDARD_INIT_IRQ_PROLOG;
-
- /* HACK ALERT! Routing is only to CPU #0. */
for (hose = hose_head; hose; hose = hose->next) {
int h = hose->index;
+ rawhide_update_irq_hw(h, hose_irq_masks[h]);
+ }
- *(vuip)MCPCIA_INT_MASK0(h) = hose_irq_masks[h];
- mb();
- *(vuip)MCPCIA_INT_MASK0(h);
+ for (i = 16; i < 128; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &rawhide_irq_type;
}
- enable_irq(2);
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
}
/*
min_mem_address: MCPCIA_DEFAULT_MEM_BASE,
nr_irqs: 128,
- irq_probe_mask: _PROBE_MASK(128),
- update_irq_hw: rawhide_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: rawhide_srm_device_interrupt,
init_arch: mcpcia_init_arch,
init_irq: rawhide_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: rawhide_map_irq,
#include <asm/core_pyxis.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-ruffian_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
-{
- if (irq >= 16) {
- /* Note inverted sense of mask bits: */
- /* Make CERTAIN none of the bogus ints get enabled... */
- *(vulp)PYXIS_INT_MASK =
- ~((long)mask >> 16) & 0x00000000ffffffbfUL;
- mb();
- /* ... and read it back to make sure it got written. */
- *(vulp)PYXIS_INT_MASK;
- }
- else if (irq >= 8)
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else
- outb(mask, 0x21); /* ISA PIC1 */
-}
-
-static void
-ruffian_ack_irq(unsigned long irq)
-{
- if (irq < 16) {
- /* Ack PYXIS ISA interrupt. */
- *(vulp)PYXIS_INT_REQ = 1L << 7; mb();
- /* ... and read it back to make sure it got written. */
- *(vulp)PYXIS_INT_REQ;
- if (irq > 7) {
- outb(0x20, 0xa0);
- }
- outb(0x20, 0x20);
- } else {
- /* Ack PYXIS PCI interrupt. */
- *(vulp)PYXIS_INT_REQ = (1UL << (irq - 16)); mb();
- /* ... and read it back to make sure it got written. */
- *(vulp)PYXIS_INT_REQ;
- }
-}
-
-static void
-ruffian_device_interrupt(unsigned long vector, struct pt_regs *regs)
-{
- unsigned long pld;
- unsigned int i;
-
- /* Read the interrupt summary register of PYXIS */
- pld = *(vulp)PYXIS_INT_REQ;
-
- /* For now, AND off any bits we are not interested in:
- * HALT (2), timer (6), ISA Bridge (7), 21142 (8)
- * then all the PCI slots/INTXs (12-31)
- * flash(5) :DWH:
- */
- pld &= 0x00000000ffffff9fUL; /* was ffff7f */
-
- /*
- * Now for every possible bit set, work through them and call
- * the appropriate interrupt handler.
- */
- while (pld) {
- i = ffz(~pld);
- pld &= pld - 1; /* clear least bit set */
- if (i == 7) { /* if ISA int */
- /* Ruffian does not have the RTC connected to
- the CPU timer interrupt. Instead, it uses the
- PIT connected to IRQ 0. So we must detect that
- and route that specifically to where we expected
- to find the timer interrupt come in. */
-
- /* Copy this code from isa_device_interrupt because
- we need to hook into int 0 for the timer. I
- refuse to soil device_interrupt with ifdefs. */
-
- /* Generate a PCI interrupt acknowledge cycle.
- The PIC will respond with the interrupt
- vector of the highest priority interrupt
- that is pending. The PALcode sets up the
- interrupts vectors such that irq level L
- generates vector L. */
-
- unsigned int j = *(vuip)PYXIS_IACK_SC & 0xff;
- if (j == 7 && !(inb(0x20) & 0x80)) {
- /* It's only a passive release... */
- } else if (j == 0) {
- handle_irq(TIMER_IRQ, -1, regs);
- ruffian_ack_irq(0);
- } else {
- handle_irq(j, j, regs);
- }
- } else { /* if not an ISA int */
- handle_irq(16 + i, 16 + i, regs);
- }
-
- *(vulp)PYXIS_INT_REQ = 1UL << i; mb();
- *(vulp)PYXIS_INT_REQ; /* read to force the write */
- }
-}
static void __init
ruffian_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
-
/* Invert 6&7 for i82371 */
*(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
*(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */
- *(vulp)PYXIS_INT_MASK = 0x00000000UL; mb();
- *(vulp)PYXIS_INT_REQ = 0xffffffffUL; mb();
outb(0x11,0xA0);
outb(0x08,0xA1);
outb(0x01,0x21);
outb(0xFF,0x21);
- /* Send -INTA pulses to clear any pending interrupts ...*/
- *(vuip) PYXIS_IACK_SC;
-
/* Finish writing the 82C59A PIC Operation Control Words */
outb(0x20,0xA0);
outb(0x20,0x20);
- /* Turn on the interrupt controller, the timer interrupt */
- enable_irq(16 + 7); /* enable ISA PIC cascade */
- enable_irq(0); /* enable timer */
- enable_irq(2); /* enable 2nd PIC cascade */
+ init_i8259a_irqs();
+
+ /* Not interested in the bogus interrupts (0,3,4,6),
+ NMI (1), HALT (2), flash (5), or 21142 (8). */
+ init_pyxis_irqs(0x17f0000);
+
+ common_init_isa_dma();
+}
+
+static void __init
+ruffian_init_rtc(struct irqaction *action)
+{
+ /* Ruffian does not have the RTC connected to the CPU timer
+ interrupt. Instead, it uses the PIT connected to IRQ 0. */
+
+ /* Setup interval timer. */
+ outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
+ outb(LATCH & 0xff, 0x40); /* LSB */
+ outb(LATCH >> 8, 0x40); /* MSB */
+
+ outb(0xb6, 0x43); /* pit counter 2: speaker */
+ outb(0x31, 0x42);
+ outb(0x13, 0x42);
+
+ setup_irq(0, action);
+}
+
+static void
+ruffian_kill_arch (int mode)
+{
+#if 0
+ /* This only causes re-entry to ARCSBIOS */
+ /* Perhaps this works for other PYXIS as well? */
+ *(vuip) PYXIS_RESET = 0x0000dead;
+ mb();
+#endif
+}
+
+static int __init
+ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ /* We don't know anything about the PCI routing, so leave
+ the IRQ unchanged. */
+ return dev->irq;
}
}
#endif /* BUILDING_FOR_MILO */
-static void
-ruffian_init_pit (void)
-{
- outb(0xb6, 0x43); /* pit counter 2: speaker */
- outb(0x31, 0x42);
- outb(0x13, 0x42);
-}
-
-static void
-ruffian_kill_arch (int mode)
-{
-#if 0
- /* This only causes re-entry to ARCSBIOS */
- /* Perhaps this works for other PYXIS as well? */
- *(vuip) PYXIS_RESET = 0x0000dead;
- mb();
-#endif
-}
-
-static int __init
-ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
- /* We don't know anything about the PCI routing, so leave
- the IRQ unchanged. */
- return dev->irq;
-}
-
-
/*
* The System Vector
*/
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 48,
- irq_probe_mask: RUFFIAN_PROBE_MASK,
- update_irq_hw: ruffian_update_irq_hw,
- ack_irq: ruffian_ack_irq,
- device_interrupt: ruffian_device_interrupt,
+ device_interrupt: pyxis_device_interrupt,
init_arch: pyxis_init_arch,
init_irq: ruffian_init_irq,
- init_pit: ruffian_init_pit,
+ init_rtc: ruffian_init_rtc,
init_pci: common_init_pci,
kill_arch: ruffian_kill_arch,
pci_map_irq: ruffian_map_irq,
#include <asm/core_polaris.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-rx164_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+/* Note mask bit is true for ENABLED irqs. */
+static unsigned long cached_irq_mask;
+
+/* Bus 0, Device 0. Nothing else matters, since we invoke the
+ POLARIS routines directly. */
+static struct pci_dev rx164_system;
+
+static inline void
+rx164_update_irq_hw(unsigned long mask)
{
- if (irq >= 16) {
- unsigned int temp;
- pcibios_write_config_dword(0, 0, 0x74, ~mask >> 16);
- pcibios_read_config_dword(0, 0, 0x74, &temp);
- }
- else if (irq >= 8)
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else
- outb(mask, 0x21); /* ISA PIC1 */
+ unsigned int temp;
+ polaris_write_config_dword(&rx164_system, 0x74, mask);
+ polaris_read_config_dword(&rx164_system, 0x74, &temp);
}
-#if 0
-static void
-rx164_srm_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+static inline void
+rx164_enable_irq(unsigned int irq)
{
- if (irq >= 16) {
- if (unmask_p)
- cserve_ena(irq - 16);
- else
- cserve_dis(irq - 16);
- }
- else if (irq >= 8)
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- else
- outb(mask, 0x21); /* ISA PIC1 */
+ rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
}
-#endif
static void
-rx164_isa_device_interrupt(unsigned long vector, struct pt_regs * regs)
+rx164_disable_irq(unsigned int irq)
+{
+ rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+}
+
+static unsigned int
+rx164_startup_irq(unsigned int irq)
{
- unsigned long pic;
-
- /*
- * It seems to me that the probability of two or more *device*
- * interrupts occurring at almost exactly the same time is
- * pretty low. So why pay the price of checking for
- * additional interrupts here if the common case can be
- * handled so much easier?
- */
- /*
- * The first read of the PIC gives you *all* interrupting lines.
- * Therefore, read the mask register and and out those lines
- * not enabled. Note that some documentation has 21 and a1
- * write only. This is not true.
- */
- pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */
- pic &= ~alpha_irq_mask; /* apply mask */
- pic &= 0xFFFB; /* mask out cascade & hibits */
-
- while (pic) {
- int j = ffz(~pic);
- pic &= pic - 1;
- handle_irq(j, j, regs);
- }
+ rx164_enable_irq(irq);
+ return 0;
}
+static struct hw_interrupt_type rx164_irq_type = {
+ typename: "RX164",
+ startup: rx164_startup_irq,
+ shutdown: rx164_disable_irq,
+ enable: rx164_enable_irq,
+ disable: rx164_disable_irq,
+ ack: rx164_disable_irq,
+ end: rx164_enable_irq,
+};
+
static void
rx164_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
+ unsigned int temp;
unsigned long pld;
- int i;
-
- /* Read the interrupt summary register. On Polaris,
- * this is the DIRR register in PCI config space (offset 0x84)
- */
- pld = 0;
- pcibios_read_config_dword(0, 0, 0x84, (unsigned int *)&pld);
-
-#if 0
- printk("PLD 0x%lx\n", pld);
-#endif
-
- if (pld & 0xffffffff00000000UL)
- pld &= 0x00000000ffffffffUL;
-
- /*
- * Now for every possible bit set, work through them and call
- * the appropriate interrupt handler.
- */
- while (pld) {
- i = ffz(~pld);
- pld &= pld - 1; /* clear least bit set */
- if (i == 20) {
- rx164_isa_device_interrupt(vector, regs);
- } else {
- handle_irq(16+i, 16+i, regs);
- }
- }
+ long i;
+
+ /* Read the interrupt summary register. On Polaris, this is
+ the DIRR register in PCI config space (offset 0x84). */
+ polaris_read_config_dword(&rx164_system, 0x84, &temp);
+ pld = temp;
+
+ /*
+ * Now for every possible bit set, work through them and call
+ * the appropriate interrupt handler.
+ */
+ while (pld) {
+ i = ffz(~pld);
+ pld &= pld - 1; /* clear least bit set */
+ if (i == 20) {
+ isa_no_iack_sc_device_interrupt(vector, regs);
+ } else {
+ handle_irq(16+i, regs);
+ }
+ }
}
-static void
+static void __init
rx164_init_irq(void)
{
- unsigned int temp;
+ long i;
- STANDARD_INIT_IRQ_PROLOG;
+ rx164_update_irq_hw(0);
+ for (i = 16; i < 40; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &rx164_irq_type;
+ }
- pcibios_write_config_dword(0, 0, 0x74, (~alpha_irq_mask >> 16));
- pcibios_read_config_dword(0, 0, 0x74, &temp);
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
- enable_irq(16 + 20); /* enable ISA interrupts */
- enable_irq(2); /* enable cascade */
+ setup_irq(16+20, &isa_cascade_irqaction);
}
-/* The RX164 changed its interrupt routing between pass1 and pass2...
+/*
+ * The RX164 changed its interrupt routing between pass1 and pass2...
*
* PASS1:
*
rx164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
#if 0
- char irq_tab_pass1[6][5] = {
- /*INT INTA INTB INTC INTD */
- { 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */
- { 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */
- { 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */
- { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */
- { 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */
- { 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */
- };
+ static char irq_tab_pass1[6][5] __initlocaldata = {
+ /*INT INTA INTB INTC INTD */
+ { 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */
+ { 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */
+ { 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */
+ { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */
+ { 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */
+ { 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */
+ };
#else
- char irq_tab[6][5] = {
- /*INT INTA INTB INTC INTD */
- { 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */
- { 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */
- { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */
- { 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */
- { 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */
- { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */
- };
+ static char irq_tab[6][5] __initlocaldata = {
+ /*INT INTA INTB INTC INTD */
+ { 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */
+ { 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */
+ { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */
+ { 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */
+ { 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */
+ { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */
+ };
#endif
const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
- /* JRP - Need to figure out how to distinguish pass1 from pass2,
+ /* JRP - Need to figure out how to distinguish pass1 from pass2,
and use the correct table. */
return COMMON_TABLE_LOOKUP;
}
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 40,
- irq_probe_mask: _PROBE_MASK(40),
- update_irq_hw: rx164_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: rx164_device_interrupt,
init_arch: polaris_init_arch,
init_irq: rx164_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: rx164_map_irq,
#include <asm/core_t2.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
* 0-7 (char at 536)
* 8-15 (char at 53a)
* 16-23 (char at 53c)
+ *
+ * Summary Registers (536/53a/53c):
+ *
+ * Bit Meaning Kernel IRQ
+ *------------------------------------------
+ * 0 PCI slot 0 34
+ * 1 NCR810 (builtin) 33
+ * 2 TULIP (builtin) 32
+ * 3 mouse 12
+ * 4 PCI slot 1 35
+ * 5 PCI slot 2 36
+ * 6 keyboard 1
+ * 7 floppy 6
+ * 8 COM2 3
+ * 9 parallel port 7
+ *10 EISA irq 3 -
+ *11 EISA irq 4 -
+ *12 EISA irq 5 5
+ *13 EISA irq 6 -
+ *14 EISA irq 7 -
+ *15 COM1 4
+ *16 EISA irq 9 9
+ *17 EISA irq 10 10
+ *18 EISA irq 11 11
+ *19 EISA irq 12 -
+ *20 EISA irq 13 -
+ *21 EISA irq 14 14
+ *22 NC 15
+ *23 IIC -
*/
-/* Note that the vector reported by the SRM PALcode corresponds to the
- interrupt mask bits, but we have to manage via more normal IRQs. */
-
static struct
{
char irq_to_mask[40];
char mask_to_irq[40];
+
+ /* Note mask bit is true for DISABLED irqs. */
unsigned long shadow_mask;
} sable_irq_swizzle = {
{
-1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
-1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
-1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
- 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
+ 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
},
{
34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
- 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
- 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
+ 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
+ 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
},
- 0
+ -1
};
+static inline void
+sable_update_irq_hw(unsigned long bit, unsigned long mask)
+{
+ int port = 0x536;
+
+ if (bit >= 16) {
+ port = 0x53d;
+ mask >>= 16;
+ } else if (bit >= 8) {
+ port = 0x53b;
+ mask >>= 8;
+ }
-static void
-sable_update_irq_hw(unsigned long irq, unsigned long unused_mask, int unmask_p)
+ outb(mask, port);
+}
+
+static inline void
+sable_ack_irq_hw(unsigned long bit)
+{
+ int port, val1, val2;
+
+ if (bit >= 16) {
+ port = 0x53c;
+ val1 = 0xE0 | (bit - 16);
+ val2 = 0xE0 | 4;
+ } else if (bit >= 8) {
+ port = 0x53a;
+ val1 = 0xE0 | (bit - 8);
+ val2 = 0xE0 | 2;
+ } else {
+ port = 0x536;
+ val1 = 0xE0 | (bit - 0);
+ val2 = 0xE0 | 1;
+ }
+
+ outb(val1, port); /* ack the slave */
+ outb(val2, 0x534); /* ack the master */
+}
+
+static inline void
+sable_enable_irq(unsigned int irq)
{
unsigned long bit, mask;
- /* The "irq" argument is really the irq, but we need it to
- be the mask bit number. Convert it now. */
-
- irq = sable_irq_swizzle.irq_to_mask[irq];
- bit = 1UL << irq;
- mask = sable_irq_swizzle.shadow_mask | bit;
- if (unmask_p)
- mask &= ~bit;
- sable_irq_swizzle.shadow_mask = mask;
-
- /* The "irq" argument is now really the mask bit number. */
- if (irq <= 7)
- outb(mask, 0x537);
- else if (irq <= 15)
- outb(mask >> 8, 0x53b);
- else
- outb(mask >> 16, 0x53d);
+ bit = sable_irq_swizzle.irq_to_mask[irq];
+ mask = sable_irq_swizzle.shadow_mask &= ~(1UL << bit);
+ sable_update_irq_hw(bit, mask);
}
static void
-sable_ack_irq(unsigned long irq)
+sable_disable_irq(unsigned int irq)
{
- /* Note that the "irq" here is really the mask bit number */
- switch (irq) {
- case 0 ... 7:
- outb(0xE0 | (irq - 0), 0x536);
- outb(0xE0 | 1, 0x534); /* slave 0 */
- break;
- case 8 ... 15:
- outb(0xE0 | (irq - 8), 0x53a);
- outb(0xE0 | 3, 0x534); /* slave 1 */
- break;
- case 16 ... 24:
- outb(0xE0 | (irq - 16), 0x53c);
- outb(0xE0 | 4, 0x534); /* slave 2 */
- break;
- }
+ unsigned long bit, mask;
+
+ bit = sable_irq_swizzle.irq_to_mask[irq];
+ mask = sable_irq_swizzle.shadow_mask |= 1UL << bit;
+ sable_update_irq_hw(bit, mask);
}
+static unsigned int
+sable_startup_irq(unsigned int irq)
+{
+ sable_enable_irq(irq);
+ return 0;
+}
+
+static void
+sable_mask_and_ack_irq(unsigned int irq)
+{
+ unsigned long bit, mask;
+
+ bit = sable_irq_swizzle.irq_to_mask[irq];
+ mask = sable_irq_swizzle.shadow_mask |= 1UL << bit;
+ sable_update_irq_hw(bit, mask);
+ sable_ack_irq_hw(bit);
+}
+
+static struct hw_interrupt_type sable_irq_type = {
+ typename: "SABLE",
+ startup: sable_startup_irq,
+ shutdown: sable_disable_irq,
+ enable: sable_enable_irq,
+ disable: sable_disable_irq,
+ ack: sable_mask_and_ack_irq,
+ end: sable_enable_irq,
+};
+
static void
sable_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
to the interrupt mask bits, but we have to manage via more
normal IRQs. */
- int irq, ack;
-
- ack = irq = (vector - 0x800) >> 4;
-
- irq = sable_irq_swizzle.mask_to_irq[(ack)];
-#if 0
- if (irq == 5 || irq == 9 || irq == 10 || irq == 11 ||
- irq == 14 || irq == 15)
- printk("srm_device_interrupt: vector=0x%lx ack=0x%x"
- " irq=0x%x\n", vector, ack, irq);
-#endif
+ int bit, irq;
- handle_irq(irq, ack, regs);
+ bit = (vector - 0x800) >> 4;
+ irq = sable_irq_swizzle.mask_to_irq[bit];
+ handle_irq(irq, regs);
}
static void __init
sable_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ long i;
- outb(alpha_irq_mask , 0x537); /* slave 0 */
- outb(alpha_irq_mask >> 8, 0x53b); /* slave 1 */
- outb(alpha_irq_mask >> 16, 0x53d); /* slave 2 */
- outb(0x44, 0x535); /* enable cascades in master */
+ outb(-1, 0x537); /* slave 0 */
+ outb(-1, 0x53b); /* slave 1 */
+ outb(-1, 0x53d); /* slave 2 */
+ outb(0x44, 0x535); /* enable cascades in master */
+
+ for (i = 0; i < 40; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &sable_irq_type;
+ }
+
+ init_rtc_irq();
+ common_init_isa_dma();
}
/*
* PCI Fixup configuration for ALPHA SABLE (2100) - 2100A is different ??
*
- * Summary Registers (536/53a/53c):
- * Bit Meaning
- *-----------------
- * 0 PCI slot 0
- * 1 NCR810 (builtin)
- * 2 TULIP (builtin)
- * 3 mouse
- * 4 PCI slot 1
- * 5 PCI slot 2
- * 6 keyboard
- * 7 floppy
- * 8 COM2
- * 9 parallel port
- *10 EISA irq 3
- *11 EISA irq 4
- *12 EISA irq 5
- *13 EISA irq 6
- *14 EISA irq 7
- *15 COM1
- *16 EISA irq 9
- *17 EISA irq 10
- *18 EISA irq 11
- *19 EISA irq 12
- *20 EISA irq 13
- *21 EISA irq 14
- *22 NC
- *23 IIC
- *
* The device to slot mapping looks like:
*
* Slot Device
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 40,
- irq_probe_mask: _PROBE_MASK(40),
- update_irq_hw: sable_update_irq_hw,
- ack_irq: sable_ack_irq,
device_interrupt: sable_srm_device_interrupt,
init_arch: t2_init_arch,
init_irq: sable_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
kill_arch: NULL,
pci_map_irq: sable_map_irq,
min_mem_address: DEFAULT_MEM_BASE,
nr_irqs: 40,
- irq_probe_mask: _PROBE_MASK(40),
- update_irq_hw: sable_update_irq_hw,
- ack_irq: sable_ack_irq,
device_interrupt: sable_srm_device_interrupt,
init_arch: t2_init_arch,
init_irq: sable_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: common_init_pci,
pci_map_irq: sable_map_irq,
pci_swizzle: common_swizzle,
#include <asm/core_lca.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-sio_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
-{
- if (irq >= 8)
- outb(mask >> 8, 0xA1);
- else
- outb(mask, 0x21);
-}
static void __init
sio_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
-
if (alpha_using_srm)
alpha_mv.device_interrupt = srm_device_interrupt;
-
- enable_irq(2); /* enable cascade */
+
+ init_i8259a_irqs();
+ init_rtc_irq();
+ common_init_isa_dma();
}
static inline void __init
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: _PROBE_MASK(16),
- update_irq_hw: sio_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: isa_device_interrupt,
init_arch: alphabook1_init_arch,
init_irq: sio_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: alphabook1_init_pci,
kill_arch: NULL,
pci_map_irq: noname_map_irq,
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: _PROBE_MASK(16),
- update_irq_hw: sio_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: isa_device_interrupt,
init_arch: apecs_init_arch,
init_irq: sio_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: noname_init_pci,
pci_map_irq: noname_map_irq,
pci_swizzle: common_swizzle,
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: _PROBE_MASK(16),
- update_irq_hw: sio_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: srm_device_interrupt,
init_arch: lca_init_arch,
init_irq: sio_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: noname_init_pci,
pci_map_irq: noname_map_irq,
pci_swizzle: common_swizzle,
min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: P2K_PROBE_MASK,
- update_irq_hw: sio_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: srm_device_interrupt,
init_arch: lca_init_arch,
init_irq: sio_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: noname_init_pci,
pci_map_irq: p2k_map_irq,
pci_swizzle: common_swizzle,
min_mem_address: XL_DEFAULT_MEM_BASE,
nr_irqs: 16,
- irq_probe_mask: _PROBE_MASK(16),
- update_irq_hw: sio_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: isa_device_interrupt,
init_arch: lca_init_arch,
init_irq: sio_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: noname_init_pci,
pci_map_irq: noname_map_irq,
pci_swizzle: common_swizzle,
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/core_pyxis.h>
#include "proto.h"
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-/* Note invert on MASK bits. */
-static unsigned long cached_irq_mask;
-
-static inline void
-sx164_change_irq_mask(unsigned long mask)
-{
- *(vulp)PYXIS_INT_MASK = mask;
- mb();
- *(vulp)PYXIS_INT_MASK;
-}
-
-static inline void
-sx164_enable_irq(unsigned int irq)
-{
- sx164_change_irq_mask(cached_irq_mask |= 1UL << (irq - 16));
-}
-
-static void
-sx164_disable_irq(unsigned int irq)
-{
- sx164_change_irq_mask(cached_irq_mask &= ~(1UL << (irq - 16)));
-}
-
-static unsigned int
-sx164_startup_irq(unsigned int irq)
-{
- sx164_enable_irq(irq);
- return 0;
-}
-
-static inline void
-sx164_srm_enable_irq(unsigned int irq)
-{
- cserve_ena(irq - 16);
-}
-
-static void
-sx164_srm_disable_irq(unsigned int irq)
-{
- cserve_dis(irq - 16);
-}
-
-static unsigned int
-sx164_srm_startup_irq(unsigned int irq)
-{
- sx164_srm_enable_irq(irq);
- return 0;
-}
-
-static struct hw_interrupt_type sx164_irq_type = {
- typename: "SX164",
- startup: sx164_startup_irq,
- shutdown: sx164_disable_irq,
- enable: sx164_enable_irq,
- disable: sx164_disable_irq,
- ack: sx164_disable_irq,
- end: sx164_enable_irq,
-};
-
-static struct hw_interrupt_type sx164_srm_irq_type = {
- typename: "SX164-SRM",
- startup: sx164_srm_startup_irq,
- shutdown: sx164_srm_disable_irq,
- enable: sx164_srm_enable_irq,
- disable: sx164_srm_disable_irq,
- ack: sx164_srm_disable_irq,
- end: sx164_srm_enable_irq,
-};
-
-static void
-sx164_device_interrupt(unsigned long vector, struct pt_regs *regs)
-{
- unsigned long pld;
- unsigned int i;
-
- /* Read the interrupt summary register of PYXIS */
- pld = *(vulp)PYXIS_INT_REQ;
-
- /*
- * For now, AND off any bits we are not interested in:
- * HALT (2), timer (6), ISA Bridge (7)
- * then all the PCI slots/INTXs (8-23)
- */
- /* Maybe HALT should only be used for SRM console boots? */
- pld &= 0x0000000000ffffc0UL;
-
- /*
- * Now for every possible bit set, work through them and call
- * the appropriate interrupt handler.
- */
- while (pld) {
- i = ffz(~pld);
- pld &= pld - 1; /* clear least bit set */
- if (i == 7) {
- isa_device_interrupt(vector, regs);
- } else if (i == 6) {
- continue;
- } else {
- /* if not timer int */
- handle_irq(16 + i, regs);
- }
-
- *(vulp)PYXIS_INT_REQ = 1UL << i;
- mb();
- *(vulp)PYXIS_INT_REQ;
- }
-}
-
-static void
+static void __init
sx164_init_irq(void)
{
- static struct irqaction timer = { no_action, 0, 0, "sx164-timer", NULL, NULL};
- static struct irqaction cascade = { no_action, 0, 0, "sx164-isa-cascade", NULL, NULL};
- struct hw_interrupt_type *ops;
- long i;
-
outb(0, DMA1_RESET_REG);
outb(0, DMA2_RESET_REG);
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
outb(0, DMA2_MASK_REG);
- init_ISA_irqs();
- init_RTC_irq();
-
- if (alpha_using_srm) {
+ if (alpha_using_srm)
alpha_mv.device_interrupt = srm_device_interrupt;
- ops = &sx164_srm_irq_type;
- }
- else {
- sx164_change_irq_mask(0);
- ops = &sx164_irq_type;
- }
- for (i = 16; i < 40; ++i) {
- /* Make CERTAIN none of the bogus ints get enabled. */
- if ((0x3b0000 >> i) & 1)
- continue;
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].handler = ops;
- }
+ init_i8259a_irqs();
+ init_rtc_irq();
+
+ /* Not interested in the bogus interrupts (0,3,4,5,40-47),
+ NMI (1), or HALT (2). */
+ if (alpha_using_srm)
+ init_srm_irqs(40, 0x3f0000);
+ else
+ init_pyxis_irqs(0xff00003f0000);
- setup_irq(16 + 6, &timer); /* enable timer */
- setup_irq(16 + 7, &cascade); /* enable ISA PIC cascade */
+ setup_irq(16+6, &timer_cascade_irqaction);
}
/*
* 7 64 bit PCI option slot 1
* 8 Cypress I/O
* 9 32 bit PCI option slot 3
- *
*/
static int __init
min_io_address: DEFAULT_IO_BASE,
min_mem_address: DEFAULT_MEM_BASE,
- nr_irqs: 40,
- device_interrupt: sx164_device_interrupt,
+ nr_irqs: 48,
+ device_interrupt: pyxis_device_interrupt,
init_arch: pyxis_init_arch,
init_irq: sx164_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: sx164_init_pci,
kill_arch: NULL,
pci_map_irq: sx164_map_irq,
#include <asm/core_cia.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
-static void
-takara_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
+/* Note mask bit is true for DISABLED irqs. */
+static unsigned long cached_irq_mask[2] = { -1, -1 };
+
+static inline void
+takara_update_irq_hw(unsigned long irq, unsigned long mask)
{
- unsigned int regaddr;
+ int regaddr;
- if (irq <= 15) {
- if (irq <= 7)
- outb(mask, 0x21); /* ISA PIC1 */
- else
- outb(mask >> 8, 0xA1); /* ISA PIC2 */
- } else {
- if (irq > 63)
- mask = _alpha_irq_masks[1] << 16;
- else
- mask = mask >> ((irq - 16) & 0x30);
- regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
- outl(mask & 0xffff0000UL, regaddr);
- }
+ mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
+ regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
+ outl(mask & 0xffff0000UL, regaddr);
+}
+
+static inline void
+takara_enable_irq(unsigned int irq)
+{
+ unsigned long mask;
+ mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
+ takara_update_irq_hw(irq, mask);
}
+static void
+takara_disable_irq(unsigned int irq)
+{
+ unsigned long mask;
+ mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
+ takara_update_irq_hw(irq, mask);
+}
+
+static unsigned int
+takara_startup_irq(unsigned int irq)
+{
+ takara_enable_irq(irq);
+ return 0; /* never anything pending */
+}
+
+static struct hw_interrupt_type takara_irq_type = {
+ typename: "TAKARA",
+ startup: takara_startup_irq,
+ shutdown: takara_disable_irq,
+ enable: takara_enable_irq,
+ disable: takara_disable_irq,
+ ack: takara_disable_irq,
+ end: takara_enable_irq,
+};
+
static void
takara_device_interrupt(unsigned long vector, struct pt_regs *regs)
{
* despatch an interrupt if it's set.
*/
- if (intstatus & 8) handle_irq(16+3, 16+3, regs);
- if (intstatus & 4) handle_irq(16+2, 16+2, regs);
- if (intstatus & 2) handle_irq(16+1, 16+1, regs);
- if (intstatus & 1) handle_irq(16+0, 16+0, regs);
+ if (intstatus & 8) handle_irq(16+3, regs);
+ if (intstatus & 4) handle_irq(16+2, regs);
+ if (intstatus & 2) handle_irq(16+1, regs);
+ if (intstatus & 1) handle_irq(16+0, regs);
} else {
isa_device_interrupt (vector, regs);
}
takara_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
{
int irq = (vector - 0x800) >> 4;
- handle_irq(irq, irq, regs);
+ handle_irq(irq, regs);
}
static void __init
takara_init_irq(void)
{
- STANDARD_INIT_IRQ_PROLOG;
+ long i;
+
+ init_i8259a_irqs();
+ init_rtc_irq();
if (alpha_using_srm) {
alpha_mv.device_interrupt = takara_srm_device_interrupt;
outl(ctlreg, 0x500);
}
- enable_irq(2);
+ for (i = 16; i < 128; i += 16)
+ takara_update_irq_hw(i, -1);
+
+ for (i = 16; i < 128; ++i) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].handler = &takara_irq_type;
+ }
+
+ common_init_isa_dma();
}
+
/*
* The Takara has PCI devices 1, 2, and 3 configured to slots 20,
* 19, and 18 respectively, in the default configuration. They can
min_mem_address: CIA_DEFAULT_MEM_BASE,
nr_irqs: 128,
- irq_probe_mask: _PROBE_MASK(48),
- update_irq_hw: takara_update_irq_hw,
- ack_irq: common_ack_irq,
device_interrupt: takara_device_interrupt,
init_arch: cia_init_arch,
init_irq: takara_init_irq,
- init_pit: common_init_pit,
+ init_rtc: common_init_rtc,
init_pci: takara_init_pci,
kill_arch: NULL,
pci_map_irq: takara_map_irq,
#include <linux/timex.h>
#include "proto.h"
-#include <asm/hw_irq.h>
+#include "irq_impl.h"
extern rwlock_t xtime_lock;
extern volatile unsigned long lost_ticks; /* kernel/sched.c */
)*60 + sec; /* finally seconds */
}
-#if 0
-/*
- * Initialize Programmable Interval Timers with standard values. Some
- * drivers depend on them being initialized (e.g., joystick driver).
- */
-
-#ifdef CONFIG_RTC
-void
-rtc_init_pit(void)
-{
- unsigned char control;
-
- /* Turn off RTC interrupts before /dev/rtc is initialized */
- control = CMOS_READ(RTC_CONTROL);
- control &= ~(RTC_PIE | RTC_AIE | RTC_UIE);
- CMOS_WRITE(control, RTC_CONTROL);
- (void) CMOS_READ(RTC_INTR_FLAGS);
-
- /* Setup interval timer. */
- outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
- outb(LATCH & 0xff, 0x40); /* LSB */
- outb(LATCH >> 8, 0x40); /* MSB */
-
- outb(0xb6, 0x43); /* pit counter 2: speaker */
- outb(0x31, 0x42);
- outb(0x13, 0x42);
-}
-
void
-rtc_kill_pit(void)
-{
- unsigned char control;
-
- cli();
-
- /* Reset periodic interrupt frequency. */
- CMOS_WRITE(0x26, RTC_FREQ_SELECT);
-
- /* Turn on periodic interrupts. */
- control = CMOS_READ(RTC_CONTROL);
- control |= RTC_PIE;
- CMOS_WRITE(control, RTC_CONTROL);
- CMOS_READ(RTC_INTR_FLAGS);
-
- sti();
-}
-#endif
-#endif
-
-void
-common_init_pit (void)
+common_init_rtc(struct irqaction *action)
{
unsigned char x;
outb(0xb6, 0x43); /* pit counter 2: speaker */
outb(0x31, 0x42);
outb(0x13, 0x42);
+
+ setup_irq(RTC_IRQ, action);
}
void
time_init(void)
{
+ static struct irqaction timer_irqaction = {
+ handler: timer_interrupt,
+ flags: SA_INTERRUPT,
+ name: "timer",
+ };
+
unsigned int year, mon, day, hour, min, sec, cc1, cc2;
unsigned long cycle_freq, one_percent;
long diff;
- static struct irqaction timer_irqaction = { timer_interrupt,
- SA_INTERRUPT, 0, "timer",
- NULL, NULL};
-
- /* Startup the timer source. */
- alpha_mv.init_pit();
/*
* The Linux interpretation of the CMOS clock register contents:
state.last_rtc_update = 0;
state.partial_tick = 0L;
- /* setup timer */
- setup_irq(TIMER_IRQ, &timer_irqaction);
+ /* Startup the timer source. */
+ alpha_mv.init_rtc(&timer_irqaction);
}
/*
-/* $Id: sparc_ksyms.c,v 1.90 2000/02/13 09:52:54 anton Exp $
+/* $Id: sparc_ksyms.c,v 1.91 2000/02/18 20:23:24 davem Exp $
* arch/sparc/kernel/ksyms.c: Sparc specific ksyms support.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
EXPORT_SYMBOL(sbus_unmap_sg);
EXPORT_SYMBOL(sbus_dma_sync_single);
EXPORT_SYMBOL(sbus_dma_sync_sg);
+EXPORT_SYMBOL(sbus_iounmap);
+EXPORT_SYMBOL(sbus_ioremap);
#endif
#if CONFIG_PCI
/* We do not have modular drivers for PCI devices yet. */
{
static struct timer_list sound_timer = { NULL, NULL, 0, 0,
kd_nosound };
-
unsigned int count = 0;
+ unsigned long flags;
if (hz > 20 && hz < 32767)
count = 1193180 / hz;
+ save_flags(flags);
cli();
del_timer(&sound_timer);
if (count) {
}
} else
kd_nosound(0);
- sti();
+ restore_flags(flags);
return;
}
printk (KERN_INFO RTL8139_DRIVER_NAME
" loaded (%d device%s registered)\n",
rc, rc > 1 ? "s" : "");
+ } else {
+ pci_unregister_driver (&rtl8139_pci_driver);
}
DPRINTK ("EXIT\n");
cards_found = pci_register_driver (&eepro100_driver);
if (cards_found <= 0) {
printk(KERN_INFO PFX "No cards found, driver not installed.\n");
+ pci_unregister_driver (&eepro100_driver);
return -ENODEV;
}
if (pci_register_driver (&epic100_driver) > 0)
return 0;
+ pci_unregister_driver (&epic100_driver);
return -ENODEV;
}
static int __init tulip_init (void)
{
- return pci_register_driver (&tulip_driver) > 0 ? 0 : -ENODEV;
+ if (pci_register_driver (&tulip_driver) > 0)
+ return 0;
+
+ pci_unregister_driver (&tulip_driver);
+ return -ENODEV;
}
{
if (debug) /* Emit version even if no cards detected. */
printk(KERN_INFO "%s", version);
- return pci_register_driver (&yellowfin_driver) > 0 ? 0 : -ENODEV;
+
+ if (pci_register_driver (&yellowfin_driver) > 0)
+ return 0;
+
+ pci_unregister_driver (&yellowfin_driver);
+ return -ENODEV;
}
for (idx = 0; idx < BPP_NO; idx += 1) {
instances[idx].opened = 0;
probeLptPort(idx);
- sprintf(devname, "%s%i", dev_name, idx);
}
devfs_handle = devfs_mk_dir (NULL, "bpp", 3, NULL);
devfs_register_series (devfs_handle, "%u", BPP_NO, DEVFS_FL_DEFAULT,
*/
#define aic7xxx_position(cmd) ((cmd)->SCp.have_data_in)
+/*
+ * The stored DMA mapping for single-buffer data transfers.
+ */
+#define aic7xxx_mapping(cmd) ((cmd)->SCp.phase)
+
/*
* So we can keep track of our host structs
*/
pci_unmap_sg(p->pdev, sg, cmd->use_sg, scsi_to_pci_dma_dir(cmd->sc_data_direction));
}
else if (cmd->request_bufflen)
- pci_unmap_single(p->pdev, le32_to_cpu(scb->sg_list[0].address),
- le32_to_cpu(scb->sg_list[0].length),
+ pci_unmap_single(p->pdev, aic7xxx_mapping(cmd),
+ cmd->request_bufflen,
scsi_to_pci_dma_dir(cmd->sc_data_direction));
+ if (scb->flags & SCB_SENSE)
+ {
+ pci_unmap_single(p->pdev,
+ le32_to_cpu(scb->sg_list[0].address),
+ sizeof(cmd->sense_buffer),
+ PCI_DMA_FROMDEVICE);
+ }
if (scb->flags & SCB_RECOVERY_SCB)
{
p->flags &= ~AHC_ABORT_PENDING;
scb->sg_list[0].address =
cpu_to_le32(pci_map_single(p->pdev, sense_buffer,
sizeof(cmd->sense_buffer),
- scsi_to_pci_dma_dir(cmd->sc_data_direction)));
+ PCI_DMA_FROMDEVICE));
hscb->data_pointer = scb->sg_list[0].address;
scb->flags |= SCB_SENSE;
unsigned int address = pci_map_single(p->pdev, cmd->request_buffer,
cmd->request_bufflen,
scsi_to_pci_dma_dir(cmd->sc_data_direction));
+ aic7xxx_mapping(cmd) = address;
scb->sg_list[0].address = cpu_to_le32(address);
scb->sg_list[0].length = cpu_to_le32(cmd->request_bufflen);
scb->sg_count = 1;
if (!pci_present()) /* No PCI bus in this machine! */
return -ENODEV;
printk(KERN_INFO "es1370: version v0.33 time " __TIME__ " " __DATE__ "\n");
- if (!pci_register_driver(&es1370_driver))
+ if (!pci_register_driver(&es1370_driver)) {
+ pci_unregister_driver(&es1370_driver);
return -ENODEV;
+ }
return 0;
}
if (!pci_present()) /* No PCI bus in this machine! */
return -ENODEV;
printk(KERN_INFO "es1371: version v0.25 time " __TIME__ " " __DATE__ "\n");
- if (!pci_register_driver(&es1371_driver))
+ if (!pci_register_driver(&es1371_driver)) {
+ pci_unregister_driver(&es1371_driver);
return -ENODEV;
+ }
return 0;
}
if (!pci_present()) /* No PCI bus in this machine! */
return -ENODEV;
printk(KERN_INFO "solo1: version v0.13 time " __TIME__ " " __DATE__ "\n");
- if (!pci_register_driver(&solo1_driver))
+ if (!pci_register_driver(&solo1_driver)) {
+ pci_unregister_driver(&solo1_driver);
return -ENODEV;
+ }
return 0;
}
* 06-01-2000 Refined and bugfixed ISA PnP support, added
* CMI 8330 support - Alessandro Zummo <azummo@ita.flashnet.it>
*
- *
* 04-02-2000 Added Soundblaster AWE 64 PnP support, isapnpjump
* Alessandro Zummo <azummo@ita.flashnet.it>
*
+ * 11-02-2000 Added Soundblaster AWE 32 PnP support, refined PnP code
+ * Alessandro Zummo <azummo@ita.flashnet.it>
+ *
+ * 13-02-2000 Hopefully fixed awe/sb16 related bugs, code cleanup.
+ * Alessandro Zummo <azummo@ita.flashnet.it>
+ *
*/
#include <linux/config.h>
struct pci_dev *sb_dev = NULL,
*wss_dev = NULL,
- *jp_dev = NULL,
+ *jp_dev = NULL,
+/* *ide_dev = NULL, */
*mpu_dev = NULL,
*wt_dev = NULL;
/*
int sm_games = 0; /* Mixer - see sb_mixer.c */
int acer = 0; /* Do acer notebook init */
-#ifdef CONFIG_ISAPNP
+#if defined CONFIGISAPNP || defined CONFIG_ISAPNP_MODULE
int isapnp = 1;
int isapnpjump = 0;
+int nosbwave = 0; /* This option will be removed when the new awe_wave driver will be in the kernel tree */
#else
int isapnp = 0;
#endif
MODULE_PARM(esstype, "i");
MODULE_PARM(acer, "i");
-#ifdef CONFIG_ISAPNP
+#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
MODULE_PARM(isapnp, "i");
MODULE_PARM(isapnpjump, "i");
+MODULE_PARM(nosbwave, "i");
MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
+MODULE_PARM_DESC(nosbwave, "Disable SB AWE 32/64 Wavetable initialization. Use this option with the new awe_wave driver.");
#endif
MODULE_PARM_DESC(io, "Soundblaster i/o base address (0x220,0x240,0x260,0x280)");
void *smw_free = NULL;
-#ifdef CONFIG_ISAPNP
+#if defined CONFIGISAPNP || defined CONFIG_ISAPNP_MODULE
/* That's useful. */
-static int check_base(char *devname, char *resname, struct resource *res)
+#define show_base(devname, resname, resptr) printk(KERN_INFO "sb: %s %s base located at %#lx\n", devname, resname, (resptr)->start)
+
+static struct pci_dev *activate_dev(char *devname, char *resname, struct pci_dev *dev)
{
- if (check_region(res->start, res->end - res->start))
+ int err;
+
+ if(dev->active)
{
- printk(KERN_ERR "sb: %s %s error, i/o at %#lx already in use\n", devname, resname, res->start);
- return 0;
+ printk(KERN_INFO "sb: %s %s already in use\n", devname, resname);
+ return(NULL);
}
- printk(KERN_INFO "sb: %s %s base located at %#lx\n", devname, resname, res->start);
- return 1;
-}
+ if((err = dev->activate(dev)) < 0)
+ {
+ printk(KERN_ERR "sb: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
+ dev->deactivate(dev);
+
+ return(NULL);
+ }
+ return(dev);
+}
/* Card's specific initialization functions
*/
-static struct pci_dev *sb_init_generic(struct pci_bus *card, struct address_info *hw_config, struct address_info *mpu_config)
+static struct pci_dev *sb_init_generic(struct pci_bus *bus, struct pci_dev *card, struct address_info *hw_config, struct address_info *mpu_config)
{
- if((sb_dev = isapnp_find_dev(card,
- card->vendor,
- card->device,
- NULL)))
+ if((sb_dev = isapnp_find_dev(bus, card->vendor, card->device, NULL)))
{
sb_dev->prepare(sb_dev);
- sb_dev->activate(sb_dev);
- if (!sb_dev->resource[0].start)
- return(NULL);
-
- hw_config->io_base = sb_dev->resource[0].start;
- hw_config->irq = sb_dev->irq_resource[0].start;
- hw_config->dma = sb_dev->dma_resource[0].start;
- hw_config->dma2 = sb_dev->dma_resource[1].start;
- mpu_config->io_base = sb_dev->resource[1].start;
+ if((sb_dev = activate_dev("Soundblaster", "sb", sb_dev)))
+ {
+ hw_config->io_base = sb_dev->resource[0].start;
+ hw_config->irq = sb_dev->irq_resource[0].start;
+ hw_config->dma = sb_dev->dma_resource[0].start;
+ hw_config->dma2 = sb_dev->dma_resource[1].start;
+ mpu_config->io_base = sb_dev->resource[1].start;
+ }
}
return(sb_dev);
}
-static struct pci_dev *sb_init_ess(struct pci_bus *card, struct address_info *hw_config, struct address_info *mpu_config)
+static struct pci_dev *sb_init_ess(struct pci_bus *bus, struct pci_dev *card, struct address_info *hw_config, struct address_info *mpu_config)
{
- if((sb_dev = isapnp_find_dev(card,
- card->vendor,
- card->device,
- NULL)))
+ if((sb_dev = isapnp_find_dev(bus, card->vendor, card->device, NULL)))
{
sb_dev->prepare(sb_dev);
- sb_dev->activate(sb_dev);
-
- if (!sb_dev->resource[0].start)
- return(NULL);
- hw_config->io_base = sb_dev->resource[0].start;
- hw_config->irq = sb_dev->irq_resource[0].start;
- hw_config->dma = sb_dev->dma_resource[0].start;
- hw_config->dma2 = sb_dev->dma_resource[1].start;
- mpu_config->io_base = sb_dev->resource[2].start;
+ if((sb_dev = activate_dev("ESS", "sb", sb_dev)))
+ {
+ hw_config->io_base = sb_dev->resource[0].start;
+ hw_config->irq = sb_dev->irq_resource[0].start;
+ hw_config->dma = sb_dev->dma_resource[0].start;
+ hw_config->dma2 = sb_dev->dma_resource[1].start;
+ mpu_config->io_base = sb_dev->resource[2].start;
+ }
}
return(sb_dev);
}
-static struct pci_dev *sb_init_cmi(struct pci_bus *card, struct address_info *hw_config, struct address_info *mpu_config)
+static struct pci_dev *sb_init_cmi(struct pci_bus *bus, struct pci_dev *card, struct address_info *hw_config, struct address_info *mpu_config)
{
- /* What a stupid chip... where did they get all those @@@ ?*/
-
- printk(KERN_INFO "sb: CMI8330 detected\n");
-
- /* Soundblaster compatible logical device. */
-
- if((sb_dev = isapnp_find_dev(card,
+ /*
+ * The CMI8330/C3D is a very 'stupid' chip... where did they get al those @@@ ?
+ * It's ISAPnP section is badly designed and has many flaws, i'll do my best
+ * to workaround them. I strongly suggest you to buy a real soundcard.
+ * The CMI8330 on my motherboard has also the bad habit to activate
+ * the rear channel of my amplifier instead of the front one.
+ */
+
+ /* @X@0001:Soundblaster.
+ */
+
+ if((sb_dev = isapnp_find_dev(bus,
ISAPNP_VENDOR('@','X','@'), ISAPNP_FUNCTION(0x0001), NULL)))
{
#ifdef CMI8330_DMA0BAD
sb_dev->prepare(sb_dev);
/* This device doesn't work with DMA 0, so we must allocate
- it to prevent PnP routines to assign it to the card.
-
- I know i could have inlined the following lines, but it's cleaner
- this way.
- */
+ * it to prevent PnP routines to assign it to the card.
+ *
+ * I know i could have inlined the following lines, but it's cleaner
+ * this way.
+ */
#ifdef CMI8330_DMA0BAD
if(sb_dev->dma_resource[0].start == 0)
}
#endif
- if(sb_dev->activate(sb_dev) >= 0)
+ if((sb_dev = activate_dev("CMI8330", "sb", sb_dev)))
{
hw_config->io_base = sb_dev->resource[0].start;
hw_config->irq = sb_dev->irq_resource[0].start;
hw_config->dma = sb_dev->dma_resource[0].start;
hw_config->dma2 = sb_dev->dma_resource[1].start;
- check_base("CMI8330", "sb", &sb_dev->resource[0]);
+ show_base("CMI8330", "sb", &sb_dev->resource[0]);
}
- else
- printk(KERN_ERR "sb: CMI8330 sb config failed (out of resources?)\n");
#ifdef CMI8330_DMA0BAD
if(dmahack)
free_dma(0);
#endif
+
+ if(!sb_dev) return(NULL);
+
}
else
- printk(KERN_ERR "sb: CMI8330 panic! sb base not found\n");
+ printk(KERN_ERR "sb: CMI8330 panic: sb base not found\n");
+
+ /* @H@0001:mpu
+ */
- if((mpu_dev = isapnp_find_dev(card,
+#ifdef CONFIG_MIDI
+ if((mpu_dev = isapnp_find_dev(bus,
ISAPNP_VENDOR('@','H','@'), ISAPNP_FUNCTION(0x0001), NULL)))
{
mpu_dev->prepare(mpu_dev);
- /* This disables the interrupt on this resource. Do we need it ? */
+ /* This disables the interrupt on this resource. Do we need it ?
+ */
mpu_dev->irq_resource[0].flags = 0;
- if(mpu_dev->activate(mpu_dev) >= 0)
+ if((mpu_dev = activate_dev("CMI8330", "mpu", mpu_dev)))
{
- if( check_base("CMI8330", "mpu", &mpu_dev->resource[0]) )
- mpu_config->io_base = mpu_dev->resource[0].start;
+ show_base("CMI8330", "mpu", &mpu_dev->resource[0]);
+ mpu_config->io_base = mpu_dev->resource[0].start;
}
- else
- printk(KERN_ERR "sb: CMI8330 mpu config failed (out of resources?)\n");
}
else
- printk(KERN_ERR "sb: CMI8330 panic! mpu not found\n");
+ printk(KERN_ERR "sb: CMI8330 panic: mpu not found\n");
+#endif
- /* Gameport. */
+ /* @P@:Gameport
+ */
- if((jp_dev = isapnp_find_dev(card,
+ if((jp_dev = isapnp_find_dev(bus,
ISAPNP_VENDOR('@','P','@'), ISAPNP_FUNCTION(0x0001), NULL)))
{
jp_dev->prepare(jp_dev);
- if(jp_dev->activate(jp_dev) >= 0)
- {
- check_base("CMI8330", "gameport", &jp_dev->resource[0]);
- }
- else
- printk(KERN_ERR "sb: CMI8330 gameport config failed (out of resources?)\n");
+
+ if((jp_dev = activate_dev("CMI8330", "gameport", jp_dev)))
+ show_base("CMI8330", "gameport", &jp_dev->resource[0]);
}
else
- printk(KERN_ERR "sb: CMI8330 panic! gameport not found\n");
-
+ printk(KERN_ERR "sb: CMI8330 panic: gameport not found\n");
- /* OPL3 support */
+ /* @@@0001:OPL3
+ */
#if defined(CONFIG_SOUND_YM3812) || defined(CONFIG_SOUND_YM3812_MODULE)
- if((wss_dev = isapnp_find_dev(card,
+ if((wss_dev = isapnp_find_dev(bus,
ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), NULL)))
{
wss_dev->prepare(wss_dev);
wss_dev->irq_resource[0].flags = 0;
wss_dev->dma_resource[0].flags = 0;
- if(wss_dev->activate(wss_dev) >= 0)
- {
- check_base("CMI8330", "opl3", &wss_dev->resource[1]);
- }
- else
- printk(KERN_ERR "sb: CMI8330 opl3 config failed (out of resources?)\n");
+ if((wss_dev = activate_dev("CMI8330", "opl3", wss_dev)))
+ show_base("CMI8330", "opl3", &wss_dev->resource[1]);
}
else
- printk(KERN_ERR "sb: CMI8330 panic! opl3 not found\n");
+ printk(KERN_ERR "sb: CMI8330 panic: opl3 not found\n");
#endif
printk(KERN_INFO "sb: CMI8330 mail reports to Alessandro Zummo <azummo@ita.flashnet.it>\n");
return(sb_dev);
}
-static struct pci_dev *sb_init_awe64(struct pci_bus *card, struct address_info *hw_config, struct address_info *mpu_config)
-{
- printk(KERN_INFO "sb: SoundBlaster AWE 64 detected\n");
-
- /* CTL0042:Audio. */
+/* Specific support for awe will be dropped when:
+ * a) The new awe_wawe driver with PnP support will be introduced in the kernel
+ * b) The joystick driver will support PnP
+ */
- if((sb_dev = isapnp_find_dev(card,
- ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0042), NULL)))
+static struct pci_dev *sb_init_awe(struct pci_bus *bus, struct pci_dev *card, struct address_info *hw_config, struct address_info *mpu_config)
+{
+ /* CTL0042:Audio SB64
+ * CTL0031:Audio SB32
+ * CTL0045:Audio SB64
+ */
+
+ if( (sb_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0042), NULL)) ||
+ (sb_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0031), NULL)) ||
+ (sb_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0045), NULL)) )
{
sb_dev->prepare(sb_dev);
- if(sb_dev->activate(sb_dev) >= 0)
+ if((sb_dev = activate_dev("AWE", "sb", sb_dev)))
{
hw_config->io_base = sb_dev->resource[0].start;
hw_config->irq = sb_dev->irq_resource[0].start;
mpu_config->io_base = sb_dev->resource[1].start;
- check_base("AWE64", "sb", &sb_dev->resource[0]);
- check_base("AWE64", "mpu", &sb_dev->resource[1]);
- check_base("AWE64", "opl3", &sb_dev->resource[2]);
+ show_base("AWE", "sb", &sb_dev->resource[0]);
+ show_base("AWE", "mpu", &sb_dev->resource[1]);
+ show_base("AWE", "opl3", &sb_dev->resource[2]);
}
else
- printk(KERN_ERR "sb: AWE64 sb config failed (out of resources?)\n");
+ return(NULL);
}
else
- printk(KERN_ERR "sb: AWE64 panic! sb base not found\n");
+ printk(KERN_ERR "sb: AWE panic: sb base not found\n");
- /* CTL7002:Game */
+ /* CTL7002:Game SB64
+ * CTL7001:Game SB32
+ */
- if((jp_dev = isapnp_find_dev(card,
- ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x7002), NULL)))
+ if( (jp_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x7002), NULL)) ||
+ (jp_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x7001), NULL)) )
{
jp_dev->prepare(jp_dev);
- if(jp_dev->activate(jp_dev) >= 0)
+ if((jp_dev = activate_dev("AWE", "gameport", jp_dev)))
+ show_base("AWE", "gameport", &jp_dev->resource[0]);
+ }
+ else
+ printk(KERN_ERR "sb: AWE panic: gameport not found\n");
+
+
+ /* CTL0022:WaveTable SB64
+ * CTL0021:WaveTable SB32
+ */
+
+ if( nosbwave == 0 &&
+ ( (wt_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0023), NULL)) ||
+ (wt_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0022), NULL)) ||
+ (wt_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0021), NULL)) ))
+ {
+ wt_dev->prepare(wt_dev);
+
+ if((wt_dev = activate_dev("AWE", "wavetable", wt_dev)))
{
- check_base("AWE64", "gameport", &jp_dev->resource[0]);
+ show_base("AWE", "wavetable", &wt_dev->resource[0]);
+ show_base("AWE", "wavetable", &wt_dev->resource[1]);
+ show_base("AWE", "wavetable", &wt_dev->resource[2]);
}
- else
- printk(KERN_ERR "sb: AWE64 gameport config failed (out of resources?)\n");
}
else
- printk(KERN_ERR "sb: AWE64 panic! gameport not found\n");
+ printk(KERN_ERR "sb: AWE panic: wavetable not found\n");
- /* CTL0022:WaveTable */
+ /* CTL2011:IDE SB32/64
+ */
- if((wt_dev = isapnp_find_dev(card,
- ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0022), NULL)))
+/* No reasons to enable this... or not? */
+/*
+ if( (ide_dev = isapnp_find_dev(bus, ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x2011), NULL)) )
{
- wt_dev->prepare(wt_dev);
+ ide_dev->prepare(ide_dev);
- if(wt_dev->activate(wt_dev) >= 0)
+ if((ide_dev = activate_dev("AWE", "IDE", ide_dev)))
{
- check_base("AWE64", "wavetable", &wt_dev->resource[0]);
- check_base("AWE64", "wavetable", &wt_dev->resource[1]);
- check_base("AWE64", "wavetable", &wt_dev->resource[2]);
+ show_base("AWE", "IDE 1", &ide_dev->resource[0]);
+ show_base("AWE", "IDE 2", &ide_dev->resource[1]);
}
- else
- printk(KERN_ERR "sb: AWE64 wavetable config failed (out of resources?)\n");
}
else
- printk(KERN_ERR "sb: AWE64 panic! wavetable not found\n");
+ printk(KERN_ERR "sb: AWE panic: IDE not found\n");
+*/
- printk(KERN_INFO "sb: AWE
64 mail reports to Alessandro Zummo <azummo@ita.flashnet.it>\n");
+ printk(KERN_INFO "sb: AWE mail reports to Alessandro Zummo <azummo@ita.flashnet.it>\n");
return(sb_dev);
}
+#define SBF_DEV 0x01
-static struct { unsigned short vendor, function; struct pci_dev * (*initfunc)(struct pci_bus *, struct address_info *, struct address_info *); char *name; }
+
+static struct { unsigned short vendor, function, flags; struct pci_dev * (*initfunc)(struct pci_bus *, struct pci_dev *, struct address_info *, struct address_info *); char *name; }
isapnp_sb_list[] __initdata = {
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0001), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0031), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0041), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0042), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0043), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0044), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0045), &sb_init_generic, "Sound Blaster 16" },
- {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x009D), &sb_init_awe64, "Sound Blaster AWE 64" },
- {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1868), &sb_init_ess, "ESS 1868" },
- {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x8611), &sb_init_ess, "ESS 1868" },
- {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1869), &sb_init_ess, "ESS 1869" },
- {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1878), &sb_init_ess, "ESS 1878" },
- {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1879), &sb_init_ess, "ESS 1879" },
- {ISAPNP_VENDOR('C','M','I'), ISAPNP_FUNCTION(0x0001), &sb_init_cmi, "CMI 8330 SoundPRO" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0001), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0031), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0041), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0042), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0043), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0045), SBF_DEV, &sb_init_generic, "Sound Blaster 16" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0044), 0, &sb_init_awe, "Sound Blaster 32" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x0039), 0, &sb_init_awe, "Sound Blaster AWE 32" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x009D), 0, &sb_init_awe, "Sound Blaster AWE 64" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x00C5), 0, &sb_init_awe, "Sound Blaster AWE 64" },
+ {ISAPNP_VENDOR('C','T','L'), ISAPNP_FUNCTION(0x00E4), 0, &sb_init_awe, "Sound Blaster AWE 64" },
+ {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1868), SBF_DEV, &sb_init_ess, "ESS 1868" },
+ {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x8611), SBF_DEV, &sb_init_ess, "ESS 1868" },
+ {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1869), SBF_DEV, &sb_init_ess, "ESS 1869" },
+ {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1878), SBF_DEV, &sb_init_ess, "ESS 1878" },
+ {ISAPNP_VENDOR('E','S','S'), ISAPNP_FUNCTION(0x1879), SBF_DEV, &sb_init_ess, "ESS 1879" },
+ {ISAPNP_VENDOR('C','M','I'), ISAPNP_FUNCTION(0x0001), 0, &sb_init_cmi, "CMI 8330 SoundPRO" },
{0}
};
+static int __init sb_init_isapnp(struct address_info *hw_config, struct address_info *mpu_config, struct pci_bus *bus, struct pci_dev *card, int slot)
+{
+ struct pci_dev *idev = NULL;
+
+ /* You missed the init func? That's bad. */
+ if(isapnp_sb_list[slot].initfunc)
+ {
+ char *busname = bus->name[0] ? bus->name : isapnp_sb_list[slot].name;
+
+ printk(KERN_INFO "sb: %s detected\n", busname);
+
+ /* Initialize this baby. */
+
+ if((idev = isapnp_sb_list[slot].initfunc(bus, card, hw_config, mpu_config)))
+ {
+ /* We got it. */
+
+ printk(KERN_NOTICE "sb: ISAPnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
+ busname,
+ hw_config->io_base, hw_config->irq, hw_config->dma,
+ hw_config->dma2);
+ return 1;
+ }
+ else
+ printk(KERN_INFO "sb: Failed to initialize %s\n", busname);
+ }
+ else
+ printk(KERN_ERR "sb: Bad entry in sb_card.c PnP table\n");
+
+ return 0;
+}
+
/* Actually this routine will detect and configure only the first card with successful
- initalization. isapnpjump could be used to jump to a specific entry.
+ initialization. isapnpjump could be used to jump to a specific entry.
Please always add entries at the end of the array.
Should this be fixed? - azummo
*/
-static int __init sb_probe_isapnp(struct address_info *hw_config, struct address_info *mpu_config) {
-
+static int __init sb_probe_isapnp(struct address_info *hw_config, struct address_info *mpu_config)
+{
int i;
/* Count entries in isapnp_sb_list */
}
for (i = isapnpjump; isapnp_sb_list[i].vendor != 0; i++) {
- struct pci_bus *card = NULL;
-
- while ((card = isapnp_find_card(
- isapnp_sb_list[i].vendor,
- isapnp_sb_list[i].function,
- card))) {
- /* You missed the init func? That's bad. */
+ if(!(isapnp_sb_list[i].flags & SBF_DEV))
+ {
+ struct pci_bus *bus = NULL;
+
+ while ((bus = isapnp_find_card(
+ isapnp_sb_list[i].vendor,
+ isapnp_sb_list[i].function,
+ bus))) {
+
+ if(sb_init_isapnp(hw_config, mpu_config, bus, NULL, i))
+ return 0;
+ }
+ }
+ }
- if(isapnp_sb_list[i].initfunc)
- {
- struct pci_dev *idev = NULL;
+ /* No cards found. I'll try now to search inside every card for a logical device
+ * that matches any entry marked with SBF_DEV in the table.
+ */
+
+ for (i = isapnpjump; isapnp_sb_list[i].vendor != 0; i++) {
- /* Initialize this baby. */
+ if(isapnp_sb_list[i].flags & SBF_DEV)
+ {
+ struct pci_dev *card = NULL;
- if((idev = isapnp_sb_list[i].initfunc(card, hw_config, mpu_config)))
- {
- /* We got it. */
+ while ((card = isapnp_find_dev(NULL,
+ isapnp_sb_list[i].vendor,
+ isapnp_sb_list[i].function,
+ card))) {
- printk(KERN_INFO "sb: ISAPnP reports %s at i/o %#x, irq %d, dma %d, %d\n",
- isapnp_sb_list[i].name,
- hw_config->io_base, hw_config->irq, hw_config->dma,
- hw_config->dma2);
+ if(sb_init_isapnp(hw_config, mpu_config, card->bus, card, i))
return 0;
- }
}
}
}
+
return -ENODEV;
}
#endif
able to disable PNP support for this single driver!
*/
-#ifdef CONFIG_ISAPNP
- if (isapnp)
+#if defined CONFIGISAPNP || defined CONFIG_ISAPNP_MODULE
+ if(isapnp && (sb_probe_isapnp(&config, &config_mpu) < 0) )
{
- if(sb_probe_isapnp(&config, &config_mpu) < 0 )
- {
- printk(KERN_ERR "sb_card: No ISAPnP cards found\n");
- return -EINVAL;
- }
+ printk(KERN_NOTICE "sb_card: No ISAPnP cards found, trying standard ones...\n");
+ isapnp = 0;
}
- else
+#endif
+ if(isapnp == 0)
{
-#endif
if (io == -1 || dma == -1 || irq == -1)
{
printk(KERN_ERR "sb_card: I/O, IRQ, and DMA are mandatory\n");
config.irq = irq;
config.dma = dma;
config.dma2 = dma16;
-#ifdef CONFIG_ISAPNP
}
-#endif
- /* If this is not before the #ifdef line, there's a reason... */
config.card_subtype = type;
if (!probe_sb(&config))
if(sb_dev) sb_dev->deactivate(sb_dev);
if(jp_dev) jp_dev->deactivate(jp_dev);
if(wt_dev) wt_dev->deactivate(wt_dev);
+/* if(ide_dev) wt_dev->deactivate(ide_dev); */
if(mpu_dev) mpu_dev->deactivate(mpu_dev);
if(wss_dev) wss_dev->deactivate(wss_dev);
}
if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
#endif
- if (!pci_register_driver(&sv_driver))
+ if (!pci_register_driver(&sv_driver)) {
+ pci_unregister_driver(&sv_driver);
return -ENODEV;
+ }
return 0;
}
/*
* A special note of gratitude to ATI's devrel for providing documentation,
- * example code and hardware. Thanks Nitya. -atong
+ * example code and hardware. Thanks Nitya. -atong and brad
*/
{"PCI_DEVICE_ID_ATI_RAGE128_RF", PCI_VENDOR_ID_ATI, 0x5246},
{"PCI_DEVICE_ID_ATI_RAGE128_RK", PCI_VENDOR_ID_ATI, 0x524b},
{"PCI_DEVICE_ID_ATI_RAGE128_RL", PCI_VENDOR_ID_ATI, 0x524c},
+ {"PCI_DEVICE_ID_ATI_RAGE128_PF", PCI_VENDOR_ID_ATI, 0x5046},
+ {"PCI_DEVICE_ID_ATI_RAGE128_PR", PCI_VENDOR_ID_ATI, 0x5052},
{NULL, 0, 0}
};
} else {
if (mac_vmode_to_var(default_vmode, default_cmode, &var))
var = default_var;
-#endif /* CONFIG_PPC */
}
+#endif /* CONFIG_PPC */
#endif /* MODULE */
if (noaccel)
* Accelerated functions
*/
-static void
-aty128_rectdraw(s16 x, s16 y, u16 width, u16 height,
- struct fb_info_aty128 *info)
-{
- /* perform rectangle operation */
- wait_for_fifo(2, info);
- aty_st_le32(DST_Y_X, (y << 16) | x);
- aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
-
- info->blitter_may_be_busy = 1;
-}
-
-
static void
aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
u_int width, u_int height,
define_tristate CONFIG_LOCKD n
fi
fi
- if [ "$CONFIG_NFSD_V3" == "y" ]; then
+ if [ "$CONFIG_NFSD_V3" = "y" ]; then
define_bool CONFIG_LOCKD_V4 y
fi
tristate 'SMB file system support (to mount WfW shares etc.)' CONFIG_SMB_FS
* Copyright (C) 1996, Olaf Kirch <okir@monad.swb.de>
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
* Copyright (C) 1996, Olaf Kirch <okir@monad.swb.de>
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/malloc.h>
* Copyright (C) 1996, Olaf Kirch <okir@monad.swb.de>
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/sched.h>
* Copyright (C) 1995, 1996 Olaf Kirch <okir@monad.swb.de>
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/utsname.h>
#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
+/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
+ Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
+#define MCPCIA_HOSE2MID(h) ((h) + 4)
+
#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
/*
-#ifndef _ALPHA_HW_IRQ_H
-#define _ALPHA_HW_IRQ_H
-/*
- * linux/arch/alpha/kernel/irq.h
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 1998 Richard Henderson
- *
- * This file contains declarations and inline functions for interfacing
- * with the IRQ handling routines in irq.c.
- */
+/* This exists merely to satisfy <linux/irq.h>. There is
+ nothing that would go here of general interest.
-#include <linux/config.h>
-
-#define STANDARD_INIT_IRQ_PROLOG \
- outb(0, DMA1_RESET_REG); \
- outb(0, DMA2_RESET_REG); \
- outb(0, DMA1_CLR_MASK_REG); \
- outb(0, DMA2_CLR_MASK_REG)
-
-extern void common_ack_irq(unsigned long irq);
-extern void isa_device_interrupt(unsigned long vector, struct pt_regs * regs);
-extern void srm_device_interrupt(unsigned long vector, struct pt_regs * regs);
-
-extern void handle_irq(int irq, struct pt_regs * regs);
-
-#define RTC_IRQ 8
-#if 0 /* on Alpha we want to use only the RTC as timer for SMP issues */
-#ifdef CONFIG_RTC
-#define TIMER_IRQ 0 /* timer is the pit */
-#else
-#define TIMER_IRQ RTC_IRQ /* timer is the rtc */
-#endif
-#else
-#define TIMER_IRQ RTC_IRQ /* timer is the rtc */
-#endif
-
-/*
- * PROBE_MASK is the bitset of irqs that we consider for autoprobing.
- */
-
-/* NOTE: we only handle the first 64 IRQs in this code. */
-
-/* The normal mask includes all the IRQs except timer IRQ 0. */
-#define _PROBE_MASK(nr_irqs) \
- (((nr_irqs > 63) ? ~0UL : ((1UL << (nr_irqs & 63)) - 1)) & ~1UL)
-
-/* Mask out unused timer irq 0 and RTC irq 8. */
-#define P2K_PROBE_MASK (_PROBE_MASK(16) & ~0x101UL)
-
-/* Mask out unused timer irq 0, "irqs" 20-30, and the EISA cascade. */
-#define ALCOR_PROBE_MASK (_PROBE_MASK(48) & ~0xfff000000001UL)
-
-/* Leave timer IRQ 0 in the mask. */
-#define RUFFIAN_PROBE_MASK (_PROBE_MASK(48) | 1UL)
-
-/* Do not probe/enable beyond the PCI devices. */
-#define TSUNAMI_PROBE_MASK _PROBE_MASK(48)
-
-#if defined(CONFIG_ALPHA_GENERIC)
-# define PROBE_MASK alpha_mv.irq_probe_mask
-#elif defined(CONFIG_ALPHA_P2K)
-# define PROBE_MASK P2K_PROBE_MASK
-#elif defined(CONFIG_ALPHA_ALCOR) || defined(CONFIG_ALPHA_XLT)
-# define PROBE_MASK ALCOR_PROBE_MASK
-#elif defined(CONFIG_ALPHA_RUFFIAN)
-# define PROBE_MASK RUFFIAN_PROBE_MASK
-#elif defined(CONFIG_ALPHA_DP264)
-# define PROBE_MASK TSUNAMI_PROBE_MASK
-#else
-# define PROBE_MASK _PROBE_MASK(NR_IRQS)
-#endif
-
-
-static inline void alpha_do_profile (unsigned long pc)
-{
- if (prof_buffer && current->pid) {
- extern char _stext;
-
- pc -= (unsigned long) &_stext;
- pc >>= prof_shift;
- /*
- * Don't ignore out-of-bounds PC values silently,
- * put them into the last histogram slot, so if
- * present, they will show up as a sharp peak.
- */
- if (pc > prof_len - 1)
- pc = prof_len - 1;
- atomic_inc((atomic_t *)&prof_buffer[pc]);
- }
-}
-
-static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
-extern void no_action(int cpl, void *dev_id, struct pt_regs *regs);
-extern void init_ISA_irqs(void);
-extern void init_RTC_irq(void);
-
-#endif
+ Everything of consequence is in arch/alpha/kernel/irq_impl.h,
+ to be used only in arch/alpha/kernel/. */
#define EV56_CPU 7 /* EV5.6 (21164) */
#define EV6_CPU 8 /* EV6 (21164) */
#define PCA56_CPU 9 /* PCA56 (21164PC) */
-#define PCA57_CPU 10 /* PCA57 (21164??) */
+#define PCA57_CPU 10 /* PCA57 (notyet) */
/*
* DEC system types for Alpha systems. Found in HWRPB.
#define ST_DTI_RUFFIAN 101 /* RUFFIAN systype */
/* Alpha Processor, Inc. systems */
-#define ST_API_BIAS 200 /* Offset for API systems */
-#define ST_API_NAUTILUS (ST_API_BIAS + 1) /* Nautilus systype */
+#define ST_API_BIAS 200
+#define ST_API_NAUTILUS 201 /* UP1000 systype */
struct pcb_struct {
unsigned long ksp;
struct pci_dev;
struct pci_ops;
struct pci_controler;
+struct irqaction;
struct alpha_machine_vector
{
void (*init_arch)(void);
void (*init_irq)(void);
- void (*init_pit)(void);
+ void (*init_rtc)(struct irqaction *);
void (*init_pci)(void);
void (*kill_arch)(int);
#define AOFF_task_pidhash_pprev 0x00000094
#define ASIZ_task_pidhash_pprev 0x00000004
#define AOFF_task_wait_chldexit 0x00000098
-#define ASIZ_task_wait_chldexit 0x00000010
-#define AOFF_task_vfork_sem 0x000000a8
+#define ASIZ_task_wait_chldexit 0x00000014
+#define AOFF_task_vfork_sem 0x000000ac
#define ASIZ_task_vfork_sem 0x00000004
-#define AOFF_task_rt_priority 0x000000ac
+#define AOFF_task_rt_priority 0x000000b0
#define ASIZ_task_rt_priority 0x00000004
-#define AOFF_task_it_real_value 0x000000b0
+#define AOFF_task_it_real_value 0x000000b4
#define ASIZ_task_it_real_value 0x00000004
-#define AOFF_task_it_prof_value 0x000000b4
+#define AOFF_task_it_prof_value 0x000000b8
#define ASIZ_task_it_prof_value 0x00000004
-#define AOFF_task_it_virt_value 0x000000b8
+#define AOFF_task_it_virt_value 0x000000bc
#define ASIZ_task_it_virt_value 0x00000004
-#define AOFF_task_it_real_incr 0x000000bc
+#define AOFF_task_it_real_incr 0x000000c0
#define ASIZ_task_it_real_incr 0x00000004
-#define AOFF_task_it_prof_incr 0x000000c0
+#define AOFF_task_it_prof_incr 0x000000c4
#define ASIZ_task_it_prof_incr 0x00000004
-#define AOFF_task_it_virt_incr 0x000000c4
+#define AOFF_task_it_virt_incr 0x000000c8
#define ASIZ_task_it_virt_incr 0x00000004
-#define AOFF_task_real_timer 0x000000c8
+#define AOFF_task_real_timer 0x000000cc
#define ASIZ_task_real_timer 0x00000018
-#define AOFF_task_times 0x000000e0
+#define AOFF_task_times 0x000000e4
#define ASIZ_task_times 0x00000010
-#define AOFF_task_start_time 0x000000f0
+#define AOFF_task_start_time 0x000000f4
#define ASIZ_task_start_time 0x00000004
-#define AOFF_task_per_cpu_utime 0x000000f4
+#define AOFF_task_per_cpu_utime 0x000000f8
#define ASIZ_task_per_cpu_utime 0x00000004
-#define AOFF_task_min_flt 0x000000fc
+#define AOFF_task_min_flt 0x00000100
#define ASIZ_task_min_flt 0x00000004
-#define AOFF_task_maj_flt 0x00000100
+#define AOFF_task_maj_flt 0x00000104
#define ASIZ_task_maj_flt 0x00000004
-#define AOFF_task_nswap 0x00000104
+#define AOFF_task_nswap 0x00000108
#define ASIZ_task_nswap 0x00000004
-#define AOFF_task_cmin_flt 0x00000108
+#define AOFF_task_cmin_flt 0x0000010c
#define ASIZ_task_cmin_flt 0x00000004
-#define AOFF_task_cmaj_flt 0x0000010c
+#define AOFF_task_cmaj_flt 0x00000110
#define ASIZ_task_cmaj_flt 0x00000004
-#define AOFF_task_cnswap 0x00000110
+#define AOFF_task_cnswap 0x00000114
#define ASIZ_task_cnswap 0x00000004
-#define AOFF_task_uid 0x00000118
+#define AOFF_task_uid 0x0000011c
#define ASIZ_task_uid 0x00000004
-#define AOFF_task_euid 0x0000011c
+#define AOFF_task_euid 0x00000120
#define ASIZ_task_euid 0x00000004
-#define AOFF_task_suid 0x00000120
+#define AOFF_task_suid 0x00000124
#define ASIZ_task_suid 0x00000004
-#define AOFF_task_fsuid 0x00000124
+#define AOFF_task_fsuid 0x00000128
#define ASIZ_task_fsuid 0x00000004
-#define AOFF_task_gid 0x00000128
+#define AOFF_task_gid 0x0000012c
#define ASIZ_task_gid 0x00000004
-#define AOFF_task_egid 0x0000012c
+#define AOFF_task_egid 0x00000130
#define ASIZ_task_egid 0x00000004
-#define AOFF_task_sgid 0x00000130
+#define AOFF_task_sgid 0x00000134
#define ASIZ_task_sgid 0x00000004
-#define AOFF_task_fsgid 0x00000134
+#define AOFF_task_fsgid 0x00000138
#define ASIZ_task_fsgid 0x00000004
-#define AOFF_task_ngroups 0x00000138
+#define AOFF_task_ngroups 0x0000013c
#define ASIZ_task_ngroups 0x00000004
-#define AOFF_task_groups 0x0000013c
+#define AOFF_task_groups 0x00000140
#define ASIZ_task_groups 0x00000080
-#define AOFF_task_cap_effective 0x000001bc
+#define AOFF_task_cap_effective 0x000001c0
#define ASIZ_task_cap_effective 0x00000004
-#define AOFF_task_cap_inheritable 0x000001c0
+#define AOFF_task_cap_inheritable 0x000001c4
#define ASIZ_task_cap_inheritable 0x00000004
-#define AOFF_task_cap_permitted 0x000001c4
+#define AOFF_task_cap_permitted 0x000001c8
#define ASIZ_task_cap_permitted 0x00000004
-#define AOFF_task_user 0x000001c8
+#define AOFF_task_user 0x000001cc
#define ASIZ_task_user 0x00000004
-#define AOFF_task_rlim 0x000001cc
+#define AOFF_task_rlim 0x000001d0
#define ASIZ_task_rlim 0x00000050
-#define AOFF_task_used_math 0x0000021c
+#define AOFF_task_used_math 0x00000220
#define ASIZ_task_used_math 0x00000002
-#define AOFF_task_comm 0x0000021e
+#define AOFF_task_comm 0x00000222
#define ASIZ_task_comm 0x00000010
-#define AOFF_task_link_count 0x00000230
+#define AOFF_task_link_count 0x00000234
#define ASIZ_task_link_count 0x00000004
-#define AOFF_task_tty 0x00000234
+#define AOFF_task_tty 0x00000238
#define ASIZ_task_tty 0x00000004
-#define AOFF_task_semundo 0x00000238
+#define AOFF_task_semundo 0x0000023c
#define ASIZ_task_semundo 0x00000004
-#define AOFF_task_semsleeping 0x0000023c
+#define AOFF_task_semsleeping 0x00000240
#define ASIZ_task_semsleeping 0x00000004
-#define AOFF_task_thread 0x00000240
+#define AOFF_task_thread 0x00000248
#define ASIZ_task_thread 0x00000380
-#define AOFF_task_fs 0x000005c0
+#define AOFF_task_fs 0x000005c8
#define ASIZ_task_fs 0x00000004
-#define AOFF_task_files 0x000005c4
+#define AOFF_task_files 0x000005cc
#define ASIZ_task_files 0x00000004
-#define AOFF_task_sigmask_lock 0x000005c8
-#define ASIZ_task_sigmask_lock 0x00000000
-#define AOFF_task_sig 0x000005c8
+#define AOFF_task_sigmask_lock 0x000005d0
+#define ASIZ_task_sigmask_lock 0x00000004
+#define AOFF_task_sig 0x000005d4
#define ASIZ_task_sig 0x00000004
-#define AOFF_task_signal 0x000005cc
+#define AOFF_task_signal 0x000005d8
#define ASIZ_task_signal 0x00000008
-#define AOFF_task_blocked 0x000005d4
+#define AOFF_task_blocked 0x000005e0
#define ASIZ_task_blocked 0x00000008
-#define AOFF_task_sigqueue 0x000005dc
+#define AOFF_task_sigqueue 0x000005e8
#define ASIZ_task_sigqueue 0x00000004
-#define AOFF_task_sigqueue_tail 0x000005e0
+#define AOFF_task_sigqueue_tail 0x000005ec
#define ASIZ_task_sigqueue_tail 0x00000004
-#define AOFF_task_sas_ss_sp 0x000005e4
+#define AOFF_task_sas_ss_sp 0x000005f0
#define ASIZ_task_sas_ss_sp 0x00000004
-#define AOFF_task_sas_ss_size 0x000005e8
+#define AOFF_task_sas_ss_size 0x000005f4
#define ASIZ_task_sas_ss_size 0x00000004
-#define AOFF_task_parent_exec_id 0x000005ec
+#define AOFF_task_parent_exec_id 0x000005f8
#define ASIZ_task_parent_exec_id 0x00000004
-#define AOFF_task_self_exec_id 0x000005f0
+#define AOFF_task_self_exec_id 0x000005fc
#define ASIZ_task_self_exec_id 0x00000004
-#define AOFF_task_exit_sem 0x000005f4
-#define ASIZ_task_exit_sem 0x0000001c
+#define AOFF_task_exit_sem 0x00000600
+#define ASIZ_task_exit_sem 0x00000020
#define AOFF_mm_mmap 0x00000000
#define ASIZ_mm_mmap 0x00000004
#define AOFF_mm_mmap_avl 0x00000004
#define AOFF_mm_map_count 0x00000018
#define ASIZ_mm_map_count 0x00000004
#define AOFF_mm_mmap_sem 0x0000001c
-#define ASIZ_mm_mmap_sem 0x0000001c
-#define AOFF_mm_page_table_lock 0x00000038
-#define ASIZ_mm_page_table_lock 0x00000000
-#define AOFF_mm_context 0x00000038
+#define ASIZ_mm_mmap_sem 0x00000020
+#define AOFF_mm_page_table_lock 0x0000003c
+#define ASIZ_mm_page_table_lock 0x00000004
+#define AOFF_mm_context 0x00000040
#define ASIZ_mm_context 0x00000004
-#define AOFF_mm_start_code 0x0000003c
+#define AOFF_mm_start_code 0x00000044
#define ASIZ_mm_start_code 0x00000004
-#define AOFF_mm_end_code 0x00000040
+#define AOFF_mm_end_code 0x00000048
#define ASIZ_mm_end_code 0x00000004
-#define AOFF_mm_start_data 0x00000044
+#define AOFF_mm_start_data 0x0000004c
#define ASIZ_mm_start_data 0x00000004
-#define AOFF_mm_end_data 0x00000048
+#define AOFF_mm_end_data 0x00000050
#define ASIZ_mm_end_data 0x00000004
-#define AOFF_mm_start_brk 0x0000004c
+#define AOFF_mm_start_brk 0x00000054
#define ASIZ_mm_start_brk 0x00000004
-#define AOFF_mm_brk 0x00000050
+#define AOFF_mm_brk 0x00000058
#define ASIZ_mm_brk 0x00000004
-#define AOFF_mm_start_stack 0x00000054
+#define AOFF_mm_start_stack 0x0000005c
#define ASIZ_mm_start_stack 0x00000004
-#define AOFF_mm_arg_start 0x00000058
+#define AOFF_mm_arg_start 0x00000060
#define ASIZ_mm_arg_start 0x00000004
-#define AOFF_mm_arg_end 0x0000005c
+#define AOFF_mm_arg_end 0x00000064
#define ASIZ_mm_arg_end 0x00000004
-#define AOFF_mm_env_start 0x00000060
+#define AOFF_mm_env_start 0x00000068
#define ASIZ_mm_env_start 0x00000004
-#define AOFF_mm_env_end 0x00000064
+#define AOFF_mm_env_end 0x0000006c
#define ASIZ_mm_env_end 0x00000004
-#define AOFF_mm_rss 0x00000068
+#define AOFF_mm_rss 0x00000070
#define ASIZ_mm_rss 0x00000004
-#define AOFF_mm_total_vm 0x0000006c
+#define AOFF_mm_total_vm 0x00000074
#define ASIZ_mm_total_vm 0x00000004
-#define AOFF_mm_locked_vm 0x00000070
+#define AOFF_mm_locked_vm 0x00000078
#define ASIZ_mm_locked_vm 0x00000004
-#define AOFF_mm_def_flags 0x00000074
+#define AOFF_mm_def_flags 0x0000007c
#define ASIZ_mm_def_flags 0x00000004
-#define AOFF_mm_cpu_vm_mask 0x00000078
+#define AOFF_mm_cpu_vm_mask 0x00000080
#define ASIZ_mm_cpu_vm_mask 0x00000004
-#define AOFF_mm_swap_cnt 0x0000007c
+#define AOFF_mm_swap_cnt 0x00000084
#define ASIZ_mm_swap_cnt 0x00000004
-#define AOFF_mm_swap_address 0x00000080
+#define AOFF_mm_swap_address 0x00000088
#define ASIZ_mm_swap_address 0x00000004
-#define AOFF_mm_segments 0x00000084
+#define AOFF_mm_segments 0x0000008c
#define ASIZ_mm_segments 0x00000004
#define AOFF_thread_uwinmask 0x00000000
#define ASIZ_thread_uwinmask 0x00000004
#define AOFF_task_pidhash_pprev 0x000000f8
#define ASIZ_task_pidhash_pprev 0x00000008
#define AOFF_task_wait_chldexit 0x00000100
-#define ASIZ_task_wait_chldexit 0x00000020
-#define AOFF_task_vfork_sem 0x00000120
+#define ASIZ_task_wait_chldexit 0x00000028
+#define AOFF_task_vfork_sem 0x00000128
#define ASIZ_task_vfork_sem 0x00000008
-#define AOFF_task_rt_priority 0x00000128
+#define AOFF_task_rt_priority 0x00000130
#define ASIZ_task_rt_priority 0x00000008
-#define AOFF_task_it_real_value 0x00000130
+#define AOFF_task_it_real_value 0x00000138
#define ASIZ_task_it_real_value 0x00000008
-#define AOFF_task_it_prof_value 0x00000138
+#define AOFF_task_it_prof_value 0x00000140
#define ASIZ_task_it_prof_value 0x00000008
-#define AOFF_task_it_virt_value 0x00000140
+#define AOFF_task_it_virt_value 0x00000148
#define ASIZ_task_it_virt_value 0x00000008
-#define AOFF_task_it_real_incr 0x00000148
+#define AOFF_task_it_real_incr 0x00000150
#define ASIZ_task_it_real_incr 0x00000008
-#define AOFF_task_it_prof_incr 0x00000150
+#define AOFF_task_it_prof_incr 0x00000158
#define ASIZ_task_it_prof_incr 0x00000008
-#define AOFF_task_it_virt_incr 0x00000158
+#define AOFF_task_it_virt_incr 0x00000160
#define ASIZ_task_it_virt_incr 0x00000008
-#define AOFF_task_real_timer 0x00000160
+#define AOFF_task_real_timer 0x00000168
#define ASIZ_task_real_timer 0x00000030
-#define AOFF_task_times 0x00000190
+#define AOFF_task_times 0x00000198
#define ASIZ_task_times 0x00000020
-#define AOFF_task_start_time 0x000001b0
+#define AOFF_task_start_time 0x000001b8
#define ASIZ_task_start_time 0x00000008
-#define AOFF_task_per_cpu_utime 0x000001b8
+#define AOFF_task_per_cpu_utime 0x000001c0
#define ASIZ_task_per_cpu_utime 0x00000008
-#define AOFF_task_min_flt 0x000001c8
+#define AOFF_task_min_flt 0x000001d0
#define ASIZ_task_min_flt 0x00000008
-#define AOFF_task_maj_flt 0x000001d0
+#define AOFF_task_maj_flt 0x000001d8
#define ASIZ_task_maj_flt 0x00000008
-#define AOFF_task_nswap 0x000001d8
+#define AOFF_task_nswap 0x000001e0
#define ASIZ_task_nswap 0x00000008
-#define AOFF_task_cmin_flt 0x000001e0
+#define AOFF_task_cmin_flt 0x000001e8
#define ASIZ_task_cmin_flt 0x00000008
-#define AOFF_task_cmaj_flt 0x000001e8
+#define AOFF_task_cmaj_flt 0x000001f0
#define ASIZ_task_cmaj_flt 0x00000008
-#define AOFF_task_cnswap 0x000001f0
+#define AOFF_task_cnswap 0x000001f8
#define ASIZ_task_cnswap 0x00000008
-#define AOFF_task_uid 0x000001fc
+#define AOFF_task_uid 0x00000204
#define ASIZ_task_uid 0x00000004
-#define AOFF_task_euid 0x00000200
+#define AOFF_task_euid 0x00000208
#define ASIZ_task_euid 0x00000004
-#define AOFF_task_suid 0x00000204
+#define AOFF_task_suid 0x0000020c
#define ASIZ_task_suid 0x00000004
-#define AOFF_task_fsuid 0x00000208
+#define AOFF_task_fsuid 0x00000210
#define ASIZ_task_fsuid 0x00000004
-#define AOFF_task_gid 0x0000020c
+#define AOFF_task_gid 0x00000214
#define ASIZ_task_gid 0x00000004
-#define AOFF_task_egid 0x00000210
+#define AOFF_task_egid 0x00000218
#define ASIZ_task_egid 0x00000004
-#define AOFF_task_sgid 0x00000214
+#define AOFF_task_sgid 0x0000021c
#define ASIZ_task_sgid 0x00000004
-#define AOFF_task_fsgid 0x00000218
+#define AOFF_task_fsgid 0x00000220
#define ASIZ_task_fsgid 0x00000004
-#define AOFF_task_ngroups 0x0000021c
+#define AOFF_task_ngroups 0x00000224
#define ASIZ_task_ngroups 0x00000004
-#define AOFF_task_groups 0x00000220
+#define AOFF_task_groups 0x00000228
#define ASIZ_task_groups 0x00000080
-#define AOFF_task_cap_effective 0x000002a0
+#define AOFF_task_cap_effective 0x000002a8
#define ASIZ_task_cap_effective 0x00000004
-#define AOFF_task_cap_inheritable 0x000002a4
+#define AOFF_task_cap_inheritable 0x000002ac
#define ASIZ_task_cap_inheritable 0x00000004
-#define AOFF_task_cap_permitted 0x000002a8
+#define AOFF_task_cap_permitted 0x000002b0
#define ASIZ_task_cap_permitted 0x00000004
-#define AOFF_task_user 0x000002b0
+#define AOFF_task_user 0x000002b8
#define ASIZ_task_user 0x00000008
-#define AOFF_task_rlim 0x000002b8
+#define AOFF_task_rlim 0x000002c0
#define ASIZ_task_rlim 0x000000a0
-#define AOFF_task_used_math 0x00000358
+#define AOFF_task_used_math 0x00000360
#define ASIZ_task_used_math 0x00000002
-#define AOFF_task_comm 0x0000035a
+#define AOFF_task_comm 0x00000362
#define ASIZ_task_comm 0x00000010
-#define AOFF_task_link_count 0x0000036c
+#define AOFF_task_link_count 0x00000374
#define ASIZ_task_link_count 0x00000004
-#define AOFF_task_tty 0x00000370
+#define AOFF_task_tty 0x00000378
#define ASIZ_task_tty 0x00000008
-#define AOFF_task_semundo 0x00000378
+#define AOFF_task_semundo 0x00000380
#define ASIZ_task_semundo 0x00000008
-#define AOFF_task_semsleeping 0x00000380
+#define AOFF_task_semsleeping 0x00000388
#define ASIZ_task_semsleeping 0x00000008
#define AOFF_task_thread 0x00000390
#define ASIZ_task_thread 0x00000450
#define AOFF_task_files 0x000007e8
#define ASIZ_task_files 0x00000008
#define AOFF_task_sigmask_lock 0x000007f0
-#define ASIZ_task_sigmask_lock 0x00000000
-#define AOFF_task_sig 0x000007f0
+#define ASIZ_task_sigmask_lock 0x00000004
+#define AOFF_task_sig 0x000007f8
#define ASIZ_task_sig 0x00000008
-#define AOFF_task_signal 0x000007f8
+#define AOFF_task_signal 0x00000800
#define ASIZ_task_signal 0x00000008
-#define AOFF_task_blocked 0x00000800
+#define AOFF_task_blocked 0x00000808
#define ASIZ_task_blocked 0x00000008
-#define AOFF_task_sigqueue 0x00000808
+#define AOFF_task_sigqueue 0x00000810
#define ASIZ_task_sigqueue 0x00000008
-#define AOFF_task_sigqueue_tail 0x00000810
+#define AOFF_task_sigqueue_tail 0x00000818
#define ASIZ_task_sigqueue_tail 0x00000008
-#define AOFF_task_sas_ss_sp 0x00000818
+#define AOFF_task_sas_ss_sp 0x00000820
#define ASIZ_task_sas_ss_sp 0x00000008
-#define AOFF_task_sas_ss_size 0x00000820
+#define AOFF_task_sas_ss_size 0x00000828
#define ASIZ_task_sas_ss_size 0x00000008
-#define AOFF_task_parent_exec_id 0x00000828
+#define AOFF_task_parent_exec_id 0x00000830
#define ASIZ_task_parent_exec_id 0x00000004
-#define AOFF_task_self_exec_id 0x0000082c
+#define AOFF_task_self_exec_id 0x00000834
#define ASIZ_task_self_exec_id 0x00000004
-#define AOFF_task_exit_sem 0x00000830
-#define ASIZ_task_exit_sem 0x00000030
-#define ASIZ_task 0x00000860
+#define AOFF_task_exit_sem 0x00000838
+#define ASIZ_task_exit_sem 0x00000038
+#define ASIZ_task 0x00000870
#define AOFF_mm_mmap 0x00000000
#define ASIZ_mm_mmap 0x00000008
#define AOFF_mm_mmap_avl 0x00000008
#define AOFF_mm_map_count 0x00000028
#define ASIZ_mm_map_count 0x00000004
#define AOFF_mm_mmap_sem 0x00000030
-#define ASIZ_mm_mmap_sem 0x00000030
-#define AOFF_mm_page_table_lock 0x00000060
-#define ASIZ_mm_page_table_lock 0x00000000
-#define AOFF_mm_context 0x00000060
+#define ASIZ_mm_mmap_sem 0x00000038
+#define AOFF_mm_page_table_lock 0x00000068
+#define ASIZ_mm_page_table_lock 0x00000004
+#define AOFF_mm_context 0x00000070
#define ASIZ_mm_context 0x00000008
-#define AOFF_mm_start_code 0x00000068
+#define AOFF_mm_start_code 0x00000078
#define ASIZ_mm_start_code 0x00000008
-#define AOFF_mm_end_code 0x00000070
+#define AOFF_mm_end_code 0x00000080
#define ASIZ_mm_end_code 0x00000008
-#define AOFF_mm_start_data 0x00000078
+#define AOFF_mm_start_data 0x00000088
#define ASIZ_mm_start_data 0x00000008
-#define AOFF_mm_end_data 0x00000080
+#define AOFF_mm_end_data 0x00000090
#define ASIZ_mm_end_data 0x00000008
-#define AOFF_mm_start_brk 0x00000088
+#define AOFF_mm_start_brk 0x00000098
#define ASIZ_mm_start_brk 0x00000008
-#define AOFF_mm_brk 0x00000090
+#define AOFF_mm_brk 0x000000a0
#define ASIZ_mm_brk 0x00000008
-#define AOFF_mm_start_stack 0x00000098
+#define AOFF_mm_start_stack 0x000000a8
#define ASIZ_mm_start_stack 0x00000008
-#define AOFF_mm_arg_start 0x000000a0
+#define AOFF_mm_arg_start 0x000000b0
#define ASIZ_mm_arg_start 0x00000008
-#define AOFF_mm_arg_end 0x000000a8
+#define AOFF_mm_arg_end 0x000000b8
#define ASIZ_mm_arg_end 0x00000008
-#define AOFF_mm_env_start 0x000000b0
+#define AOFF_mm_env_start 0x000000c0
#define ASIZ_mm_env_start 0x00000008
-#define AOFF_mm_env_end 0x000000b8
+#define AOFF_mm_env_end 0x000000c8
#define ASIZ_mm_env_end 0x00000008
-#define AOFF_mm_rss 0x000000c0
+#define AOFF_mm_rss 0x000000d0
#define ASIZ_mm_rss 0x00000008
-#define AOFF_mm_total_vm 0x000000c8
+#define AOFF_mm_total_vm 0x000000d8
#define ASIZ_mm_total_vm 0x00000008
-#define AOFF_mm_locked_vm 0x000000d0
+#define AOFF_mm_locked_vm 0x000000e0
#define ASIZ_mm_locked_vm 0x00000008
-#define AOFF_mm_def_flags 0x000000d8
+#define AOFF_mm_def_flags 0x000000e8
#define ASIZ_mm_def_flags 0x00000008
-#define AOFF_mm_cpu_vm_mask 0x000000e0
+#define AOFF_mm_cpu_vm_mask 0x000000f0
#define ASIZ_mm_cpu_vm_mask 0x00000008
-#define AOFF_mm_swap_cnt 0x000000e8
+#define AOFF_mm_swap_cnt 0x000000f8
#define ASIZ_mm_swap_cnt 0x00000008
-#define AOFF_mm_swap_address 0x000000f0
+#define AOFF_mm_swap_address 0x00000100
#define ASIZ_mm_swap_address 0x00000008
-#define AOFF_mm_segments 0x000000f8
+#define AOFF_mm_segments 0x00000108
#define ASIZ_mm_segments 0x00000008
-#define ASIZ_mm 0x00000100
+#define ASIZ_mm 0x00000110
#define AOFF_thread_ksp 0x00000000
#define ASIZ_thread_ksp 0x00000008
#define AOFF_thread_wstate 0x00000008
#ifdef __KERNEL__
+#include <linux/config.h>
#include <linux/in.h>
#include <linux/fs.h>
#include <linux/utsname.h>
#ifndef LINUX_LOCKD_NLM_H
#define LINUX_LOCKD_NLM_H
+#include <linux/config.h>
+
/* Maximum file offset in file_lock.fl_end */
#ifdef OFFSET_MAX
# define NLM_OFFSET_MAX OFFSET_MAX
#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246
#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b
#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
+#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_VLSI_82C592 0x0005
/*
* Your basic spinlocks, allowing only a single CPU anywhere
*
- * Gcc-2.7.x has a nasty bug with empty initializers.
+ * Most gcc versions have a nasty bug with empty initializers.
*/
-#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)
+#if (__GNUC__ > 2)
typedef struct { } spinlock_t;
#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
#else
* irq-safe write-lock, but readers can get non-irqsafe
* read-locks.
*
- * Gcc-2.7.x has a nasty bug with empty initializers.
+ * Most gcc versions have a nasty bug with empty initializers.
*/
-#if (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)
+#if (__GNUC__ > 2)
typedef struct { } rwlock_t;
#define RW_LOCK_UNLOCKED (rwlock_t) { }
#else
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <asm/atomic.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/inetdevice.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <linux/inetdevice.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <linux/inetdevice.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include "br_private.h"
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <linux/smp_lock.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include "br_private.h"
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <linux/smp_lock.h>
* 2 of the License, or (at your option) any later version.
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/if_bridge.h>
#include <linux/smp_lock.h>
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