From a6b5d7445e3678cd064b3f8091009019bdade637 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 23 Nov 2007 15:17:45 -0500 Subject: [PATCH] Import 2.1.133pre5 --- arch/i386/kernel/smp.c | 17 ----------------- include/asm-i386/system.h | 11 +++++++++++ include/asm-i386/system.h.lock~ | 1 - kernel/sched.c | 4 ++-- 4 files changed, 13 insertions(+), 20 deletions(-) delete mode 100644 include/asm-i386/system.h.lock~ diff --git a/arch/i386/kernel/smp.c b/arch/i386/kernel/smp.c index 0105843ad906..b6a779dfe3e0 100644 --- a/arch/i386/kernel/smp.c +++ b/arch/i386/kernel/smp.c @@ -44,7 +44,6 @@ #include #include #include -#include #ifdef CONFIG_MTRR # include @@ -1225,12 +1224,10 @@ static inline unsigned int __get_ICR (void) int count = 0; unsigned int cfg; - IO_trace (IO_smp_wait_apic_start, 0, 0, 0, 0); while (count < 1000) { cfg = slow_ICR; if (!(cfg&(1<<12))) { - IO_trace (IO_smp_wait_apic_end, 0, 0, 0, 0); if (count) atomic_add(count, (atomic_t*)&ipi_count); return cfg; @@ -1299,9 +1296,6 @@ static inline void __send_IPI_shortcut(unsigned int shortcut, int vector) /* * Send the IPI. The write to APIC_ICR fires this off. */ - - IO_trace (IO_smp_send_ipi, shortcut, vector, cfg, 0); - apic_write(APIC_ICR, cfg); #if FORCE_APIC_SERIALIZATION __restore_flags(flags); @@ -1348,9 +1342,6 @@ static inline void send_IPI_single(int dest, int vector) /* * Send the IPI. The write to APIC_ICR fires this off. */ - - IO_trace (IO_smp_send_ipi, dest, vector, cfg, 0); - apic_write(APIC_ICR, cfg); #if FORCE_APIC_SERIALIZATION __restore_flags(flags); @@ -1390,8 +1381,6 @@ void smp_flush_tlb(void) __save_flags(flags); __cli(); - IO_trace (IO_smp_message, 0, 0, 0, 0); - send_IPI_allbutself(INVALIDATE_TLB_VECTOR); /* @@ -1556,9 +1545,6 @@ void smp_apic_timer_interrupt(struct pt_regs * regs) */ asmlinkage void smp_reschedule_interrupt(void) { - IO_trace (IO_smp_reschedule, current->need_resched, - current->priority, current->counter, 0); - ack_APIC_irq(); } @@ -1567,9 +1553,6 @@ asmlinkage void smp_reschedule_interrupt(void) */ asmlinkage void smp_invalidate_interrupt(void) { - IO_trace (IO_smp_tlbflush, - atomic_read((atomic_t *)&smp_invalidate_needed), 0, 0, 0); - if (test_and_clear_bit(smp_processor_id(), &smp_invalidate_needed)) local_flush_tlb(); diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index 9e01b26174d4..3399a9684d1d 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -165,8 +165,19 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) * Force strict CPU ordering. * And yes, this is required on UP too when we're talking * to devices. + * + * For now, "wmb()" doesn't actually do anything, as all + * intel CPU's follow what intel calls a *Processor Order*, + * in which all writes are seen in the program order even + * outside the CPU. + * + * I expect future intel CPU's to have a weaker ordering, + * but I'd also expect them to finally get their act together + * and add some real memory barriers if so. */ #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("": : :"memory") /* interrupt control.. */ #define __sti() __asm__ __volatile__ ("sti": : :"memory") diff --git a/include/asm-i386/system.h.lock~ b/include/asm-i386/system.h.lock~ deleted file mode 100644 index 860783bc11b3..000000000000 --- a/include/asm-i386/system.h.lock~ +++ /dev/null @@ -1 +0,0 @@ -torvalds@penguin.transmeta.com \ No newline at end of file diff --git a/kernel/sched.c b/kernel/sched.c index ad151d1198d5..28f72e2559bf 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -594,9 +594,9 @@ static inline void __schedule_tail (void) * We have dropped all locks, and we must make sure that we * only mark the previous process as no longer having a CPU * after all other state has been seen by other CPU's. Thus - * the memory barrier! + * the write memory barrier! */ - mb(); + wmb(); sched_data->prev->has_cpu = 0; #endif /* __SMP__ */ } -- 2.39.5