From b8030f2601b2231c7a5187058395d474a296f3a4 Mon Sep 17 00:00:00 2001 From: Dave Jones Date: Mon, 5 Jan 2004 18:30:48 +0000 Subject: [PATCH] [CPUFREQ] Support for 533 MHz FSB in speedstep driver. --- arch/i386/kernel/cpu/cpufreq/speedstep-lib.c | 37 ++++++++++++++++++-- arch/i386/kernel/cpu/cpufreq/speedstep-lib.h | 2 +- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c index e3a75684f1d1..927d3bebd6ff 100644 --- a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c +++ b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c @@ -106,14 +106,45 @@ static unsigned int pentium3_get_frequency (unsigned int processor) static unsigned int pentium4_get_frequency(void) { - u32 msr_lo, msr_hi; + struct cpuinfo_x86 *c = &boot_cpu_data; + u32 msr_lo, msr_hi, mult; + unsigned int fsb = 0; rdmsr(0x2c, msr_lo, msr_hi); dprintk(KERN_DEBUG "speedstep-lib: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); - msr_lo >>= 24; - return (msr_lo * 100000); + /* decode the FSB: see IA-32 Intel (C) Architecture Software + * Developer's Manual, Volume 3: System Prgramming Guide, + * revision #12 in Table B-1: MSRs in the Pentium 4 and + * Intel Xeon Processors, on page B-4 and B-5. + */ + if (c->x86_model < 2) + fsb = 100 * 1000; + else { + u8 fsb_code = (msr_lo >> 16) & 0x7; + switch (fsb_code) { + case 0: + fsb = 100 * 1000; + break; + case 1: + fsb = 13333 * 10; + break; + case 2: + fsb = 200 * 1000; + break; + } + } + + if (!fsb) + printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to \n"); + + /* Multiplier. */ + mult = msr_lo >> 24; + + dprintk(KERN_DEBUG "speedstep-lib: P4 - FSB %u kHz; Multiplier %u\n", fsb, mult); + + return (fsb * mult); } diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h index 04951e0e65d1..ff7521d0195d 100644 --- a/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h +++ b/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h @@ -15,7 +15,7 @@ #define SPEEDSTEP_PROCESSOR_PIII_C_EARLY 0x00000001 /* Coppermine core */ #define SPEEDSTEP_PROCESSOR_PIII_C 0x00000002 /* Coppermine core */ #define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */ -#define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M with 100 MHz FSB */ +#define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M */ /* speedstep states -- only two of them */ -- 2.39.5