From f270bc9ef748afc89a776908f405e5496863d479 Mon Sep 17 00:00:00 2001 From: Eli Carter Date: Thu, 17 Apr 2003 19:37:48 +0100 Subject: [PATCH] [ARM PATCH] 1503/1: Adds basic support for the iq80321 board Patch from Eli Carter # Tue Apr 15 16:07:34 CDT 2003 ejc@rnd-linux-c84 # add-iq80321 # # Adds basic support for the iq80321 board. # # Diff'ed against 2.5.65-rmk1+1472-4+1502 # Applies to 2.5.67-rmk1+1502 with offsets # # arch/arm/boot/Makefile | 1 # arch/arm/boot/compressed/head-xscale.S | 6 # arch/arm/def-configs/iq80321 | 676 ++++++++++++++++++++++++++++++ # arch/arm/kernel/debug.S | 10 # arch/arm/kernel/entry-armv.S | 22 # arch/arm/mach-iop3xx/Kconfig | 12 # arch/arm/mach-iop3xx/Makefile | 16 # arch/arm/mach-iop3xx/arch.c | 26 + # arch/arm/mach-iop3xx/iop321-irq.c | 95 ++++ # arch/arm/mach-iop3xx/iop321-pci.c | 257 +++++++++++ # arch/arm/mach-iop3xx/iop321-time.c | 92 ++++ # arch/arm/mach-iop3xx/iq80321-pci.c | 98 ++++ # arch/arm/mach-iop3xx/mm-321.c | 64 ++ # arch/arm/mm/proc-xscale.S | 19 # include/asm-arm/arch-iop3xx/hardware.h | 17 # include/asm-arm/arch-iop3xx/iop321-irqs.h | 83 +++ # include/asm-arm/arch-iop3xx/iop321.h | 143 ++++++ # include/asm-arm/arch-iop3xx/iq80321.h | 17 # include/asm-arm/arch-iop3xx/irqs.h | 67 -- # include/asm-arm/arch-iop3xx/memory.h | 11 # include/asm-arm/arch-iop3xx/serial.h | 11 # include/asm-arm/arch-iop3xx/timex.h | 6 # include/asm-arm/arch-iop3xx/uncompress.h | 7 # include/asm-arm/mach/pci.h | 4 # 24 files changed, 1691 insertions(+), 69 deletions(-) --- arch/arm/boot/Makefile | 1 + arch/arm/boot/compressed/head-xscale.S | 6 + arch/arm/def-configs/iq80321 | 676 ++++++++++++++++++++++ arch/arm/kernel/debug.S | 10 +- arch/arm/kernel/entry-armv.S | 22 + arch/arm/mach-iop3xx/Kconfig | 12 + arch/arm/mach-iop3xx/Makefile | 16 +- arch/arm/mach-iop3xx/arch.c | 26 + arch/arm/mach-iop3xx/iop321-irq.c | 95 +++ arch/arm/mach-iop3xx/iop321-pci.c | 257 ++++++++ arch/arm/mach-iop3xx/iop321-time.c | 92 +++ arch/arm/mach-iop3xx/iq80321-pci.c | 98 ++++ arch/arm/mach-iop3xx/mm-321.c | 64 ++ arch/arm/mm/proc-xscale.S | 19 + include/asm-arm/arch-iop3xx/hardware.h | 17 + include/asm-arm/arch-iop3xx/iop321-irqs.h | 83 +++ include/asm-arm/arch-iop3xx/iop321.h | 143 +++++ include/asm-arm/arch-iop3xx/iq80321.h | 17 + include/asm-arm/arch-iop3xx/irqs.h | 67 +-- include/asm-arm/arch-iop3xx/memory.h | 11 + include/asm-arm/arch-iop3xx/serial.h | 11 + include/asm-arm/arch-iop3xx/timex.h | 6 +- include/asm-arm/arch-iop3xx/uncompress.h | 7 +- include/asm-arm/mach/pci.h | 4 + 24 files changed, 1691 insertions(+), 69 deletions(-) create mode 100644 arch/arm/def-configs/iq80321 create mode 100644 arch/arm/mach-iop3xx/iop321-irq.c create mode 100644 arch/arm/mach-iop3xx/iop321-pci.c create mode 100644 arch/arm/mach-iop3xx/iop321-time.c create mode 100644 arch/arm/mach-iop3xx/iq80321-pci.c create mode 100644 arch/arm/mach-iop3xx/mm-321.c create mode 100644 include/asm-arm/arch-iop3xx/iop321-irqs.h create mode 100644 include/asm-arm/arch-iop3xx/iop321.h create mode 100644 include/asm-arm/arch-iop3xx/iq80321.h diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 6c939f814ca6..93718d4e5fba 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -45,6 +45,7 @@ endif zreladdr-$(CONFIG_ARCH_PXA) := 0xa0008000 zreladdr-$(CONFIG_ARCH_ANAKIN) := 0x20008000 zreladdr-$(CONFIG_ARCH_IQ80310) := 0xa0008000 + zreladdr-$(CONFIG_ARCH_IQ80321) := 0xa0008000 zreladdr-$(CONFIG_ARCH_ADIFCC) := 0xc0008000 ZRELADDR := $(zreladdr-y) diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index cf9a9c9d065d..29ada3eb46fd 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -34,6 +34,12 @@ __XScale_start: bic r0, r0, #0x1000 @ clear Icache mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_ARCH_IQ80321 + orr pc, pc, #0xa0000000 + nop + mov r7, #MACH_TYPE_IQ80321 +#endif + #ifdef CONFIG_ARCH_LUBBOCK mov r7, #MACH_TYPE_LUBBOCK #endif diff --git a/arch/arm/def-configs/iq80321 b/arch/arm/def-configs/iq80321 new file mode 100644 index 000000000000..129def68e676 --- /dev/null +++ b/arch/arm/def-configs/iq80321 @@ -0,0 +1,676 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_SWAP=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +# CONFIG_EXPERIMENTAL is not set + +# +# General setup +# +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_IOP3XX=y +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set + +# +# Archimedes/A5000 Implementations +# + +# +# Archimedes/A5000 Implementations (select only ONE) +# + +# +# CLPS711X/EP721X Implementations +# + +# +# Epxa10db +# + +# +# Footbridge Implementations +# + +# +# IOP3xx Implementation Options +# +# CONFIG_ARCH_IQ80310 is not set +CONFIG_ARCH_IQ80321=y +# CONFIG_ARCH_IOP310 is not set +CONFIG_ARCH_IOP321=y + +# +# IOP3xx Chipset Features +# + +# +# Intel PXA250/210 Implementations +# + +# +# SA11x0 Implementations +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y + +# +# Processor Features +# +CONFIG_XSCALE_PMU=y + +# +# General setup +# +CONFIG_PCI=y +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_PCI_LEGACY_PROC is not set +CONFIG_PCI_NAMES=y +# CONFIG_HOTPLUG is not set + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_AOUT=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_REDBOOT_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_IQ80321=y +# CONFIG_MTD_EDB7312 is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_UCLINUX is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_XFRM_USER is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_DGRS is not set +CONFIG_EEPRO100=y +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_FDDI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +CONFIG_BLK_DEV_IDECD=y +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +CONFIG_IDEDMA_PCI_AUTO=y +# CONFIG_IDEDMA_ONLYDISK is not set +CONFIG_BLK_DEV_IDEDMA=y +CONFIG_BLK_DEV_ADMA=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_SL82C105 is not set +CONFIG_IDEDMA_AUTO=y +# CONFIG_IDEDMA_IVB is not set +CONFIG_BLK_DEV_IDE_MODES=y + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Userland interfaces +# + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# + +# +# Character devices +# +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_DZ is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# + +# +# L3 serial bus support +# +# CONFIG_L3 is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=y + +# +# Video For Linux +# +# CONFIG_VIDEO_PROC_FS is not set + +# +# Video Adapters +# +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set + +# +# Radio Adapters +# +# CONFIG_RADIO_GEMTEK_PCI is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_MAESTRO is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_FAT_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set +CONFIG_TMPFS=y +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_XFS_FS is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +# CONFIG_CIFS is not set +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set + +# +# Console Switches +# +# CONFIG_SWITCHES is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_KALLSYMS is not set +CONFIG_DEBUG_LL=y + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 783be704b70c..ab3c1431933e 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -414,7 +414,13 @@ .macro addruart,rx mov \rx, #0xfe000000 @ physical - orr \rx, \rx, #0x00810000 +#ifdef CONFIG_ARCH_IQ80310 + orr \rx, \rx, #0x00810000 @ location of the UART +#elif defined(CONFIG_ARCH_IQ80321) + orr \rx, \rx, #0x00800000 @ location of the UART +#else +#error Unknown IOP3XX implementation +#endif .endm .macro senduart,rd,rx @@ -429,9 +435,11 @@ .endm .macro waituart,rd,rx +#ifndef CONFIG_ARCH_IQ80321 1001: ldrb \rd, [\rx, #0x6] tst \rd, #0x10 beq 1001b +#endif .endm #elif defined(CONFIG_ARCH_ADI_EVB) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index ec13c1d9110a..d1ed876d9acc 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -584,6 +584,28 @@ ENTRY(anakin_active_irqs) .macro irq_prio_table .endm +#elif defined(CONFIG_ARCH_IOP321) + .macro disable_fiq + .endm + + /* + * Note: only deal with normal interrupts, not FIQ + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + beq 1001f + clz \irqnr, \irqstat + mov \base, #31 + subs \irqnr,\base,\irqnr + add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT +1001: + .endm + + .macro irq_prio_table + .endm + #elif defined(CONFIG_ARCH_PXA) .macro disable_fiq diff --git a/arch/arm/mach-iop3xx/Kconfig b/arch/arm/mach-iop3xx/Kconfig index 97d888fde028..b234d4586435 100644 --- a/arch/arm/mach-iop3xx/Kconfig +++ b/arch/arm/mach-iop3xx/Kconfig @@ -12,6 +12,12 @@ config ARCH_IQ80310 Say Y here if you want to run your kernel on the Intel IQ80310 evaluation kit for the IOP310 chipset. +config ARCH_IQ80321 + bool "IQ80321" + depends on ARCH_IOP3XX + help + Say Y here if you want to run your kernel on the Intel IQ80321 + evaluation kit for the IOP321 chipset. endchoice # Which IOP variant are we running? @@ -21,6 +27,12 @@ config ARCH_IOP310 help The IQ80310 uses the IOP310 variant. +config ARCH_IOP321 + bool + default ARCH_IQ80321 + help + The IQ80321 uses the IOP321 variant. + comment "IOP3xx Chipset Features" config IOP3XX_AAU diff --git a/arch/arm/mach-iop3xx/Makefile b/arch/arm/mach-iop3xx/Makefile index 1d7c7f1e80d0..a6d1cf98b75a 100644 --- a/arch/arm/mach-iop3xx/Makefile +++ b/arch/arm/mach-iop3xx/Makefile @@ -4,16 +4,24 @@ # Object file lists. -obj-y := arch.o mm.o xs80200-irq.o iop310-irq.o \ - iop310-pci.o +obj-y := arch.o + obj-m := obj-n := obj- := +obj-$(CONFIG_ARCH_IOP310) += xs80200-irq.o iop310-irq.o iop310-pci.o mm.o + obj-$(CONFIG_ARCH_IQ80310) += iq80310-pci.o iq80310-irq.o -ifneq ($(CONFIG_XSCALE_PMU_TIMER),y) -obj-y += iq80310-time.o +obj-$(CONFIG_ARCH_IOP321) += iop321-irq.o iop321-pci.o mm-321.o iop321-time.o + +obj-$(CONFIG_ARCH_IQ80321) += iq80321-pci.o + +ifeq ($(CONFIG_ARCH_IQ80310),y) + ifneq ($(CONFIG_XSCALE_PMU_TIMER),y) + obj-y += iq80310-time.o + endif endif obj-$(CONFIG_IOP3XX_AAU) += aau.o diff --git a/arch/arm/mach-iop3xx/arch.c b/arch/arm/mach-iop3xx/arch.c index 6a80d035a566..eb3bab2db9c4 100644 --- a/arch/arm/mach-iop3xx/arch.c +++ b/arch/arm/mach-iop3xx/arch.c @@ -24,7 +24,14 @@ #ifdef CONFIG_ARCH_IQ80310 extern void iq80310_map_io(void); extern void iq80310_init_irq(void); +#endif + +#ifdef CONFIG_ARCH_IQ80321 +extern void iq80321_map_io(void); +extern void iop321_init_irq(void); +#endif +#ifdef CONFIG_ARCH_IQ80310 static void __init fixup_iq80310(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) @@ -34,7 +41,17 @@ fixup_iq80310(struct machine_desc *desc, struct tag *tags, if (system_rev) system_rev = 0xF; } +#endif + +#ifdef CONFIG_ARCH_IQ80321 +static void __init +fixup_iop321(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ +} +#endif +#ifdef CONFIG_ARCH_IQ80310 MACHINE_START(IQ80310, "Cyclone IQ80310") MAINTAINER("MontaVista Software Inc.") BOOT_MEM(0xa0000000, 0xfe000000, 0xfe000000) @@ -43,6 +60,15 @@ MACHINE_START(IQ80310, "Cyclone IQ80310") INITIRQ(iq80310_init_irq) MACHINE_END +#elif defined(CONFIG_ARCH_IQ80321) +MACHINE_START(IQ80321, "Intel IQ80321") + MAINTAINER("MontaVista Software, Inc.") + BOOT_MEM(PHYS_OFFSET, IQ80321_UART1, 0xfe800000) + FIXUP(fixup_iop321) + MAPIO(iq80321_map_io) + INITIRQ(iop321_init_irq) +MACHINE_END + #else #error No machine descriptor defined for this IOP310 implementation #endif diff --git a/arch/arm/mach-iop3xx/iop321-irq.c b/arch/arm/mach-iop3xx/iop321-irq.c new file mode 100644 index 000000000000..472faf58256c --- /dev/null +++ b/arch/arm/mach-iop3xx/iop321-irq.c @@ -0,0 +1,95 @@ +/* + * linux/arch/arm/mach-iop3xx/iop321-irq.c + * + * Generic IOP321 IRQ handling functionality + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Added IOP3XX chipset and IQ80321 board masking code. + * + */ +#include +#include +#include + +#include +#include +#include + +#include + +static u32 iop321_mask /* = 0 */; + +static inline void intctl_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); +} + +static inline void intstr_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); +} + +static void +iop321_irq_mask (unsigned int irq) +{ + + iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +static void +iop321_irq_unmask (unsigned int irq) +{ + iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +struct irqchip ext_chip = { + .ack = iop321_irq_mask, + .mask = iop321_irq_mask, + .unmask = iop321_irq_unmask, +}; + +void __init iop321_init_irq(void) +{ + unsigned int i, tmp; + + /* Enable access to coprocessor 6 for dealing with IRQs. + * From RMK: + * Basically, the Intel documentation here is poor. It appears that + * you need to set the bit to be able to access the coprocessor from + * SVC mode. Whether that allows access from user space or not is + * unclear. + */ + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "orr %0, %0, %1\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + /* The action is delayed, so we have to do this: */ + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4" + : "=r" (tmp) : "i" (1 << 6) ); + + intctl_write(0); // disable all interrupts + intstr_write(0); // treat all as IRQ + if(machine_is_iq80321()) // all interrupts are inputs to chip + *IOP321_PCIIRSR = 0x0f; + + for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++) + { + set_irq_chip(i, &ext_chip); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + + } +} + diff --git a/arch/arm/mach-iop3xx/iop321-pci.c b/arch/arm/mach-iop3xx/iop321-pci.c new file mode 100644 index 000000000000..893c160c9c4a --- /dev/null +++ b/arch/arm/mach-iop3xx/iop321-pci.c @@ -0,0 +1,257 @@ +/* + * arch/arm/mach-iop3xx/iop321-pci.c + * + * PCI support for the Intel IOP321 chipset + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +// #define DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) do { } while (0) +#endif + +/* + * This routine builds either a type0 or type1 configuration command. If the + * bus is on the 80321 then a type0 made, else a type1 is created. + */ +static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where) +{ + struct pci_sys_data *sys = bus->sysdata; + u32 addr; + + if (sys->busnr == bus->number) + addr = 1 << (PCI_SLOT(devfn) + 16); + else + addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; + + addr |= PCI_FUNC(devfn) << 8 | (where & ~3); + + return addr; +} + +/* + * This routine checks the status of the last configuration cycle. If an error + * was detected it returns a 1, else it returns a 0. The errors being checked + * are parity, master abort, target abort (master and target). These types of + * errors occure during a config cycle where there is no device, like during + * the discovery stage. + */ +static int iop321_pci_status(void) +{ + unsigned int status; + int ret = 0; + + /* + * Check the status registers. + */ + status = *IOP321_ATUSR; + if (status & 0xf900) + { + DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); + *IOP321_ATUSR = status & 0xf900; + ret = 1; + } + status = *IOP321_ATUISR; + if (status & 0x679f) + { + DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); + *IOP321_ATUISR = status & 0x679f; + ret = 1; + } + return ret; +} + +/* + * Simply write the address register and read the configuration + * data. Note that the 4 nop's ensure that we are able to handle + * a delayed abort (in theory.) + */ +static inline u32 iop321_read(unsigned long addr) +{ + u32 val; + + __asm__ __volatile__( + "str %1, [%2]\n\t" + "ldr %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : "=r" (val) + : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); + + return val; +} + +/* + * The read routines must check the error status of the last configuration + * cycle. If there was an error, the routine returns all hex f's. + */ +static int +iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = iop321_cfg_address(bus, devfn, where); + u32 val = iop321_read(addr) >> ((where & 3) * 8); + + if( iop321_pci_status() ) + val = 0xffffffff; + + *value = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = iop321_cfg_address(bus, devfn, where); + u32 val; + + if (size != 4) { + val = iop321_read(addr); + if (!iop321_pci_status() == 0) + return PCIBIOS_SUCCESSFUL; + + where = (where & 3) * 8; + + if (size == 1) + val &= ~(0xff << where); + else + val &= ~(0xffff << where); + + *IOP321_OCCDR = val | value << where; + } else { + asm volatile( + "str %1, [%2]\n\t" + "str %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : + : "r" (value), "r" (addr), + "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); + } +} + +static struct pci_ops iop321_ops = { + .read = iop321_read_config, + .write = iop321_write_config, +}; + +/* + * When a PCI device does not exist during config cycles, the 80200 gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +int +iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +/* + * Scan an IOP321 PCI bus. sys->bus defines which bus we scan. + */ +struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &iop321_ops, sys); +} + +/* + * Setup the system data for controller 'nr'. Return 0 if none found, + * 1 if found, or negative error. + */ +int iop321_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if (nr >= 1) + return 0; + + res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + memset(res, 0, sizeof(struct resource) * 2); + + switch (nr) { + case 0: + res[0].start = IOP321_PCI_LOWER_IO + 0x6e000000; + res[0].end = IOP321_PCI_LOWER_IO + 0x6e00ffff; + res[0].name = "PCI IO Primary"; + res[0].flags = IORESOURCE_IO; + + res[1].start = IOP321_PCI_LOWER_MEM; + res[1].end = IOP321_PCI_LOWER_MEM + IOP321_PCI_WINDOW_SIZE; + res[1].name = "PCI Memory Primary"; + res[1].flags = IORESOURCE_MEM; + break; + } + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + sys->io_offset = 0x6e000000; + + return 1; +} + + + + +void iop321_init(void) +{ + DBG("PCI: Intel 80321 PCI init code.\n"); + DBG("\tATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD); + DBG("\tATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n", + *IOP321_OMWTVR0, + *IOP321_OIOWTVR); + DBG("\tATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR); + DBG("\tATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0); + DBG("\tATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR); + DBG("\tATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2); + DBG("\tATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3); + + hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort"); + +} + diff --git a/arch/arm/mach-iop3xx/iop321-time.c b/arch/arm/mach-iop3xx/iop321-time.c new file mode 100644 index 000000000000..d1686217a1c4 --- /dev/null +++ b/arch/arm/mach-iop3xx/iop321-time.c @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-iop3xx/iop321-time.c + * + * Timer code for IOP321 based systems + * + * Author: Deepak Saxena + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static unsigned long iop321_gettimeoffset(void) +{ + unsigned long elapsed, usec; + + /* + * FIXME: Implement what is described in this comment. + * + * If an interrupt was pending before we read the timer, + * we've already wrapped. Factor this into the time. + * If an interrupt was pending after we read the timer, + * it may have wrapped between checking the interrupt + * status and reading the timer. Re-read the timer to + * be sure its value is after the wrap. + */ + + elapsed = *IOP321_TU_TCR0; + + /* + * Now convert them to usec. + */ + usec = (unsigned long)((LATCH - elapsed) * (tick_nsec / 1000)) / LATCH; + + return usec; +} + +static void iop321_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + u32 tisr; + + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); + + tisr |= 1; + + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); + + do_timer(regs); +} + +extern unsigned long (*gettimeoffset)(void); + +static struct irqaction timer_irq = { + .name = "timer", + .handler = iop321_timer_interrupt, +}; + +extern int setup_arm_irq(int, struct irqaction*); + +void __init time_init(void) +{ + u32 timer_ctl; + u32 latch = LATCH; + + gettimeoffset = iop321_gettimeoffset; + setup_irq(IRQ_IOP321_TIMER0, &timer_irq); + + timer_ctl = IOP321_TMR_EN | IOP321_TMR_PRIVILEGED | IOP321_TMR_RELOAD | + IOP321_TMR_RATIO_1_1; + + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); + + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); +} + + diff --git a/arch/arm/mach-iop3xx/iq80321-pci.c b/arch/arm/mach-iop3xx/iq80321-pci.c new file mode 100644 index 000000000000..7dce5dfa627e --- /dev/null +++ b/arch/arm/mach-iop3xx/iq80321-pci.c @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-iop3xx/iq80321-pci.c + * + * PCI support for the Intel IQ80321 reference board + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#include +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + unsigned int _idsel = idsel - minid; \ + if (_idsel <= maxid) \ + _ctl_ = pci_irq_table[_idsel][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ80321_INTA +#define INTB IRQ_IQ80321_INTB +#define INTC IRQ_IQ80321_INTC +#define INTD IRQ_IQ80321_INTD + +#define INTE IRQ_IQ80321_I82544 + +typedef u8 irq_table[4]; + +static irq_table pci_irq_table[] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {INTE, INTE, INTE, INTE}, /* Gig-E */ + {INTD, INTC, INTD, INTA}, /* Unused */ + {INTC, INTD, INTA, INTB}, /* PCI-X Slot */ +}; + +static inline int __init +iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + BUG_ON(pin < 1 || pin > 4); + + return PCI_IRQ_TABLE_LOOKUP(2, 3); +} + +static int iq80321_setup(int nr, struct pci_sys_data *sys) +{ + switch (nr) { + case 0: + sys->map_irq = iq80321_map_irq; + break; + default: + return 0; + } + + return iop321_setup(nr, sys); +} + +static void iq80321_preinit(void) +{ + iop321_init(); +} + +static struct hw_pci iq80321_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iq80321_setup, + .scan = iop321_scan_bus, + .preinit = iq80321_preinit, +}; + +static int __init iq80321_pci_init(void) +{ + if (machine_is_iq80321()) + pci_common_init(&iq80321_pci); + return 0; +} + +subsys_initcall(iq80321_pci_init); + + + + diff --git a/arch/arm/mach-iop3xx/mm-321.c b/arch/arm/mach-iop3xx/mm-321.c new file mode 100644 index 000000000000..b345481e2488 --- /dev/null +++ b/arch/arm/mach-iop3xx/mm-321.c @@ -0,0 +1,64 @@ +/* + * linux/arch/arm/mach-iop3xx/mm.c + * + * Low level memory intialization for IOP321 based systems + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include +#include + + +/* + * Standard IO mapping for all IOP321 based systems + */ +static struct map_desc iop80321_std_desc[] __initdata = { + /* virtual physical length type */ + + /* mem mapped registers */ + { 0xfff00000, 0xffffe000, 0x00002000, MT_DEVICE }, + + /* PCI IO space */ + { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE } +}; + +void __init iop321_map_io(void) +{ + iotable_init(iop80321_std_desc, ARRAY_SIZE(iop80321_std_desc)); +} + +/* + * IQ80321 specific IO mappings + * + * We use RedBoot's setup for the onboard devices. + */ +#ifdef CONFIG_ARCH_IQ80321 +static struct map_desc iq80321_io_desc[] __initdata = { + /* virtual physical length type */ + + /* on-board devices */ + { 0xfe800000, 0xfe800000, 0x00100000, MT_DEVICE } +}; + +void __init iq80321_map_io(void) +{ + iop321_map_io(); + + iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); +} +#endif // CONFIG_ARCH_IQ80321 diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2e96fd8178f7..ba13ebc13e2e 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -654,6 +654,9 @@ ENTRY(cpu_xscale_set_pte) cpu_80200_name: .asciz "XScale-80200" +cpu_80321_name: + .asciz "XScale-IOP80321" + cpu_pxa250_name: .asciz "XScale-PXA250" @@ -748,6 +751,22 @@ __80200_proc_info: .long xscale_mc_user_fns .size __80200_proc_info, . - __80200_proc_info + .type __80321_proc_info,#object +__80321_proc_info: + .long 0x69052420 + .long 0xfffffff0 + .long 0x00000c0e + b __xscale_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_80321_name + .long xscale_processor_functions + .long v4wbi_tlb_fns + .long xscale_mc_user_fns + .long xscale_cache_fns + .size __80321_proc_info, . - __80321_proc_info + .type __pxa250_proc_info,#object __pxa250_proc_info: .long 0x69052100 diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h index 4fb2bcbb112f..03338ca25a9e 100644 --- a/include/asm-arm/arch-iop3xx/hardware.h +++ b/include/asm-arm/arch-iop3xx/hardware.h @@ -20,6 +20,7 @@ #define pcibios_assign_all_busses() 1 +#ifdef CONFIG_ARCH_IOP310 /* * these are the values for the secondary PCI bus on the 80312 chip. I will * have to do some fixup in the bus/dev fixup code @@ -34,5 +35,21 @@ #if defined(CONFIG_ARCH_IQ80310) #include "iq80310.h" #endif +#endif + +#ifdef CONFIG_ARCH_IOP321 + +#define PCIBIOS_MIN_IO 0x90000000 +#define PCIBIOS_MIN_MEM 0x80000000 + +#include "iop321.h" + +#ifdef CONFIG_ARCH_IQ80321 +#include "iq80321.h" +#endif +#endif + + + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h new file mode 100644 index 000000000000..6e757b819105 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop321-irqs.h @@ -0,0 +1,83 @@ +/* + * linux/include/asm-arm/arch-iop3xx/irqs.h + * + * Author: Rory Bolt + * Copyright: (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + +/* + * IOP80321 chipset interrupts + */ +#define IOP321_IRQ_OFS 0 +#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0) +#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1) +#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2) +#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3) +#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4) +#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5) +#define IRQ_IOP321_AA_EOT IOP321_IRQ(6) +#define IRQ_IOP321_AA_EOC IOP321_IRQ(7) +#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8) +#define IRQ_IOP321_TIMER0 IOP321_IRQ(9) +#define IRQ_IOP321_TIMER1 IOP321_IRQ(10) +#define IRQ_IOP321_I2C_0 IOP321_IRQ(11) +#define IRQ_IOP321_I2C_1 IOP321_IRQ(12) +#define IRQ_IOP321_MESSAGING IOP321_IRQ(13) +#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14) +#define IRQ_IOP321_PERFMON IOP321_IRQ(15) +#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16) +#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17) +#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18) +#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19) +#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20) +#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21) +#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22) +#define IRQ_IOP321_AA_ERR IOP321_IRQ(23) +#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24) +#define IRQ_IOP321_SSP IOP321_IRQ(25) +#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26) +#define IRQ_IOP321_XINT0 IOP321_IRQ(27) +#define IRQ_IOP321_XINT1 IOP321_IRQ(28) +#define IRQ_IOP321_XINT2 IOP321_IRQ(29) +#define IRQ_IOP321_XINT3 IOP321_IRQ(30) +#define IRQ_IOP321_HPI IOP321_IRQ(31) + +#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1) + +#define NR_IRQS NR_IOP321_IRQS + + +/* + * Interrupts available on the IQ80321 board + */ +#ifdef CONFIG_ARCH_IQ80321 + +/* + * On board devices + */ +#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0 +#define IRQ_IQ80321_UART IRQ_IOP321_XINT1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0 +#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1 +#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2 +#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3 + +#endif // CONFIG_ARCH_IQ80321 + +#define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU + diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h new file mode 100644 index 000000000000..34bb2da3c586 --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iop321.h @@ -0,0 +1,143 @@ +/* + * linux/include/asm/arch-iop3xx/iop321.h + * + * Intel IOP321 Chip definitions + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP321_HW_H_ +#define _IOP321_HW_H_ + +/* + * IOP321 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP321_PCI_LOWER_IO 0x90000000 +#define IOP321_PCI_UPPER_IO 0x9000ffff +#define IOP321_PCI_LOWER_MEM 0x80000000 +#define IOP321_PCI_UPPER_MEM 0x83ffffff + +#define IOP321_PCI_WINDOW_SIZE 64 * 0x100000 + +/* + * IOP321 chipset registers + */ +#define IOP321_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/ +#define IOP321_PHY_MEM_BASE 0xffffe000 /* chip physical memory address */ +#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg)) + +/* Reserved 0x00000000 through 0x000000FF */ + +/* Address Translation Unit 0x00000100 through 0x000001FF */ +#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100) +#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102) +#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104) +#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106) +#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108) +#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109) +#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C) +#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D) +#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E) +#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F) +#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110) +#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114) +#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118) +#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C) +#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120) +#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124) +#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C) +#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E) +#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130) +/* Reserved 0x00000134 through 0x0000013B */ +#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C) +#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D) +#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E) +#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F) +#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140) +#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144) +#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148) +#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C) +#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150) +#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154) +#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158) +#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C) +#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160) +#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164) +#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168) +#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C) +/* Reserved 0x00000170 through 0x00000177*/ +#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178) +/* Reserved 0x0000017C through 0x0000017F*/ +#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180) +#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184) +#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188) +#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C) +#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190) +#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194) +#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198) +#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C) +/* Reserved 0x000001A0 through 0x000001A3*/ +#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4) +/* Reserved 0x000001A8 through 0x000001AB*/ +#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC) +/* Reserved 0x000001B0 through 0x000001BB*/ +#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC) +#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0) +#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1) +#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2) +#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4) +/* Reserved 0x000001C6 through 0x000001DF */ +#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0) +#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1) +#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2) +#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4) +#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC) + +/* Messaging Unit 0x00000300 through 0x000003FF */ +/* DMA Controller 0x00000400 through 0x000004FF */ +/* Memory controller 0x00000500 through 0x0005FF */ +/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ +/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ +/* Internal arbitration unit 0x00000780 through 0x0007BF */ + +/* Interrupt Controller */ +#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0) +#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4) +#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) +#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) + +/* Timers */ + +#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0) +#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4) + +#define IOP321_TMR_TC 0x01 +#define IOP321_TMR_EN 0x02 +#define IOP321_TMR_RELOAD 0x04 +#define IOP321_TMR_PRIVILEGED 0x09 + +#define IOP321_TMR_RATIO_1_1 0x00 +#define IOP321_TMR_RATIO_4_1 0x10 +#define IOP321_TMR_RATIO_8_1 0x20 +#define IOP321_TMR_RATIO_16_1 0x30 + +#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8) +#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC) +#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0) +#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4) +#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8) +#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC) + +/* Application accelerator unit 0x00000800 - 0x000008FF */ +#define IOP321_AAUACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) +#define IOP321_AAUASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) +#define IOP321_AAUANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C) + +/* SSP serial port unit 0x00001600 - 0x0000167F */ +/* I2C bus interface unit 0x00001680 - 0x000016FF */ +#endif // _IOP321_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop3xx/iq80321.h new file mode 100644 index 000000000000..8a94ce8ffacf --- /dev/null +++ b/include/asm-arm/arch-iop3xx/iq80321.h @@ -0,0 +1,17 @@ +/* + * linux/include/asm/arch-iop3xx/iq80321.h + * + * Intel IQ-80321 evaluation board registers + */ + +#ifndef _IQ80321_H_ +#define _IQ80321_H_ + +#define IQ80321_RAMBASE 0xa0000000 +#define IQ80321_UART1 0xfe800000 /* UART #1 */ +#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#endif // _IQ80321_H_ diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h index c18c69537acd..7468fab71d94 100644 --- a/include/asm-arm/arch-iop3xx/irqs.h +++ b/include/asm-arm/arch-iop3xx/irqs.h @@ -1,80 +1,25 @@ /* * linux/include/asm-arm/arch-iop3xx/irqs.h * - * Author: Nicolas Pitre * Copyright: (C) 2001 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * 06/13/01: Added 80310 on-chip interrupt sources * */ -#include /* - * XS80200 specific IRQs + * Whic iop3xx implementation is this? */ -#define IRQ_XS80200_BCU 0 /* Bus Control Unit */ -#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */ -#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */ -#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */ +#ifdef CONFIG_ARCH_IOP310 -#define NR_XS80200_IRQS 4 +#include "iop310-irqs.h" -#define XSCALE_PMU_IRQ IRQ_XS80200_PMU +#else -/* - * IOP80310 chipset interrupts - */ -#define IOP310_IRQ_OFS NR_XS80200_IRQS -#define IOP310_IRQ(x) (IOP310_IRQ_OFS + (x)) - -/* - * On FIQ1ISR register - */ -#define IRQ_IOP310_DMA0 IOP310_IRQ(0) /* DMA Channel 0 */ -#define IRQ_IOP310_DMA1 IOP310_IRQ(1) /* DMA Channel 1 */ -#define IRQ_IOP310_DMA2 IOP310_IRQ(2) /* DMA Channel 2 */ -#define IRQ_IOP310_PMON IOP310_IRQ(3) /* Bus performance Unit */ -#define IRQ_IOP310_AAU IOP310_IRQ(4) /* Application Accelator Unit */ - -/* - * On FIQ2ISR register - */ -#define IRQ_IOP310_I2C IOP310_IRQ(5) /* I2C unit */ -#define IRQ_IOP310_MU IOP310_IRQ(6) /* messaging unit */ - -#define NR_IOP310_IRQS (IOP310_IRQ(6) + 1) - -#define NR_IRQS NR_IOP310_IRQS - - -/* - * Interrupts available on the Cyclone IQ80310 board - */ -#ifdef CONFIG_ARCH_IQ80310 - -#define IQ80310_IRQ_OFS NR_IOP310_IRQS -#define IQ80310_IRQ(y) ((IQ80310_IRQ_OFS) + (y)) - -#define IRQ_IQ80310_TIMER IQ80310_IRQ(0) /* Timer Interrupt */ -#define IRQ_IQ80310_I82559 IQ80310_IRQ(1) /* I82559 Ethernet Interrupt */ -#define IRQ_IQ80310_UART1 IQ80310_IRQ(2) /* UART1 Interrupt */ -#define IRQ_IQ80310_UART2 IQ80310_IRQ(3) /* UART2 Interrupt */ -#define IRQ_IQ80310_INTD IQ80310_IRQ(4) /* PCI INTD */ - - -/* - * ONLY AVAILABLE ON REV F OR NEWER BOARDS! - */ -#define IRQ_IQ80310_INTA IQ80310_IRQ(5) /* PCI INTA */ -#define IRQ_IQ80310_INTB IQ80310_IRQ(6) /* PCI INTB */ -#define IRQ_IQ80310_INTC IQ80310_IRQ(7) /* PCI INTC */ - -#undef NR_IRQS -#define NR_IRQS (IQ80310_IRQ(7) + 1) +#include "iop321-irqs.h" -#endif // CONFIG_ARCH_IQ80310 +#endif diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h index 5ffe1f0f8c69..4d376436be6a 100644 --- a/include/asm-arm/arch-iop3xx/memory.h +++ b/include/asm-arm/arch-iop3xx/memory.h @@ -7,6 +7,7 @@ #include #include +#include /* * Task size: 3GB @@ -47,9 +48,19 @@ */ #define __virt_to_bus__is_a_macro #define __bus_to_virt__is_a_macro + +#ifdef CONFIG_ARCH_IOP310 + #define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0)) #define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR))) +#elif defined(CONFIG_ARCH_IOP321) + +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) + +#endif + /* boot mem allocate global pointer for MU circular queues QBAR */ #ifdef CONFIG_IOP3XX_MU extern void *mu_mem; diff --git a/include/asm-arm/arch-iop3xx/serial.h b/include/asm-arm/arch-iop3xx/serial.h index ee5b32899e6e..60a2b61e75e1 100644 --- a/include/asm-arm/arch-iop3xx/serial.h +++ b/include/asm-arm/arch-iop3xx/serial.h @@ -29,6 +29,17 @@ #endif // CONFIG_ARCH_IQ80310 +#ifdef CONFIG_ARCH_IQ80321 + +#define IRQ_UART1 IRQ_IQ80321_UART + +#define RS_TABLE_SIZE 1 + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS }, /* ttyS0 */ +#endif // CONFIG_ARCH_IQ80321 + #define EXTRA_SERIAL_PORT_DEFNS diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h index de726e9f88a9..2aec857754b4 100644 --- a/include/asm-arm/arch-iop3xx/timex.h +++ b/include/asm-arm/arch-iop3xx/timex.h @@ -14,7 +14,11 @@ #else /* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */ #define CLOCK_TICK_RATE 733000000 -#endif +#endif // IQ80310 + +#elif defined(CONFIG_ARCH_IQ80321) + +#define CLOCK_TICK_RATE 200000000 #else diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h index c8d6a6ca859a..fd7e72b7d113 100644 --- a/include/asm-arm/arch-iop3xx/uncompress.h +++ b/include/asm-arm/arch-iop3xx/uncompress.h @@ -2,10 +2,13 @@ * linux/include/asm-arm/arch-iop80310/uncompress.h */ #include +#include +#include #ifdef CONFIG_ARCH_IQ80310 -#define UART1_BASE ((volatile unsigned char *)0xfe800000) -#define UART2_BASE ((volatile unsigned char *)0xfe810000) +#define UART2_BASE ((volatile unsigned char *)IQ80310_UART2) +#elif defined(CONFIG_ARCH_IQ80321) +#define UART2_BASE ((volatile unsigned char *)IQ80321_UART1) #endif static __inline__ void putc(char c) diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 57b6289e6b59..ea0b992eebc2 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -56,6 +56,10 @@ extern int iop310_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *); extern void iop310_init(void); +extern int iop321_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *); +extern void iop321_init(void); + extern int dc21285_setup(int nr, struct pci_sys_data *); extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); -- 2.39.5